Method to reduce back-side contact resistance

Abstract

One or more embodiments of this disclosure relate to methods for forming semiconductor devices (e.g., gate-all-around (GAA) transistors used in FEOL and / or BEOL processes). The processes described herein can be integrated and executed in any suitable cluster tool. Some embodiments of this disclosure relate to cavity forming processes. Further embodiments of this disclosure relate to logic transistors having wrap-around back-side source / drain contacts.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of semiconductor devices and semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to a method for reducing backside contact resistance in both NMOS contacts and PMOS contacts.

Background Art

[0002]

[0002] Integrated circuits have evolved into complex devices that can accommodate millions of transistors, capacitors, and resistors on a single chip. In the process of the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the form factor size (i.e., the smallest component (or line) that can be fabricated using the manufacturing process) has decreased.

[0003]

[0003] Transistors are important components in most integrated circuits. Since the drive current of a transistor, and thus its speed, is proportional to the gate width of the transistor, generally, faster transistors need to have a larger gate width. Therefore, there is a trade-off relationship between the size and speed of a transistor, and in order to achieve the conflicting goals of maximum drive current and minimum size, "fin-type" field effect transistors (FinFETs) have been developed. FinFETs are characterized by a fin-type channel region that significantly increases the size of the transistor without significantly increasing the installation area of the transistor, and are currently applied to many integrated circuits. However, FinFETs have specific drawbacks.

[0004]

[0004] In order to achieve higher density and higher performance of circuits, the feature size of transistor devices continues to shrink, and there is a need to improve the structure of transistor devices and reduce contact resistance. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and gate-all-around (GAA) structures. The performance of logic gates depends not only on the thickness and area of ​​the structural layers but also on the properties of the materials used. However, when adjusting some gate characteristics to accommodate device scaling, challenges arise.

[0005]

[0005] As the semiconductor manufacturing industry moves to advanced nodes of 2nm or less, there is a need to reduce contact resistance and improve device speed and drive current. Therefore, there is a need for methods to reduce contact resistance.

[0006]

[0006] Connecting semiconductor power rails is typically done on the front of the cell (e.g., the semiconductor substrate), requiring a considerable cell area. The formation of back-side power rails, i.e., the technique of connecting the back of the source epitaxial layer (source-epi) to logic transistors (e.g., FinFETs or GAAs) (known as BPR Gen-II), is being considered for continuous area scaling in next-generation logic nodes.

[0007]

[0007] However, currently known methods for backside contact of the epitaxial layer of the source have limitations on the area and resistivity of the contact interface. When the area and resistivity of the contact interface are limited, the contact resistance increases. Also, when the area of ​​the contact interface is limited, current crowding occurs, and the resistance of the epitaxial layer of the source also increases. When the source resistance and contact resistance increase, the overall resistance of the device increases, and the performance of the device (drive current and speed) decreases. Furthermore, there is a need for improved methods to reduce contact resistance in order to obtain direct bottom contact of the source / drain region without an etching stop layer when forming backside power rails, and to obtain a self-aligned bottom contact structure. [Overview of the Initiative]

[0008]

[0008] One or more embodiments of the present disclosure relate to a method for forming a semiconductor device. The method includes forming a first liner layer on a semiconductor substrate. The semiconductor substrate includes a source / drain region below a top surface and a superlattice structure on the top surface of the semiconductor substrate. The source / drain region includes a silicon germanium (SiGe) layer filling the source / drain region and a capping layer on the silicon germanium (SiGe) layer. The superlattice structure includes a plurality of first layers of a first material and a plurality of corresponding second layers arranged alternately in a plurality of stacked pairs. The first liner layer is formed along the plurality of first layers and the plurality of second layers. The method further includes etching the bottom of a first liner layer to form an etched first liner layer; epitaxially growing a second liner layer along the first liner layer in a superlattice structure; inverting the semiconductor substrate to expose the back side of the semiconductor substrate; etching to remove the capping layer and silicon germanium (SiGe) layer to form an opening in the source / drain region of the back side; depositing a metal silicide layer on the top surface of the opening; depositing a barrier layer along the opening in the source / drain region on the back side and on the metal silicide layer; and depositing a metallic material on the barrier layer to fill the opening and form back side contact.

[0009]

[0009] Further embodiments of the present disclosure relate to a method for forming a semiconductor device. The method includes forming a first liner layer and a second liner layer on a semiconductor substrate. The semiconductor substrate includes a source / drain region below a top surface and a superlattice structure on the top surface of the semiconductor substrate. The source / drain region includes a silicon germanium (SiGe) layer filling the source / drain region and a capping layer on the silicon germanium (SiGe) layer. The superlattice structure includes a plurality of first layers of a first material and a plurality of corresponding second layers of a second material arranged alternately in a plurality of stacked pairs. The first liner layer is formed along the plurality of first layers and the plurality of second layers, and the second liner layer is formed within the superlattice structure and along the first liner layer. This method further includes inverting a semiconductor substrate to expose the back side of the semiconductor substrate; etching the bottom of a first liner layer to form an etched first liner layer; etching to remove the capping layer and silicon germanium (SiGe) layer to form an opening in the source / drain region of the back side; etching a cavity in the opening to remove a portion of the etched first liner layer and a portion of the second liner layer to form an etched second liner layer; depositing a metal silicide layer on the upper surface of the opening in the source / drain region of the back side; depositing a barrier layer along the opening in the source / drain region on the back side and on the metal silicide layer; and depositing a metallic material on the barrier layer to fill the opening and form back side contact.

[0010]

[0010] Further embodiments of the present disclosure relate to a method for forming a semiconductor device. The method comprises forming a first liner layer and a second liner layer on a semiconductor substrate. The semiconductor substrate includes a source / drain region below a top surface and a superlattice structure on the top surface of the semiconductor substrate. The source / drain region includes a silicon germanium (SiGe) layer filling the source / drain region and a capping layer on the silicon germanium (SiGe) layer. The superlattice structure includes a plurality of first layers of a first material and a plurality of second layers of a corresponding second material, arranged alternately in a plurality of stacked pairs. The first liner layer is formed along the plurality of first layers and the plurality of second layers, and the second liner layer is formed within the superlattice structure and along the first liner layer. This method further includes inverting a semiconductor substrate to expose its back surface, selectively removing a silicon germanium (SiGe) layer to form an opening in the source / drain region on the back surface, depositing a third liner layer in the opening, and punch-through etching a portion of the third liner layer, capping layer, first liner layer, and second liner layer to form a concave source / drain region. The concave source / drain region has an upper portion within the superlattice structure that is above the top surface of the semiconductor substrate, and a bottom portion within the semiconductor substrate that is below the top surface of the semiconductor substrate. This method further includes depositing a metal silicide layer on the upper surface of the concave source / drain region, depositing a barrier layer on the bottom of the concave source / drain region on the third liner layer, and depositing a metallic material in the opening to form back-side contact.

[0011]

[0011] To enable a more detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been concisely summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate one or more embodiments of the Disclosure and should not be considered to limit the scope of the Disclosure, as the Disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0012] [Figure 1]

[0012] A process flow diagram of a method for forming a semiconductor device according to one or more embodiments is shown. [Figure 2A]

[0013] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 2B]

[0014] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 2C]

[0015] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 2D]

[0016] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 2E]

[0017] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 2F]

[0018] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 3]

[0019] This shows a process flow diagram of a method for forming a semiconductor device according to one or more embodiments. [Figure 4A]

[0020] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 4B]

[0021] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 4C]

[0022] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 4D]

[0023] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 4E]

[0024] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 4F]

[0025] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 5]

[0026] Shows a process flow diagram of a method for forming a semiconductor device according to one or more embodiments. [Figure 6A]

[0027] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 6B]

[0028] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 6C]

[0029] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 6D]

[0030] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 6E]

[0031] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 6F]

[0032] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 6G]

[0033] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 7A]

[0034] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 7B]

[0035] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 7C]

[0036] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 7D]

[0037] Shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 8]

[0038] A schematic top view of an exemplary multi-chamber processing system according to one or more embodiments is shown. [Modes for carrying out the invention]

[0013]

[0039] For ease of understanding, unless otherwise noted, the same reference numerals have been used to indicate identical elements common to the drawings. It is assumed that elements of one embodiment may be usefully incorporated into other embodiments without further description.

[0014]

[0040] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the structural or process step details described below. Other embodiments of this disclosure are possible and can be implemented or performed in a variety of ways.

[0015]

[0041] The following description includes numerous specific details to provide a comprehensive understanding of the embodiments of this disclosure. Those skilled in the art will see that the embodiments can be carried out without these specific details. In other cases, well-known embodiments are not described in detail so as not to unnecessarily obscure the embodiments.

[0016]

[0042] As used herein, the term “approximately” means roughly or nearly, and refers to a variation of no more than ±15% of a given number or range. For example, a difference of approximately ±14%, ±10%, ±5%, ±2%, ±1%, ±0.5%, or ±0.1% satisfies the definition of “approximately.”

[0017]

[0043] To describe the relationship between one element and one or more other elements, or for the purpose of simplifying the explanation, as shown in the diagram, spatial relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used. It will be understood that spatial relative terms are intended to encompass different orientations of a device in use or operation (such as a semiconductor device) in addition to the illustrated orientation. For example, if the device in the diagram is upside down, an element described as “below” or “directly below” another element or feature would be oriented “above” the other element or feature. Thus, the exemplary term “below” may encompass both up and down orientations. The device may be oriented differently (rotated 90 degrees or oriented in other orientations), and the spatial relative descriptions used herein may be interpreted accordingly.

[0018]

[0044] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar references should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless the context clearly contradicts this interpretation. The range descriptions of values ​​herein are merely intended to serve as abbreviations for each individual value within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually described herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or unless the context clearly contradicts this interpretation. Any and all examples or exemplary language provided herein (e.g., “such as”) is merely intended to more preferably describe the materials and methods and does not limit their scope unless specifically asserted. The language herein should not be interpreted as indicating that non-claimed elements are essential for the implementation of the disclosed materials and methods.

[0019]

[0045] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” “several embodiments,” or “embodiments” means that the specific elements, structures, materials, or properties described in relation to those embodiments are included in at least one embodiment of this disclosure. Therefore, phrases such as “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” “several embodiments,” and “in an embodiment” used in various places throughout this specification do not necessarily refer to the same embodiments of this disclosure. In one or more embodiments, the specific elements, structures, materials, or properties are combined in any suitable manner.

[0020]

[0046] The above description and figures, as well as the description below, include numerous specific details (such as specific materials, chemical properties, and element dimensions) to facilitate a full understanding of one or more embodiments of the disclosure. However, it will be apparent to those skilled in the art that one or more embodiments of the disclosure can be practiced even without these specific details. In other examples, semiconductor manufacturing processes, techniques, materials, and equipment are not described in great detail to avoid unnecessarily obscuring the description. Those skilled in the art will be able to implement appropriate functionality using the descriptions contained herein without conducting unnecessary experiments.

[0021]

[0047] As used herein and in the appended claims, the terms “substrate” or “wafer” refer to the surface or portion of a surface on which the process is performed. Furthermore, unless otherwise clearly indicated by the context, a reference to a substrate may refer to only a portion of the substrate. Moreover, when a reference is made to deposition on a substrate, it may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0022]

[0048] As used herein, “substrate” refers to any substrate or material surface formed on a substrate on which layer or film processing is performed during the manufacturing process. For example, substrate surfaces on which processing may be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pre-treatment processes for polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, any disclosed film processing step may be performed on underlying layers formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such underlying layers as the context indicates. Therefore, for example, when a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0023]

[0049] The term "on" indicates direct contact between elements. The term "directly on ~" indicates direct contact between elements without the presence of an intervening element.

[0024]

[0050] As used herein, the term “in-situ” refers to a process that is performed entirely within the same processing chamber, or within different processing chambers connected as part of an integrated processing system, where each of the processes is performed without intervening vacuum breaking. As used herein, the term “ex-situ” refers to a process that is performed in at least two different processing chambers, where one or more of the processes are performed with intervening vacuum breaking. In some embodiments, the process is performed without breaking the vacuum or being exposed to ambient air.

[0025]

[0051] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable and refer to any gas species that can react with the substrate surface.

[0026]

[0052] As used herein, “atomic layer deposition” or “periodic deposition” refers to the sequential exposure of two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate or a portion of the substrate is exposed separately to two or more reactive compounds introduced into the reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay so that each compound can adhere to and / or react on the substrate surface and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different portions of the substrate surface, or material on the substrate surface, are exposed to two or more reactive compounds simultaneously such that no given point on the substrate is substantially exposed to multiple reactive compounds at the same time. As used herein and in the appended claims, the term “substantially” as used in this respect means, as understood by those skilled in the art, that small portions of the substrate may be simultaneously exposed to multiple reactive gases by diffusion, and that this simultaneous exposure is not intended.

[0027]

[0053] In one embodiment of a time-domain ALD process, a first time delay is introduced after a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone. Next, a second delay is introduced after a second precursor or compound B is pulsed into the reaction zone. At each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or to remove any remaining reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulsed deliveries of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or thickness is formed on the substrate surface. In either case, one ALD process consists of pulsed delivery of compound A, purge gas, compound B, and purge gas. A cycle can begin with either compound A or compound B, and each sequence of cycles can continue until a film of a predetermined thickness is achieved.

[0028]

[0054] In an embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied simultaneously to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply device so that any given point on the substrate is exposed to the first and second reactive gases.

[0029]

[0055] One or more layers deposited on a substrate or substrate surface are continuous. As used herein, the term “continuous” refers to a layer that covers the entire exposed surface without gaps or bare spots that expose the material beneath the deposited layer. A continuous layer may have gaps or bare spots with a surface area of ​​less than about 15% or less than 10% of the total surface area of ​​the layer.

[0030]

[0056] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped substrate regions and may exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode of the substrate and the channel region. In one or more embodiments, the gate surrounds all of the nanosheets between the bottom substrate and the channel.

[0031]

[0057] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) where carriers enter the channel, the drain (D) where carriers exit the channel, and the gate (G) which adjusts the conductivity of the channel. In the conventional method, the current entering the channel at the source (S) is I S The following is displayed, and the current entering the channel at the drain (D) is I D This is what is displayed. The drain-source voltage is V DS This is displayed. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ) can be controlled.

[0032]

[0058] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage applied to it determines the device's conductivity. This ability to change conductivity depending on the magnitude of the applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by a metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type, the opposite type to the body region. The source and drain are highly doped (unlike the body), and the doping type is indicated by a "+" sign.

[0033]

[0059] If the MOSFET is an n-channel type, i.e., an nMOS FET, the source and drain are in the n+ region, and the body is in the p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are in the p+ region, and the body is in the n region. The source is so named because it is the source of charge carriers (electrons in the case of an n-channel, and holes in the case of a p-channel) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0034]

[0060] As used herein, the term "fin-type field-effect transistor (FinFET)" refers to a MOSFET transistor fabricated on a substrate with gates on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are commonly named FinFETs because the channel region forms "fins" on the substrate. FinFET devices offer fast switching times and high current densities.

[0035]

[0061] As used herein, the term “gate all around (GAA)” is used to refer to an electronic device (e.g., a transistor) in which the gate material surrounds the channel region on all four sides. The channel region of a GAA transistor may include nanowires or nanoslabs, a rod-shaped channel, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of horizontal nanowires or horizontal bars spaced vertically apart, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0036]

[0062] As used herein, the term "nanowire" refers to a nanometer (10⁻¹⁰) -9 The term "nanowire" refers to a nanostructure having a diameter in units of meters. A nanowire can also be defined as having a length-to-width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure whose thickness and diameter are limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0037]

[0063] Generally, the front-end of line (FEOL) refers to the first part of integrated circuit manufacturing, including transistor manufacturing; the middle of line (MOL) refers to connecting the transistors and interconnects of the chip using a series of contact structures; and the back-end of line (BEOL) refers to the series of process steps after transistor manufacturing up to the completion of the wafer. One or more embodiments of this disclosure relate to methods for forming gate-all-around (GAA) transistors that may be used in FEOL and / or BEOL processes.

[0038]

[0064] In one or more embodiments, transistors, such as GAA transistors, are manufactured using a standard process flow. One or more figures show part or part of a multi-stage manufacturing process for semiconductor devices, particularly during back-side power supply (BPD).

[0039]

[0065] Connecting semiconductors to power rails is typically done on the front of the cell, which requires a considerable amount of cell area. The formation of back-side power rails, i.e., the technique of connecting the back of the epitaxial layer of the source of logic transistors (such as FinFETs or GAAs) (known as BPR Gen-II), has been explored for continuous area scaling in next-generation logic nodes.

[0040]

[0066] However, currently known methods for back-side contact of the epitaxial layer of a source have limitations on the contact interface area and contact resistivity. When the contact interface area and contact resistivity are limited, the contact resistance increases. Also, when the contact interface area is limited, current concentrates, and the resistance of the epitaxial layer of the source also increases. When the source resistance and contact resistance increase, the overall resistance of the device increases, and the performance of the device (drive current and speed) decreases.

[0041]

[0067] While I don't intend to be bound by theory, for example, in NMOS contacts, the resistance on the back side is 144% greater than the resistance on the front side.

[0042]

[0068] Embodiments of this disclosure advantageously provide novel integration methods for reducing back-side contact resistance. Some embodiments relate to processes that advantageously increase the area of ​​the contact interface. Some embodiments relate to processes that advantageously reduce the contact resistivity. Some embodiments relate to processes that advantageously increase the area of ​​the contact interface and reduce the contact resistivity.

[0043]

[0069] Some embodiments advantageously provide a method for reducing the contact resistance of an resulting semiconductor device compared to a semiconductor device comprising only a molybdenum silicide (MoSi) layer.

[0044]

[0070] The processes described herein may be integrated into and executed in any suitable cluster tool. The cluster tool may include processing chambers for manufacturing semiconductor devices, such as etching, deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used in the manufacture of semiconductor devices.

[0045]

[0071] Some embodiments of this disclosure relate to cavity forming processes. In some embodiments, the method for reducing backside contact resistance includes multiple cavity forming processes. In some embodiments, the method for reducing backside contact resistance includes a backside contact injection process after backside contact opening. The processes described herein may be integrated methods performed in a cluster tool.

[0046]

[0072] One or more embodiments of the present disclosure relate to a process comprising back trench etching with sidewall liners. Some embodiments relate to a cavity forming etching process for forming recesses on the front side of source / drain regions. Some embodiments relate to a high-dose selective contact epitaxial growth process, formation of a metal silicide layer, and filling of metal contact trenches for forming back contacts.

[0047]

[0073] In some embodiments, a method including a pre-cleaning process, a selective epitaxial growth process, and deposition of a metal silicide, and optionally filling the backside contact openings with metal, is performed in the cluster tool. Further embodiments of the present disclosure relate to logic transistors having wrap-around backside source / drain contact.

[0048]

[0074] Embodiments of this disclosure are described by diagrams illustrating devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of this disclosure. The illustrated processes merely illustrate possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated uses.

[0049]

[0075] Figure 1 shows a process flow diagram of Method 100 for forming a semiconductor device (e.g., semiconductor device 200) according to one or more embodiments of the present disclosure. Method 100 is described below with respect to Figures 2A-2F, which show the manufacturing stages of the semiconductor device 200 according to one or more embodiments of the present disclosure. Figures 2A-2F show cross-sectional views of the semiconductor device 200. Method 100 may be part of a multi-stage manufacturing process. Therefore, Method 100 may be an integrated method performed within any suitable processing chamber coupled to a cluster tool such as the processing system 800 shown in Figure 8. The processing system 800 may include, for example, processing chambers configured for etching, deposition, or any other suitable chambers used for manufacturing the semiconductor device 200.

[0050]

[0076] Figures 2A and 2B illustrate the steps involved in manufacturing the semiconductor device 200 as part of the baseline process. In other words, the processes illustrated in Figures 2A and 2B, and the explanatory processes associated with Figures 2A and 2B, will be understood by those skilled in the art in the field of semiconductor manufacturing.

[0051]

[0077] Referring to Figures 2A-2B, the baseline process includes forming recesses in source / drain regions 204 within a semiconductor substrate 202 having a superlattice structure 210 formed on the upper surface 203 of the semiconductor substrate 202. The source / drain region 204 can be defined by an aspect ratio (the ratio of the depth of the source / drain region 204 to the width of the source / drain region 204). The source / drain region 204 may have any suitable aspect ratio. Next, a protective layer, such as a liner layer 212, is deposited along the superlattice structure 210 up to the upper surface 203. The semiconductor device 200 includes a gate 260 on the superlattice structure 210. In one or more embodiments, the gate 260 includes a gate metal 261 surrounded by a dielectric material 262. In one or more embodiments, the dielectric material 262 is composed of multiple dielectric material layers. The gate metal 261 and the dielectric material 262 may each be composed of any suitable material. In one or more embodiments, the dielectric material 262 and the liner layer 212 are made of the same dielectric material.

[0052]

[0078] The baseline process includes depositing a silicon germanium (SiGe) layer 204A and further including a bottom-up filling process to fill the source / drain region 204. The baseline process includes depositing a capping layer 214 on the silicon germanium (SiGe) layer 204A, followed by etching the semiconductor substrate 202 to remove the liner layer 212.

[0053]

[0079] Method 100 begins with step 110, which includes forming a first liner layer 216 on a semiconductor substrate 202. As will be described in more detail below, the semiconductor substrate 202 includes a source / drain region 204 located below the top surface 203 of the semiconductor substrate 202, and a superlattice structure 210 formed on the top surface 203 of the semiconductor substrate 202. The source / drain region 204 includes a silicon germanium (SiGe) layer 204A filling the source / drain region 204, and a capping layer 214 on the silicon germanium (SiGe) layer 204A. The superlattice structure 210 includes a plurality of first layers 206 of a first material and a plurality of corresponding second layers 208 of a second material, arranged alternately in a plurality of stacked pairs. In step 110, the first liner layer 216 is formed along the plurality of first layers 206 and the plurality of second layers 208.

[0054]

[0080] Method 100 comprises etching the bottom of the first liner layer 216 to form an etched first liner layer 216' (step 120), epitaxially growing a second liner layer 218 along the first liner layer 216 within the superlattice structure 210 (step 130), inverting the semiconductor substrate 202 to expose the back surface 220 of the semiconductor substrate 202 (step 140), and removing the capping layer 214 and the silicon germanium (SiGe) layer 204A to saw the back surface 220. The method further includes etching to form an opening 230 within the source / drain region 204 (step 150), depositing a metal silicide layer 232 on the upper surface of the opening 230 (step 160), depositing a barrier layer 234 along the opening 230 of the source / drain region 204 on the back surface 220 and on the metal silicide layer 232 (step 170), and depositing a metallic material 236 on the barrier layer 234 to fill the opening 230 and form a back contact 250 (step 180). In one or more embodiments, the method 100 consists substantially of steps 110, 120, 130, 140, 150, 160, 170, and 180.

[0055]

[0081] The semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 comprises a semiconductor material (e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof). In one or more embodiments, the semiconductor substrate 202 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). In one or more embodiments, the semiconductor substrate 202 comprises silicon (Si). While some examples of materials that can form a semiconductor substrate 202 are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed is included in the spirit and scope of this disclosure.

[0056]

[0082] The source / drain region 204 includes a silicon germanium (SiGe) layer 204A that fills the source / drain region 204 and a capping layer 214 on the silicon germanium (SiGe) layer 204A. In one or more embodiments, the capping layer 214 includes silicon (SiN).

[0057]

[0083] In some embodiments, the superlattice structure 210 includes a plurality of first layers 206 of a first material and a plurality of corresponding second layers 208 of a second material, arranged alternately in a plurality of stacked pairs. The terms “plural first layers 206” and “plural nanosheet release layers 206” as used herein may be used interchangeably. The terms “plural second layers 208” and “plural nanosheet channel layers 208” as used herein may be used interchangeably.

[0058]

[0084] In some embodiments, the plurality of nanosheet release layers 206 and the plurality of nanosheet channel layers 208 may include any number of pairs of lattice-matched materials suitable for forming a vertically stacked superlattice structure 210. In some embodiments, the superlattice structure 210 has 1 to 5 pairs in which the nanosheet channel layers 208 and nanosheet release layers 206 are stacked alternately.

[0059]

[0085] The nanosheet release layer 206 may have any suitable thickness. In one or more embodiments, each nanosheet release layer 206 has a thickness in the range of 5 nm to 15 nm. The nanosheet channel layer 208 may have any suitable thickness. In one or more embodiments, each nanosheet channel layer 208 has a thickness in the range of 5 nm to 15 nm.

[0060]

[0086] In some embodiments, each of the nanosheet channel layers 208 independently contains silicon (Si). In other words, in one or more embodiments, the second material contains silicon (Si). In some embodiments, each of the nanosheet release layers 206 independently contains silicon germanium (SiGe). In other words, in one or more embodiments, the first material contains silicon germanium (SiGe).

[0061]

[0087] Embodiments of the present disclosure advantageously provide a semiconductor device 200 comprising a fully strained vertically stacked superlattice structure 210 having a second layer 208 (e.g., a nanosheet channel layer 208) that is defect-free or substantially defect-free. In some embodiments, the presence of defects in the nanosheet channel layer 208 is determined by reciprocal space mapping (RSM) methods. Generally, RSM is an X-ray diffraction method that collects diffraction data of a vertically stacked superlattice structure 210 in which the presence of defects may be observed. As used herein, the term “substantially free” means that the nanosheet channel layer 208 is substantially defect-free as determined by RSM methods.

[0062]

[0088] Referring to Figures 1 and 2C-2F, the first liner layer 216 and the second liner layer 218 may each contain any suitable material. In some embodiments, the first liner layer 216 contains silicon (Si) doped with germanium (Ge) in the range of 0 to 60 atomic percent, silicon (Si) doped with phosphorus (P), or silicon germanium (SiGe) doped with boron (B). In some embodiments, the second liner layer 218 contains silicon (Si) doped with germanium (Ge) in the range of 0 to 60 atomic percent, silicon (Si) doped with phosphorus (P), or silicon germanium (SiGe) doped with boron (B).

[0063]

[0089] In some embodiments, the first liner layer 216 has a first dopant concentration, and the second liner layer 218 has a second dopant concentration. In one or more embodiments, the first dopant concentration and the second dopant concentration are the same. In one or more embodiments, the first dopant concentration and the second dopant concentration are different. In one or more embodiments, the second dopant concentration is higher than the first dopant concentration.

[0064]

[0090] Referring to Figures 1 and 2C, in one or more embodiments, in step 110, a first liner layer 216 is grown or deposited along a plurality of first layers 206 and a plurality of second layers 208 using a technique such as (but not limited to) an epitaxial growth process, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0065]

[0091] Referring to Figures 1 and 2D, Method 100 further includes etching the bottom of the first liner layer 216' to form an etched first liner layer 216' (Step 120). The etching process can be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using one or more of ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-cleaning process includes using a ratio of DI:NH4OH in the range of 100:1 to 5:1.

[0066]

[0092] In some embodiments, the pre-cleaning process includes using either SC-1 solution or SC-2 solution. In one or more embodiments, SC-1 solution contains one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, SC-2 solution contains one or more of hydrochloric acid or hydrogen peroxide.

[0067]

[0093] Referring to Figures 1 and 2D, in one or more embodiments, step 130 of method 100 includes epitaxially growing a second liner layer 218 along a first liner layer 216 within a superlattice structure 210 (step 130). The second liner layer 218 is grown or deposited using techniques such as (but not limited to) epitaxial growth processes, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0068]

[0094] In one or more embodiments, step 140 of method 100 includes inverting the semiconductor substrate 202 to expose the back surface 220 of the semiconductor substrate 202 as shown in Figure 2E.

[0069]

[0095] Referring further to Figures 1 and 2E, in one or more embodiments, step 150 of method 100 includes etching to remove the capping layer 214 and the silicon germanium (SiGe) layer 204A, etching the second liner layer 218 to form an etched second liner layer 218', and forming an opening 230 within the source / drain region 204 on the back surface 220. The etching process of step 150 may be the same as or similar to the etching process of step 120.

[0070]

[0096] Referring to Figures 1 and 2F, in one or more embodiments, in step 160, method 100 includes depositing a metal silicide layer 232 on the upper surface of the opening 230. In one or more embodiments, the metal silicide layer 232 is grown or deposited using techniques such as (but not limited to) epitaxial growth processes, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0071]

[0097] The metal silicide layer 232 may contain any suitable metal silicide. In one or more embodiments, the metal silicide layer 232 contains one or more of molybdenum silicide (MoSi), titanium silicide (TiSi), cobalt silicide (CoSi), or nickel silicide (NiSi). The metal silicide layer 232 may have any suitable thickness.

[0072]

[0098] Referring further to Figures 1 and 2F, in one or more embodiments, in step 170, method 100 includes depositing a barrier layer 234 on the back surface 220 and on the metal silicide layer 232 along the opening 230 of the source / drain region 204.

[0073]

[0099] In one or more embodiments, the barrier layer 234 is grown or deposited using techniques such as (but not limited to) epitaxial growth processes, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the barrier layer 234 comprises a metal nitride. The barrier layer 234 may comprise any suitable metal nitride. In one or more embodiments, the barrier layer 234 comprises tantalum nitride (TaN) or titanium nitride (TiN).

[0074]

[0100] Further referring to Figures 1 and 2F, in one or more embodiments, in step 180, method 100 includes depositing a metallic material 236 on the barrier layer 234 to fill the opening 230 and form a back contact 250.

[0075]

[0101] In one or more embodiments, the metallic material 236 is grown or deposited using techniques such as (but not limited to) epitaxial growth processes, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the metallic material 236 is free of seams and / or voids. In one or more embodiments, the metallic material 236 comprises one or more of cobalt (Co), molybdenum (Mo), tungsten (W), nickel (Ni), or ruthenium (Ru).

[0076]

[0102] Method 100 advantageously reduces the contact resistance of the semiconductor device 200 compared to the contact resistance of a semiconductor device comprising only a molybdenum silicide (MoSi) layer.

[0077]

[0103] Figure 3 shows a process flow diagram of Method 300 for forming a semiconductor device (e.g., semiconductor device 400) according to one or more embodiments of the present disclosure. Method 300 is described below with respect to Figures 4A-4F, which show the manufacturing stages of the semiconductor device 400 according to one or more embodiments of the present disclosure. Figures 4A-4F show cross-sectional views of the semiconductor device 400. Method 300 may be part of a multi-stage manufacturing process. Therefore, Method 300 may be an integrated method performed within any suitable processing chamber coupled to a cluster tool such as the processing system 800 shown in Figure 8. The processing system 800 may include, for example, processing chambers configured for etching, deposition, or any other suitable chambers used for manufacturing the semiconductor device 400.

[0078]

[0104] Figures 4A–4B illustrate the steps involved in manufacturing the semiconductor device 400 as part of a baseline process. In other words, the processes illustrated in Figures 4A–4B and described in relation to Figures 4A–4B will be understood by those skilled in the art of semiconductor manufacturing. In some embodiments, the baseline processes shown in Figures 4A–4B are the same as the baseline processes described herein with respect to Figures 2A–2B.

[0079]

[0105] The semiconductor device 400 includes a gate 460 on a superlattice structure 410. In one or more embodiments, the gate 460 includes a gate metal 461 surrounded by a dielectric material 462. In one or more embodiments, the dielectric material 462 is composed of multiple dielectric material layers. The gate metal 461 and the dielectric material 462 may each be composed of any suitable material. In one or more embodiments, the dielectric material 462 and the liner layer 412 are composed of the same dielectric material.

[0080]

[0106] Method 300 begins with step 310, which includes forming a first liner layer 416 and a second liner layer 418 on a semiconductor substrate 402. The semiconductor substrate 402 includes a source / drain region 404 located below the upper surface 403 of the semiconductor substrate 402, and a superlattice structure 410 formed on the upper surface 403 of the semiconductor substrate 402. The source / drain region 404 includes a silicon germanium (SiGe) layer 404A filling the source / drain region 404, and a capping layer 414 on the silicon germanium (SiGe) layer 404A. The superlattice structure 410 includes a plurality of first layers 406 of a first material and a plurality of corresponding second layers 408 of a second material, arranged alternately in a plurality of stacked pairs. In step 310, the first liner layer 416 is formed along a plurality of first layers 406 and a plurality of second layers 408, and the second liner layer 418 is formed within the superlattice structure 410 and along the first liner layer 416.

[0081]

[0107] Method 300 involves inverting the semiconductor substrate 402 to expose the back surface 420 (step 320), etching the bottom of the first liner layer 416 to form an etched first liner layer 416' (step 330), etching to remove the capping layer 414 and the silicon germanium (SiGe) layer 404A to form an opening 430 within the source / drain region 404 of the back surface 420 (step 340), and removing a portion of the etched first liner layer 416' and a portion of the second liner layer 418. The method further includes etching the cavity 435 within the opening 430 to form a second liner layer 418' (step 350), depositing a metal silicide layer 432 on the upper surface of the opening 430 in the source / drain region 404 of the back surface 420 (step 360), depositing a barrier layer 434 along the opening 430 in the source / drain region 404 on the back surface 420 and the metal silicide layer 432 (step 370), and depositing a metallic material 436 on the barrier layer 434 to fill the opening 430 and form a back contact 450 (step 380). In one or more embodiments, the method 300 substantially comprises steps 310, 320, 330, 340, 350, 360, 370, and 380. In one or more embodiments, method 300 comprises steps 310, 320, 330, 340, 350, 360, 370, and 380.

[0082]

[0108] The semiconductor device 400 may have the same or similar components as the semiconductor device 200. For example, in one or more embodiments, the semiconductor substrate 202 may be the same as the semiconductor substrate 402 in the semiconductor device 400.

[0083]

[0109] Referring to Figures 3 and 4C-4F, the first liner layer 416 and the second liner layer 418 may each contain any suitable material. In some embodiments, the first liner layer 416 contains silicon (Si) doped with germanium (Ge) in the range of 0 to 60 atomic percent, silicon (Si) doped with phosphorus (P), or silicon germanium (SiGe) doped with boron (B). In some embodiments, the second liner layer 418 contains silicon (Si) doped with germanium (Ge) in the range of 0 to 60 atomic percent, silicon (Si) doped with phosphorus (P), or silicon germanium (SiGe) doped with boron (B).

[0084]

[0110] In some embodiments, the first liner layer 416 has a first dopant concentration, and the second liner layer 418 has a second dopant concentration. In one or more embodiments, the first dopant concentration and the second dopant concentration are the same. In one or more embodiments, the first dopant concentration and the second dopant concentration are different. In one or more embodiments, the second dopant concentration is higher than the first dopant concentration.

[0085]

[0111] Referring to Figures 3 and 4C-4D, in one or more embodiments, in step 310, a first liner layer 416 and a second liner layer 418 are grown or deposited along a plurality of first layers 406 and a plurality of second layers 408 using techniques such as epitaxial growth, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the first liner layer 416 is formed along a plurality of first layers 406 and a plurality of second layers 408, and the second liner layer 418 is formed within the superlattice structure 410 and along the first liner layer 416. In one or more embodiments, the first liner layer 416 is formed by ALD, and the second liner layer 418 is formed by an epitaxial growth process.

[0086]

[0112] Referring to Figures 3 and 4E, in one or more embodiments, step 320 of method 300 includes inverting the semiconductor substrate 402 to expose the back surface 420 of the semiconductor substrate 402.

[0087]

[0113] Referring further to Figures 3 and 4E, in one or more embodiments, the method 300 includes, in step 330, etching the bottom of the first liner layer 416 to form an etched first liner layer 416'; in step 340, etching to remove the capping layer 414 and the silicon germanium (SiGe) layer 404A to form an opening 430 in the source / drain region 404 of the back surface 420; and in step 350, etching the cavity 435 in the opening 430 to remove a portion of the etched first liner layer 416' and a portion of the second liner layer 418 to form an etched second liner layer 418'.

[0088]

[0114] Advantageously, etching the cavity 435 in step 350 was found to increase the contact interface area by, for example, three times, six times, or nine times. Several embodiments of etching the cavity 435 in step 350 advantageously result in an improvement in contact resistivity of 30% or more, 40% or more, or 50% or more. The amount of etching of the cavity was found to generally correspond to the increase in contact interface area and the amount of contact resistivity. In other words, it was found that reducing the cavity depth by 10 nm (e.g., etching the cavity 435 in step 350) increased the contact interface area by three times, etching the cavity 435 by 20 nm in step 350 increased the contact interface area by six times, and etching the cavity 435 by 30 nm in step 350 increased the contact interface area by nine times. Furthermore, it was found that etching cavity 435 at 3nm in process 350 reduces the contact resistivity by approximately 37%, etching cavity 435 at 6nm in process 350 reduces the contact resistivity by approximately 43%, etching cavity 435 at 11nm in process 350 reduces the contact resistivity by approximately 49%, and etching cavity 435 at 25.5nm in process 350 reduces the contact resistivity by approximately 55%.

[0089]

[0115] The etching processes of steps 330, 340, and 350 may be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes either a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using one or more of ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-cleaning process includes using a ratio of DI:NH4OH in the range of 100:1 to 5:1.

[0090]

[0116] In some embodiments, the pre-cleaning process includes using either SC-1 solution or SC-2 solution. In one or more embodiments, SC-1 solution contains one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In one or more embodiments, SC-2 solution contains one or more of hydrochloric acid or hydrogen peroxide.

[0091]

[0117] The cavity 435 can define any suitable shape within the opening 430. In some embodiments, the cavity 435 defines a non-rectangular shape.

[0092]

[0118] In some embodiments, etching the cavity 435 in step 350 can be completed by multiple different processes or as part of a series of processes.

[0093]

[0119] In one or more embodiments, method 300 further includes performing a contact epitaxial growth process to fill the cavity after etching the cavity in step 350. In one or more embodiments not shown, the contact epitaxial growth process includes a back silicon etching and contact opening step, cavity forming in step 350, hard mask removal step, contact epitaxial growth step, and silicide, liner, and metal filling formation step. Those skilled in the art will be able to implement the appropriate functionality without performing unnecessary experiments by using the descriptions contained herein. In one or more embodiments, the contact epitaxial growth process to fill the cavity after etching the cavity in step 350 reduces the contact resistivity by about 45%.

[0094]

[0120] In one or more embodiments, method 300 further includes repeating step 350 (for example, re-etching the cavity after the contact epitaxial growth process).

[0095]

[0121] In one or more embodiments not shown, the sequence of operations when repeating step 350 includes back silicon etching and contact opening operations, cavity forming in step 350, hard mask removal operations, contact epitaxial growth operations, cavity forming in step 350, and silicide, liner, and metal filling formation operations. Those skilled in the art will be able to achieve the desired functionality without conducting unnecessary experiments by using the descriptions contained herein.

[0096]

[0122] In one or more embodiments, method 300 further includes performing a contact injection process after etching the cavity in step 350.

[0097]

[0123] In one or more embodiments not shown, the contact injection process includes back silicon etching and contact opening operations, cavity forming in step 350, hard mask removal operations, contact injection operations, and silicide, liner, and metal filling formation operations. Those skilled in the art will be able to achieve the desired functionality without conducting unnecessary experiments by using the descriptions contained herein.

[0098]

[0124] In one or more embodiments not shown, method 300 further includes directly depositing a third liner layer onto the upper surface of the cavity.

[0099]

[0125] In one or more embodiments not shown, the process for depositing the third liner layer includes back silicon etching and contact opening operations, cavity forming in step 350, hard mask removal operations, liner-like contact epitaxial growth operations, and silicide, liner, and metal filling formation operations. Those skilled in the art will be able to achieve the desired functionality without unnecessary experimentation by using the descriptions contained herein.

[0100]

[0126] In one or more embodiments, the methods described herein include performing a wrap-around contact process instead of etching the cavity. In a specific embodiment, for example, method 300 includes performing a wrap-around contact process instead of etching the cavity 435 in step 350.

[0101]

[0127] One or more embodiments of the present disclosure include forming a first liner layer 416 along a plurality of first layers 406 and a plurality of second layers 408, and forming a second liner layer 418 along the first liner layer 416 within a superlattice structure 410 (step 310), inverting the semiconductor substrate 402 to expose the back surface 420 of the semiconductor substrate 402 (step 320), etching the bottom of the first liner layer 416 to form an etched first liner layer 416' (step 330), and removing the capping layer 414 and the silicon germanium (SiGe) layer 404A to source / drain the back surface 420. The present invention relates to a method comprising etching to form an opening 430 within a source / drain region 404 (step 340), performing a wrap-around contact process (as further described below), depositing a metal silicide layer 432 on the upper surface of the opening 430 of the source / drain region 404 on the back surface 420 (step 360), depositing a barrier layer 434 along the opening 430 of the source / drain region 404 on the back surface 420 and the metal silicide layer 432 (step 370), and depositing a metallic material 436 on the barrier layer 434 to fill the opening 430 and form a back contact 450 (step 380).

[0102]

[0128] Embodiments in which a method (e.g., Method 300) includes performing a wrap-around contact process instead of etching a cavity will be described below with reference to Figures 7A-7D, which show steps in the manufacture of a semiconductor device 700 according to one or more embodiments of the present disclosure. Figures 7A-7D show cross-sectional views of the semiconductor device 700. The processing system 800 may include processing chambers configured for, for example, etching, deposition, or any other suitable chambers used in the manufacture of the semiconductor device 700.

[0103]

[0129] In one or more embodiments not shown, one or more baseline operations may be performed to process the semiconductor substrate 702. In some embodiments, the baseline process may include, for example, inverting the semiconductor substrate 702 after front-side processing, chemically mechanically polishing (CMP) the semiconductor substrate 702 to shallow trench isolation (STI), depositing a hard mask 770, performing back-side contact patterning and back-side silicon etching, and creating contact openings. Those skilled in the art will be able to understand and perform, without excessive trial and error, how to implement appropriate functions in the baseline process based on the description provided.

[0104]

[0130] Figures 7A to 7D show the manufacturing steps of a semiconductor device 700 having a semiconductor substrate 702. The semiconductor device 700 may have one or more of the same elements as semiconductor devices 200, 400, and 600, which have similar reference numbers. For example, semiconductor device 200 includes a superlattice structure 210, and semiconductor device 700 includes a superlattice structure 710. It will be understood that one or more processing steps used to form semiconductor devices 200, 400, and 600 may also be used to form semiconductor device 700.

[0105]

[0131] The semiconductor substrate 702 includes a superlattice structure 710 on its upper surface 703. The superlattice structure 710 has a plurality of first layers (e.g., nanosheet release layers containing silicon (Si) or silicon germanium (SiGe)) and a corresponding plurality of second layers (e.g., nanosheet channel layers containing silicon (Si) or silicon germanium (SiGe)). The semiconductor device 700 shows a state where the front side processing is complete and it has already been inverted.

[0106]

[0132] The semiconductor device 700 includes a first liner layer 716 and a second liner layer 718 on the first liner layer 716. In one or more embodiments, there are spacer footings 760 that contact the first liner layer 716 and the second liner layer 718, respectively. The spacer footings may include any suitable material known to those skilled in the art. In some embodiments, an opening 730 extends from the top surface 703 of the semiconductor substrate 702 to the bottom surface of the semiconductor substrate 702. In one or more embodiments, the opening 730 extends from the top surface 703 of the semiconductor substrate 702 through the source / drain region of the semiconductor substrate 702 to the bottom surface of the semiconductor substrate 702. In one or more embodiments, a hard mask 770 is deposited on the bottom surface of the semiconductor substrate 702. The hard mask 770 may include any suitable material known to those skilled in the art.

[0107]

[0133] Specific aspects of the wrap-around contact process will not be described in detail to avoid unnecessarily obscuring the embodiments. In one or more embodiments, the wrap-around contact process includes a back-side silicon etching and contact opening process (shown in Figure 7A). In a specific embodiment, Figure 7A shows an opening 730 extending from the top surface 703 of the semiconductor substrate 702, through the source / drain region of the semiconductor substrate 702, to the bottom surface of the semiconductor substrate 702. The opening 730 may be formed by any suitable method known to those skilled in the art. In one or more embodiments, the opening 730 is formed by one or more etching processes disclosed herein.

[0108]

[0134] Figure 7B shows the removal of the spacer footing 760 in contact with each of the first liner layer 716 and the second liner layer 718. The spacer footing 760 can be removed by any suitable method known to those skilled in the art. In one or more embodiments, the spacer footing 760 is removed by one or more etching processes disclosed herein.

[0109]

[0135] Figure 7C shows the removal of the hard mask 770. The hard mask 770 can be removed by any suitable method known to those skilled in the art. In one or more embodiments, the hard mask 770 is removed by an etching process disclosed herein.

[0110]

[0136] Figure 7D illustrates the wrap-around silicide and back contact formation process. In one or more embodiments, a metal silicide layer 732 is deposited on the upper surface of the opening 730 (for example, on the first liner layer 716 and the second liner layer 718, respectively, from which the spacer footing 760 has been removed). In Figure 7D, a barrier layer 734 is deposited along the opening 730 on the metal silicide layer 732, and a metal material 736 is deposited on the barrier layer 734 to fill the opening 730 and form the back contact 750.

[0111]

[0137] Those skilled in the art will be able to implement the appropriate functionality of the wrap-around contact process disclosed herein without excessive experimentation, based on the description and illustrated embodiments contained in Figures 7A-7D.

[0112]

[0138] In one or more embodiments, the method shown in Figures 7A to 7D includes a back-side silicon etching and contact opening operation (Figure 7A), a spacer removal operation (Figure 7B), a hard mask removal operation (Figure 7C), and a wrap-around silicide and back-side contact formation operation (Figure 7D). In one or more embodiments, the method shown in Figures 7A to 7D consists substantially of a back-side silicon etching and contact opening operation (Figure 7A), a spacer removal operation (Figure 7B), a hard mask removal operation (Figure 7C), and a wrap-around silicide and back-side contact formation operation (Figure 7D). In one or more embodiments, the method shown in Figures 7A to 7D consists of a back-side silicon etching and contact opening operation (Figure 7A), a spacer removal operation (Figure 7B), a hard mask removal operation (Figure 7C), and a wrap-around silicide and back-side contact formation operation (Figure 7D).

[0113]

[0139] Advantageously, the wrap-around contact process has been found to significantly improve resistivity by more than 10% compared to conventional back-side contact processes, such as those involving the deposition of a molybdenum silicide (MoSi) layer alone. The wrap-around contact process of this disclosure advantageously reduces current concentration, leading to improved source / drain epitaxial layer resistance (S / D epi resistance). Furthermore, the wrap-around contact process of this disclosure advantageously increases contact area, leading to improved contact resistance.

[0114]

[0140] Referring again to Figures 3 and 4F, in one or more embodiments, in step 360, method 300 includes depositing a metal silicide layer 432 on the upper surface of the opening 430 (e.g., the upper surface of the formed cavity 435). In one or more embodiments, the metal silicide layer 432 is grown or deposited using techniques such as (but not limited to) an epitaxial growth process, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0115]

[0141] The metal silicide layer 432 may contain any suitable metal silicide. In one or more embodiments, the metal silicide layer 432 contains one or more of molybdenum silicide (MoSi), titanium silicide (TiSi), cobalt silicide (CoSi), or nickel silicide (NiSi). The metal silicide layer 432 may have any suitable thickness.

[0116]

[0142] In Figures 3 and 4F, in one or more embodiments, step 370 includes depositing a barrier layer 434 on the back surface 420 and on the metal silicide layer 432 along the opening 430 of the source / drain region 404.

[0117]

[0143] In one or more embodiments, the barrier layer 434 is grown or deposited using techniques such as (but not limited to) epitaxial growth processes, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the barrier layer 434 comprises a metal nitride.

[0118]

[0144] In Figures 3 and 4F, in one or more embodiments, step 380 includes depositing a metallic material 436 on a barrier layer 434 to fill the opening 430 and form a back contact 450.

[0119]

[0145] In one or more embodiments, the metallic material 436 is grown or deposited using techniques such as (but not limited to) epitaxial growth processes, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the metallic material 436 is free of seams and / or voids. In one or more embodiments, the metallic material 436 comprises one or more of cobalt (Co), molybdenum (Mo), tungsten (W), nickel (Ni), or ruthenium (Ru).

[0120]

[0146] Method 300 advantageously reduces the contact resistance of semiconductor device 400 compared to semiconductor device containing only a molybdenum silicide (MoSi) layer.

[0121]

[0147] Figure 5 shows a process flow diagram of Method 500 for forming a semiconductor device (e.g., semiconductor device 600) according to one or more embodiments of the present disclosure. Method 500 is described below with respect to Figures 6A-6G, which show the manufacturing steps of the semiconductor device 600 according to one or more embodiments of the present disclosure. Figures 6A-6G show cross-sectional views of the semiconductor device 600. Method 500 may be part of a multi-stage manufacturing process. Therefore, Method 500 may be an integrated method performed within any suitable processing chamber coupled to a cluster tool such as the processing system 800 shown in Figure 8. The processing system 800 may include, for example, processing chambers configured for etching, deposition, or any other suitable chambers used for manufacturing the semiconductor device 600.

[0122]

[0148] Figures 6A–6B illustrate the steps involved in manufacturing the semiconductor device 600 as part of a baseline process. In other words, the processes illustrated in and associated with Figures 6A–6B will be understood by those skilled in the art of semiconductor manufacturing. In some embodiments, the baseline processes shown in Figures 6A–6B are the same as the baseline processes described herein with respect to Figures 2A–2B.

[0123]

[0149] The semiconductor device 600 includes a gate 660 on a superlattice structure 610. In one or more embodiments, the gate 660 includes a gate metal 661 surrounded by a dielectric material 662. In one or more embodiments, the dielectric material 662 is composed of multiple dielectric material layers. The gate metal 661 and the dielectric material 662 may each be composed of any suitable material. In one or more embodiments, the dielectric material 662 and the liner layer 612 are composed of the same dielectric material.

[0124]

[0150] Method 500 begins with step 510, which includes forming a first liner layer 616 and a second liner layer 618 on a semiconductor substrate 602. As will be described in more detail below, the semiconductor substrate 602 includes a source / drain region 604 below the top surface 603 of the semiconductor substrate 602 and a superlattice structure 610 formed on the top surface 603 of the semiconductor substrate 602. The source / drain region 604 includes a silicon germanium (SiGe) layer 604A filling the source / drain region 604 and a capping layer 614 on the silicon germanium (SiGe) layer 604A. The superlattice structure 610 includes a plurality of first layers 606 of a first material and a plurality of corresponding second layers 608 of a second material, arranged alternately in a plurality of stacked pairs. In step 510, the first liner layer 616 is formed along a plurality of first layers 606 and a plurality of second layers 608, and the second liner layer 618 is formed within the superlattice structure 610 and along the first liner layer 616.

[0125]

[0151] Method 500 comprises inverting the semiconductor substrate 602 to expose the back surface 620 of the semiconductor substrate 602 (step 520), selectively removing the silicon germanium (SiGe) layer 604A to form an opening 630 within the source / drain region 604 on the back surface 620 (step 530), and depositing a third liner layer 619 within the opening 630 (step 540). The process further includes punch-through etching a portion of each of the third liner layer 619, the capping layer 614, the first liner layer 616, and the second liner layer 618 to form a concave source / drain region 604', wherein the concave source / drain region 604' has an upper portion within the superlattice structure 610 that is above the upper surface 603 of the semiconductor substrate 602, and a bottom portion within the semiconductor substrate 602 that is below the upper surface 603 of the semiconductor substrate 602, and punch-through etching a portion of each of these portions (step 550), depositing a metal silicide layer 632 on the upper surface of the upper portion of the concave source / drain region 604' (step 560), depositing a barrier layer 634 on the bottom portion of the concave source / drain region 604' on the third liner layer 619 (step 570), and depositing a metallic material 636 in the opening 630 to form a back contact 650 (step 580). In one or more embodiments, method 500 substantially comprises steps 510, 520, 530, 540, 550, 560, 570, and 580.

[0126]

[0152] The semiconductor device 600 may have the same or similar components as the semiconductor device 200 and / or the semiconductor device 400. For example, in one or more embodiments, the semiconductor substrate 202 and / or the semiconductor substrate 402 may be the same as the semiconductor substrate 602 in the semiconductor device 600.

[0127]

[0153] Referring to Figures 5 and 6C-6G, the first liner layer 616 and the second liner layer 618 may each contain any suitable material. In some embodiments, the first liner layer 616 contains silicon (Si) doped with germanium (Ge) in the range of 0 to 60 atomic percent, silicon (Si) doped with phosphorus (P), or silicon germanium (SiGe) doped with boron (B). In some embodiments, the second liner layer 618 contains silicon (Si) doped with germanium (Ge) in the range of 0 to 60 atomic percent, silicon (Si) doped with phosphorus (P), or silicon germanium (SiGe) doped with boron (B).

[0128]

[0154] In some embodiments, the first liner layer 616 has a first dopant concentration, and the second liner layer 618 has a second dopant concentration. In one or more embodiments, the first dopant concentration and the second dopant concentration are the same. In one or more embodiments, the first dopant concentration and the second dopant concentration are different. In one or more embodiments, the second dopant concentration is higher than the first dopant concentration.

[0129]

[0155] Referring to Figures 5 and 6C-6D, in one or more embodiments, in step 510, a first liner layer 616 and a second liner layer 618 are grown or deposited along a plurality of first layers 606 and a plurality of second layers 608 using techniques such as epitaxial growth, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the first liner layer 616 is formed along a plurality of first layers 606 and a plurality of second layers 608, and the second liner layer 618 is formed within the superlattice structure 610 and along the first liner layer 616. In one or more embodiments, the first liner layer 616 is formed by ALD, and the second liner layer 618 is formed by an epitaxial growth process.

[0130]

[0156] Referring to Figures 5 and 6E, in one or more embodiments, Method 500 includes inverting the semiconductor substrate 602 to expose the back surface 620 of the semiconductor substrate 602 (Step 320) and selectively removing the silicon germanium (SiGe) layer 604A to form an opening 630 within the source / drain region 604 on the back surface 620 (Step 330). According to one or more embodiments, the silicon germanium (SiGe) layer 604A may be selectively removed using any suitable process to form an opening 630 within the source / drain region 604 on the back surface 620.

[0131]

[0157] Referring further to Figures 5 and 6E, in one or more embodiments, Method 500 includes depositing a third liner layer 619 within the opening 630 using a technique such as (but not limited to) an epitaxial growth process, ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In one or more embodiments, the third liner layer 619 is formed along the sidewalls of the opening 630 and does not fill the opening. In one or more embodiments, the third liner layer 619 is deposited by ALD. In one or more embodiments, the third liner layer 619 includes a dielectric material. The third liner layer 619 may include any suitable dielectric material used to protect the semiconductor substrate 202. In some embodiments, the third liner layer 619 comprises one or more of silicon nitride (SiN), silicon oxide (SiOx), silicon carbide (SiC), silicon oxycarbide (SiOC), or silicon oxycarbonite (SiOCN).

[0132]

[0158] Referring to Figures 5 and 6F, in one or more embodiments, method 500 includes punch-through etching of portions of each of the third liner layer 619, the capping layer 614, the first liner layer 616, and the second liner layer 618 to form a concave source / drain region 604'. In one or more embodiments, as a result of punch-through etching, the concave source / drain region 604' includes an etched third liner layer 619', an etched capping layer 614', an etched first liner layer 616', and an etched second liner layer 618'. In one or more embodiments, as a result of punch-through etching, the concave source / drain region 604' has an upper portion within the superlattice structure 610 and above the upper surface 603 of the semiconductor substrate 602, and a lower portion within the semiconductor substrate 602 and below the upper surface 603 of the semiconductor substrate 602.

[0133]

[0159] The source / drain region 604 can be defined by its aspect ratio (the ratio of the depth of the source / drain region 604 to the width of the source / drain region 604). The source / drain region 604 may have any suitable aspect ratio.

[0134]

[0160] In one or more embodiments, the concave source / drain region 604' includes an aspect ratio greater than the aspect ratio of the source / drain region 604. In one or more embodiments, the concave source / drain region 604' has a depth greater than the depth of the source / drain region 604. In one or more embodiments, the concave source / drain region 604' has a width greater than the width of the source / drain region 604.

[0135]

[0161] In one or more embodiments, the concave source / drain region 604' has a depth and width greater than the respective depth and width of the source / drain region 604.

[0136]

[0162] Referring to Figures 5 and 6G, Method 500 includes depositing a metal silicide layer 632 on the upper surface of the concave source / drain region 604' (Step 560), depositing a barrier layer 634 on the bottom of the concave source / drain region 604' on the third liner layer 619 (Step 570), and depositing a metallic material 636 in the opening 630 to form a back contact 650 (Step 580).

[0137]

[0163] In one or more embodiments, a portion of the metal silicide layer 632 is in contact with a portion of the barrier layer 634. In one or more embodiments, the metal silicide layer 632 is formed on the upper part of the concave source / drain region 604', and the barrier layer 634 is formed on the bottom of the concave source / drain region 604'. In one or more embodiments, the metal silicide layer 632 is formed over the entire upper part of the concave source / drain region 604', and the barrier layer 634 is formed over the entire bottom of the concave source / drain region 604'.

[0138]

[0164] Method 500 advantageously reduces the contact resistance of semiconductor device 600 compared to semiconductor device containing only a molybdenum silicide (MoSi) layer.

[0139]

[0165] Figure 8 shows a schematic top view of one example of a multi-chamber processing system 800, according to several examples of the present disclosure. The terms “multi-chamber processing system 800” and “processing system 800” as used herein may be used interchangeably. The processing system 800 generally includes a factory interface 802, load lock chambers 804, 806, transfer chambers 808, 810 with their respective transfer robots 812, 814, holding chambers 816, 818, and processing chambers 820, 822, 824, 826, 828, 830. As described in detail herein, wafers (e.g., semiconductor substrates) within the processing system 800 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 800 (e.g., the atmospheric environment that may exist in a semiconductor manufacturing plant). For example, wafers can be processed in various chambers and transferred between various chambers at low pressure (e.g., approximately 300 Torr or less) or in a vacuum environment without disrupting the low pressure or vacuum environment during the various processes performed on the wafers within the processing system 800. Thus, the processing system 800 can provide an integrated solution for several processing steps of a wafer.

[0140]

[0166] Existing processing systems may be suitably modified in accordance with the teachings provided herein and / or adapted to benefit from the embodiments described herein.

[0141]

[0167] In the example shown in Figure 8, the factory interface 802 includes a docking station 840 and a factory interface robot 842 to facilitate wafer transfer. The docking station 840 is configured to receive one or more forward-opening unified pods (FOUPs) 844. In some examples, each factory interface robot 842 generally includes a blade 848 located at one end of the factory interface robot 842, configured to transfer wafers from the factory interface 802 to load lock chambers 804, 806.

[0142]

[0168] Load lock chambers 804 and 806 have ports 850 and 852, respectively, connected to the factory interface 802, and ports 854 and 856, respectively, connected to the transfer chamber 808. The transfer chamber 808 further has ports 858 and 860, respectively, connected to the holding chambers 816 and 818, and ports 862 and 864, respectively, connected to the processing chambers 820 and 822. Similarly, the transfer chamber 810 has ports 866 and 868, respectively, connected to the holding chambers 816 and 818, and ports 870, 872, 874, and 876, respectively, connected to the processing chambers 824, 826, 828, and 830. Ports 854, 856, 858, 860, 862, 864, 866, 868, 870, 872, 874, and 876 may be slit valve openings equipped with slit valves to allow wafers to pass through, for example, by transfer robots 812 and 814, and to provide a seal between each chamber to prevent gas from passing between them. Generally, any port is open for wafer transfer; otherwise, the port is closed.

[0143]

[0169] The load lock chambers 804, 806, transfer chambers 808, 810, holding chambers 816, 818, and processing chambers 820, 822, 824, 826, 828, 830 may be in fluid communication with a gas and pressure control system (not shown in particular). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and conduits that provide fluid communication to the various chambers. During operation, the factory interface robot 842 transfers wafers from FOUP 844 through port 850 or 852 to the load lock chamber 804 or 806. The gas and pressure control system then pumps down the load lock chamber 804 or 806. The gas and pressure control system further maintains the transfer chambers 808, 810 and the holding chambers 816, 818 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 804 or 806 facilitates the passage of the wafer between, for example, the atmospheric environment of the factory interface 802 and the low-pressure or vacuum environment of the transfer chamber 808.

[0144]

[0170] With the wafer in the pumped-down load lock chamber 804 or 806, the transfer robot 812 transfers the wafer from the load lock chamber 804 or 806 to the transfer chamber 808 through port 854 or 856. The transfer robot 812 can then transfer the wafer to one of the processing chambers 820 or 822 through their respective ports 862 or 864 for processing, and to the holding chambers 816 or 818 through their respective ports 858 or 860 for holding awaiting further transfers. Similarly, the transfer robot 814 can access the wafer in the holding chamber 816 or 818 through port 866 or 868 and transfer the wafer to one of the processing chambers 824, 826, 828 or 830 for processing, and / or between them through their respective ports 870, 872, 874 or 876, and transfer the wafer to the holding chambers 816 or 818 through their respective ports 866 or 868 for holding awaiting further transfers. Wafer transfer and holding within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0145]

[0171] Processing chambers 820, 822, 824, 826, 828, and 830 can be any suitable chamber for processing wafers. In some embodiments, processing chamber 820 can perform an annealing process, processing chamber 822 can perform a cleaning process, and processing chambers 824, 826, 828, and 830 can perform epitaxial growth processes. In some examples, processing chamber 822 can perform a cleaning process (e.g., a pre-cleaning process), processing chamber 820 can perform an etching process, and processing chambers 824, 826, 828, and 830 can perform their respective epitaxial growth processes.

[0146]

[0172] The system controller 890 is coupled to the processing system 800 to control the processing system 800 or its components. For example, the system controller 890 can control the operation of the processing system 800 by using direct control of the chambers 804, 806, 808, 816, 818, 810, 820, 822, 824, 826, 828, and 830 of the processing system 800, or by controlling controllers associated with the chambers 804, 806, 808, 816, 818, 810, 820, 822, 824, 826, 828, and 830. During operation, the system controller 890 enables data collection and feedback from each chamber to adjust the performance of the processing system 800.

[0147]

[0173] The system controller 890 generally includes a central processing unit (CPU) 892, memory 894, and support circuitry 896. The CPU 892 may be one of any form of general-purpose processor available for use in an industrial environment. Memory 894, or non-temporary computer-readable media, is accessible by the CPU 892 and may be one or more memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or other forms of local or remote digital storage. Support circuitry 896 is coupled to the CPU 892 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Various methods disclosed herein can generally be implemented by the CPU 892 executing computer instruction code, for example, stored in memory 894 (or memory of a particular processing chamber) as a software routine, under the control of the CPU 892. Once the computer instruction code is executed by the CPU 892, the CPU 892 controls the chamber to perform processing according to various methods.

[0148]

[0174] Embodiments of this disclosure relate to a non-transient, computer-readable medium that, when executed by a controller of a processing chamber (e.g., a controller 890 of a processing system 800), causes a processing chamber (or processing system) to perform any of the operations described herein. In some embodiments, the controller 890 causes the processing system 800 to perform one or more operations of method 100. In some embodiments, the controller 890 causes the processing system 800 to perform one or more operations of method 300. In some embodiments, the controller 890 causes the processing system 800 to perform one or more operations of method 500. In some embodiments, the controller 890 causes the processing system 800 to perform one or more operations of the methods shown in Figures 7A to 7D.

[0149]

[0175] Other processing systems can also have other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 808, 810 and holding chambers 816, 818. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device within the processing system.

[0150]

[0176] While the disclosures herein have been described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and uses of the disclosure. It will be apparent to those skilled in the art that various modifications and changes can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and changes that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, wherein the method is The present invention relates to forming a first liner layer on a semiconductor substrate, wherein the semiconductor substrate includes a source / drain region below the upper surface of the semiconductor substrate and includes a superlattice structure formed on the upper surface of the semiconductor substrate, the source / drain region includes a silicon germanium (SiGe) layer filling the source / drain region and a capping layer on the silicon germanium (SiGe) layer, the superlattice structure includes a plurality of first layers of a first material arranged alternately in a plurality of stacked pairs and a plurality of second layers of a corresponding second material, and the first liner layer is formed along the plurality of first layers and the plurality of second layers. To form an etched first liner layer, the bottom of the first liner layer is etched, Within the superlattice structure, the second liner layer is epitaxially grown along the etched first liner layer, In order to expose the back surface of the semiconductor substrate, the semiconductor substrate is inverted, Etching is performed to remove the capping layer and the silicon germanium (SiGe) layer and to form an opening in the source / drain region of the back surface. A metal silicide layer is deposited on the upper surface of the opening, A barrier layer is deposited along the opening in the source / drain region on the back surface and the metal silicide layer, In order to fill the opening and form back-side contact, a metal material is deposited on the barrier layer. Methods that include...

2. The method according to claim 1, which reduces the contact resistance of a semiconductor device compared to the contact resistance of a semiconductor device comprising only a molybdenum silicide (MoSi) layer.

3. The method according to claim 1, wherein the first material comprises silicon germanium (SiGe) and the second material comprises silicon (Si).

4. The method according to claim 1, wherein the first liner layer has a first dopant concentration, and the second liner layer has a second dopant concentration, the second dopant concentration being higher than the first dopant concentration.

5. The method according to claim 4, wherein each of the first liner layer and the second liner layer comprises germanium (Ge)-doped silicon (Si), phosphorus (P)-doped silicon (Si), or boron (B)-doped silicon germanium (SiGe).

6. The method according to claim 1, wherein the capping layer comprises silicon (Si).

7. The method according to claim 1, wherein the method is an integrated method performed within a cluster tool.

8. A method for forming a semiconductor device, wherein the method is The present invention relates to forming a first liner layer and a second liner layer on a semiconductor substrate, wherein the semiconductor substrate includes a source / drain region below the upper surface of the semiconductor substrate and includes a superlattice structure formed on the upper surface of the semiconductor substrate, the source / drain region includes a silicon germanium (SiGe) layer filling the source / drain region and a capping layer on the silicon germanium (SiGe) layer, the superlattice structure includes a plurality of first layers of a first material arranged alternately in a plurality of stacked pairs and a plurality of second layers of a corresponding second material, the first liner layer is formed along the plurality of first layers and the plurality of second layers, and the second liner layer is formed within the superlattice structure and along the first liner layer, thereby forming the first liner layer and the second liner layer. In order to expose the back surface of the semiconductor substrate, the semiconductor substrate is inverted, To form an etched first liner layer, the bottom of the first liner layer is etched, Etching is performed to remove the capping layer and the silicon germanium (SiGe) layer and to form an opening in the source / drain region of the back surface. To remove a portion of the etched first liner layer and a portion of the second liner layer and form an etched second liner layer, the cavity in the opening is etched, A metal silicide layer is deposited on the upper surface of the opening in the source / drain region of the back side, A barrier layer is deposited along the opening in the source / drain region on the back surface and the metal silicide layer, In order to fill the opening and form back-side contact, a metal material is deposited on the barrier layer. Methods that include...

9. The method according to claim 8, wherein each of the first liner layer and the second liner layer comprises germanium (Ge)-doped silicon (Si), phosphorus (P)-doped silicon (Si), or boron (B)-doped silicon germanium (SiGe).

10. The method according to claim 8, wherein the capping layer comprises silicon (Si).

11. The method according to claim 8, wherein the cavity defines a non-rectangular shape.

12. The method according to claim 8, further comprising performing a contact epitaxial growth process to fill the cavity after etching the cavity.

13. The method according to claim 8, further comprising performing a contact injection process after etching the cavity.

14. The method according to claim 8, further comprising depositing a third liner layer directly onto the upper surface of the cavity.

15. The method according to claim 12, further comprising etching the cavity after the contact epitaxial growth process.

16. The method according to claim 8, wherein the method is an integrated method performed within a cluster tool.

17. A method for forming a semiconductor device, wherein the method is The present invention relates to forming a first liner layer and a second liner layer on a semiconductor substrate, wherein the semiconductor substrate includes a source / drain region below the upper surface of the semiconductor substrate and includes a superlattice structure formed on the upper surface of the semiconductor substrate, the source / drain region includes a silicon germanium (SiGe) layer filling the source / drain region and a capping layer on the silicon germanium (SiGe) layer, the superlattice structure includes a plurality of first layers of a first material arranged alternately in a plurality of stacked pairs and a plurality of second layers of a corresponding second material, the first liner layer is formed along the plurality of first layers and the plurality of second layers, and the second liner layer is formed within the superlattice structure and along the first liner layer, thereby forming the first liner layer and the second liner layer. In order to expose the back surface of the semiconductor substrate, the semiconductor substrate is inverted, In order to form an opening in the source / drain region on the back surface, the silicon germanium (SiGe) layer is selectively removed, A third liner layer is deposited in the aforementioned opening, To form a concave source / drain region, punch-through etching is performed on a portion of each of the third liner layer, the capping layer, the first liner layer, and the second liner layer, wherein the concave source / drain region has an upper portion within the superlattice structure that is above the upper surface of the semiconductor substrate, and a lower portion within the semiconductor substrate that is below the upper surface of the semiconductor substrate, and punch-through etching is performed on a portion of each of these portions. A metal silicide layer is deposited on the upper surface of the upper part of the concave source / drain region, Depositing a barrier layer at the bottom of the concave source / drain region on the third liner layer, In order to form back-side contact, a metal material is deposited in the opening and Methods that include...

18. The method according to claim 17, wherein each of the first liner layer and the second liner layer comprises germanium (Ge)-doped silicon (Si), phosphorus (P)-doped silicon (Si), or boron (B)-doped silicon germanium (SiGe).

19. The method according to claim 17, wherein the capping layer comprises silicon (Si).

20. The method according to claim 17, wherein the third liner layer includes a dielectric material.

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