Doping profile for reduced floating body effect in 4F2 DRAM

Abstract

This technology includes a vertical cell array transistor (VCAAT) with improved floating body effect. The array includes one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The array includes one or more channels extending vertically substantially orthogonal to the first and second horizontal directions such that the bit lines intersect the source / drain regions of the multiple channels and the word lines intersect the gate regions of the multiple channels. The array includes a case where the source / drain region has a first section adjacent to the source / drain junction and a second section adjacent to the channel body, and the first section has a higher doping concentration than the second section.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application is a copy of the "DOPING PROFILE FOR REDUCED FLOATING BODY EFFECT IN 4F" filed on October 12, 2023. 2 We claim the interests and priority of U.S. Patent Application No. 63 / 589,920, entitled “DRAM,” which is incorporated herein by reference in its entirety.

[0002]

[0002] This disclosure generally refers to 4F 2 This disclosure describes the design of a dynamic random access memory array. More specifically, this disclosure describes a 4F array with reduced floating body effects and improved threshold voltage stability. 2 Let's discuss memory arrays. [Background technology]

[0003]

[0003] Advances in computing technology have made computing devices smaller and increased their processing power. Therefore, it is necessary to increase storage and memory to meet the programming and computing needs of the devices. By increasing the number of storage units with smaller form factors, miniaturization of devices with increased storage capacity can be achieved.

[0004]

[0004] Dynamic random access memory (DRAM) architectures have been shrinking over time. For example, a one-transistor, one-capacitor (1T-1C) DRAM cell architecture is 8F 2 Sizes up to 6F 2 We successfully reduced the size to 6F (where F is the minimum feature size). 2 From 4th floor 2 Further design scheme modifications could help improve area density. 4F 2In the DRAM method, the storage node (capacitor) and the bit line are located at the top and bottom of the vertical cell transistor, and the channel remains completely separated from the body. With this configuration, due to the body connection of the channel, the floating body effect that does not pose a problem in the current 8F 2 or 6F 2 DRAM cell architecture becomes a major technical issue for 4F 2 DRAM. Therefore, improvement in this technical field is necessary.

Summary of the Invention

[0005]

[0005] This technology generally relates to vertical cell array transistors (VCATs) and methods of forming such devices. The transistor includes one or more bit lines arranged in a first horizontal direction, one or more word lines arranged in a second horizontal direction, and one or more channels extending in a vertical direction. The transistor includes cases where the vertical direction is generally orthogonal to the first horizontal direction and the second horizontal direction such that one or more bit lines intersect the source / drain regions of one or more channels and one or more word lines intersect the gate regions of one or more channels. The transistor includes cases where the source / drain region includes a first section adjacent to the source / drain junction and a second section adjacent to the channel body, and the first section has a doping concentration higher than that of the second section.

[0006]

[0006] In an embodiment, the doping concentration of the source / drain region exhibits a Gaussian (normal) distribution having a peak concentration approximately at the source / drain junction. In more embodiments, the doping concentration of the first section is about two times or more higher than that of the second section. Further, in an embodiment, the doping concentration of the first section is greater than 1×10 19 cm 3 . In more embodiments, the doping concentration of the first section is 4×10 19 cm -3It exceeds. In addition or alternatively, in the embodiment, the doping concentration of the second section is about 1 × 10 19 cm -3 The following applies: In further embodiments, the channel further includes one or more p-type doped regions. Embodiments include cases where the channel has a height extending between a source / drain region and a second source / drain region, and one or more p-type doped regions are formed at a height of about 20% to about 80% of the channel height. In many more embodiments, one or more p-type doped regions are about 5 × 10 16 cm -3 The above ~ approximately 1 x 10 20 cm -3 The doping concentration is shown. Furthermore, in the embodiment, the channel has a height extending between the source / drain region and the second source / drain region, and one or more p-type doped regions have a thickness of about 5% to about 30% of the channel height.

[0007]

[0007] The technology also generally applies to vertical cell array transistors (VCATs). A transistor includes a plurality of bit lines arranged in a first horizontal direction, a plurality of word lines arranged in a second horizontal direction, and a plurality of channels extending vertically from a first source / drain region to a second source / drain region. The transistor includes cases where the vertical direction is substantially orthogonal to the first and second horizontal directions such that the plurality of bit lines intersect the first and / or second source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels. The transistor also includes cases where at least a portion of the plurality of channels includes one or more p-type doped regions located between the first source / drain region and the second source / drain region.

[0008]

[0008] In embodiments, at least a portion of the multiple channels have a height extending between the first source / drain region and the second source / drain region, and one or more p-type doped regions are formed at a height of about 20% to about 80% of the channel height. In more embodiments, the transistor further includes at least a second p-type doped region of one or more p-type doped regions. Furthermore, in embodiments, one or more p-type doped regions are about 5 × 10 16 cm -3 The above ~ approximately 1 x 10 20 cm -3 This indicates the doping concentration. In yet another embodiment, the channel has a height extending between a first source / drain region and a second source / drain region, and one or more p-type doped regions have a thickness of about 5% to about 30% of the channel height.

[0009]

[0009] The technology also generally covers methods for forming vertical cell array transistors (VCATs). The method includes etching a substrate to form one or more shallow trench isolations (STIs) and a plurality of vertically extending channels. The method includes contacting one or more of the plurality of vertically extending channels with one or more ion implanters to form a first source / drain region. The method includes forming a p-type doped region along one or more of the plurality of vertically extending channels and forming a second source / drain region. The method includes the case where the first source / drain region includes a first section adjacent to the source / drain junction and a second section adjacent to the channel body, and the first section has a higher doping concentration than the second section.

[0010]

[0010] In some embodiments, the p-type doped region is formed using a second ion implanter. In more embodiments, the method includes annealing one or more ion implanters and / or a second ion implanter. In further embodiments, the method includes etching a portion of one or more channels of a plurality of channels and forming a p-type doped region within the etched portion. In further embodiments, forming includes epitaxial growth of the p-type doped region.

[0011]

[0011] Such technologies can offer numerous advantages over conventional systems and techniques. For example, the processes and systems can reduce the floating body effect and reduce threshold voltage degradation over time. Furthermore, the processes and systems can significantly improve gate-induced drain leakage by, for example, resulting in a gradual change in the potential of the storage node contacts in one or more source / drain regions compared to the channel potential. These embodiments and other embodiments, along with their many advantages and features, are described in detail in the following description and accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1A] This shows a top view of an exemplary processing chamber according to an embodiment of this technology. [Figure 1B] This shows the top view of a conventional 4F2 memory array. [Figure 1C] This is a perspective view of a conventional 4F2 memory array. [Figure 2] The selected steps in the formation method according to the embodiment of this technology are shown. [Figure 3A] This shows a perspective view of a semiconductor structure according to an embodiment of this technology, which has dielectric material filling after STI formation. [Figure 3B] A perspective view of a semiconductor structure according to an embodiment of this technology, patterned for the formation of a second STI, is shown. [Figure 3C] A perspective view of a semiconductor structure according to an embodiment of this technology, having a gate oxide and a low work function material deposited word line separation area, is shown. [Figure 3D] A perspective view of a semiconductor structure according to an embodiment of this technology having doped source / drain regions is shown. [Figure 4A] A cross-sectional view of the joint according to an embodiment of this technology is shown. [Figure 4B] A cross-sectional view of the joint according to an embodiment of this technology is shown. [Modes for carrying out the invention]

[0014]

[0023] Some drawings are included as schematic diagrams. These diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0015]

[0024] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0016]

[0025] Traditionally, DRAM chip bit density has increased by approximately 25% from node to node. However, the increase in bit density between nodes has decreased to nearly 20% in more recent generations, mainly due to challenges associated with scaling the cell area. The cell design architecture for the latest DRAM technology is 6F 2Based on shape dimensions, "F" is the minimum feature size of a given technology node. 6F 2 From 4th floor 2 Switching to the cell architecture could result in a 33% increase in bit density at the same technology node. Furthermore, 4F 2 The patterning difficulty of DRAM is 6F 2 This is significantly reduced compared to 4F. 2 In the DRAM system, the capacitor and bit line are 6F 2 This is due to the fact that they are located at the two ends of the vertical cell transistors, rather than being tightly packed on the same side as the DRAM.

[0017]

[0026] However, 4F 2 DRAM design has its own challenges. For example, 4F 2 In memory cells, transistor channels are placed between the bit lines and the capacitor layer, and there is no common substrate remaining to connect the channels, resulting in a floating body effect in these transistors. For example, in conventional 4F 2 DRAM access devices are thought to exhibit off-leak current problems. Off-leak current is caused by the floating body effect (e.g., 4F due to isolated channels). 2 This is due to the accumulation of holes in the body of the DRAM device. Electron-hole pairs can be formed within the semiconductor channel by interband tunneling. Electrons can flow into the n-type source or drain region of the transistor, but holes cannot. 4F without substrate connection 2In DRAM devices, holes have no path to leave the channel and continue to accumulate. Therefore, the floating body effect can lead to channel activation without gate activation, which ultimately translates into leakage current from the capacitor or the data storage side of the device, as well as a degradation of the threshold voltage over time. Attempts have been made to provide body connections using embedded body connection methods. However, such attempts can result in gate overlap at the source / drain junction edge, leading to undesirable gate-induced drain leakage or limitations on scalability to small dimensions. Furthermore, such design schemes also make it possible to manufacture high aspect ratio structures that challenge existing doping techniques.

[0018]

[0027] At least partially due to the stray body effect, vertical channel access array transistors (VCAATs) are susceptible to increased leakage current values, such as gate-induced drain leakage. This phenomenon can further exacerbate the stray body effect. For example, continued hole accumulation can lead to charge buildup on the bit line, potentially lowering the potential between the channel and the storage node. This can allow for increased interband tunneling and further lower the threshold voltage of the access transistor.

[0019]

[0028] This technology overcomes these and other problems by providing a source / drain doping profile that reduces the rate of change of the storage node contact potential in one or more source / drain regions. Specifically, by carefully controlling the doping profile of one or more source / drain regions, the barrier between the channel potential and the storage node contact potential can be increased. Since interband tunneling is exponentially related to barrier thickness, the systems and devices described herein may significantly reduce interband tunneling and, consequently, the stray body effect. Furthermore, this technology has found that by carefully forming one or more sinks within the channel region, holes can be further dissipated and the stray body effect can be further improved. Thus, unlike conventional attempts, this technology can provide a word line that maintains the threshold voltage required for low off-current leakage while reducing gate-induced drain leakage and, even, the stray body effect of vertical channel access array transistors (VCAATs).

[0020]

[0029] In the remaining disclosures, 4F 2 While this disclosure routinely identifies specific deposition and etching processes used for forming vertical cell-access array transistors (VCAATs) such as DRAM devices, it will be readily apparent that the systems and methods are equally applicable to gate-all-around and Schottky barrier VCAATs, other devices suffering from the floating-body effect, and processes for forming such devices. Therefore, this technology should not be considered limited to use in these specific devices or systems alone. Before describing additional modifications and adjustments to this device according to embodiments of this technology, this disclosure describes a possible semiconductor device, which may include one or more components, using one or more word lines according to embodiments of this technology.

[0021]

[0030] Figure 1A shows a top view of a multi-chamber processing system 100, which may be specifically configured to implement aspects or operations according to several embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, in order to form semiconductor devices. The multi-chamber processing system 100 may include some or all of a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113 and may be mounted on the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be mounted on the transfer chamber 106. The processing chambers 122 and 124 may be mounted on the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between robots 126 and 128. Platforms 102 and 104 may be open to the transfer chamber and the buffer chamber, or they may be selectively isolated or sealed from the chambers so that varying operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105 for orientation or measurement operations, etc.

[0022]

[0031] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to implement the operations described below. Thus, the computer system 130 may be a general-purpose computer comprising a controller or an array of controllers and / or software stored on a non-temporary computer-readable medium that, when executed, can perform the steps described in relation to the methods according to embodiments of this art. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the manufacture of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing steps, including, among any number of other substrate processes, dry etching, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation.

[0023]

[0032] Figures 1B and 1C show the conventional 4F 2 A top view and a perspective view of the memory array 150 are shown. The memory array 150 may include a plurality of word lines 152 arranged in a first layer on a substrate. The word lines 152 may be conductive traces used to select the word lines of memory cells in the memory array 150. The memory array 150 may further include a plurality of bit lines 154 arranged in a second layer on a substrate. The plurality of bit lines may be conductive traces used to select the bit lines of memory cells in the memory array 150. Individual cells in the memory array 150 can be selected by activating one of the plurality of bit lines 154 and one of the plurality of word lines 152. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer having the word lines 152 may be formed on top of the second layer having the bit lines 154 such that the two layers do not intersect.

[0024]

[0033] Multiple vertical memory cells may be arranged on the intersections between multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor, which may be called a vertical pillar transistor or vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar or any other substrate, which will be described in more detail below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing charge in the vertical capacitor 156 to indicate a stored memory state. However, although Figures 1B and 1C show the arrangement of vertical transistors and capacitors in a rectangular, generally orthogonal grid pattern (where "generally orthogonal" is within about 10° of orthogonal, e.g., about 7.5° or less from orthogonal, e.g., about 5° or less, e.g., about 2.5° or less, e.g., about 1° or less, or any range or value in between, and "generally" may be used to similarly vary "vertical," "horizontal," etc.), it should be understood that other directions are also possible. For example, in one embodiment, capacitors and vertical transistors may be spaced apart in alternating rows offset by half the distance between vertical transistors. That is, in one embodiment, the first row of memory cells may be regularly spaced in a row in a first direction, and the second row of memory cells may also be regularly spaced in a row in a first direction, but the second row of memory cells may be offset from the first row of memory cells, for example, aligned approximately midway between the vertical transistors and capacitors of the first row. Such a pattern is sometimes referred to as a "honeycomb" or "hexagonal pattern" in comparison to the square pattern shown in Figures 1B and 1C. Therefore, it should be understood that any suitable orientation can be used in this technology.

[0025]

[0034] This conventional 4F 2It is useful to characterize the dimensions of the unit cell region 166 of the memory array for comparison with a simple memory array described later. For example, the capacitor footprint 158 ​​can be defined as the circular region around each vertical capacitor 156. The capacitor footprint 158 ​​may include the horizontal cross-sectional area of ​​the capacitor, which expands until its cross-sectional area contacts the capacitor region from an adjacent memory cell. Assume that the word line pitch 162 for multiple word lines 152 and the bit line pitch 164 for multiple bit lines 154 can be defined as 2F. This gives the overall cross-sectional area of ​​the unit cell region 166 to be 4F. 2 It will become.

[0026]

[0035] Figure 2 shows exemplary operation of Method 200 according to several embodiments of the present technology. This method can be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of arbitrary operations, some of which may or may not be particularly relevant to certain embodiments of the method relating to the present technology. For example, many operations are described to provide a wider range of structural forms, but may not be important to the present technology or may be carried out by alternative methods that are easily understood. In addition, while the method can be described in a perpendicular manner, it should be understood that other orientations from the bit line to the word line side may also be utilized.

[0027]

[0036] Method 200 may include additional steps before commencing the enumerated steps. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing material. The pre-processing steps may be performed in the chamber in which Method 200 may be performed, or the processing may be performed in one or more other processing chambers before delivering the substrate into the semiconductor processing chamber in which Method 200 may be performed. In any case, Method 200 may optionally include delivering the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to a processing area of ​​another chamber, which may include the components described above. The substrate may be a pedestal, such as a substrate support 104, and may be deposited on a substrate support / transfer platform that may be present in a processing area of ​​a chamber, such as the processing area of ​​the processing chamber 120 described above. Method 200 describes the steps schematically shown in Figures 3A-3D, 4A, and 4B, which are described in conjunction with the steps of Method 200. Figures 3A–3D, 4A, and 4B show only partial schematic diagrams, and it should be understood that the semiconductor substrate may include further components shown in the figures, as well as alternative components of any size or configuration from which the embodiments of this technology can still be beneficial.

[0028]

[0037] Method 200 may or may not include optional operations to develop the semiconductor structure into a specific manufacturing operation. It should be understood that Method 200 can be performed on any number of semiconductor structures 300 or substrates 302, as shown in Figures 3A-3D, 4A, and 4B, including exemplary structures on which selectively deposited material can be formed. As shown in Figure 3A, the substrate 302 may be any number of materials, for example, a base wafer or substrate made from silicon or a silicon-containing material, germanium, other substrate materials, and one or more materials that can be formed on the substrate during semiconductor processing.

[0029]

[0038] In embodiments, the structure 300 may be a semiconductor substrate including a bulk substrate, an epitaxially grown substrate, and / or silicon on an insulating wafer. As used herein, the term “semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is included in the spirit and scope of this disclosure.

[0030]

[0039] In embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron-donating element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0031]

[0040] As shown in Figure 3A, the structure 300 includes a substrate 302 on which STI 308 has already been formed, and a first dielectric material 306 fills the STI 308. In addition, two or more walls 305 are formed between each of the first STI 308, and the illustrated walls 305 are spaced apart in a row extending horizontally and generally perpendicular to the word line direction in this embodiment. However, as will be understood by those skilled in the art, in this embodiment the STI may first be cut in a direction generally parallel to the word line direction.

[0032]

[0041] While various deposition and filling processes are described, in embodiments, the semiconductor structure may be transferred to, or between, one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermochemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), plasma atomic layer deposition (PEALD), etc. Therefore, it should be understood that, unless otherwise specified, any one or more of the above methods known in the art may be used. Similarly, the semiconductor structure may be transferred to, or between, one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, such as inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, and other etching processes known in the art.

[0033]

[0042] Nevertheless, in step 201, method 200 may include forming both a first STI as shown in Figure 3A and a second STI 346 as shown in Figure 3B. For example, in an embodiment, the substrate 302 may be loaded into load locks 110, 112 and transported via robots 126, 128 to a processing chamber (such as processing chamber 114), and the semiconductor structure 300 may undergo the formation of a mask 340 and the formation of a second STI 346 in step 201 (the second STI 346 may extend in a generally horizontal direction that is generally parallel to the word line direction, and is therefore also referred to herein as word line trench formation). For example, Figure 3B shows the formation of a mask 340, which may be any patterning mask known in the art, and in an embodiment, etching a wall 305 into a channel 348 by using the mask 340 to etch in a direction that extends in a second horizontal direction that is generally perpendicular to the first horizontal direction. That is, as described above, to form an STI 308 between walls 305, a pattern or mask 340 defining a second STI 346 can be used to form a separation between channels 348 formed by the etching process, which are in rows parallel to the word lines or extending in a plane with respect to the word lines. The resulting channels 348 may have a uniform or non-uniform width and / or a width generally equal to the walls 305. The second STI 346 may serve to separate adjacent channels 348. Thus, a semiconductor structure 300 including first and second STIs may be provided, as shown in Figures 3A and 3B, where the first STI may include a dielectric material deposited or filled as described above. It should be understood that the substrate may be transferred between each process step, or only a portion of the process steps, because some process steps may be completed within the same processing chamber.

[0034]

[0043] As shown in Figure 3C, in the embodiment, the formation of the source / drain region 304 is carried out as one or more ion implanters, followed by an annealing process. The implantation process may be a single implantation or may include a series of multiple implantations, as will be described in more detail below. If multiple implanters are used, each implanter may utilize the same or different ions. However, it should be understood that the source / drain region 304 may be formed from any suitable process, but in the embodiment, the source / drain region 304 may be given one or more doping gradients. That is, as will be described in more detail with respect to Figures 4A and 4B, the technique has found that, surprisingly, by utilizing doping gradients for the first source / drain region 304 and / or the second source / drain region 324, the rate of change of the contact potential of the storage node in each source / drain region can be carefully adjusted, thereby reducing interband tunneling and stray body effects. Nevertheless, the method may include providing a semiconductor structure having a first source / drain region 304 for a plurality of vertical channels and forming a plurality of word lines in contact with the first source / drain region. However, in embodiments, the formation of the first source / drain region 304 may be performed before step 201. Overall, the process may gradually form each stage of the transistor on top of the previously completed stage.

[0035]

[0044] An optional step 203 may include forming one or more p-type doped regions within one or more channels 348. While the uniquely formed source / drain regions 304 / 324 by the Art can address the stray body effect and other issues described above, in embodiments it may be desirable to further include one or more p-type doped regions 310. That is, the Art has surprisingly found that by including one or more p-type doped regions 310 within one or more channels 348, the p-type doped regions can function as sinks for hole accumulation. Furthermore, such p-type doped regions 310 can also increase the threshold voltage of the channel, broaden the voltage range in which the channel is off-oriented, and reduce gate-induced drain leakage.

[0036]

[0045] In the embodiment, one or more doped regions 310 have a doping level sufficient to prevent significant charge sharing, for example, a V exceeding the gate threshold of each channel 348 in which the p-type doped region 310 is formed. tIt may have a doping level sufficient to provide. Nevertheless, since each p-type doped region 310 has a higher level of dopant than channel 348, each p-type doped region 310 can diffuse dopant from the center of each p-type doped region 310 toward and into adjacent channels 348. Thus, diffusion can form a dopant gradient from each p-type doped region 310 toward source / drain regions 304, 324. Such a phenomenon may improve hole attraction and reduce the floating body effect, as holes may move from the problematic region of one or more channels 348 to the p-type doped region 310, collecting the holes and dissipating the effect. However, if the doping level is too high within one or more p-type doped regions 310 compared to each channel 348, dopant diffusion may increase the doping level of one or more channels 348 to a level above the threshold of channel 348. Therefore, in the embodiment, the doping level of each p-type doped region 310 compared to channel 348 is carefully selected. Nevertheless, the technique has surprisingly found that the p-type doped regions 310 significantly reduce the stray body effect by reducing the increase in channel potential and decreasing leakage current, among other things.

[0037]

[0046] In the embodiment, the doping concentration of one or more p-type doped regions 310 is approximately 5 × 10⁻⁶. 16 cm -3 For example, approximately 6 x 10 16 cm -3 For example, approximately 7 x 10 16 cm -3 For example, approximately 8 x 10 16 cm -3 For example, approximately 9 x 10 16 cm -3 For example, approximately 1 × 10 17 cm -3 For example, approximately 2 × 10 17 cm -3 For example, approximately 4 x 10 17 cm-3 For example, approximately 6 x 10 17 cm -3 For example, approximately 8 x 10 17 cm -3 For example, approximately 1 × 10 18 cm -3 For example, approximately 2 × 10 18 cm -3 For example, approximately 4 x 10 18 cm -3 For example, approximately 6 x 10 18 cm -3 For example, approximately 8 x 10 18 cm -3 For example, approximately 1 × 10 19 cm -3 For example, approximately 2 × 10 19 cm -3 The above, or approximately 1 x 10 20 cm -3 For example, approximately 8 x 10 19 cm -3 For example, approximately 6 x 10 19 cm -3 For example, approximately 4 x 10 19 cm -3 For example, approximately 2 × 10 19 cm -3 The following may be any range or value between these.

[0038]

[0047] Nevertheless, in embodiments, several different materials may be used for one or more p-type doped regions 310. For example, one or more p-type doped regions 310 may include crystalline semiconductors such as silicon, germanium, silicon-germanium, one or more dielectric materials, and / or other suitable structural support materials. In embodiments, one or more p-type doped regions may be formed from crystalline silicon (e.g., single-crystal silicon in embodiments), or any one or more of the semiconductor materials described above, a dielectric material, and any other material suitable for deposition between adjacent channels to provide structural support. Nevertheless, these materials may also be used in the form of polycrystalline semiconductors.

[0039]

[0048] In embodiments, one or more p-doped regions 310 may be formed by epitaxially growing material onto recessed channel material 348 within the STI 308. Thus, in embodiments, such a process may be referred to as a selective epitaxial deposition process. Alternatively, one or more p-doped regions 310 may be formed by conformally filling adjacent STI 308 with one or more p-doped region 310 material, or by depositing one or more p-doped region 310 material 0 using other deposition methods known in the art. Additionally or alternatively, portions of the channels 348 may be doped by injection and annealing treatments, etc. Regardless of the method used, the material used for one or more p-doped regions 310 should be clearly depositable, grown, or formed. If a deposition or growth method is utilized, a second channel material, which may be the same channel material as described above, may be formed on top of the p-doped regions 310 to form the channels 348.

[0040]

[0049] In the embodiment, one or more p-doped regions 310 are formed on only a portion of one or more channels 348. For example, as shown in Figure 3C, one or more p-doped regions 310 have a thickness t of about 5% to about 30% of the height h of each channel 348, and may have a thickness t of, for example, about 7.5% or more, for example about 10% or more, for example about 12.5% ​​or more, for example about 15% or more, for example about 17.5% or more, for example about 20% or more, for example about 22.5% or more, for example about 25% or more, for example about 27.5% or more, or about 30% or less, for example about 27.5% or less, for example about 25% or less, for example about 22.5% or less, for example about 20% or less, or any range or value of thickness t in between. By selecting one or more p-doped regions 310, each having a thickness, or the total thickness of the p-doped regions conforming to the above range, excellent stray body effect and leakage current characteristics can be achieved without adversely affecting the channel.

[0041]

[0050] In other words, in the embodiment, the thickness t of one or more p-type doped regions 310 may be about 2 nm or more, for example about 4 nm or more, for example about 6 nm or more, for example about 8 nm or more, for example about 10 nm or more, for example about 12 nm or more, for example about 14 nm or more, for example about 16 nm or more, for example about 18 nm or more, for example about 20 nm or more, for example about 22 nm, for example about 24 nm or more, for example about 26 nm or more, for example about 28 nm or more, for example about 30 nm or more, for example about 32 nm or more, for example about 34 nm or more, for example about 36 nm or more, for example about 38 nm or more, for example about 40 nm or more, or for example about 70 nm or less, for example about 60 nm or less, for example about 55 nm or less, for example about 50 nm or less, for example about 45 nm or less, for example about 40 nm or less, or any range or value in between these. That is, in the embodiment, the thickness may be selected to provide sufficient sink and doping characteristics without affecting the overall electrical characteristics of each channel.

[0042]

[0051] In addition, as described above, in the embodiment, one or more p-type doped regions 310 may be formed at the approximate center of each channel 348, such as between the first source / drain region and the second source / drain region, or between the source / drain 304 and the top surface 307 in Figure 3C. That is, by utilizing one or more p-type doped regions 310 at the approximate center, a larger hole distribution can be shown and gate-induced drain leakage can be reduced. However, it should be understood that in the embodiment, more than one p-type doped region 310 may be utilized within each channel, and none or one of such p-type doped regions 310 have to be located at the approximate center. For example, a p-type doped region 310 may be located adjacent to the source / drain region 304, or a p-type doped region 310 may be formed adjacent to the second source / drain region of the semiconductor structure 300 (see, for example, Figure 4B). Nevertheless, regardless of the number of p-type doped regions 310 utilized within each channel, the channel 348 may have a height h extending between the first source / drain region and the second source / drain region, where at least one of the p-type doped regions may be formed at a height of approximately 20% to approximately 80% of the channel height, e.g., approximately 30% to approximately 60%, e.g., approximately 40% to approximately 60%, e.g., approximately 45% to approximately 55%, or any range or value in between.

[0043]

[0052] After forming one or more p regions 310 and optionally forming the upper part of the channel 348, the structure 300 is 4F as needed. 2 The process can then re-enter the normal processing flow for vertical cell DRAM arrays, such as DRAM arrays, and perform one or more further processing steps until the second source / drain region 324 is doped in step 204. For example, as shown in the figure, the gate dielectric 326 and gate metal 328 may be formed along the STI 346. Furthermore, after the formation of the gate dielectric 326 and gate metal 328, the second dielectric 330 may be filled into the STI 346.

[0044]

[0053] In embodiments, the gate metal 328 may be a low-resistance metal such as tungsten, titanium nitride, titanium, ruthenium, cobalt, molybdenum, or a combination thereof. In embodiments, the gate dielectric 326 may be formed from any dielectric material known in the art, such as silicon nitride, silicon oxynitride, silicon dioxide, silicon oxide, or other similar materials. In addition, the second dielectric material 330 may be formed from any one or more of the dielectric materials described herein. Nevertheless, as illustrated, the second source / drain region 324 may be formed by any one or more of the methods described above, or as described in more detail below. In embodiments, the second source / drain region 324 may be formed before filling with the second dielectric material 330. Additionally or alternatively, the second dielectric material 330 may be filled and etched back to a depth below the desired source / drain region 324 of the channel 348. After etch-back, a second source / drain region 324 can be formed by one or more injections or other methods, followed by refilling with the second dielectric material 330.

[0045]

[0054] Nevertheless, in embodiments, as shown in Figures 4A and 4B, one or more of the first source / drain regions 404 and / or the second source / drain regions 424 may be formed to exhibit a doping gradient. In embodiments, the first source / drain region 404, the second source / drain region 424, or both the first and second source / drain regions 404 and 424 may have a first section 404a / 424a adjacent to an end face such as the bit line 462 and storage node contact 464 of the channel 448. The first section 404a / 424a exhibits a higher doping concentration than the other sections of the source / drain region 404 / 424 (e.g., all other sections). In embodiments, the first section of each source / drain region may be directly adjacent to an end face such as the bit line 462 and storage node contact 464 of the respective channel, and may form all or part of the end face (e.g., may form a source / drain junction). Reference numeral 426 in Figures 4A and 4B indicates a gate oxide of a transistor, which may be monolayer or multilayer, formed of one or more dielectric layers. One or more gate oxide layers may include various dopings of SiO2, SiON, SiN, HfO2, HfZrO, HfOx, other oxides known in the art, and combinations thereof. Although Figures 4A and 4B are shown in cross-section, in embodiments, the gate oxide 426 may extend around a channel 448, for example, in a gate-all-around structure.

[0046]

[0055] Furthermore, the opposing end regions shown by section 404f / 424f of FIGS. 4A and 4B may be disposed adjacent to the gate 430 of the transistor that doubles the word line 430 and may form an interface with the word line 430. In embodiments, the section adjacent to the channel body may have a lower doping concentration than other sections, such as all of the other sections of the source / drain regions 404 / 424. Although FIGS. 4A and 4B are shown in cross-section, it should be understood that in embodiments, the word line 430 may extend around the channel 448, for example, in a gate all around structure.

[0047]

[0056] For example, in embodiments, all or part of the first section 404a and / or 424a is about 5×10 19 cm -3 or more, such as about 6×10 19 cm -3 or more, such as about 7×10 19 cm -3 or more, such as about 8×10 19 cm -3 or more, such as about 9×10 19 cm -3 or more, such as about 1×10 20 cm -3 or more, such as about 2×10 20 cm -3 or more, such as about 3×10 20 cm -3 or more, such as about 4×10 20 cm -3 or more, such as about 5×10 20 cm -3 or more, such as about 6×10 20 cm -3 or more, such as about 7×10 20 cm -3 or more, such as about 8×10 20 cm -3 or more, such as about 9×10 20 cm -3 or more, or about 1×10 21 cm -3 or less, such as about 9×10 20 cm -3 or less, such as about 8×1020 cm -3 For example, approximately 7 x 10 20 cm -3 For example, 6 x 10 20 cm -3 The doping concentration may be any range or value between the following or any other therein. In the embodiment, end faces 462 and / or 464 may exhibit any one or more of the above concentrations, and the concentration may decrease as it moves away from end faces 462 / 464 toward the channel body 428.

[0048]

[0057] Furthermore, in the embodiment, all or part of sections 404f and / or 424f are approximately 5 × 10 19 cm -3 For example, approximately 4 x 10 19 cm -3 For example, approximately 3 x 10 19 cm -3 For example, approximately 2 × 10 19 cm -3 For example, approximately 1 × 10 19 cm -3 For example, approximately 9 x 10 18 cm -3 For example, approximately 8 x 10 18 cm -3 For example, approximately 7 x 10 18 cm -3 For example, approximately 6 x 10 18 cm -3 For example, approximately 5 x 10 18 cm -3 For example, approximately 4 x 10 18 cm -3 For example, approximately 3 x 10 18 cm -3 For example, approximately 2 × 10 18 cm -3 For example, approximately 1 × 10 18 cm -3 The following, or for example, about 5 x 10 17 cm -3 For example, approximately 6 x 10 17 cm -3 For example, approximately 7 x 10 17 cm -3 For example, approximately 8 x 10 17 cm-3 The above is approximately 9 x 10 17 cm -3 In summary, approximately 1 x 10 18 cm -3 The doping concentration may be any range or value between these values.

[0049]

[0058] Therefore, in the embodiment, the first sections 404a and / or 424a may have a higher doping concentration than the doping concentrations in sections 404f and / or 424f. In the embodiment, the first sections 404a and / or 424a adjacent to one or more ends 462 / 464 may have a doping concentration about 1.5 times or more higher than the doping concentration of sections 404f and / or 424f adjacent to the channel body 428, for example, about 2 times or more higher than the doping concentration of sections or gate / word lines 430 that are adjacent to or in contact with the channel body 428, for example, about 2.5 times or more, for example, about 3 times or more, for example, about 3.5 times or more, for example, about 4 times or more, for example, about 4.5 times or more, for example, about 5 times or more, for example, about 5.5 times or more, for example, about 6 times or more, for example, about 6.5 times or more, for example, about 7 times or more, for example, about 7.5 times or more, for example, about 8 times or more, for example, about 8.5 times or more, for example, about 9 times or more, for example, about 9.5 times or more, for example, even about 10 times or more higher.

[0050]

[0059] Surprisingly, in the double-gate VCAAT embodiment, we have found that by using a roughly Gaussian or normal distribution with respect to the doping concentration extending from end faces 462 and / or 464 to sections 404f and / or 424f adjacent to the channel body 428, and in the gate-all-around VCAAT embodiment, to the word line (for example, with peak concentrations located or approximately located at end faces 462 and / or 46), the contact potential of the storage node can be controlled to significantly reduce, if not completely eliminate, the occurrence of interband tunneling, stray body effects, and / or gate-induced leakage current. That is, without wishing to be bound by theory, by forming one or more source-drain regions according to the gradients described herein, the change in potential can have a smaller slope and the barrier thickness between the storage node contact potential and the channel potential can be increased. This reduces the risk of interband tunneling due to the increased barrier thickness and also results in increased hole accumulation before interband tunneling occurs due to the increased channel potential. Thus, this technique can also reduce threshold voltage degradation over time.

[0051]

[0060] Although four additional sections are shown in the source / drain regions 404 / 424 (404b-404e, 424b-424e), it should become clear that the source / drain regions 404 and / or 424 may have any number of sections such that one or more source / drain regions 404 / 424 exhibit the gradient described above. Furthermore, in embodiments, there are no delimited sections, and instead, the doping concentration may gradually decrease from the ends 462 / 464 toward the channel body 428, or, in the case of a double-gate VCAAT embodiment, from the regions 404f / 424f adjacent to the channel body 428, and in the case of a gate-all-around VCAAT embodiment, from the word line toward the channel ends 462 / 464.

[0052]

[0061] In embodiments, the source / drain regions 404 / 424 can be formed by any one or more methods known in the art, provided that a gradient is provided. In embodiments, multiple injectors can be utilized. For example, the source / drain regions may first come into contact with a lightly doped injector adjacent to the channel body, and then with one or more high-energy injections moving outward toward the end faces 462 / 464. Alternatively, a single or multiple injectors can be utilized, but with varying annealing temperatures. Furthermore, in embodiments, combinations of methods can be utilized, such as forming one or more low-doped regions, followed by high-energy injections and / or varying annealing temperatures. Nevertheless, it should be clear that various methods can be utilized to form the source / drain regions 404 / 424, provided that an appropriate gradient is provided.

[0053]

[0062] Regardless of the method and timing of the formation of the source / drain regions 304 and 324, the semiconductor structure 300 / 400 may re-enter the normal processing flow and undergo one or more further processing steps. For example, the semiconductor structure may undergo contact redistribution, coupling pad formation, and / or copper contact formation. Nevertheless, the semiconductor structure can still have significantly reduced gate-induced leakage current, off-current leakage, and / or stray body effects.

[0054]

[0063] The specific step shown in the figure is 4F according to various embodiments. 2 It should be understood that this provides a specific method for forming a DRAM array. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in the figures may include multiple substeps that may be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0055]

[0064] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0056]

[0065] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0057]

[0066] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the above description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0058]

[0067] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0059]

[0068] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. While flowcharts may sometimes describe processes as sequential, many processes can be executed in parallel or simultaneously. Moreover, the order of processes may be rearranged. A process terminates when a process is completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0060]

[0069] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0061]

[0070] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0062]

[0071] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0063]

[0072] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical disks, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. A vertical cell access array transistor (VCAAT), A first horizontally arranged bit line or one or more bit lines, A second horizontally arranged word line, One or more channels, each extending in a vertical direction substantially perpendicular to the first horizontal and second horizontal directions, such that the bit lines of the one or more channels intersect the source / drain regions of the one or more channels and the word lines of the one or more channels intersect the gate regions of the one or more channels, Includes, The source / drain region includes a first section adjacent to the source / drain junction and a second section adjacent to the channel body, wherein the first section has a doping concentration higher than that of the second section. Vertical cell access array transistor (VCAAT).

2. The vertical cell array transistor (VCAAT) according to claim 1, wherein the doping concentration in the source / drain region exhibits a Gaussian (normal) distribution with a peak concentration approximately at the source / drain junction.

3. The vertical cell array transistor (VCAAT) according to claim 1, wherein the doping concentration in the first section is at least twice as high as the doping concentration in the second section.

4. The doping concentration in the first section is 1 × 10 １９ cm －３ A larger vertical cell array transistor (VCAAT) according to claim 1.

5. The doping concentration in the first section is 4 × 10 １９ cm －３ A larger vertical cell array transistor (VCAAT) according to claim 4.

6. The doping concentration in the second section is approximately 1 × 10⁻⁶ １９ cm －３ The vertical cell array transistor (VCAAT) described in claim 1 is as follows:

7. The vertical cell array transistor (VCAAT) according to claim 1, wherein the channel further comprises one or more p-type doped regions.

8. The vertical cell array transistor (VCAAT) according to claim 7, wherein the channel includes a height extending between the source / drain region and a second source / drain region, and the one or more p-type doped regions are formed to a height of about 20% to about 80% of the height of the channel.

9. The one or more p-type doped regions are from about 5×10 １６ cm －３ or more to about 1×10 ２０ cm －３ in doping concentration, and the vertical cell array transistor (VCAAT) according to claim 7.

10. The vertical cell array transistor (VCAAT) according to claim 7, wherein the channel includes a height extending between the source / drain region and a second source / drain region, and the one or more p-type doped regions include a thickness of about 5% to about 30% of the height of the channel.

11. A vertical cell array transistor (VCAAT), A first set of horizontally arranged bit lines, A second set of horizontally arranged word lines, A plurality of channels, wherein the plurality of bit lines intersect with the first source / drain region and / or second source / drain region of the plurality of channels, and the plurality of word lines intersect with the gate region of the plurality of channels, and the plurality of channels extend from the first source / drain region to the second source / drain region in a vertical direction substantially orthogonal to the first horizontal direction and the second horizontal direction, Includes, A vertical cell array transistor (VCAAT) in which at least a portion of the plurality of channels includes one or more p-type doped regions located between the first source / drain region and the second source / drain region.

12. The vertical cell array transistor (VCAAT) according to claim 11, wherein the channel includes a height extending between the first source / drain region and the second source / drain region, and the one or more p-type doped regions are formed to a height of about 20% to about 80% of the height of the channel.

13. The vertical cell array transistor (VCAAT) according to claim 11, further comprising at least a second p-type doped region among the one or more p-type doped regions.

14. The aforementioned one or more p-doped regions are approximately 5 × 10 １６ cm －３ From the above, approximately 1 x 10 ２０ cm －３ A vertical cell array transistor (VCAAT) according to claim 13, comprising the doping concentration of the above.

15. The vertical cell array transistor (VCAAT) according to claim 11, wherein the channel includes a height extending between the first source / drain region and the second source / drain region, and the one or more p-type doped regions include a thickness of about 5% to about 30% of the height of the channel.

16. A method for forming a vertical cell array transistor (VCAAT), Etching the substrate to form one or more STIs and multiple vertically extending channels, To bring one or more of the plurality of vertically extending channels into contact with one or more ion implanters to form a first source / drain region, To form a p-type doped region along one or more of the aforementioned plurality of vertically extending channels, To form a second source / drain region, Includes, The first source / drain region includes a first section adjacent to the source / drain junction and a second section adjacent to the channel body, wherein the first section has a doping concentration higher than that of the second section. method.

17. The method according to claim 16, wherein the p-type doped region is formed using a second ion implanter.

18. The method according to claim 17, comprising annealing the one or more ion implanters and / or the second ion implanter.

19. The method according to claim 16, comprising etching one or a portion of the plurality of channels and forming the p-type doped region within the etched portion.

20. The method according to claim 19, wherein forming the p-type doped region involves epitaxial growth.

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