Pulse voltage-assisted plasma strike

Abstract

Embodiments provided herein generally include apparatus, plasma processing systems, and methods for controlling plasma initiation and maintenance. Some embodiments relate to apparatus for processing substrates in a plasma processing system. The apparatus generally includes a pulsed voltage (PV) signal generator configured to provide a bias signal to a plasma load to initiate plasma in a plasma chamber, and a first burst including a first burst having a first duration comprising a series of pulses, and a radio frequency (RF) signal generator configured to provide an RF signal of a second duration to the plasma load, wherein the first duration is less than 10% of the second duration, and the first burst occurs at the start of the second duration.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to systems and methods used during semiconductor device manufacturing. More specifically, embodiments of the present disclosure relate to plasma processing systems used to process substrates.

[0002]

[0002] Manufacturing high aspect ratio features reliably is one of the important technical challenges for next-generation semiconductor devices. In one way to form high aspect ratio features, a plasma-assisted etching process such as a reactive ion etching (RIE) plasma process is used to form high aspect ratio openings in a material layer (such as a dielectric layer) of a substrate. In a normal RIE plasma process, plasma is formed in the processing chamber, and ions from the plasma are accelerated towards the substrate surface to form openings in the material layer disposed beneath a mask layer formed on the substrate surface.

[0003]

[0003] A typical RIE plasma processing chamber includes a radio frequency (RF) bias generator that supplies an RF voltage to a power electrode. In capacitively coupled gas discharge, plasma is generated by using an RF generator connected to a power electrode disposed within an electrostatic chuck (ESC) assembly or another part of the processing chamber. In some cases, it may be difficult to ignite plasma in the chamber, or the plasma may not be maintained for a sufficient length of time to process the substrate.

[0004]

[0004] Therefore, there is a need for an apparatus and method for processing a substrate in a plasma processing system that solves the above problems.

Summary of the Invention

[0005]

[0005] Embodiments provided herein generally include an apparatus, a plasma processing system, and a method for igniting and maintaining plasma in a processing chamber.

[0006]

[0006] Some embodiments relate to apparatus for processing substrates in a plasma processing system. The apparatus generally includes a pulsed voltage (PV) signal generator configured to provide a bias signal to a plasma load to start a plasma in a plasma chamber, and includes a first burst having a first duration comprising a series of pulses, and a radio frequency (RF) signal generator configured to provide an RF signal to the plasma load over a second duration, the first duration being less than 10% of the second duration, and the first burst occurring at the start of the second duration.

[0007]

[0007] Some embodiments relate to methods for processing a substrate in a plasma processing system. The method generally involves providing a bias signal to a plasma load to start a plasma in a plasma chamber via a pulsed voltage (PV) signal generator, the bias signal including a first burst having a first duration, which includes a series of pulses; and providing an RF signal to the plasma load via a radio frequency (RF) signal generator for a second duration, the first duration being less than 10% of the second duration, and the first burst occurring at the start of the second duration.

[0008]

[0008] Some embodiments relate to plasma processing systems. A plasma processing system generally includes a plasma chamber and a pulsed voltage (PV) signal generator connected to the plasma chamber and configured to provide a bias signal to a plasma load to start a plasma in the plasma chamber, the pulsed voltage (PV) signal generator including a first burst having a first duration, and a radio frequency (RF) signal generator connected to the plasma chamber and configured to provide an RF signal to the plasma load over a second duration, the first duration being less than 10% of the second duration, and the first burst occurring at the start of the second duration.

[0009]

[0009] To enable a detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be obtained by reference to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only exemplary embodiments and should not be considered to limit the scope of the Disclosure, as other equally valid embodiments are also permissible. [Brief explanation of the drawing]

[0010] [Figure 1A] This is a schematic diagram of a plasma processing system according to a specific embodiment of the present disclosure. [Figure 1B] This is a schematic detail cross-sectional view of a plasma processing system according to a particular embodiment of the present disclosure. [Figure 2] The voltage waveform established on the substrate by the voltage waveform applied to the electrodes of the processing chamber according to a specific embodiment of this disclosure is shown. [Figure 3] This is a graph illustrating an exemplary pulse scheme for semiconductor processing relating to a particular aspect of this disclosure. [Figure 4] This is a graph illustrating an exemplary pulse scheme for semiconductor processing relating to a particular aspect of this disclosure. [Figure 5] This is a graph illustrating an exemplary pulse scheme for semiconductor processing relating to a particular aspect of this disclosure. [Figure 6] This is a graph illustrating an exemplary pulse scheme for semiconductor processing relating to a particular aspect of this disclosure. [Figure 7] This disclosure describes macrostrikes and microbursts used to initiate and control plasma within a processing chamber, according to specific aspects of this disclosure. [Figure 8] This is a process flow diagram illustrating a method for processing a substrate in a plasma processing system according to a specific embodiment of the present disclosure. [Modes for carrying out the invention]

[0011]

[0019] To facilitate understanding, the same reference numerals were used where possible to indicate identical elements common to multiple figures. It is assumed that elements and features of one embodiment may be usefully incorporated into other embodiments without further description.

[0012]

[0020] Embodiments of this disclosure generally relate to systems used in semiconductor device manufacturing processes. More specifically, embodiments provided herein generally include apparatus and methods for plasma control within a processing chamber that are more reliable than conventional implementations. For example, one or more microbursts may be used to start and maintain plasma during semiconductor processing. One or more microbursts may be used to start plasma within a chamber after the radio frequency (RF) power to the chamber has been turned off. Microbursts enable the plasma to be started and maintained for the entire duration that RF power is supplied for semiconductor processing. Without microbursts, plasma may be lost if the bias voltage level (and / or RF power level) used for semiconductor processing is too low, as described in more detail herein. Certain aspects of this disclosure provide one or more advantages, such as reliable control and maintenance of the plasma within the processing chamber, and offer greater flexibility with respect to the bias voltage level and / or RF power level used for semiconductor processing.

[0013] Examples of plasma treatment systems

[0021] Figure 1A is a schematic diagram of a plasma processing system. The plasma processing system 10 is configured for plasma-assisted etching processes such as reactive ion etching (RIE) plasma processing. The plasma processing system 10 can also be used for other plasma-assisted processes such as plasma-enhanced deposition processes (e.g., plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD), plasma processing, plasma-based ion implantation, or plasma doping (PLAD). In one configuration, as shown in Figure 1A, the plasma processing system 10 is configured to form a capacitively coupled plasma (CCP). However, in some embodiments, plasma may be alternately generated by an inductively coupled source located above the processing area of ​​the plasma processing system 10.

[0014]

[0022] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas supply system 182, a high DC voltage supply source 173, a radio frequency (RF) generator 171, and an RF matcher 172 (e.g., an RF impedance matching network). The chamber lid 123 includes one or more side walls and a chamber base, which are configured to withstand the pressure and energy applied to them while the plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing.

[0015]

[0023] A gas supply system 182 connected to the processing space 129 of the processing chamber 100 is configured to supply at least one processing gas from at least one gas processing source 119 to the processing space 129 of the processing chamber 100. The gas supply system 182 includes the processing gas source 119 and one or more gas inlets 128 positioned through the chamber lid 123. The gas inlets 128 are configured to supply one or more processing gases to the processing space 129 of the processing chamber 100.

[0016]

[0024] The processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) and a lower electrode (e.g., a substrate support assembly 136) positioned within the processing space 129 of the processing chamber 100. The upper and lower electrodes face each other. In one embodiment, an RF generator 171 is electrically coupled to the lower electrode. The RF generator 171 is configured to provide an RF signal for igniting and maintaining a plasma 101 between the upper and lower electrodes. In some alternative configurations, the RF generator 171 may be electrically coupled to the upper electrode. For example, the RF generator 171 may supply RF source power to an RF base plate within the cathode assembly (e.g., within the substrate support assembly 136) for plasma generation, while the upper electrode is grounded. The center frequency of the RF source power can range from 13.56 MHz to very high frequency bands such as 40 MHz, 60 MHz, 120 MHz, or 162 MHz. In some embodiments, the RF source power may also be supplied through the upper electrode. The RF source power can operate in continuous mode or pulsed mode. The pulse frequency of the RF power can be between 100 and 10 kHz, and the duty cycle is in the range of 5% to 95%. The RF generator 171 has frequency tuning capability and can adjust its RF power frequency within a range of, for example, ±5% or ±10%. In some embodiments, the RF generator 171 switches the RF power frequency at a predetermined speed (e.g., 2 nanoseconds, 50 nanoseconds, etc.).

[0017]

[0025] Referring to FIGS. 1A and 1B, there is a more detailed schematic cross-sectional view of the plasma processing system. The substrate support assembly 136 can be coupled to a high voltage DC power supply 173 that supplies a chucking voltage. The high voltage DC supply 173 can be coupled to a filter assembly 178 disposed between the high DC voltage power supply 173 and the substrate support assembly 136.

[0018]

[0026] The filter assembly 178 is configured to electronically isolate the high voltage DC power supply 173 during plasma processing. In one configuration, the static DV voltage is between about -5000 V and about 5000 V and is supplied using electrical conductors (such as coaxial power supply lines). The filter assembly 178 can include multiple filtering components or a single common filter.

[0019]

[0027] The substrate support assembly 136 is coupled to a pulse voltage (PV) waveform generator 175 configured to supply PV to bias the substrate support assembly 136. The PV waveform generator 175 is coupled to the filter assembly 178. The filter assembly 178 is disposed between the PV waveform generator 175 and the substrate support assembly 136. The filter assembly 178 is configured to electronically isolate the PV waveform generator 175 during plasma processing.

[0020]

[0028] The substrate support assembly 136 is coupled to an RF generator 171 configured to provide an RF signal to the processing space 129 of the processing chamber 100. The RF generator 171 is electronically coupled to an RF matcher 172 disposed between the RF generator 171 and the processing space 129 of the processing chamber 100. For example, the RF matcher 172 is an electrical circuit used between the RF generator 171 and a plasma reactor (e.g., the processing space 129 of the processing chamber 100) to optimize power supply efficiency. One or more RF filters (e.g., within the RF matcher 172) are designed to allow RF power in a selected frequency range to pass through and to isolate RF power sources from each other. In some cases, the bandwidth of the RF filter must be greater than the frequency tuning range of the RF generator 171.

[0021]

[0029] During plasma processing, the RF generator 171 provides an RF signal to the substrate support assembly 136 via the RF matcher 172. For example, the RF signal is applied to a load (e.g., gas) within the processing space 129 of the processing chamber 100. If the impedance of the load does not properly match the impedance of the source (e.g., the RF generator 171), a portion of the waveform may be reflected back in the opposite direction. Thus, in some implementations, to prevent a substantial portion of the waveform from reflecting, as the source and load impedances change, a matching impedance (e.g., a matching point) is found by adjusting one or more components of the RF matcher 172.

[0022]

[0030] The RF matcher 172 is electrically coupled to the RF generator 171, the substrate support assembly 136, and a PV waveform generator 175. The RF matcher 172 is configured to receive a synchronization signal from either or both of the RF generator 171 and the PV waveform generator 175.

[0023]

[0031] The RF generator 171 and the PV waveform generator 175 are each directly coupled to a system controller 126. The system controller 126 synchronizes the respective generated RF signals and PV waveforms.

[0024]

[0032] Voltage and current sensors may be placed at the inputs and / or outputs of the RF matcher 172 to measure impedance and other parameters. These sensors can be synchronized by determining their timing internally using an external transistor-to-transistor logic (TTL) synchronization signal from a high-performance waveform generator and / or RF generator, or using measured voltage and current data. For example, output sensor 117 is configured to measure the impedance of the plasma processing chamber 100, and other characteristics such as voltage, current, harmonics, and phase. Input sensor 116 is configured to measure the impedance of the RF generator 171, and / or other characteristics such as voltage, current, harmonics, and phase. Based on either the synchronization signal or the characteristics of the plasma processing chamber 100, the RF matcher 172 can capture rapid impedance changes and optimize impedance matching.

[0025]

[0033] The PV waveform generator 175 is used to supply the PV waveform and / or a tuned voltage waveform, which is the sum of the harmonic frequencies associated with the waveform. The PV waveform generator 175 can output a synchronous TTL signal to the RF matcher 172. The voltage waveform is coupled to a bias electrode (e.g., bias electrode 104 shown in Figure 1B) via a filter assembly 178. A high DC voltage source 173 is applied to chuck the substrate during the process for thermal control of the substrate. In some cases, a third electrode may be present at the edge of the cathode assembly for edge uniformity control.

[0026]

[0034] Figure 1B is a schematic detailed cross-sectional view of the plasma processing system 10. As shown in Figure 1B, the plasma processing system 10 is configured to form a capacitively coupled plasma (CCP). However, in some embodiments, the plasma 101 may instead be generated by an inductively coupled source located above the processing area of ​​the plasma processing system 10. In this configuration, the coil may be located above the ceramic lid (e.g., vacuum boundary) of the plasma processing chamber 100.

[0027]

[0035] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas supply system 182, a DC power system 183, an RF power system 189, and a system controller 126. The processing chamber 100 includes a chamber body 113 which includes a chamber lid 123, one or more side walls 122, and a chamber base 124. Collectively, the chamber lid 123, one or more side walls 122, and the chamber base 124 define the processing space 129 of the processing chamber 100. The one or more side walls 122 and the chamber base 124 are sized and shaped to form structural supports for the elements of the processing chamber 100 and include materials (such as aluminum, aluminum alloy, etc.) configured to withstand the pressure and additional energy applied to them while plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. The substrate 103 is loaded into the processing space 129 of the processing chamber 100 through one of the openings (not shown) in the side wall 122 and removed from there. The opening is sealed by a slit valve (not shown) during the plasma processing of the substrate 103.

[0028]

[0036] The gas supply system 182 connected to the processing space 129 of the processing chamber 100 includes a processing gas source 119 and a gas inlet 128 located through the chamber lid 123. The gas inlet 128 is configured to supply one or more processing gases from the processing gas source 119 to the processing space 129 of the processing chamber 100.

[0029]

[0037] As described above, the processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) and a lower electrode (e.g., a substrate support assembly 136) located within the processing space 129 of the processing chamber 100. The upper and lower electrodes are positioned facing each other. As shown in Figure 1B, the RF generator 171 is electrically connected to the lower electrode. The RF generator 171 is configured to provide an RF signal for igniting and maintaining the plasma 101 between the upper and lower electrodes. In some alternative configurations, the RF generator 171 may be electrically coupled to the upper electrode.

[0030]

[0038] The substrate support assembly 136 includes a substrate support 105, a substrate support base 107, an insulating plate 111, a grounding plate 112, a plurality of lift pins 186, one or more substrate potential sensing assemblies 184 (including, for example, a signal detection assembly 188), and a bias electrode 104. Each lift pin 186 is positioned through a through hole 185 formed in the substrate support assembly 136 and is used to facilitate the transfer of the substrate 103 between the substrate support 105 and the substrate receiving surface 105A. The substrate support 105 is formed of a dielectric material. The dielectric material may include bulk sintered ceramic materials, corrosion-resistant metal oxides (e.g., aluminum oxide (Al2O3), titanium oxide (TiO), yttrium oxide (Y2O3)), metal nitride materials (e.g., aluminum nitride (AIN), titanium nitride (TiN)), mixtures thereof, or combinations thereof.

[0031]

[0039] The substrate support base 107 is formed from a conductive material (e.g., aluminum, an aluminum alloy, or a stainless steel alloy). The substrate support base 107 is electrically insulated from the chamber base 124 by an insulating plate 111 and a grounding plate 112 interposed between the insulating plate 111 and the chamber base 124. The substrate support base 107 is configured to regulate the temperature of both the substrate support 105 and the substrate 103 placed on the substrate support 105 during substrate processing. The substrate support base 107 includes one or more cooling channels (not shown) located therein, which are fluidly coupled to and in fluid communication with a coolant source (not shown), such as a refrigerant source or substrate source having relatively high electrical resistance. The substrate support 105 includes a heater (not shown) for heating the substrate support 105 and the substrate 103 placed on the substrate support 105.

[0032]

[0040] The bias electrode 104 is embedded in the dielectric material of the substrate support 105. The bias electrode 104 is formed of one or more conductive components. The conductive components include mesh, foil, plate, or a combination thereof. The bias electrode 104 functions as a chuck electrode (i.e., an electrostatic chuck electrode) used to fix the substrate 103 to the substrate receiving surface 105A of the substrate support 105 (e.g., electrostatic chuck). A parallel plate-like structure is formed by the bias electrode 104 and a layer of dielectric material placed between the bias electrode 104 and the substrate receiving surface 105A. The dielectric material may have an effective capacitance CE between about 5 nF and about 50 nF. The layer of dielectric material (e.g., aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) has a thickness between about 0.3 mm and about 5 mm, for example between about 0.1 mm and about 3 mm, for example between about 0.1 mm and about 1 mm, or further between about 0.1 mm and 0.5 mm. The bias electrode 104 is electrically coupled to a clamp network that supplies the chuck voltage. The clamp network includes a DC voltage source 173 (e.g., a high-voltage DC source) coupled to a filter 178A of a filter assembly 178 positioned between the DC voltage source 173 and the bias electrode 104. The filter 178A is a low-pass filter and is configured to prevent RF frequency and PV waveform signals provided by other bias components found within the processing chamber 100 from reaching the DC voltage source 173 during plasma processing. The static DV voltage is between approximately -5000V and approximately 5000V and is supplied using an electrical conductor (e.g., a coaxial power supply line 106). The bias electrode 104 may bias the substrate 103 to the plasma 101 using one or more of the PV bias schemes.

[0033]

[0041] The substrate support assembly 136 includes an edge control electrode 115. The edge control electrode 115 is formed from one or more conductive components. The conductive components include mesh, foil, plate, or a combination thereof. The edge control electrode 115 is positioned below the edge ring 114, surrounding the bias electrode 104, and / or at a certain distance from the center of the bias electrode 104. In the case of a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular in shape, made from a conductive material, and configured to surround at least a portion of the bias electrode 104. As shown in Figure 1B, the edge control electrode 115 is positioned within the region of the substrate support 105 and is biased by the use of a PV waveform generator 175. The edge control electrode 115 is biased using a different PV waveform generator than the one used for the bias electrode 104. The edge control electrode 115 is biased by splitting a portion of the signal supplied from the PV waveform generator 175 to the bias electrode 104.

[0034]

[0042] The DC power system 183 includes a DC voltage source 173, a PV waveform generator 175, and a current source 177. The RF power system 189 includes an RF waveform generator 171, an RF matcher 172, and an RF filter 174. As shown in Figure 1B, the power supply line 163 electrically connects the output of the RF generator 171 to the RF matcher 172, the RF filter 174, and the substrate support base 107. As described above, during plasma processing, the DC voltage source 173 supplies a constant chucking voltage, while the RF generator 171 provides an RF signal to the processing area, and the PV waveform generator 175 establishes a PV waveform at the bias electrode 104. For example, a sufficient amount of RF power is applied to an RF bias voltage signal (also referred to herein as an RF waveform), and the RF waveform is supplied to an electrode (e.g., a substrate support base 107) to form a plasma 101 in the processing space 129 of the processing chamber 100. The RF waveform has a frequency range between approximately 1 MHz and approximately 200 MHz, for example, between 2 MHz and 40 MHz.

[0035]

[0043] The DC power system 183 includes a filter assembly 178 for electrically isolating one or more of the components contained within the DC power system 183. Power supply line 160 electrically connects the output of DC voltage source 173 to filter assembly 178. Power supply line 161 electrically connects the output of PV waveform generator 175 to filter assembly 178. Power supply line 162 connects the output of current source 177 to filter assembly 178.

[0036]

[0044] The current source 177 is selectively coupled to the bias electrode 104 using a switch (not shown) located within the power supply line 162, allowing the current source 177 to supply a desired current to the bias electrode 104 during one or more stages (e.g., the ion current stage) of the voltage waveform generated by the PV waveform generator 175.

[0037]

[0045] The filter assembly 178 includes several separate filtering components (i.e., separate filters 178A to 178C) each electrically connected to the output node via the power supply line 164. The filter assembly 178 may include one common filter electrically connected to the output node via the power supply line 164. The power supply lines 160 to 164 include conductors, including combinations of coaxial cables such as rigid coaxial cables and flexible coaxial cables connected in series, insulated high-voltage corona-resistant hookup wires, bare wires, metal rods, electrical connectors, and any combination of the above.

[0038]

[0046] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence used to process the substrate 103. The CPU is a computer processor configured for use in an industrial environment to control the processing chamber and its associated subprocessors. The memory 134 described herein, which is generally non-volatile memory, may include random access memory, read-inline memory, a hard disk drive, or other suitable form of local or remote digital storage. The support circuitry 135 is connected to the CPU 133 and includes a cache, clock circuitry, input / output subsystems, power supply, etc., and combinations thereof. Software instructions (programs) and data may be coded and stored in the memory 134 to instruct the processor in the CPU 133. Software programs (or computer instructions) readable by the CPU 133 in the system controller 126 determine which tasks can be performed by the components in the plasma processing system 10.

[0039]

[0047] A program readable by the CPU 133 in the system controller 126, when executed by the CPU 133, includes code that performs tasks related to the plasma processing scheme described herein. The program may include instructions used to control various hardware and electrical components in the plasma processing system 10 for performing various process tasks and various process sequences used to perform the method described herein. The program includes instructions used to perform one or more of the steps described herein.

[0040]

[0048] Figure 2 shows two distinct voltage waveforms established on a substrate 103 placed on the substrate receiving surface 105A of the substrate support assembly 136 of the processing chamber 100 by supplying a PV waveform to the bias electrode 104 of the processing chamber 100 using a PV waveform generator 175. The first waveform (e.g., waveform 225) is an example of an uncompensated PV waveform established on the substrate 103 during plasma processing. The second waveform (e.g., waveform 230) is an example of a compensated PV waveform established on the substrate 103 by applying a negative slope waveform to the bias electrode 104 of the processing chamber 100 during the "ion current phase" portion of the PV waveform cycle using a current source 177. The compensated PV waveform can alternatively be established by applying a negative voltage ramp during the ion current phase of the PV waveform generated by the PV waveform generator 175. The PV waveform cycles of waveforms 225 and 230 each have a period Tp, which is typically between 2 microseconds (μs) and 10 μs, for example, 2.5 μs. The ion current phase of the PV waveform cycle typically accounts for about 50% to 95% of the period Tp, such as about 80% to 90% of the period Tp.

[0041]

[0049] Waveforms 225 and 230 include two main stages, namely the ion current stage and the sheath collapse stage. Both parts of waveforms 225 and 230 (e.g., the ion current stage and the sheath collapse stage) can be established alternately and / or separately on the substrate 103 during plasma processing. At the start of the ion current stage, the supply of the negative portion (e.g., the ion current portion) of the PV waveform supplied to the bias electrode 104 by the PV waveform generator 175 causes a voltage drop on the substrate 103, creating a high-voltage sheath on the substrate 103. The high-voltage sheath allows plasma-generated positive ions to be accelerated toward the biased substrate 103 during the ion current stage, and thus, in the case of the RIE process, controls the amount and characteristics of the etching process that occurs on the surface of the substrate 103 during plasma processing. In some embodiments, it is desirable that the ion current stage includes a region of the PV waveform that achieves a voltage on the substrate 103 that is stable or minimally fluctuating throughout the stage, as shown in Figure 2 by waveform 230. It should be noted that significant fluctuations in the voltage established on the substrate 103 during the ion current stage, such as those indicated by the positive slope of waveform 225, undesirably cause fluctuations in the ion energy distribution (IED), resulting in the formation of undesirable characteristics of the etched features on the substrate 103 during the RIE process.

[0042]

[0050] The impedance of the plasma sheath changes depending on the supplied PV waveform voltage. The RF matcher 172 can sample the impedance at various processing stages using one or both of the synchronization signals and / or its internal sensors. In one embodiment, the synchronization signal or characteristic determined by the input sensor 116 or the output sensor 117 is used to trigger the RF matcher 172 to determine at least two different impedances at different processing stages. The RF matcher 172 then updates its matching point based on at least two different impedances.

[0043]

[0051] Silicon carbide (SiC) based Schottky diodes exhibit low junction capacitance (e.g., in the range of tens of picofarads) when reverse-biased to some extent. When such a reverse-biased Schottky diode stack with low junction capacitance is placed in the path of an RF signal (for example, having a frequency of 13.56 MHz), the diodes provide high impedance to the RF signal, thereby blocking the RF signal. On the flip side, when forward-biased, the diode functions as a short-circuited path under the influence of the forward bias, allowing the RF signal to pass through the same Schottky diode stack. Therefore, the Schottky diode can function as an RF switch (RFS) through a circuit that can switch between forward-biased and reverse-biased states at the PV waveform frequency. This method allows the user to change the total impedance of the matched network at higher frequencies than conventional implementations by switching the RF switch on and off using reverse and forward bias. Conventional matched networks may not be tunable at such high frequencies.

[0044] Pulse voltage-assisted plasma strike

[0052] In some implementations, bias power is used in combination with source power to enhance plasma ignition. In some embodiments, pulsed voltage (PV) may be used to enhance plasma ignition using PV waveform parameters set to improve voltage supply. By using PV waveforms, multilevel pulse capability can enhance plasma ignition on macro-scale and micro-scale timescales.

[0045]

[0053] Certain embodiments implement PV blend strike capability by providing a pulsed voltage burst before or at the start of the RF source sequence. Ignition parameters can be tuned experimentally to characterize strike performance, provide ignition repeatability, and reduce reflected power. Certain embodiments implement strike via recipe settings. Ignition can be improved by implementing more complex ignition sequences, such as tuning the bias signal slope. In some cases, multiple bursts may be used to reduce the impact on semiconductor processing, as will be described in more detail herein.

[0046]

[0054] Figures 3–5 are graphs 300, 400, and 500 illustrating exemplary pulse schemes for semiconductor processing according to specific embodiments of the present disclosure. Pulsing schemes that include a source-off state (e.g., the RF source from generator 171 is off) can introduce plasma stability issues. Specific embodiments of the present disclosure relate to providing a series of pulsed voltages (e.g., microbursts) at a high voltage (e.g., 1000V or higher) as a bias for semiconductor processing. Using high-voltage bursts can impose limitations on the processing space, particularly with respect to logic recipes with low-voltage specifications or requirements. Some embodiments relate to using at least one microburst (e.g., including low-duration pulses less than 15) in each RF power burst for source recombination. The supply of microbursts helps in initiating and maintaining the plasma. After the microbursts, the bias voltage can be reduced to below the high voltage (e.g., 1000V) to facilitate the semiconductor processing recipe. A microburst refers to a series of pulses at a specific frequency, such as 400KHz, as described with respect to Figure 2.

[0047]

[0055] For the sake of simplicity, the bias signals shown in the figures herein are represented as increasing in magnitude from zero reference; however, actual bias signals applied to any of the embodiments disclosed herein may have either positive or negative polarity. In one or more embodiments, the applied bias signal applied to the electrodes in the plasma processing chamber has substantially negative polarity with respect to the ground reference.

[0048]

[0056] As shown in Figure 3, graph 300 shows the voltages of the bias signal 304 (e.g., a PV signal from a PV waveform generator 175) and the RF power pulse 302 (watts (Ws)) from an RF source (e.g., an RF generator 171) (e.g., an RF signal 171). The bias signal 304 can be applied to any electrode capacitively coupled to the chamber. For example, the bias signal 304 can be applied to the bias electrode 104 described with respect to Figure 1B or to an edge electrode of the chamber (e.g., an edge ring).

[0049]

[0057] A microburst 306 (e.g., a series of pulses with a 1000V peak) may be applied via the PV waveform generator 175. The burst may be initiated with an RF power pulse 302 that increases according to a specific processing recipe. For example, the burst 306 may be applied with RF power increasing up to 550 watts, as shown in the figure. After the microburst 306, the voltage of the bias signal 304 may be set based on the requirements of the plasma processing recipe. For example, as shown in graph 300, the voltage of the bias signal 304 may be reduced to 0 volts by time 308. Then, the voltage of the bias signal 304 may increase (e.g., up to 500 volts) after a certain period of time, as shown in the figure, and then decrease to 0 volts. In this case, the RF signal power pulse 302 may be reduced to 0 watts at time 310, as shown in the figure. The microburst 306 allows the plasma to be started and maintained while RF power is supplied during a portion of the processing period 350 (e.g., any point between 100 microseconds (μs) and 100 milliseconds (ms)). Part of the bias signal 304 is shown as a constant voltage (e.g., a constant voltage at voltage V1), but the bias signal 304 includes a series of pulses (e.g., 400 kHz as shown in Figure 2). The bias signal voltage shown in the illustration represents the peak voltage of the pulse. For example, burst 306 may include a series of pulses with a peak voltage of 1000 volts.

[0050]

[0058] The bias voltage and RF power during the processing period may follow the processing recipe. For example, as shown in the figure, the duration from the start of burst 306 to time 308 may be 5% of the total processing period 350. The duration for which the bias signal voltage is set to 300 volts may be 20% of the processing period 350. The duration between time 308 and time 310 may be 45% of the processing period 350, and the duration from time 310 to the end of processing period 350 may be 50% of the processing period 350. The pulsing sequence performed by the bias signal 304 and RF power pulse 302 during processing period 350 may be repeated once or multiple times as needed.

[0051]

[0059] Microburst 306 can be used to facilitate the initiation and maintenance of plasma for any processing recipe, such as the processing recipes described with respect to Figures 3 to 5. For example, as shown in Figure 4, after burst 306, the bias signal voltage may decrease to voltage V1 (e.g., 300 volts) by time 402. Then, the bias signal voltage may increase to voltage V2 (e.g., 500 volts) by time 404, and thereafter decrease to 0 volts. The RF signal power pulse 302 may be 850 watts by time 402, then reduced to 550 watts by time 404, and then reduced to 0 watts as shown.

[0052]

[0060] The duration of the microburst 306 may be relatively short to avoid adverse effects on the semiconductor being processed (e.g., undesirable etching or mask damage). Therefore, the voltage and duration of the burst 306 may be selected to start and properly maintain the plasma in the chamber without adversely affecting the semiconductor processing. In some cases, the duration of the burst 306 (e.g., 10 to 200 microseconds) may be less than 2% or 5% of the processing period 350, or less than the duration for which RF power is supplied to the chamber. Microbursts may be used to start and maintain plasma when the RF source power is 0 watts for a certain duration or longer.

[0053]

[0061] As another example shown in Figure 5, after burst 306, the voltage of the bias signal 304 may be reduced to V1 (for example, the peak voltage of the pulses forming the bias signal 304 may be 300 volts) until time 502, after which the voltage of the bias signal 304 may be reduced to 0 volts. As shown in the figure, the RF signal power pulse 302 may be set to a first power (for example, 850 watts) from the start of the processing period until time 502, and then reduced to 0 watts as shown in the figure. The exemplary pulse scheme shown in Figure 5 may include two RF power bursts, each beginning as a microburst. For example, at time 504, another burst 540 may be provided, after which the voltage of the bias signal 304 may be reduced to a voltage V2 (for example, V2 is greater than V1) until time 506, when the voltage of the bias signal 304 decreases to 0 volts. The RF signal power may be set to a second power (e.g., 550 watts) which is less than the first power between times 504 and 506, as shown in the figure, and then reduced to 0 watts. The duration from the start of processing period 350 to time 502 may be 20% of processing period 350. The duration between times 502 and 504 may be 30% of processing period 350. The duration between times 504 and 506 may be 25% of processing period 350, and the duration from time 506 to the end of processing period 350 may be 25% of processing period 350.

[0054]

[0062] Some embodiments described herein use a single burst to start and maintain plasma in a chamber, but any appropriate number of bursts may be used. For example, five bursts may be used to start and maintain plasma in a chamber. In some cases, more bursts may be used if the plasma in the chamber is off for an extended period.

[0055]

[0063] In some cases, a macrostrike method may be used to initiate plasma within the chamber, as will be explained in more detail with respect to Figure 6. For example, a macrostrike method may be used when the RF source is off for an extended period, such as between processing steps.

[0056]

[0064] Figure 6 shows a macrostrike scheme according to a particular aspect of this disclosure. As shown in Graph 600, the RF source power may be increased to W1 at the start of the processing period. As shown in Graph 610, the bias signal voltage may be increased to V1 to provide a macrostrike for initiating the plasma. The RF signal power and voltage of the bias signal may be set to W1 and V1, respectively, for the duration of the macrostrike for initiating the plasma in the chamber. After the macrostrike duration, the RF signal power may be adjusted to W2 and the bias signal voltage may be adjusted to V2 for semiconductor processing. In Graphs 600 and 610, the power W2 for semiconductor processing is less than W1 and the bias signal voltage V2 is less than V1, although in some cases W2 may be greater than W1 and V2 may be greater than V1. The macrostrike duration may be long (e.g., 1 second) if the plasma is off for a long period, such as during a cold start of the chamber.

[0057]

[0065] Figure 7 shows a macrostrike and a series of microbursts used to start and control plasma in a processing chamber according to a particular aspect of the present disclosure. As shown, semiconductor processing may involve a plurality of processing steps 1 to n (where n is a positive integer). Each processing step may be associated with a specific processing recipe (e.g., set pressure, RF power, bias voltage, and / or temperature). Between processing steps, the RF power may be turned off (e.g., zero) while the chamber conditions are stable, as shown. At the start of each processing step (e.g., if the RF power has been off for a long time), the plasma can be started in the chamber using a macrostrike as described with respect to graph 610 in Figure 6. If the RF source is turned on and off within each processing step and multiple RF power phases may be provided, a pulsed method (e.g., 100 kHz pulsing) may be used. Each time the RF source is turned on (e.g., at the start of each RF power phase other than the initial RF power phase of the step), a microburst (e.g., a single burst) may be used to start and maintain the plasma.

[0058]

[0066] If the macrostrike duration is too long relative to the processing period, the macrostrike duration may adversely affect the semiconductor processing. In other words, a long macrostrike duration may put stress on the semiconductor. In some aspects of this disclosure, the macrostrike duration may be implemented with multiple microbursts 650 (e.g., can be replaced by microbursts 650), as shown in Graph 612 of Figure 6. Microbursts may be implemented as a series of bursts having a duty cycle of 1 to 10% and a specific frequency. That is, the duration of each burst may be 1 to 10% of the total duration from the start of one burst to the next. The strike duration, including bursts 650, may be, for example, less than 1 second. In any of the various bursts disclosed herein, the duty cycle of the pulse (e.g., the ratio of the voltage of the "on time" (e.g., "ion current stage") to the period (Tp) of the pulse supplied in the burst (Figure 2)) may be, for example, between about 50% and about 95%.

[0059]

[0067] For ease of understanding, five bursts are shown in Graph 612, but any appropriate number of bursts may be used. For example, two microbursts 652 may be used, as shown in Graph 614. The strike duration may be implemented with bursts having a duty cycle of 1 to 10% per second, and each burst may contain a series of pulses having a frequency of 400 kHz.

[0060]

[0068] Certain aspects of this disclosure relate to controlling the gradient of a pulse (e.g., the pulse shown in Figure 2) to more efficiently initiate and maintain plasma in a chamber. The gradient of the PV signal pulse (e.g., controlling the rise and fall times of the PV in the sheath collapse phase, as described with respect to Figure 2) can be controlled to provide a pulse shape that improves processing performance. While gradient control improves processing performance, it can negatively impact striking (e.g., plasma initiation). With respect to plasma initiation, providing faster rise and fall times for the PV signal enables more efficient plasma striking. Faster rise and fall times can reduce the voltage of the microburst for plasma initiation, thereby reducing the risk of damaging the semiconductor or the chamber when generating plasma in the chamber. In other words, assuming that the typical rise and fall times of the PV signal are 300us for semiconductor processing, the rise and fall times can be reduced to 20-30us for plasma initiation.

[0061]

[0069] Figure 8 is a process flow diagram showing method 800 for processing a substrate in a plasma processing system according to a particular embodiment of the present disclosure. Method 800 can be performed by a plasma processing system.

[0062]

[0070] In step 810, the plasma processing system provides a bias signal to the plasma load via a PV signal generator to initiate plasma in the plasma chamber. The bias signal may include a first burst having a first duration (e.g., a microburst such as burst 306 in Figure 3).

[0063]

[0071] In step 820, the plasma processing system provides an RF signal to the plasma load via an RF signal generator for a second duration. The first duration may be less than 10% of the second duration. A first burst may occur at the start of the second duration. The RF signal may have different power levels during the second duration.

[0064]

[0072] The bias signal may include at least one second burst (e.g., burst 540) each having a third duration. The third duration may be less than 10% of the second duration. The third duration may be equal to the first duration.

[0065]

[0073] The first burst may have a first voltage. The bias signal may have a second voltage lower than the first voltage after a first duration. The second voltage may follow a semiconductor processing recipe.

[0066]

[0074] In some embodiments, the plasma processing system generates a series of bursts via a PV signal generator, including a first burst for initiating plasma in the plasma chamber at the start of the initial RF power phase in each of the multiple semiconductor processing steps (e.g., processing steps 1 to n shown in Figure 7). Each of the multiple semiconductor processing steps may include multiple RF power phases. The plasma processing system may generate a single burst via the PV signal generator at the start of each of the multiple RF power phases following the initial RF power phase for initiating plasma in the plasma chamber. The RF signal generator may transition from providing zero power to providing greater than zero power at the start of each of the multiple RF power phases.

[0067]

[0075] In some embodiments, the plasma processing system may generate at least one second burst for semiconductor processing. The rise and fall times of one or more pulses of the first burst may be less than the rise and fall times of one or more pulses of the at least one second pulse.

[0068]

[0076] The above description applies to embodiments of the present disclosure, but other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A device for processing substrates within a plasma processing system, A pulsed voltage (PV) signal generator configured to provide a bias signal to a plasma load for initiating plasma in a plasma chamber, wherein the bias signal includes a first burst having a first duration, and the first burst includes a series of pulses. A radio frequency (RF) signal generator configured to provide an RF signal to the plasma load over a second duration, wherein the first duration is less than 10% of the second duration, and the first burst occurs at the start of the second duration. A device equipped with the following features.

2. The apparatus according to claim 1, wherein the RF signal has different power levels during the second duration.

3. The apparatus according to claim 1, wherein the bias signal includes at least one second burst, each having a third duration, the third duration being less than 10% of the second duration.

4. The apparatus according to claim 3, wherein the third duration is equal to the first duration.

5. The apparatus according to claim 1, wherein the first burst has a first voltage, and the bias signal has a second voltage less than the first voltage after a first duration.

6. The apparatus according to claim 5, wherein the second voltage is determined according to a semiconductor processing recipe.

7. The PV signal generator, Each of the plurality of semiconductor processing steps generates a series of bursts, including a first burst, to start the plasma in the plasma chamber at the start of the initial RF power phase, wherein each of the plurality of semiconductor processing steps generates a series of bursts, each including a plurality of RF power phases. To generate a single burst within the plasma chamber at the start of each of the plurality of RF power phases following the initial RF power phase, The apparatus according to claim 1, configured to perform the following:

8. The apparatus according to claim 7, wherein the RF signal generator is configured to transition from providing zero power to providing greater than zero power at the start of each of the plurality of RF power phases.

9. The apparatus according to claim 1, wherein the PV signal generator is configured to generate at least one second burst for semiconductor processing, and the rise and fall times of one or more pulses of the first burst are less than the rise and fall times of one or more pulses of the at least one second burst.

10. A method for processing a substrate in a plasma processing system, To provide a bias signal to a plasma load via a pulsed voltage (PV) signal generator in order to start a plasma in a plasma chamber, wherein the bias signal includes a first burst having a first duration, and the first burst includes a series of pulses. The method involves providing an RF signal to a plasma load via a radio frequency (RF) signal generator for a second duration, wherein the first duration is less than 10% of the second duration, and the first burst occurs at the start of the second duration. Methods that include...

11. The method according to claim 10, wherein the RF signal has different power levels during the second duration.

12. The method according to claim 10, wherein the bias signal comprises at least one second burst, each having a third duration, the third duration being less than 10% of the second duration.

13. The method according to claim 12, wherein the third duration is equal to the first duration.

14. The method according to claim 10, wherein the first burst has a first voltage, and the bias signal has a second voltage less than the first voltage after the first duration.

15. The method according to claim 14, wherein the second voltage is determined according to a semiconductor processing recipe.

16. The PV signal generator generates a series of bursts, including the first burst for initiating the plasma in the plasma chamber at the start of the initial RF power phase in each of the plurality of semiconductor processing steps, wherein each of the plurality of semiconductor processing steps generates a series of bursts, each including a plurality of RF power phases. The PV signal generator generates a single burst to start the plasma in the plasma chamber at the beginning of each of the plurality of RF power phases after the initial RF power phase, The method according to claim 10, including the method described in claim 10.

17. The method according to claim 16, further comprising transitioning from providing zero power to providing greater than zero power at the start of each of the plurality of RF power phases.

18. The method according to claim 10, further comprising generating at least one second burst for semiconductor processing, wherein the rise and fall times of one or more pulses of the first burst are less than the rise and fall times of one or more pulses of the at least one second burst.

19. A plasma processing system, Plasma chamber and A pulsed voltage (PV) signal generator connected to the plasma chamber and configured to provide a bias signal to a plasma load to start a plasma in the plasma chamber, comprising a first burst having a first duration, wherein the first burst comprises a series of pulses, A radio frequency (RF) signal generator connected to the plasma chamber and configured to provide an RF signal to the plasma load over a second duration, wherein the first duration is less than 10% of the second duration, and the first burst occurs at the start of the second duration. A plasma processing system equipped with [the following features].

20. The plasma processing system according to claim 1, wherein the bias signal includes at least one second burst, each having a third duration, the third duration being less than 10% of the second duration.

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