Method and material system for tunable hybrid junction interconnect resistors

Abstract

Interconnect resistance in hybrid junction structures can be controlled and designed. The resistance of each interconnect can be controlled by the via width, the number of vias, and the thickness of the liner within the vias. The first and second interconnects of a hybrid junction structure may have different interconnect resistances, even though they are on the same wafer or chip. The techniques described herein include designing interconnects and forming interconnects with specific resistances.

Description

Technical Field

[0001] Cross - reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non - Provisional Application No. 18 / 464,926, filed on September 11, 2023, entitled "METHOD AND MATERIAL SYSTEM FOR TUNABLE HYBRID BOND INTERCONNECT RESISTANCE", and the content of such U.S. Non - Provisional Application is hereby incorporated by reference in its entirety for all purposes.

[0002]

[0002] This technology relates to semiconductor systems, processes, and devices. More specifically, this technology relates to processes and semiconductor devices for hybrid bonding.

Background Art

[0003]

[0003] Hybrid bonding (which may also be referred to as heterogeneous integration) is a semiconductor manufacturing technology that enables the miniaturization of three - dimensional semiconductor device manufacturing processes related to advanced node technologies that require heterogeneous integration. Hybrid bonding involves creating a strong bond between dies, wafers, and / or substrates without the need for adhesives or separate interconnect materials. However, each interconnect between wafers can have different resistance requirements. In designs using hybrid bonding, since it is necessary to more accurately control both individual interconnect resistance and total interconnect resistance, standard hybrid bonding technologies and systems may not be able to provide accurate control of interconnect resistance.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to improve the precise control of interconnect resistance in semiconductor manufacturing techniques using hybrid bonding. This technology addresses these needs and others.

Summary of the Invention

[0005]

[0005] In some embodiments, the method may include identifying a first interconnect among a plurality of interconnects between a first substrate and a second substrate, wherein the first substrate is configured to be hybrid bonded to the second substrate; receiving a first target resistance for the first interconnect; and determining a first design for the first interconnect such that the first interconnect has an actual resistance less than or equal to the first target resistance, wherein determining the first design for the first interconnect may include determining a first number of vias of the first interconnect, wherein the first number of vias connect a first contact pad of the first substrate to a second contact pad of the second substrate when the first substrate is hybrid bonded to the second substrate.

[0006]

[0006] In some embodiments, a method for forming a semiconductor device may include determining a first target resistance for a first interconnect between a first structure and a second structure, determining a second target resistance for a second interconnect between a first structure and a second structure, and forming the first structure, wherein forming the first structure involves forming a metal layer on a substrate, forming a dielectric layer on the metal layer, and etching a first number of vias of the first interconnect within the dielectric layer, the first number of vias being the first Based on a target resistance, the method may include etching a first set of vias, each via of which extends downward from the top surface of the dielectric layer to a first contact pad of the metal layer, and etching a second set of vias of a second interconnect within the dielectric layer, wherein each of the second set of vias extends downward from the top surface of the dielectric layer to a second contact pad of the metal layer, and the first set of vias is different from the second set of vias.

[0007]

[0007] In some embodiments, the semiconductor device may include a first structure and a second structure, the first structure may include a metal layer overlapping a substrate and a dielectric layer overlapping the metal layer and defining a first number of vias and a second number of vias, each via of the first number of vias extending downward from the upper surface of the dielectric layer to a first contact pad of the metal layer, and each via of the second number of vias extending downward from the upper surface of the dielectric layer to a second contact pad of the metal layer, the second structure may include a second metal layer overlapping a second substrate and a second dielectric layer overlapping the second metal layer, the dielectric layer defining a third number of vias in the second dielectric layer and a fourth number of vias in the second dielectric layer, Some vias of the third structure correspond to some vias of the first structure, some vias of the fourth structure correspond to some vias of the second structure, each via of the third structure extends downward from the top surface of the second dielectric layer to the third contact pad of the second metal layer, each via of the fourth structure extends downward from the top surface of the second dielectric layer to the fourth contact pad of the second metal layer, the dielectric layer of the first structure is hybrid-junctioned to the second dielectric layer of the second structure, some vias of the first structure are connected to some vias of the third structure to form a first interconnect having a first resistance, and some vias of the second structure are connected to some vias of the fourth structure to form a second interconnect having a second resistance different from the first resistance.

[0008]

[0008] In any embodiment, any and all of the following features can be implemented in any combination, without limitation. The first structure of the semiconductor device may include a first liner in a first number of vias, the first liner having a first thickness, and a second liner in a second number of vias having a second thickness, with the first and second thicknesses being different. The first liner may be located between the dielectric layer and the copper-containing material inside the first number of vias. The second liner may be located between the dielectric layer and the copper-containing material inside the second number of vias. The first number of vias may have a first width. The second number of vias may have a second width. The second structure of the semiconductor device may include a third liner in a third number of vias, the third liner having substantially a first thickness, and a fourth liner located in the second number of vias, the fourth liner having substantially a second thickness. The method also includes identifying a second interconnect among a plurality of interconnects between a first substrate and a second substrate, receiving a second target resistor for the second interconnect, and determining a second design for the second interconnect such that the second interconnect has an actual resistance less than or equal to the second target resistor, wherein determining a second design for the second interconnect is different from the second target resistor, and determining a second design for the second interconnect may include determining a second number of vias of the second interconnect, such that when the first substrate is hybrid-bonded to the second substrate, the second number of vias connect a third contact pad of the first substrate to a fourth contact pad of the second substrate. The method may also include determining a set of manufacturing parameters for manufacturing the first and second interconnects. The method may also include determining a set of manufacturing parameters for manufacturing the first and second substrates.The method also involves bringing a first structure into contact with a second structure, the second structure may include a second metal layer overlapping a second substrate, and a second dielectric layer overlapping the second metal layer, the dielectric layer defining a third number of vias in the second dielectric layer and a fourth number of vias in the second dielectric layer, wherein the third number of vias corresponds to a first number of vias, the fourth number of vias corresponds to a second number of vias, and each of the third number of vias extends downward from the upper surface of the second dielectric layer to a third contact pad of the second metal layer, and the fourth number of vias The first structure is brought into contact with the second structure and bonded to the second structure, wherein each of several vias extends downward from the upper surface of the second dielectric layer to the fourth contact pad of the second metal layer, and the dielectric layer of the first structure is hybrid bonded to the second dielectric layer of the second structure, and some of the first vias are connected to some of the third vias to form a first interconnect, and some of the second vias are connected to some of the fourth vias to form a second interconnect. Determining the first design for the first interconnect may further include determining the first width of the first vias of the first some vias. Determining the first design for the first interconnect may further include determining the second width of the second vias of the first some vias, the second width being different from the first width. Forming the first structure may further include depositing a first liner in a first number of vias, depositing a first liner having a first thickness, and depositing a second liner in a second number of vias, wherein the second liner has a second thickness, and the first and second thicknesses are different. Each of the first number of vias may have a substantially first width. Manufacturing parameters may include the length of time for forming the liners inside the first number of vias and the second number of vias of the first substrate. The particle size of the metal-containing material used in the first interconnect may be substantially the size of each of the first number of vias. The first thickness may correspond to a first width of the first number of vias. The second thickness may correspond to a second width of the second number of vias.Some of the first vias may have a first width based on a first target resistance. Some of the second vias may have a second width based on a second target resistance. Manufacturing parameters may include the length of time for forming the liner inside some of the first and second vias on the first substrate.

[0009]

[0009] A further understanding of the properties and advantages of various embodiments can be achieved by referring to the remainder of this specification and the drawings. In the drawings, similar reference numbers are used across several drawings to refer to similar components. In some cases, sublabels are associated with reference numbers to indicate one of several similar components. When a reference number is referred to without specifying an existing sublabel, it is intended to refer to all such several similar components. [Brief explanation of the drawing]

[0010] [Figure 1] A top view of one embodiment of a deposition, etching, baking, and curing chamber processing system, which may be included or configured according to several embodiments of this technology, is shown. [Figure 2] The steps of a semiconductor design method according to several embodiments of this technology are shown. [Figure 3] The following are schematic cross-sectional diagrams illustrating the structure according to several embodiments of this technology. [Figure 4] The steps of a semiconductor processing method according to several embodiments of this technology are shown. [Figures 5A-5D] The following are illustrative schematic cross-sectional views of a structure that includes a material layer and is processed, according to several embodiments of this technology. [Modes for carrying out the invention]

[0011]

[0015] By adjusting the resistance of each interconnect between the upper wafer, chip, or structure hybrid-bonded to the bottom wafer, chip, or structure, semiconductor devices requiring more precise and / or accurate interconnect resistance can be formed. Each interconnect between the upper and bottom wafers can be precisely and / or accurately tuned by controlling the number of vias in each interconnect, the metal grain size within each via, and the liner-to-metal ratio within each via. The metal grain size within each via and the liner-to-metal ratio within each via are adjustable by the width of each via.

[0012]

[0016] Conventional hybrid junction systems cannot precisely control interconnect resistance. This inability to precisely control interconnect resistance prevents hybrid junction manufacturing methods from being used in more complex chip designs. The techniques described in this document enable precise control of interconnect resistance when using hybrid junction manufacturing methods.

[0013]

[0017] Hybrid bonding may involve matching multiple interconnects between an upper wafer, chip, or structure and a lower wafer, chip, or structure. Each interconnect has resistance. When designing wafers, chips, and / or structures, chip designers may want to be able to precisely and / or precisely control the resistance of each interconnect. Chip designers may also want to be able to independently tune each interconnect resistance so that a first interconnect may have a first resistance, a second interconnect may have a second resistance, and so on. By precisely and / or precisely controlling the resistance of each interconnect, chip designers can more accurately predict chip performance and thus increase the manufacturing yield of usable wafers, chips, and / or structures. Furthermore, by precisely and / or precisely controlling interconnect resistance, it becomes possible to manufacture more complex chips and designs using hybrid bonding.

[0014]

[0018] In summary, hybrid bonding is a semiconductor manufacturing technique that combines the advantages of both direct bonding and conventional bonding methods. This allows for the integration of different materials at the molecular level, facilitating the development of advanced semiconductor devices with improved performance, functionality, and miniaturization, without the need for metal interconnects. Hybrid bonding is particularly useful for the fabrication of three-dimensional semiconductor devices.

[0015]

[0019] When a system consisting of two wafers (die, substrate, etc.) is joined to each other via a hybrid bond, the dielectric layers of the wafers are first treated to create a reactive layer via surface activation. The dielectric layers can then be brought into contact with each other and bonded, for example, by spontaneous hydrophilic oxide-oxide bonding. Once the dielectric layers are bonded, the metal pads of each wafer are separated by a dishing gap. The system can then be annealed so that the dielectric layers remain approximately the same size as the metal, while the metal pads of each wafer thermally expand and connect. Upon completion of annealing, the wafers are joined by the hybrid bond.

[0016]

[0020] The remaining disclosure will, as is customary, identify specific hybrid bonding processes that utilize the disclosed technology, but it will be readily apparent that the systems and methods are equally applicable to a variety of other processes that may occur in the described chambers. Therefore, the technology should not be considered limited to use in the described etching or deposition processes alone. Before describing the systems and methods or steps of exemplary process sequences according to several embodiments of the technology, this disclosure will discuss one possible system that can be used in the technology. It should be understood that the technology is not limited to the described apparatus, and the processes discussed can be performed in any number of processing chambers and systems.

[0017]

[0021] Figure 1 shows a top view of one embodiment of a deposition, etching, baking, and curing chamber processing system 100, which may be included or configured according to several embodiments of the present technology. In this figure, a pair of front-opening uniform pods 102 supply substrates of various sizes. These substrates are received by a robotic arm 104, placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a-f arranged in tandem sections 109a-c. A second robotic arm 110 may be used to transport substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and in the reverse direction. Each substrate processing chamber 108a-f may be equipped to perform several substrate processing steps, including periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma processing, degassing, orientation, and other substrate processing, as well as dry etching processing as described herein.

[0018]

[0022] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching material films on a substrate or wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit material on the substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to cure, anneal, or process the deposited film. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit and cure films on the substrate. Any one or more of the processes described may be performed in additional chambers separated from the manufacturing system shown in different embodiments. It will be understood that system 100 envisions further configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for material films. In addition, any number of other processing systems may be used in conjunction with this technology, and these processing systems may incorporate chambers for performing any of the specific steps. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various sections such as the aforementioned holding and transfer areas may enable processes to be executed within multiple chambers while maintaining a specific vacuum environment between individual processes.

[0019]

[0023] A chamber incorporated into System 100, or more specifically into System 100 or another processing system, may be used to manufacture structures according to some embodiments of the present technology.

[0020]

[0024] FIG. 2 shows a flow diagram of exemplary steps in a method 200 for designing and / or controlling the resistance of an interconnect between hybrid junction structures for enabling control of the resistance of each interconnect according to some embodiments of the present technology. Method 200 may include one or more steps before the start of method 200. Method 200 may include a number of optional steps, which may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. Method 200 can describe the steps schematically shown in relation to FIG. 3, the illustration of which is described in conjunction with the steps of method 200. It should be understood that the figures show only partial schematics, and substrate 302 may include any number of additional materials and features (characteristics) having various characteristics and aspects as shown in the figures.

[0021]

[0025] It should be understood that the specific steps shown in FIG. 2 provide a specific method for designing and / or controlling the resistance of an interconnect between hybrid junction structures according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Further, the individual steps shown in FIG. 2 may include a plurality of sub-steps, and the plurality of sub-steps may be performed in various sequences depending on the individual steps. Further, additional steps may be added or removed depending on a particular application. Many variations, modifications, and alternatives are also included within the scope of the present disclosure.

[0022]

[0026] In step 202, the method of designing and / or controlling the resistance of the interconnect between the hybrid junction structures in flowchart 200 may include identifying the first interconnect. As shown in Figure 3, the design of the hybrid junction structure 300 includes the first structure 301 which is hybrid-junctioned to the second structure 302. A more detailed description of the method for forming the hybrid junction structure 300, the first structure 301, and the second structure 331 is described below in relation to Figures 4 and 5A to 5D. Part of designing the hybrid junction structure 300 may include designing and creating the interconnect between the first structure 301 and the second structure 302. The first interconnect 310 can connect the first contact pad 312 of the first structure 301 to the second contact pad 322 of the second structure 302. The first structure 301 may include a first via 314 in a dielectric layer filled with a metal-containing material. The first via 314 may be lined with a liner 316 to separate the metal-containing material from the dielectric layer. Similarly, the second structure 302 may include a second via 324 within a second dielectric layer filled with the metal-containing material. The second via 324 may be lined with a second liner 326 to separate the metal-containing material from the second dielectric layer. The hybrid junction structure may include multiple interconnects, as shown in Figure 3.

[0023]

[0027] In step 204, the method of designing and / or controlling the resistance for the interconnect between the hybrid junction structures in flowchart 200 may include receiving a first target resistance. The first target resistance may be the target resistance of the first interconnect 310. In some embodiments, the first target resistance may be an upper limit resistance such that the interconnect must be less than the resistance. In some embodiments, the first target resistance may be a lower limit resistance such that the interconnect must be greater than the resistance. In some embodiments, the first target resistance may be a range such that the interconnect must be within the resistance range.

[0024]

[0028] In operation 206, the method of flowchart 200 for designing and / or controlling the resistance of an interconnect between hybrid junction structures may include determining the design of a first interconnect. In some embodiments, the first interconnect 310 may be designed to have a resistance that is approximately or less than a first target resistance. In some embodiments, the first interconnect 310 may be designed to have a resistance that is about one or more resistances of the first target resistance. In some embodiments, the first interconnect 310 may be designed to have a resistance within a range around the first target resistance. The resistance of an interconnect can be affected in multiple ways. A first factor in the resistance of an interconnect can include the metal grain size of the metal within the interconnect. As the metal grain size increases, the resistance of the interconnect can decrease. The metal grain size of an interconnect can be substantially the width of the interconnect (or a via that makes up the interconnect). Thus, a wider interconnect is more likely to have a lower resistance than a smaller interconnect.

[0025]

[0029] A second factor in the resistance of an interconnect can include several vias. As the number of several vias of equal width within an interconnect increases, the resistance of the interconnect may decrease. In some examples, an interconnect having several vias may have vias of different widths. By having several vias of different widths in a single interconnect, a more accurate design of the interconnect may be possible.

[0026]

[0030] A third factor in interconnect resistance may include the ratio of metal to liner. A thicker liner between the metal and contact pad within a via can increase interconnect resistance. In some examples, the thickness of the liner between the metal and contact pad within a via may be a result of the process used to form the liner within the via. In some embodiments, the liner can be formed by chemical vapor deposition. In some embodiments, the liner can be formed by atomic layer deposition. Some processes for forming the liner may result in a thicker liner in wider vias on the same substrate than in thinner vias on the same substrate. In some examples, the width of the via may be a factor in the thickness of the liner between the metal-containing material and contact pad within the via.

[0027]

[0031] In some embodiments, as shown in Figure 3, a wide interconnect, such as the first interconnect 310, may have lower resistance than the second interconnect 320, which contains three thinner vias. Other factors may also affect the resistance of the interconnect. These other factors may include manufacturing parameters for producing the first and second structures. Manufacturing parameters may affect the thickness of the liner within the vias. For example, the length of time it takes to form the liner within the vias may affect the via thickness.

[0028]

[0032] In step 208, the method of designing and / or controlling the resistance for the interconnect between the hybrid bond structures in flowchart 200 may include determining a second design for the second interconnect. Determining the second design may include taking into account the design specifications of the first interconnect 310. For example, since the first interconnect 310 and the second interconnect 320 are located on the same hybrid bond structure, the manufacturing parameters of the first interconnect 310 and the second interconnect 320 may be the same. For example, the first interconnect 310 and the second interconnect 320 may have the same liner forming process. However, as mentioned above, the liner thickness may differ between the first interconnect 310 and the second interconnect 320. The liner thickness in the first interconnect 310 and the second interconnect 320 can be determined during the design process. Determining a second design for the second interconnect 320 may include identifying the second interconnect of the hybrid junction structure 300. Determining a second design for the second interconnect 320 may also include receiving a second target resistance. Determining a second design for the second interconnect 320 may include determining a second number of vias of the second interconnect. Determining a second design for the second interconnect 320 can be done in much the same way as determining the first design. In some embodiments, the first interconnect 310 and the second interconnect 320 may have different target resistances. In some embodiments, the first interconnect 310 and the second interconnect 320 may have vias of different widths. In some embodiments, the first interconnect 310 and the second interconnect 320 may have a different number of vias. In some embodiments, the first interconnect 310 and the second interconnect 320 may have liners of different thicknesses.

[0029]

[0033] Figure 4 shows an exemplary step flow diagram in Method 400 for forming a semiconductor device 500 for a hybrid junction that enables control of the resistance of each interconnect according to several embodiments of the present technology. Method 400 may be performed in various processing chambers in which the process may be carried out, such as the chamber incorporated into the System 100 described above. Method 400 may include one or more steps prior to the commencement of Method 400, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that may be performed prior to the described steps. Method 400 may include a number of optional steps that may or may not be specifically associated with some embodiments of the method according to embodiments of the present technology. Method 400 can describe the steps schematically shown in Figures 5A to 5D, and the illustrations thereof will be described in conjunction with the steps of Method 400. The figures show only partial schematics, and it should be understood that the substrate 502 may include any number of additional materials and features having various properties and embodiments, as shown in the figures.

[0030]

[0034] It should be understood that the specific steps shown in Figure 4 provide a specific method for forming a semiconductor device 500 for a hybrid junction according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in Figure 4 may include a plurality of substeps, which may be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0031]

[0035] Figures 5A to 5D illustrate progressive structures for forming a semiconductor device 500 for a hybrid junction according to several embodiments. The method of flow diagram 400 describes the steps schematically shown in Figures 5A to 5D, and its illustration is described in conjunction with the steps of this method. The drawings show only partial schematic diagrams with limited detail, and it should be understood that in some embodiments the substrate may include any number of semiconductor regions having the embodiments shown in the drawings, as well as alternative structural embodiments from which benefits can still be obtained from any of the embodiments of this art.

[0032]

[0036] In step 402, the method of forming the first structure 501 in flowchart 400 may include forming a metal layer 504 on a substrate 502. As shown in Figure 5A, the structure 500 may include a substrate 502. In various embodiments, the substrate 502 may have a substantially planar surface or a non-uniform surface. The substrate 502 may be made of materials such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, silicon-on-insulator, carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, or sapphire. The substrate 426 may have various dimensions, such as wafers with a diameter of 400 mm or 300 mm, and rectangular or square panels. The substrate 502 may be placed within the processing area of ​​a semiconductor processing chamber. Although shown as a planar substrate, it should be understood that substrate 502 is included simply to represent the underlying structure and may include any number of layers or features on a wafer or other substrate on which structures such as those described below may be formed.

[0033]

[0037] As shown in Figure 5A, the structure 500 forming the first structure 501 may include a metal layer 504. The metal layer 504 may include various integrated circuits. For example, the integrated circuit can be fabricated using techniques such as CMOS, NMOS, or any other suitable integrated circuit technique. Thus, the metal layer 504 may include various layers of metal, oxide, and semiconductor. The metal used in the metal layer may include copper or any other highly conductive metal. Although copper is discussed periodically in this application, it should be understood that any number of conductive metallic materials may be used in embodiments of the art, and the art should not be limited to any particular conductive metallic material. The metal layer 504 may include contact pads 503 that connect vias to integrated circuits within the metal layer 504.

[0034]

[0038] In some embodiments, the layers described herein (e.g., the substrate 502, the metal layer 504, and the barrier film 506, and other layers described herein such as the dielectric layer 508) can overlap each other directly, such that the first layer overlaps the second layer. For example, the metal layer 504 can overlap the substrate 502 directly, such that there is no intervening layer. In some embodiments, the layers described herein may have layers between them. For example, the metal layer 504 may overlap an intervening layer that overlaps the substrate 502. Furthermore, any process for forming or depositing materials can be used when forming the layers. For example, chemical vapor deposition (CVD) can be used in some embodiments, and atomic layer deposition (ALD) can be used in other embodiments. Details relating to specific layers and / or materials are also described herein.

[0035]

[0039] In step 404, the method of forming the first structure 501 in flowchart 400 may include forming a dielectric layer 508 on the metal layer 504. As shown in Figure 5A, the dielectric layer 508 may comprise one or more layers of dielectric material. Exemplary dielectric materials may include silicon oxide, tetraethyl orthosilicate (also known as TEOS or TeOs), silicon carbonitride (SiCN), silicon oxynitride (SiON), or any other type of dielectric material. In some embodiments, the dielectric layer 508 may be TEOS. In some embodiments, the dielectric layer 508 may be silicon oxide.

[0036]

[0040] In some examples, the first structure 501 may include a barrier film 506 between the dielectric layer 508 and the metal layer 504. The barrier film 506 may have a low dielectric constant to reduce the dielectric constant of the copper damascene structure in order to realize faster and stronger devices. Some barrier films may have a dielectric constant of less than 5 or lower. Exemplary barrier films include silicon nitride films and low dielectric constant barrier films such as BLoK (Si-CH compound) or N-BLoK (Si-CHN compound) developed by Applied Materials. The barrier film 506 may also be called a capping layer of the metal layer 504.

[0037]

[0041] In some embodiments, the formation of each of the dielectric layer 508, barrier film 506, metal layer 504, and / or substrate 502 can be carried out in different chambers. In some embodiments, the formation of the dielectric layer 508, barrier film, metal layer 504, and / or substrate 502 can be carried out in a single chamber.

[0038]

[0042] In step 406, the method of forming the first structure 501 in flowchart 400 may include etching features into the dielectric layer 508 and the barrier film 506 (if applicable). Features etched into the dielectric layer 508 may include trenches, openings, vias, or any other structures useful for semiconductor processing. As shown in Figure 5B, the structure 500 may include a first via 520, a second via 560, and a third via 570 within the dielectric layer 508. The first via 520, the second via 560, and the third via 570 may extend downward from the upper surface of the dielectric layer 508 to at least the upper surface of the metal layer 504. In this way, the first via 520, the second via 560, and the third via 570 extend from the upper surface of the dielectric layer 508 to the contact pad 503. Generally, vias are used to form interconnects when the first structure 501 is hybrid-bonded to another structure. As shown in Figure 5B, the first via 520 may be wider than the second via 560. Next, the second via 560 may be wider than the third via 570. The widths of the first via 520, the second via 560, and the third via 570 may be designed to provide different interconnect resistances when the vias are connected to corresponding vias from other structures, as described later (as explained in relation to Figures 2 and 3 above). Similarly, several vias connected to the contact pads may be different to control the interconnect resistance, as described in this document. Although only six vias are shown in the figure, it should be understood that according to embodiments of this technology, the exemplary structure may have any number of features defined along the structure.

[0039]

[0043] The etchants used to etch features in the dielectric layer 508 and the barrier film 506 may include a variety of semiconductor processing etchings, such as chlorine, fluorine, oxygen plasma, or solutions or plasmas of fluorine and oxygen. In some embodiments, etchants may be applied one at a time. In some embodiments, multiple etchants can be combined to form a multi-material etching. In some embodiments, fluorine etching can be used on the TEOS layer of the dielectric layer 508. In some embodiments, ashing etching, such as oxygen plasma, can be used to remove organic matter. In some embodiments, fluorine and oxygen etching can be used on the BLoK layer or n-BLoK layer of the dielectric layer 508. In some embodiments, one or more etchings may be dry reactive ion etchings. In some embodiments, one or more etchings may be wet etchings. Different etchants may have selectivity for different layers, so that when an etchant is used, it primarily etches the target layer rather than other layers exposed to etching. For example, fluorine etching used on the TEOS layer of the dielectric layer 508 may selectively etch the TEOS layer. The etching selectivity is such that the target layer can be etched at a rate of approximately 1.5:1 or higher compared to one or more other layers, and can be approximately 1.6:1 or higher, approximately 1.7:1 or higher, approximately 1.8:1 or higher, approximately 1.9:1 or higher, approximately 2.0:1 or higher, approximately 2.1:1 or higher, approximately 2.2:1 or higher, approximately 2.3:1 or higher, approximately 2.4:1 or higher, approximately 2.5:1 or higher, approximately 2.6 or higher, approximately 2.7:1 or higher, approximately 2.8:1 or higher, approximately 2.9:1 or higher, approximately 3.0:1 or higher, or higher.

[0040]

[0044] In step 408, the method of forming the first structure 501 in flowchart 400 may include filling the features with a metal-containing material. As shown in Figure 5C, the structure 500 may include a metal-containing material 522 within a first via 520. The metal-containing material 522 may be a highly conductive material that can be used as an interconnect between integrated circuits. In some examples, the metal in the metal-containing material 522 includes copper, such that the metal-containing material 522 is a copper-containing material. The metal used to fill the features may include copper or any other highly conductive metal. Although copper is discussed periodically in this application, it should be understood that any number of conductive metallic materials may be used in embodiments of the Art, and the Art should not be limited to any particular conductive metallic material.

[0041]

[0045] In some examples, a liner is formed within the vias before the vias are filled with the metal-containing material. As shown in Figure 5C, the structure 500 may include a liner 524 within the first via 520 such that the liner is present between the first via 520 in the dielectric layer 508 and the metal-containing material 522. In some embodiments, the liner 524 may be tantalum nitride or any other suitable liner material incorporated to limit or prevent the diffusion of metal into the dielectric material.

[0042]

[0046] Similarly, liner 564 may be formed within the second via 560, and liner 574 may be formed within the third via 570. The thickness of the liner may be related to the width of the via. For example, the second via 560 is thinner than the first via 520 (e.g., narrower in width). Here, liner 564 may be thinner than liner 524. Similarly, liner 574 may be thinner than liner 564 because the third via 570 is thinner than the second via 560.

[0043]

[0047] In some examples, after the features are filled with the metal-containing material 522, the first structure 501 may be polished via a chemical mechanical polishing (CMP) process. After the first structure 501 has been polished via the CMP process, the upper surface of the metal-containing material 522 may be recessed relative to the upper surface of the dielectric layer 508, for example, as shown in Figure 5C. The CMP process may cause the upper surface of the metal-containing material to form a recessed or dished shape characterized by a nadia or dish depth, respectively, which is the difference in height between the lowest point in the metal and the surface in the dielectric material where the feature is formed, or the difference in edge height of the metal within the feature. If the depth of the recess from the upper surface of the metal-containing material 522 to the upper surface of the dielectric layer 508 combined with the nadia or dish depth (referred to as the combined depth) is too large, the material may not be useful for a particular end product. For example, copper-to-copper hybrid bonding is one such application that can be sensitive to inaccurate combined depths. In some applications of copper-copper hybrid junctions, if the combined depth is too large, the copper-copper bond may not be strong enough, or may not occur at all, due to limited contact between the mating feature and the stud. Combined depths of less than 5 nm may be small enough, for example, for copper-to-copper hybrid junctions.

[0044]

[0048] In some embodiments, the liner 524 may be polished by a CMP process so that its upper surface aligns with the upper surface of the dielectric layer 508. In some embodiments, the liner 524 may be polished via a CMP process so that its upper surface aligns with the upper surface of the metal-containing material 522, as shown in Figure 5C. In some examples, the liner 524 may be polished via a CMP process so that its upper surface is recessed relative to the upper surface of the metal-containing material 522 and protrudes relative to the upper surface of the dielectric layer 508.

[0045]

[0049] In step 410, the method of flow chart 400 may further include bonding the first structure 501 to the second structure 531 via a hybrid bond, as shown in Figure 5D. In some embodiments, the second structure 531 is similar to the first structure 501 in the layout, layers, and materials used. The second structure 531 may include a second metal layer 534 overlapping the second substrate 532. The second metal layer 534 may be similar to the metal layer 504 so that all descriptions of the metal layer 504 are applicable to the second metal layer 534. The second substrate 532 may be similar to the substrate 502 so that all descriptions of the substrate 502 are applicable to the second metal substrate 532. The second structure 531 may further include a second dielectric layer 538 overlapping the second metal layer 534 and defining a second set of one or more features within the second dielectric layer 538. The second dielectric layer 538 of the second structure 531 may be similar to the dielectric layer 508 of the first structure 501, such that all descriptions of the dielectric layer 508 are applicable to the second dielectric layer 538. In some embodiments, the second structure 531 may include a second barrier film 536 between the second dielectric layer 538 and the second metal layer 534. The second barrier film 536 may be similar to the barrier film 506, such that all descriptions of the barrier film 506 are applicable to the second barrier film 536. The second structure 531 may include a second metal-containing material 554 deposited within a second set of one or more features. The second metal-containing material 554 may be similar to the metal-containing material 522, such that all descriptions of the metal-containing material 522 are applicable to the second metal-containing material 554. In some embodiments, the material used for the metal-containing material 522 is the same material used for the second metal-containing material 554. In some embodiments, the second structure 531 may include a second contact pad 533. The second metal-containing material 554 can connect the second contact pad 533 to the metal-containing material 522 and the contact pad 503 in order to form an interconnect between the first structure 501 and the second structure 531.In some embodiments, the second structure 531 may include the second liner 554 within a second set of one or more features, such that the second liner 554 lies between a second set of one or more features in the second dielectric layer 538 and the second metal-containing material 554. The second liner 554 may be similar to liner 524, such that all descriptions of liner 524 are applicable to the second liner 554. In some embodiments, the first structure 501 may be considered hybrid-bonded to the second structure 531. In some embodiments, the dielectric layer 508 may be considered hybrid-bonded to the second dielectric layer 538. In some embodiments, the metal-containing material 522 may be considered hybrid-bonded to the second metal-containing material 554.

[0046]

[0050] In some embodiments, bonding the first structure 501 to the second structure 531 may involve using a surface activation process on the first structure 501 and / or the second structure 531. The surface activation process may involve contacting the first structure 501 and / or the second structure 531 with a hydrogen-containing precursor. The surface activation process can activate the upper surface of the dielectric layer 508 of the first structure 501 and / or the upper surface of the second dielectric layer 538 of the second structure 531 such that one or both of its surfaces are hydroxylated to have dangling hydroxyl groups. In some embodiments, water is then applied to the upper surface of the dielectric layer 508 of the first structure 501 and / or the upper surface of the second dielectric layer 538 of the second structure 531.

[0047]

[0051] Next, the upper surface of the dielectric layer 508 of the first structure 501 and the upper surface of the second dielectric layer 538 of the second structure 531 can be aligned and brought into contact. The upper surface of the dielectric layer 508 of the first structure 501 and the upper surface of the second dielectric layer 538 of the second structure 531 are aligned to form an interconnect between the vias of the first structure 501 and the vias of the second structure 531. When the upper surface of the dielectric layer 508 comes into contact with the upper surface of the second dielectric layer 538, a spontaneous coupling occurs mainly via van der Waals coupling, and an initial coupling is established between the upper surface of the dielectric layer 508 and the upper surface of the second dielectric layer 538. As a result, the first structure 501 and the second structure 531 are joined to each other through the contact between the upper surface of the dielectric layer 508 and the upper surface of the second dielectric layer 538. The initial bond between the first structure 501 and the second structure 531 may not be the final bond, but it can be used to keep the first structure 501 and the second structure 531 aligned as additional processes are performed to finalize the hybrid bond.

[0048]

[0052] The combined structure of the first structure 501 and the second structure 531 can then be annealed. During the annealing process, the dielectric layer 508 and the second dielectric layer 538 may further form oxide-oxide covalent bonds that increase the junction strength between the dielectric layer 508 and the second dielectric layer 538. In some embodiments, water and / or dangling hydroxyl groups help to form oxide-oxide covalent bonds between the dielectric layer 508 and the second dielectric layer 538. Once oxide-oxide covalent bonds are formed between the dielectric layer 508 and the second dielectric layer 538, the bonds between the dielectric layer 508 and the second dielectric layer 538 may be indistinguishable from the bonds within the dielectric layer 508 and / or the second dielectric layer 538.

[0049]

[0053] Annealing of the combined structure can also extrude the metal-containing material 522 toward the second metal-containing material 554. As previously mentioned, the combined depth of the metal-containing material 522 (and by extension of the second metal-containing material 554) is important for the bonding of the metal-containing materials. If the combined depth is 5 nm or less, the subsequent annealing for bonding the metal-containing material 522 and the second metal-containing material 554 can be effective because the metal-containing material 522 and the second metal-containing material 554 can come close enough to bond to each other during the annealing step of the hybrid bond. During the annealing step, the metal-containing materials from the two structures can be extruded toward each other, come into contact with each other, and bond. Furthermore, during the annealing step (and other steps), the metal grain size of the metal-containing material 522 and the second metal-containing material 554 can grow. At some point before the end of the annealing step, the metal grain size of the metal-containing material 522 and the second metal-containing material 554 can be set to the size of the vias containing the metal-containing material. With the reduction in annealing temperature according to some embodiments of this technology, the amount of expansion may be insufficient to allow proper bonding between coppers unless dishing is sufficiently reduced. By performing a polishing step according to this technology, dishing can be reduced, thereby improving the bonding ability between substrates at a reduced annealing temperature.

[0050]

[0054] An interconnect is formed between the first structure 501 and the second structure 531 by joining the metal-containing material 522 and the second metal-containing material 554. Each interconnect has resistance. As described herein, the resistance of each interconnect can be precisely and / or precisely controlled. The resistance of each interconnect can be controlled and / or designed by adjusting the via width, the number of vias, and the thickness of the liner within the vias, as described herein.

[0051]

[0055] Once the annealing process is complete, the first structure 501 and the second structure 531 are hybrid-junctioned to form a single semiconductor device or a single structure. Using hybrid junctions makes it possible to manufacture complex semiconductor devices from multiple structures and to form interconnects between them.

[0052]

[0056] In some embodiments, different steps (e.g., steps 402, 404, 406, 408, 410) and parts of different steps can be carried out in different chambers of system 100. When the substrate is moved from the first chamber to the second chamber, the substrate moves without being exposed to the external atmosphere. For example, step 404 for forming a dielectric layer on a metal layer can be carried out in a different chamber than step 410 for hybrid bonding the two structures. The use of different chambers may relate to different conditions required for different steps.

[0053]

[0057] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0054]

[0058] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0055]

[0059] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0056]

[0060] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0057]

[0061] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may sometimes describe processes as sequential, many processes can be executed in parallel or simultaneously. Moreover, the order of processes may be rearranged. A process terminates when a process is completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0058]

[0062] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0059]

[0063] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0060]

[0064] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0061]

[0065] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical discs, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. It is a method, Identifying a first interconnect among a plurality of interconnects between a first substrate and a second substrate, wherein the first interconnect is configured such that the first substrate is hybrid-bonded to the second substrate. Receiving the first target resistor for the first interconnect, The first design for the first interconnect is determined such that the first interconnect has an actual resistance less than or equal to the first target resistance, Including determining the first design for the first interconnect, The process includes determining a number of first vias of the first interconnect, such that when the first substrate is hybrid-bonded to the second substrate, the number of first vias connects a first contact pad of the first substrate to a second contact pad of the second substrate. method.

2. Determining the first design for the first interconnect is The method according to claim 1, further comprising determining a first width of a first via among a number of first vias.

3. Determining the first design for the first interconnect is The method according to claim 2, further comprising determining a second width of a second via among several first vias, wherein the second width is different from the first width.

4. The method according to claim 2, wherein each of the first of the vias is substantially the first width.

5. Identifying the second interconnect among the plurality of interconnects between the first substrate and the second substrate, Receiving a second target resistor for the second interconnect, Determining a second design for the second interconnect such that the second interconnect has an actual resistance less than or equal to the second target resistance, wherein the first target resistance is different from the second target resistance, Further including determining the second design for the second interconnect, The method according to claim 1, comprising determining a second number of vias of the second interconnect, wherein, when the first substrate is hybrid-bonded to the second substrate, the second number of vias connect a third contact pad of the first substrate to a fourth contact pad of the second substrate.

6. The method according to claim 5, further comprising determining a set of manufacturing parameters for manufacturing the first interconnect and the second interconnect.

7. The method according to claim 6, wherein the manufacturing parameter includes the length of time for forming a liner inside some first vias and some second vias of the first substrate.

8. The method according to claim 1, wherein the particle size of the metal-containing material used in the first interconnect is substantially equal to the size of each of the first vias.

9. A method for forming a semiconductor device, Determining a first target resistance for the first interconnect between the first structure and the second structure, Determining a second target resistance for a second interconnect between the first structure and the second structure, To form the structure of the above 1, Including, forming the structure of the above first, Forming a metal layer on a substrate, Forming a dielectric layer on the aforementioned metal layer, Etching a number of first vias of the first interconnect within the dielectric layer, wherein the number of first vias is based on the first target resistance, and each of the first vias extends downward from the upper surface of the dielectric layer to the first contact pad of the metal layer. Etching a second number of vias of the second interconnect within the dielectric layer, wherein each of the second number of vias extends downward from the upper surface of the dielectric layer to the second contact pad of the metal layer, and the first number of vias is different from the second number of vias, based on the second target resistance, method.

10. Forming the structure of the first step A first liner having a first thickness is deposited in some of the first vias, The method according to claim 9, further comprising depositing a second liner having a second thickness different from the first thickness in some of the second vias.

11. The method according to claim 10, wherein the first thickness corresponds to a first width of some of the first vias, and the second thickness corresponds to a second width of some of the second vias.

12. The method described above is The first structure is brought into contact with the second structure, wherein the second structure is A second metal layer overlapping the second substrate, A second dielectric layer overlapping the second metal layer, the second dielectric layer defining several third vias and several fourth vias within the second dielectric layer, wherein the several third vias correspond to several first vias, the several fourth vias correspond to several second vias, each via of the several third vias extends downward from the upper surface of the second dielectric layer to the third contact pad of the second metal layer, and each via of the several fourth vias extends downward from the upper surface of the second dielectric layer to the fourth contact pad of the second metal layer, thereby bringing the first structure into contact with the second structure. The method according to claim 9, further comprising joining the first structure to the second structure, wherein the dielectric layer of the first structure is hybrid-joined to the second dielectric layer of the second structure, some of the first vias are connected to some of the third vias to form the first interconnect, and some of the second vias are connected to some of the fourth vias to form the second interconnect.

13. The method according to claim 12, wherein some of the first vias have a first width based on the first target resistance, and some of the second vias have a second width based on the second target resistance.

14. The method according to claim 9, further comprising determining a set of manufacturing parameters for manufacturing a first substrate and a second substrate.

15. The method according to claim 14, wherein the manufacturing parameter includes the length of time for forming a liner inside some first vias and some second vias of the first substrate.

16. It is a semiconductor device, The first structure, The second structure, The first structure is equipped with, A metal layer overlapping the substrate, The device comprises a dielectric layer overlapping the metal layer and defining a number of first vias and a number of second vias, wherein each of the first vias extends downward from the upper surface of the dielectric layer to a first contact pad of the metal layer, and each of the second vias extends downward from the upper surface of the dielectric layer to a second contact pad of the metal layer. The second structure described above is A second metal layer overlapping the second substrate, A second dielectric layer overlapping the second metal layer, comprising a second dielectric layer defining several third vias and several fourth vias within the second dielectric layer, wherein the several third vias correspond to several first vias, the several fourth vias correspond to several second vias, each via of the several third vias extends downward from the upper surface of the second dielectric layer to the third contact pad of the second metal layer, and each via of the several fourth vias extends downward from the upper surface of the second dielectric layer to the fourth contact pad of the second metal layer. The dielectric layer of the first structure is hybrid-junctioned to the second dielectric layer of the second structure, some of the first vias are connected to some of the third vias to form a first interconnect having a first resistance, and some of the second vias are connected to some of the fourth vias to form a second interconnect having a second resistance different from the first resistance. Semiconductor devices.

17. The semiconductor device according to claim 16, wherein some of the first vias have a first width and some of the second vias have a second width.

18. The first structure is A first liner having a first thickness in some of the first vias, The semiconductor device according to claim 16, further comprising a second liner having a second thickness different from the first thickness, located within some of the second vias.

19. The semiconductor device according to claim 18, wherein the first liner is located between the dielectric layer and the copper-containing material inside the first vias, and the second liner is located between the dielectric layer and the copper-containing material inside the second vias.

20. The second structure described above is A third liner having substantially the first thickness within some of the third vias, The semiconductor device according to claim 19, further comprising a fourth liner having substantially the second thickness within some of the second vias.

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