Dual field-effect transistor 4F2 cell

Abstract

This technology generally relates to vertical dynamic random access memory (DRAM) cells and arrays that include a shared word line between two adjacent channels, and to methods for forming such cells and arrays. A cell includes a first horizontally arranged bit line, a first channel, a second channel, and a second horizontally arranged shared word line between the first and second channels. The cell includes cases where the first channel and the second channel extend vertically, substantially orthogonal to the first and second horizontal directions, such that the bit line intersects the source / drain regions of the first and second channels, and the shared word line intersects the gate regions of both the first and second channels.

Description

[Technical Field]

[0001]

[0001] This application is for the "DUAL FIELD EFFECT TRANSISTOR 4F" filed on June 20, 2023. 2 We claim the interests and priority of U.S. Patent Application No. 63 / 509,209, entitled “CELL”, which is incorporated herein by reference in its entirety.

[0002]

[0002] This disclosure generally refers to 4F 2 This disclosure describes the design of a two-dimensional dynamic random access memory array. More specifically, this disclosure describes a 4F array with reduced floating body effects. 2 Let's discuss memory arrays. [Background technology]

[0003]

[0003] Advances in computing technology have made computing devices smaller and increased their processing power. Therefore, it is necessary to increase storage and memory to meet the programming and computing needs of the devices. By increasing the number of storage units with smaller form factors, miniaturization of devices with increased storage capacity can be achieved.

[0004]

[0004] Dynamic Random Access Memory (DRAM) architectures have been shrinking over time. For example, a one-transistor, one-capacitor (1T-1C) DRAM cell architecture is 8F 2 Sizes up to 6F 2 We successfully reduced the size to 6F (where F is the minimum feature size). 2 From 4th floor 2Further design scheme modifications could help improve area density. DRAM cell manufacturing involves the production of transistors, capacitors, and three contacts (one each for bit lines, word lines, and reference voltage). There is a continuous desire to reduce the size of individual cells and increase memory cell density, enabling more memory to be included on a single memory chip, especially at densities exceeding 256 megabits. However, further increases in density have proven problematic. Therefore, improvements in this field are needed. [Overview of the Initiative]

[0005]

[0005] Embodiments of the present technology generally relate to a vertical dynamic random access memory (DRAM) cell that includes a shared word line between two adjacent channels. The cell includes a first horizontally arranged bit line, a first channel, a second channel, and a second horizontally arranged shared word line between the first channel and the second channel. The cell includes cases where the first channel and the second channel extend vertically, substantially orthogonal to the first and second horizontal directions, such that the bit line intersects the source / drain regions of the first and second channels, and the shared word line intersects the gate regions of both the first and second channels.

[0006]

[0006] In embodiments, the cell includes a case where the vertical dynamic random access memory cell contains only one word line for every two channels. In more embodiments, the first dielectric layer extends along the first side from the first end of the word line trench to the second end of the word line trench, and the second dielectric layer extends on the opposite side from the first side from the first end of the word line trench to the second end of the word line trench. In further embodiments, the first dielectric layer is formed from a material having a first work function, and the second dielectric layer is formed from a material having a second work function, wherein the first work function is different from the second work function.

[0007]

[0007] In the embodiment, the first side of the word line trench is adjacent to the first channel, and the second side is adjacent to the second channel. In an additional embodiment, the first channel is an n-MOS channel, and the second channel is a p-MOS channel. Additionally or alternatively, in the embodiment, the first dielectric material includes a positive work function material. In the embodiment, the first dielectric layer material includes an oxide containing a metallic substance having a Fermi level lower than that of aluminum (Al), niobium (Nb), tantalum (Ta), hafnium (Hf), or a combination thereof. In yet another embodiment, the second dielectric layer material includes a negative work function material. In yet another embodiment, the second dielectric layer material includes an oxide containing one or more lanthanum species or combinations thereof.

[0008]

[0008] The technology also covers vertical cell dynamic random access memory (DRAM) arrays having generally reduced size and increased memory density. The array includes a first vertical dynamic random access memory cell located adjacent to a second vertical dynamic random access memory cell. Each cell includes a first horizontally positioned bit line, a first channel, a second channel, and a second horizontally positioned word line between the first and second channels. The cell includes cases where the first channel and the second channel extend vertically, substantially orthogonal to the first and second horizontal directions, such that the bit line intersects the source / drain regions of the first and second channels, and the word line intersects the gate regions of both the first and second channels. The array further includes an electrical insulator between the first vertical dynamic access memory cell and the second vertical dynamic random access memory cell.

[0009]

[0009] In some embodiments, the first vertical dynamic random access memory cell and the second vertical dynamic random access memory cell each include only one word line for every two channels. In more embodiments, the array includes a third vertical dynamic random access memory cell adjacent to the second vertical dynamic random access memory cell, with an electrical insulator placed between the second vertical dynamic random access memory cell and the third vertical dynamic random access memory cell, and the third vertical dynamic access memory cell includes a shared word line between two adjacent channels. In further embodiments, the electrical insulator includes one or more dielectric materials, air gaps, or a combination thereof. In more embodiments, the array includes bit lines and a substrate layer placed between the source / drain regions of the first and second channels.

[0010]

[0010] The technology also generally covers methods for forming vertical dynamic random access memory (DRAM) cells and arrays. The method involves etching a word line trench between a first vertically extending channel and a second vertically extending channel, the word line trench having a first end opposite to the second end and a first side opposite to the second side. The method involves forming a shared word line within the word line trench such that the word line intersects the gate regions of both the first vertically extending channel and the second vertically extending channel.

[0011]

[0011] In embodiments, the method includes lining a word line trench with a gate dielectric before forming a shared word line. In further embodiments, the method includes forming a first dielectric material on the gate dielectric along a first side of the word line trench and forming a second dielectric material on the gate dielectric along a second side of the word line trench. In further embodiments, the method includes forming a substrate by sidewall epitaxy on a vertical dynamic random access memory cell adjacent to the second end of the word line trench and the bit line layer of the substrate layer. In yet another embodiment, the method includes the case where the substrate layer is formed from alternating layers of p-type substrate material, selective etching material, and n-type substrate material. Additionally or alternatively, in embodiments, the method includes removing the selective etching material and forming source / drain connections between a vertically extending first channel and the bit line, and between a vertically extending second channel and the bit line.

[0012]

[0012] Such technologies can offer numerous advantages over conventional systems and techniques. For example, processes and devices can reduce the number of word lines required, enabling increased memory density and reduced word line pitch. That is, processes and devices can significantly increase memory density while maintaining excellent electrical response and characteristics, and the increase in density may be shown in conjunction with an increase in word line width. These embodiments and other embodiments, along with their many advantages and features, are described in detail in the following description and accompanying drawings.

[0013]

[0013] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0014] [Figure 1A] This shows a top view of an exemplary processing chamber according to an embodiment of this technology. [Figure 1B] This shows a top view of a conventional 4F2 memory array. [Figure 1C] It is a perspective view of a conventional 4F2 memory array. [Figure 1D] It shows a cross-sectional view of a conventional 4F2 memory array. [Figure 2] It shows selected operations in the forming method according to an embodiment of the present technology. [Figure 3] It shows a schematic view of a 4F2 memory array according to an embodiment of the present technology.

Mode for Carrying Out the Invention

[0015]

[0020] Some of the drawings are included as schematic views. The figures are for illustrative purposes and should not be considered to be to scale unless expressly stated to be so. Further, as schematic views, the drawings are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include materials emphasized for illustrative purposes.

[0016]

[0021] In the accompanying drawings, similar components and / or features may have the same reference numerals. Further, various components of the same type can be distinguished according to the reference numerals by letters that distinguish between similar components. When only the first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral regardless of the letters.

[0017]

[0022] 4F 2 DRAM arrays classified as such are important because they have fewer patterned layers required since the memory cells are cross-point cells. However, since the minimum feature size or critical feature size (referred to as "F") continues to shrink, it is becoming difficult to increase the memory density within existing 4F 2 memory arrays. For example, existing 4F 2Memory cells are generally double-gated, meaning each channel is adjacent to another by two dedicated word lines to ensure careful electrostatic control of each channel. Such an arrangement prevents coupling of adjacent channels and unintended activation of channels. Therefore, due to the advantages of such a double-gated arrangement, efforts have been made to maintain word line orientation, such as reducing the thickness (or width) of the word lines.

[0018]

[0023] However, due to pitch and maximum resistance requirements, each word wire has a minimum thickness. That is, efforts to reduce the pitch by decreasing the width or thickness of the word wires resulted in an undesirable increase in the resistance of the word wires. Therefore, efforts to reduce the thickness of the word wires are 4F 2 It has been proven insufficient to substantially increase the memory density of memory arrays.

[0019]

[0024] Attempts have been made to eliminate the gates between adjacent channels in order to provide a single-gate memory cell. In such attempts, the two gates located between adjacent channels can be replaced with insulating material such as an air gap. However, even with advances in materials that result in improved insulation due to reduced thickness or width, such single-gate efforts remain limited. 2 We have still failed to substantially reduce the size of memory cells, for example, by at least 5%.

[0020]

[0025] In addition, 4F 2 Memory cells have transistor channels positioned between the bit lines and the capacitor layer, and therefore there is no common substrate connecting the channels, resulting in a floating body effect in these transistors. 2 DRAM devices suffer from leakage current problems due to the floating body effect (e.g., 4F due to isolated channels). 2This shows the accumulation of holes in the body of a DRAM device. For example, electron-hole pairs are formed within the semiconductor channel by band-to-band tunneling. Electrons can flow into the n-type source or drain region of the transistor, but holes cannot. 4F without substrate connection 2 In DRAM devices, holes have no path to leave the channel and continue to accumulate. Therefore, the stray body effect leads to channel activation without gate activation, which is ultimately converted into leakage current from the capacitor or the data storage side of the device.

[0021]

[0026] This technology overcomes these and other problems by forming two adjacent transistors (e.g., field-effect transistors, FETs) within a vertical cell dynamic random access memory (DRAM) array with a shared word line. Such an arrangement makes it possible to alternatively see the formation of a dual-transistor cell or a memory cell with half a word line per channel. That is, the technology has surprisingly discovered that two adjacent channels can be controlled using a single channel by utilizing inherent doping and isolation arrangements. For example, the technology provides control of adjacent channels in complementary metal oxide semiconductors, as well as other devices configured so that adjacent channels carry opposite doping charges using a single word line. Thus, a significant reduction in size per memory cell is achieved, resulting in a DRAM array with increased memory density. Moreover, surprisingly, such a size reduction can be obtained by utilizing such an arrangement even if the thickness of the shared word line is increased from that of a conventional cell. Therefore, in addition to the reduction in resistance due to the increase in the thickness of the shared word line, the technology results in a significant reduction in the word line pitch of the vertical cell DRAM array. In addition, in embodiments, such a reduction in pitch can enable a reduction in the corresponding capacitor size and reduce the required drive current. In addition, in exemplary embodiments, the overall reduction in cell size makes it possible to include a substrate layer between the bit lines and channels, providing a path for holes to move between channels when the gate is off and reducing the impact of the floating body effect on defective channels.

[0022]

[0027] The remaining disclosures include specific cells of the vertical cell dynamic random access memory (DRAM), as well as 4F 2The arrays and processes used to form vertical cell dynamic random access memory cells and arrays, such as DRAM devices, are identified as usual. In addition, the remaining disclosure identifies certain complementary metal-oxide-semiconductor (CMOS) and their components as usual. However, it will be readily apparent that the systems and methods are equally applicable to other DRAM and field-effect devices, other devices that benefit from high density, other devices that suffer from the stray-body effect, and their orientations, as well as processes for forming such devices. Therefore, the technology should not be considered to be limited to use in these specific devices or systems only. Before describing additional modifications and adjustments to this device according to embodiments of the technology, this disclosure describes one possible semiconductor device that may include one or more components according to embodiments of the technology.

[0023]

[0028] Figure 1A shows a top view of a multi-chamber processing system 100, which may be specifically configured to implement aspects or operations according to several embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, in order to form semiconductor devices. The multi-chamber processing system 100 may include some or all of a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113 and may be mounted on the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be mounted on the transfer chamber 106. The processing chambers 122 and 124 may be mounted on the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between robots 126 and 128. Platforms 102 and 104 may be open to the transfer chamber and the buffer chamber, or they may be selectively isolated or sealed from the chambers so that varying operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105 for orientation or measurement operations, etc.

[0024]

[0029] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to implement the operations described below. Thus, the computer system 130 may be a controller or array of controllers and / or a general-purpose computer, comprising software stored on a non-transient computer-readable medium, which, when executed, can perform the operations described in relation to the methods according to embodiments of the Art. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the manufacture of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing operations, including, among any number of other substrate processes, dry etching, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation.

[0025]

[0030] Figures 1B to 1D show the conventional 4F 2 A top view, perspective view, and cross-sectional view of the memory array 150 are shown. The memory array 150 may include a plurality of word lines 152 arranged in a first layer on a substrate. The word lines 152 may be conductive traces used to select the word lines of memory cells in the memory array 150. The memory array 150 may further include a plurality of bit lines 154 arranged in a second layer on a substrate. The plurality of bit lines may be conductive traces used to select the bit lines of memory cells in the memory array 150. Individual cells in the memory array 150 can be selected by activating one of the plurality of bit lines 154 and one of the plurality of word lines 152. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer having the word lines 152 may be formed on top of the second layer having the bit lines 154 such that the two layers do not intersect.

[0026]

[0031] As shown more clearly in Figure 1D and above, the conventional 4F 2 Each channel 160 of the memory array 150 contains two word lines 152 for each channel 160 (for example, conventional systems are typically double-gated). Some conventional systems have reduced this to a single word line 152 per channel 160 by removing the word lines 151 and 153 between adjacent channels and replacing the word lines 151 and 153 with gaps. As is known in the art, gaps can be used to provide an effective oxide thickness between adjacent channels with a smaller overall width or thickness. However, as shown in Figure 1D, each channel 160 still contains at least one word line 152 per channel 160, as well as gaps between adjacent channels, in order to isolate and turn on each channel.

[0027]

[0032] Nevertheless, multiple vertical memory cells may be arranged on the intersections between multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor 170, which may be referred to as a vertical pillar transistor or vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar or any other substrate as described in more detail below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing charge in the vertical capacitor 156 to indicate a stored memory state. However, please understand that Figures 1B and 1C show the arrangement of the vertical transistor 170 and capacitor in a rectangular orthogonal grid pattern (where orthogonal generally means within about 10° of orthogonal, e.g., about 7.5° or less, about 5° or less, e.g., about 2.5° or less of orthogonal, e.g., about 1° or less, or any range or value in between these), which is intended for use in this technology. For example, in an embodiment, capacitors and vertical transistors may be spaced in alternating rows offset by half the distance between vertical transistors. That is, in an embodiment, the first row of memory cells may be regularly spaced in a row in a first direction, and the second row of memory cells may also be regularly spaced in a row in a first direction, but the second row of memory cells may be offset from the first row of memory cells, for example, positioned approximately midway between the vertical transistors and capacitors of the first row. Such a pattern is sometimes referred to as a "honeycomb" or "hexagonal pattern" in comparison to the square pattern shown in Figures 1B and 1C. Therefore, it should be understood that any suitable orientation can be used in this technology.

[0028]

[0033] This conventional 4F 2It is useful to characterize the dimensions of the unit cell region 166 of the memory array for comparison with a simple memory array described later. For example, the capacitor footprint 158 ​​can be defined as the circular region around each vertical capacitor 156. The capacitor footprint 158 ​​may include the horizontal cross-sectional area of ​​the capacitor, which expands until its cross-sectional area contacts the capacitor region from an adjacent memory cell. Assume that the word line pitch 162 for multiple word lines 152 and the bit line pitch 164 for multiple bit lines 154 can be defined as 2F. This gives the overall cross-sectional area of ​​the unit cell region 166 to be 4F. 2 It will become.

[0029]

[0034] Figure 2 shows exemplary operation of Method 200 according to several embodiments of the present technology. This method can be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of arbitrary operations, some of which may or may not be particularly relevant to certain embodiments of the method relating to the present technology. For example, many operations are described to provide a broader range of structural forms, but may not be important to the present technology or may be carried out by easily understandable alternative methods.

[0030]

[0035] Method 200 may include additional operations before commencing the enumerated operations. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing material. The prior processing operations may be performed in the chamber in which Method 200 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is brought into the semiconductor processing chamber in which Method 200 may be performed. In any case, Method 200 may optionally include delivering the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to a processing area of ​​another chamber, which may include the components described above. The substrate may be a pedestal, such as a substrate support 104, and may be deposited on a substrate support / transfer platform that may be present in a processing area of ​​a chamber, such as the processing area of ​​the processing chamber 120 described above. Method 200 describes the operations for developing the semiconductor structure 300 shown in Figure 3, which will be described in conjunction with the operations of Method 200. Figure 3 shows only a partial schematic diagram, and it should be understood that the semiconductor substrate may include further components shown in the figure, as well as alternative components of any size or configuration from which the embodiments of this technology can still be beneficial.

[0031]

[0036] Method 200 may or may not include optional operations to develop the semiconductor structure shown in Figure 3 into a specific manufacturing operation. It should be understood that Method 200 can be performed on any number of semiconductor structures 300, including exemplary structures in which one or more layers or semiconductor features may be formed on the substrate, as shown in Figure 3. As shown in Figure 3, the substrate material 302 (shown in a polished and doped form after the formation of the structure 300) may be any number of materials (e.g., a base wafer or substrate made from silicon or a silicon-containing material, germanium, other substrate materials, and one or more materials that may be formed on the substrate during semiconductor processing).

[0032]

[0037] In embodiments, the structure 300 may be a semiconductor substrate including a bulk substrate, an epitaxially grown substrate, and / or silicon on an insulating wafer. As used herein, the term “semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 302 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is included in the spirit and scope of this disclosure.

[0033]

[0038] In embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron-donating element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0034]

[0039] Figure 3 shows a semiconductor structure 300 according to an embodiment of the present technology. As shown in the figure, in the embodiment, the substrate material 302 has a first source / drain 304a corresponding to a first channel 306a and a second source / drain 304b corresponding to a second channel 306b. Each of the source / drain regions 304a and 304b is formed on the upper surface 305 and the opposing lower surface 307 of the respective channels 306a and 306b. The source / drains 304a and 304b formed adjacent to the lower surface 307 are shown as elongated tabs extending through only a portion of the thickness or width of the lower surface 307 of the respective channels 306a and 306b, but as will be described in more detail below, in the embodiment they include the surface 305 of each channel 306a and 306b, which may be formed identically to the source / drains 304a and 304b of the lower surface 307.

[0035]

[0040] For example, in an embodiment, the source / drain regions 304a, 304b may be formed by exposing each channel 306a, 306b to one or more ion implantations followed by an annealing process. The implantation process may be a single implantation or may include a series of multiple implantations. If multiple implantations are used, each implantation may utilize the same or different ions. However, it should be understood that the source / drain regions 304a, 304b may be formed from any suitable process. For example, as is known in the art, a method may include providing a semiconductor structure having first source / drain regions 304a, 304b for multiple vertical channels and forming multiple word lines in contact with the first source / drain regions. Overall, this process may gradually form each stage of the transistor on top of the previously completed stages.

[0036]

[0041] Furthermore, various deposition and filling processes may be used to deposit or fill any of the layers shown in Figure 3 or described herein, but in embodiments, the semiconductor structure may be transferred to or between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), etc. Therefore, unless otherwise specified, any one or more of the above methods known in the art may be used to deposit any of the layers and materials described herein. Similarly, the semiconductor structure can be transferred to one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, for example, one or more of the following: inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, and other etching processes known in the art.

[0037]

[0042] Nevertheless, the method 200 for forming a semiconductor structure such as the semiconductor structure 300 may include, in operation 201, forming word line trenches 308 by etching or by other methods known in the art. For example, in an embodiment, a substrate 302 is loaded into load locks 110, 112 and transferred via robots 126, 128 to a processing chamber (such as processing chamber 114), and the semiconductor structure 300 is subjected to the word line trench formation operation 201. It should be understood that the substrate may be transferred between each operation step, or only a portion of the operation steps, because some operation steps may be completed within the same processing chamber. Nevertheless, each word line trench 308 extends from a first end 309 to an opposing second end 310, defining the trench depth between them. Furthermore, the word line trench formation operation 201 may be performed by any method known in the art.

[0038]

[0043] In any case, as described above, the formation of the word line trench 308 can be carried out by any method known in the art, but the present art has surprisingly discovered that by carefully doping oxide around the outer periphery of the word line trench 308 and separating adjacent channels not separated by the word line 320 (e.g., channels that do not share the word line 320, also called channels in adjacent cells), it is possible to control two separate channels 306a, 306b located on either side of the word line 320 using a single word line. Thus, in embodiments, operation 201 may consist only of forming a single word line 320 for each of the two channels 306a, 306b in the semiconductor device 300. Thus, as illustrated, the array according to the present art has a first channel adjacent to the word line, a second channel adjacent to the world line opposite the first channel, and an electrical insulator adjacent to the second side of the second channel, and orientation can be restarted by arranging the second cell at intervals. Each element is spaced along a first horizontal direction, which may be a first horizontal direction extending independently or parallel to the bit line 324.

[0039]

[0044] As shown in Figure 3, in the embodiment, the electrical insulator 312 may be formed in operation 202 between channels 306a, 306b of adjacent cells (for example, channel 306b of the first cell 301 and channel 306a of the second cell 303 that is not separated by the word line 320). The electrical insulator 312 may be formed simultaneously with the word line formation operation 201, or may be formed or etched before or after the formation of the word line trench 320.

[0040]

[0045] In embodiments, the electrical insulator 312 may include, alone or in combination with voids, any electrical insulating material known in the art. For example, in embodiments, the electrical insulating material may be a dielectric material such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or other dielectric materials known in the art, and / or voids formed using any of the aforementioned filling methods known in the art. While silicon oxide or silicon nitride as dielectric materials and / or spacer materials will be discussed periodically in the following description, any number of dielectric materials may be used in embodiments of the art, and it should be understood that the art should not be limited to any specific dielectric material on which features can be formed.

[0041]

[0046] In addition, although the electrical insulator 312 is shown to include two dielectric layers 312a and 312b together with the void 312c, it should be understood that the electrical insulator 312 can be formed from one electrical insulating material, two electrical insulating materials, or more. For example, in embodiments, the void 312c can be removed, and the electrical insulator 312 can be formed from one or more dielectric materials. That is, in embodiments, the dielectric materials 312a and 312b can be formed from the same material, different materials, or materials that may have the same or different starting compositions (e.g., dielectric materials doped to have different work functions, as will be described in more detail). In addition, although two or more dielectric materials or dielectric layers are shown, in embodiments it should become clear that only one dielectric material layer may be used in the electrical insulator 312, depending on the insulating properties of the selected material. For example, in embodiments, the dielectric layers 312a and / or 312b can be removed, and the void 312c can be used alone or with only one dielectric layer.

[0042]

[0047] Regardless of the formed electrical insulator 312, the electrical insulator 312 may have a width w of about 90% or less of the thickness t of the word wire 320, for example, about 85% or less, about 80% or less, about 75% or less, about 70% or less, about 65% or less, about 60% or less, about 55% or less, about 50% or less, about 45% or less, for example about 40% or less, for example about 35% or less, about 30% or less, or any range or value in between these.

[0043]

[0048] For example, in the embodiment, the electrical insulator 312 may have a size of approximately 12 nm or less, for example approximately 11 nm or less, for example approximately 10 nm or less, for example approximately 9 nm or less, for example approximately 8 nm or less, for example approximately 7 nm or less, for example approximately 6 nm or less, for example approximately 5 nm or less, for example approximately 4 nm or less, or any range or value in between these.

[0044]

[0049] Therefore, due to the reduction in the width of the electrical insulator 312, each channel requires only half the width of the word line according to this technology, so in the embodiment, each of the formed word lines 320 can have its thickness t increased without increasing the size of the cell. Thus, in the embodiment, the thickness t may be about 5 nm or more, for example about 6 nm or more, for example about 7 nm or more, for example about 8 nm or more, for example about 9 nm or more, for example about 10 nm or more, for example about 11 nm or more, for example about 12 nm or more, for example about 13 nm or more, for example about 14 nm or more, for example about 15 nm or more, or any range or value in between these.

[0045]

[0050] Therefore, in this embodiment, compared to a semiconductor structure having one word line per channel, it is possible to increase the thickness t of the word lines 320 while reducing the total word line pitch by about 5% or more, for example, about 7.5% or more, for example, about 10% or more, for example, about 12.5% ​​or more, for example, about 15% or more, for example, about 17.5% or more, for example, about 20% or more, for example, about 22.5% or more, for example, about 25% or more.

[0046]

[0051] In other words, in the embodiment, the semiconductor device 300 according to this technology may have a word line cell pitch of, for example, about 45 nm or less, about 42.5 nm or less, about 40 nm or less, about 37.5 nm or less, about 35 nm or less, about 32.5 nm or less, about 30 nm or less, about 27.5 nm or less, about 25 nm or less, about 22.5 nm or less, or any range or value in between thereof.

[0047]

[0052] Regardless of the thickness of the word wire 320, the width of the electrical insulator 312, or the final cell size, the Art has found that by carefully lining the opposing sides of the gate dielectric 311, positioned around the outer periphery of the word wire trench 308, with one or more dielectric materials having different work functions, it is possible to obtain a single word wire 320 exhibiting two different threshold voltages and thus having the size advantages described herein without sacrificing electrical properties. Accordingly, in embodiments, the gate dielectric 311 may be formed along channels 316a, 316b in operation 203 utilizing methods known in the Art. In embodiments, the gate dielectric 311 may be formed from any one or more of the above-mentioned materials, such as silicon oxide.

[0048]

[0053] Nevertheless, after the formation of the gate dielectric 311, in operation 204, a first dielectric layer 314 is formed on the first side 315 of the word line trench 308, and in operation 205, a second dielectric layer 316 is formed on the opposing second side 317 of the word line trench 308 using any one or more of the above-described methods well known in the art. It should be understood that, as will be described in more detail, in embodiments the second dielectric layer 316 may be applied before the first dielectric layer 314.

[0049]

[0054] In embodiments, the first dielectric layer 314, the second dielectric layer, or both the first dielectric layer 314 and the second dielectric layer 316 may be formed from any one or more of the dielectric materials described above. Nevertheless, in embodiments, the first dielectric layer 314, the second dielectric layer, or both the first dielectric layer 314 and the second dielectric layer 316 may be oxide layers. In embodiments, the first dielectric layer 314, the second dielectric layer, or both the first dielectric layer 314 and the second dielectric layer 316 may be formed from, for example, silicon dioxide (SiO2) and / or a high dielectric constant dielectric material. In embodiments, the high dielectric constant dielectric material may include any dielectric material having a dielectric constant of about 10 or more, for example about 15 or more, for example about 20 or more, for example about 25 or more, or any range or value in between these, and this includes aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfSiO4), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO4), yttrium oxide (Y2O3), lanthanum oxide (La2O3), cerium oxide (CeO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), other dielectric materials, or combinations thereof. The first dielectric layer 314, the second dielectric layer, or both the first dielectric layer 314 and the second dielectric layer 316 may be formed, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or other suitable semiconductor processing adapted to form dielectric material layers as described above.

[0050]

[0055] However, in some embodiments, the high dielectric constant dielectric layer may be applied using an atomic layer deposition (ALD) process in which metal-containing precursors and oxygen-containing precursors are alternately supplied to the gate dielectric 311. In some embodiments, the metal-containing precursors are purged before the oxygen-containing precursors are supplied. The metal may be a transition metal such as hafnium (Hf), zirconium (Zr), or titanium (Ti); a rare earth metal such as lanthanum (La), ytterbium (Yb), or yttrium (Y); an alkaline earth metal such as strontium (Sr); or another metal such as aluminum (Al). As an oxidizing agent, any oxygen-containing precursor that may react with the metal can be used. For example, the oxygen-containing precursor may be or may include water, diatomic oxygen, ozone, a hydroxyl-containing precursor or alcohol, a nitrogen and oxygen-containing precursor, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material containing oxygen that can be incorporated with the metal to form a metal oxide layer on the gate dielectric 311.

[0051]

[0056] Nevertheless, it should be understood that, in the embodiment, as described above, the first dielectric layer 314 and the second dielectric layer 316 may be independently selected to have different work functions in order to impart different threshold voltage differences to the word lines adjacent to the first and second dielectric layers 314 and 316. For example, in the embodiment, the first side 315 of the word line trench 308 may be adjacent to an n-MOS channel (e.g., channel 306a), and the second side 317 of the word line trench 308 may be adjacent to a p-MOS channel (e.g., channel 306b). In such an example, the first dielectric 314 may be formed from a material having a higher work function, and the second dielectric 316 may be formed from a material having a lower work function. In this way, the threshold voltage adjacent to the n-MOS channel (306a in this embodiment) is higher than the threshold voltage adjacent to the p-most channel (306b in this embodiment). Therefore, in this configuration, both the n-MOS channel and the p-MOS channel may be "off" when the gate voltage is set to near zero. Furthermore, when a positive voltage is applied to the gate, the n-MOS channel is activated while the p-MOS channel remains off, and when a negative voltage is applied to the gate, the n-MOS channel is activated while the p-MOS channel remains off. However, as will be apparent to those skilled in the art, the orientation can be completely reversed as long as the correct dielectrics 314, 316 are adjacent to the corresponding channels 306a, 306b (for example, 306a may be a p-MOS channel, 314 a negative work function material, 306b an n-MOS channel, and 316 a higher work function material).

[0052]

[0057] In embodiments, the first dielectric 314 may be adjacent to the n-MOS channel and may be formed from a material that generates a dipole between the first dielectric material 314 and the channel 306a, thus exhibiting a positive work function shift. In such examples, the first dielectric may include dielectric and oxide materials containing any metallic substance having a Fermi level lower than aluminum (Al), niobium (Nb), tantalum (Ta), or hafnium (Hf). Suitable aluminum (Al)-containing materials include aluminum oxide (Al2O3), and suitable niobium (Nb)-containing materials include niobium nitride (NbN), niobium oxide (NbOx), and titanium niobium nitride (TiNbN).

[0053]

[0058] Furthermore, in embodiments, the second dielectric 316 may be adjacent to the p-MOS channel and may be formed from a material that creates a dipole between the second dielectric material 316 and the channel 306b, but exhibits a negative work function shift. In such examples, the first dielectric may include dielectric and oxide materials comprising one or more lanthanum (La) species, silicon nitrite, combinations thereof, or one or more other species that provide a negative work function shift, as is known in the art.

[0054]

[0059] In other words, as described above, this technology has surprisingly found that by utilizing such a first dielectric 314 and a second dielectric 316, one or more threshold voltages described herein can be obtained even when using very thin channels 306a and 306b. Therefore, the dielectric materials described herein can be useful in providing the required threshold voltages between the word line 320 and adjacent n-MOS channels, and between the word line and adjacent p-MOS channels.

[0055]

[0060] In embodiments, it should be understood that positive and negative work function materials are present during the formation of the first dielectric 314 and second dielectric 316 layers. However, in some embodiments, an oxide layer may be formed first, and then negative or positive work function materials may be formed on top of the oxide layer. Subsequently, an annealing process may be utilized to diffuse the positive or negative work function into the oxide layer and form the first dielectric 314 and / or second dielectric 316. In embodiments, such an annealing process may include thermal annealing in the presence of an inert gas. However, in embodiments, the underlying oxide layer may already contain the respective positive or negative work function materials (for example, when using one or more of the high dielectric constant materials described above), but it may subsequently undergo the incorporation of additional sets of work function materials using an annealing process to achieve the desired work function levels for activation and deactivation of the respective channels.

[0056]

[0061] For example, in this embodiment, a first dielectric 314 that may be adjacent to the n-MOS channel may have a positive work function to provide a region 315 between the word line or gate and the first dielectric 314 having a threshold voltage of about 0.5 volts (V) or more, for example, about 0.6 V or more, for example, about 0.7 V or more, for example, about 0.8 V or more, for example, about 0.9 V or more, for example, about 1 V or more, for example, about 1.1 V or more, for example, about 1.2 V or more, for example, about 1.3 V or more, for example, about 1.4 V or more, for example, about 1.5 V or more, for example, about 1.6 V or more, for example, about 1.7 V or more, for example, about 1.8 V or more, for example, about 1.9 V or more, for example, about 2 V or more, for example, about 2.1 V or more, for example, about 2.2 V or more, for example, about 2.3 V or more, for example, about 2.4 V or more, for example, about 2.5 V or more, or any range or value in between these.

[0057]

[0062] Furthermore, in this embodiment, a second dielectric 316 that may be adjacent to the p-MOS channel may have a negative work function to provide a region 317 between the word line or gate and the second dielectric 316 having a threshold voltage of about -0.5 volts (V) or less, for example, -0.6V or less, about -0.7V or less, about -0.8V or less, about -0.9V or less, about -1V or less, about -1.1V or less, about -1.2V or less, about -1.3V or less, about -1.4V or less, about -1.5V or less, about -1.6V or less, about -1.7V or less, etc., up to -1.8V, for example, about -1.9V or less, for example, about -2.1V or less, for example, about -2.2V or less, for example, about -2.3V or less, for example, about -2.4V or less, for example, about -2.5V or less, or any range or value in between these.

[0058]

[0063] Therefore, in this embodiment, when the applied voltage is approximately -0.4V or higher, for example, approximately -0.3V or higher, approximately -0.2V or higher, approximately -0.1V or higher, approximately 0.5V or lower, approximately 0.4V or lower, approximately 0.3V or lower, approximately 0.2V or lower, approximately 0.1V or lower, approximately 0 volts, or any range or value in between, the word line or gate can be in the off position for both the n-MOS channel and the p-MOS channel.

[0059]

[0064] Furthermore, the p-MOS channel can be turned on when the word line voltage is approximately -2.6V or less, for example, approximately -2.7V or less, for example, approximately -2.8V or less, for example, approximately -2.9V or less, for example, approximately -3V or less, for example, approximately -3.1V or less, for example, approximately -3.2V or less, for example, approximately -3.3V or less, for example, approximately -3.4V or less, for example, approximately -3.5V or less, or any value.

[0060]

[0065] Similarly, the n-MOS channel can be turned on when the word line voltage is approximately 2.6V or higher, for example approximately 2.7V or higher, for example approximately 2.8V or higher, for example approximately 2.9V or higher, for example approximately 3V or higher, for example approximately 3.1V or higher, for example approximately 3.2V or higher, for example approximately 3.3V or higher, for example approximately 3.4V or higher, for example approximately 3.5V or higher, or any range or value in between these.

[0061]

[0066] Furthermore, due to the reduction in capacitor size, at least partially, this technology has surprisingly found that the drive current required to discharge the charge of each capacitor is low, even in the p-MOS region. Therefore, this technology provides smaller memory cells that offer improved memory cell density while maintaining excellent electrical properties between capacitors and transistors, as well as across the entire cell and array.

[0062]

[0067] Nevertheless, after the formation of the first dielectric layer 314 and the second dielectric layer 316, the word line 320 may be formed in operation 206 using any method known in the art. The word line may extend in a second horizontal direction distinct from the first horizontal direction. In embodiments, the word line may be a low-resistance metal such as tungsten, titanium nitride, titanium, ruthenium, cobalt, molybdenum, or a combination thereof. As shown in the illustration, in embodiments, the word line 320 may be etched below a second source / drain region 304a / 304b adjacent to the first end 309 of the word line trench 308.

[0063]

[0068] In embodiments, an optional substrate layer 322 may be formed on the surface of a cell 301 adjacent to the lower surface 307 of channels 306a, 306b during an optional operation 207. That is, as described above, it may be desirable to include an additional substrate layer 322 while still obtaining an overall reduction in cell size due to the size reduction made possible by this technique. In embodiments, if a substrate layer 322 is included, it may be desirable to include alternating vertical layers of p-type substrate under the n-MOS region and n-type substrate under the p-MOS region (for example, in directions substantially orthogonal to the first and second horizontal directions, such as the vertical direction of the vertically extending channel 320). Thus, the technique can act as p-wells and n-wells connected to bit lines 324 and attract a small number of carriers from the defective channels, thus 4F 2 This can provide a reduction or elimination of the floating body effect exhibited by the array.

[0064]

[0069] Therefore, in this embodiment, the substrate layer 322 may be formed by sidewall epitaxy. In this embodiment, moving horizontally along a first horizontal direction (e.g., along bit line 324) from left to right across Figure 3, moving from sidewall 326 toward source / drain 304a, a layer of p-type substrate may be deposited. At source / drain 304a, a vertical layer of material having different etching specificities than the substrate layer 322 may be deposited; for example, if doped Si is used as the substrate, SiGe may be deposited as an example. Then, using sidewall epitaxy, further deposition of p-type doped or n-type doped substrate material is carried out until a second source / drain 304b is reached, at which point another vertical layer of selective etching material may be deposited, and subsequently, an n-type substrate is deposited beneath the p-MOS region. After such substrate formation operation 207, the selective etching material is removed, and source / drain regions 304a, 304b may be formed within the etching region. However, as described above, in this embodiment, the substrate layer 322 is not utilized, and the source-drain regions 304a and 304b can be formed according to standard processes such as ion implantation as described above.

[0065]

[0070] Whether or not the substrate layer 322 is formed, the bit wire 324 is formed in contact with the source / drain 304a / 304b of the first horizontally extending lower surface 307. The bit wire 324 may be formed from material deposited by any suitable technique known in the art, such as one or more of the deposition or filing techniques described above. In some embodiments, the bit wire 324 includes one or more of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). In embodiments, the bit wire 324 material is one or more of ruthenium or tungsten.

[0066]

[0071] After the formation of the bit line 324, the semiconductor structure 300 is 4F 2The semiconductor structure may re-enter the normal processing flow of a vertical cell DRAM array, such as a DRAM array, and undergo one or more further processing steps. For example, the semiconductor structure 300 may undergo contact formation and redistribution, bonding pad formation, and / or copper contact formation. Nevertheless, the semiconductor structure may exhibit significantly smaller size and increased density, either alone or in combination with reduced or eliminated floating body effects.

[0067]

[0072] Nevertheless, in some embodiments, it may be necessary to utilize spaced contact pads to connect the capacitor to the transistor. For example, in embodiments where the electrical insulator 312 has a width w smaller than the thickness t of the word wire 320, the reduction in thickness results in a lack of uniformity in the spacing between cells, which may be called mismatched overlap. In such embodiments, the cell contacts can be offset by a portion of the pitch from the center of each row (e.g., one row has a portion of the pitch stagger to the right, and the next row has a portion of the pitch stagger to the left) to provide good contact to each row. However, in embodiments, depending on the width of the word wire and the thickness of the electrical insulator 312, staggering may not be necessary.

[0068]

[0073] The specific steps shown in the figure are 4F according to various embodiments. 2 It should be understood that this provides a specific method for forming a DRAM array. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in the figures may include multiple substeps that may be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0069]

[0074] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0070]

[0075] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0071]

[0076] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0072]

[0077] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0073]

[0078] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Moreover, the order of operations may be rearranged. A process terminates when an operation is completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0074]

[0079] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0075]

[0080] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0076]

[0081] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0077]

[0082] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical disks, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. A vertical dynamic random access memory (DRAM) cell, The first horizontally arranged bit line, The first channel, The second channel, and A second horizontally arranged shared word line between the first channel and the second channel, Equipped with, A vertical dynamic random access memory (DRAM) cell in which the first channel and the second channel extend in a vertical direction substantially orthogonal to the first horizontal direction and the second horizontal direction, such that the bit lines intersect the source / drain regions of the first channel and the second channel, and the shared word lines intersect the gate regions of both the first channel and the second channel.

2. The vertical dynamic random access memory (DRAM) cell according to claim 1, wherein the vertical dynamic random access memory (DRAM) cell includes only one word line for every two channels.

3. A vertical dynamic random access memory (DRAM) cell according to claim 1, further comprising: a first dielectric layer extending along a first side from a first end of a word line trench to a second end of the word line trench, the second end of which is on the opposite side of the first end; and a second dielectric layer extending along a second side from a first end of the word line trench to a second end of the word line trench, the second side of which is on the opposite side of the first side.

4. The vertical dynamic random access memory (DRAM) cell according to claim 3, wherein the first dielectric layer is formed from a material having a first work function, and the second dielectric layer is formed from a material having a second work function, and the first work function is different from the second work function.

5. The vertical dynamic random access memory (DRAM) cell according to claim 4, wherein the first side is adjacent to the first channel, the second side is adjacent to the second channel, the first channel includes an n-MOS channel, and the second channel includes a p-MOS channel.

6. The vertical dynamic random access memory (DRAM) cell according to claim 5, wherein the first dielectric layer material includes a material with a positive work function.

7. The vertical dynamic random access memory (DRAM) cell according to claim 6, wherein the first dielectric layer material includes an oxide containing a metallic substance having a Fermi level lower than that of aluminum (Al), niobium (Nb), tantalum (Ta), hafnium (Hf), or a combination thereof.

8. The vertical dynamic random access memory (DRAM) cell according to claim 5, wherein the second dielectric layer material includes a negative work function material.

9. The vertical dynamic random access memory (DRAM) cell according to claim 8, wherein the second dielectric layer material comprises an oxide containing one or more lanthanum species, silicon nitrite, or a combination thereof.

10. A vertical cell dynamic random access memory (DRAM) array, A first vertical dynamic random access memory cell is arranged adjacent to a second vertical dynamic random access memory cell, wherein the first vertical dynamic random access memory cell and the second dynamic random access memory cell are A first horizontally arranged bit line, The first channel and, The second channel and A second horizontally positioned word line is located between the first channel and the second channel, Includes, The first channel and the second channel are A second vertical dynamic random access memory cell, extending in a vertical direction substantially perpendicular to the first and second horizontal directions, such that the bit lines intersect the source / drain regions of the first and second channels, and the word lines intersect the gate regions of the first and second channels, and Electrical insulator between the first vertical dynamic random access memory cell and the second vertical dynamic random access memory cell A vertical-cell dynamic random-access memory (DRAM) array, including [a specific component].

11. The vertical cell dynamic random access memory (DRAM) array according to claim 10, wherein the first vertical dynamic random access memory cell and the second vertical dynamic random access memory cell each include only one word line for every two channels.

12. A vertical cell dynamic random access memory (DRAM) array according to claim 10, further comprising a third vertical dynamic random access memory adjacent to the second vertical dynamic random access memory memory, wherein an electrical insulator is disposed between the second vertical dynamic random access memory memory and the third vertical dynamic random access memory memory, and the third vertical dynamic random access memory memory includes a shared word line between two adjacent channels.

13. The vertical cell dynamic random access memory (DRAM) array according to claim 10, wherein the electrical insulator comprises one or more dielectric materials, air gaps, or a combination thereof.

14. The vertical cell dynamic random access memory (DRAM) array according to claim 10, further comprising a substrate layer disposed between the bit lines and the source / drain regions of the first channel and the second channel.

15. A method for forming a vertical dynamic random access memory (DRAM) cell, Etching a word line trench between a first vertically extending channel and a second vertically extending channel, wherein the word line trench has a first end opposite to the second end and a first side opposite to the second side. A shared word line is formed within the word line trench such that the word line intersects with the gate regions of both the first vertically extending channel and the second vertically extending channel. A method that includes this.

16. The method according to claim 15, further comprising lining the word line trench with a gate dielectric before forming the shared word line.

17. The method according to claim 16, further comprising forming a first dielectric material on the gate dielectric along the first side of the word line trench, and forming a second dielectric material on the gate dielectric along the second side of the word line trench.

18. The method according to claim 17, comprising forming a substrate layer by sidewall epitaxy on a vertical dynamic random access memory cell adjacent to the second end of the word line trench, and forming a bit line layer on the substrate layer.

19. The method according to claim 18, wherein the substrate layer is formed from alternating layers of a p-type substrate material, a selective etching material, and an n-type substrate material.

20. The method according to claim 19, further comprising removing the selective etching material and forming source / drain connections between the first vertically extending channel and the bit line, and between the second vertically extending channel and the bit line.

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