AG mirror sealing method

Abstract

This disclosure provides a method comprising depositing mirrors on a waveguide having an input coupler and an output coupler. A sealing layer is deposited on the mirrors. A resist is formed on the input coupler, exposing the remaining sealing portion of the sealing layer on the non-input coupler region. The remaining sealing portion of the sealing layer is removed, exposing the remaining mirror portion of the mirror on the non-input coupler region. The remaining mirror portion of the mirror on the input coupler is removed, exposing the non-input region of the waveguide. The resist on the input coupler is removed, and the waveguide has mirrors only on the input coupler and the sealing layer only on the mirrors.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to waveguides for augmented reality, virtual reality, and mixed reality.

Background Art

[0002]

[0002] A waveguide can be used to manipulate the propagation of light using a waveguide structure formed on a substrate. The waveguide includes an arrangement of structures having planar dimensions smaller than half of the design wavelength of light. These structures have submicron critical dimensions (e.g., nano-sized dimensions) and change the propagation of light by manipulating photons, causing local phase discontinuities (i.e., abrupt changes in phase over distances shorter than the wavelength of light). It is also possible to apply a metal coating on the structures, and this metal coating functions as a mirror to guide light and enhance the efficiency of the device. However, metal coatings often react with oxygen and / or sulfur-containing gases in the ambient atmosphere and corrode.

[0003]

[0003] Therefore, an improved method for forming a waveguide is needed.

Summary of the Invention

[0004]

[0004] The present disclosure provides a method. The method includes depositing a mirror on a waveguide having an input coupler and an output coupler. A sealing layer is deposited on the mirror. A resist is formed on the input coupler, exposing a remaining sealing portion of the sealing layer on the non-input coupler region. The remaining sealing portion of the sealing layer is removed, exposing a remaining mirror portion of the mirror on the non-input coupler region. The remaining mirror portion of the mirror of the input coupler is removed, exposing the non-input region of the waveguide. The resist on the input coupler is removed, and the waveguide has a mirror only on the input coupler, and the sealing layer is only on the mirror.

[0005]

[0005] The present disclosure further provides a method, which comprises depositing a mirror on a waveguide having an input coupler and an output coupler. A first resist is formed on the input coupler, exposing the remaining mirror portion of the mirror on the non-input coupler region. The remaining mirror portion of the mirror on the non-input coupler region is exposed. The first resist is removed. A sealing layer is deposited on the mirror and the non-input coupler region. A second resist is formed on the mirror, exposing the remaining sealing portion of the sealing layer on the non-input coupler region. The remaining sealing portion is removed, exposing the non-input coupler region of the waveguide. The second resist is removed, and the waveguide has a mirror only on the input coupler, and the sealing layer is on the mirror only, or on the mirror and on the outer portion of the input coupler surrounding the grating of the input coupler.

[0006]

[0006] The present disclosure further provides a method. This method includes depositing a mirror containing silver or aluminum on a waveguide. The waveguide has an input coupler and an output coupler. A sealing layer containing chromium or silicon nitride is deposited on the mirror. A resist is formed on the input coupler. The remaining sealing portion of the sealing layer on the non-input coupler region is exposed. The remaining sealing portion of the sealing layer on the non-input coupler region and the remaining mirror portion of the mirror are removed. The resist on the input coupler is removed.

[0007]

[0007] To allow for a more detailed understanding of the above-mentioned features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be given by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show exemplary embodiments of the Disclosure and are not intended to limit the scope of the Disclosure, and other equally effective embodiments are also permitted. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic diagram of a waveguide according to an aspect of the present disclosure. [Figure 2] This is a flowchart of a method for forming a waveguide according to an aspect of the present disclosure. [Figure 3A]This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 3B] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 3C] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 3D] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 3E] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 4] This is a flowchart of a method for forming a waveguide according to an aspect of the present disclosure. [Figure 5A] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 5B] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 5C] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 5D] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 5E] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 5F] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Figure 5G] This is a schematic cross-sectional view of a substrate in a method according to an aspect of the present disclosure. [Modes for carrying out the invention]

[0009]

[0013] For ease of understanding, the same reference numerals are used whenever possible to indicate identical elements common to the figures. It is assumed that elements and features of one embodiment can be usefully incorporated into other embodiments without further detail.

[0010]

[0014] Embodiments of this disclosure generally relate to methods for manufacturing input couplers for waveguides for augmented reality and virtual reality devices. The methods described herein provide waveguides having a mirror only on the input coupler, as shown in Figure 1, and having a sealing layer only on the mirror, or on the mirror and on the outer portion of the input coupler surrounding the grating of the input coupler. The mirror layer only on the input coupler and the sealing layer provide a barrier against the ingress of oxygen, sulfur, and moisture. The sealing layer protects the mirror from corrosion in the ambient atmosphere.

[0011]

[0015] The sealing layer of this disclosure does not require an electron beam PVD deposition process. Instead, other deposition processes, such as PVD, or printing methods such as screen printing or inkjet printing, can be used, and these PVD or printing methods reduce costs and improve process flow. The deposition processes described herein make it possible to deposit a sealing layer without impairing the optical performance of AR / VR devices. Overall, this disclosure provides a method for forming an input coupler that is reflective and protected from oxidation or other chemical reactions.

[0012]

[0016] Waveguide 100 includes a substrate 101. The substrate 101 can be selected to transmit light of the operating wavelength. In some embodiments, but not limited to, the substrate 101 is configured to transmit about 50%, 60%, 70%, 80%, 90%, 95%, 99% or more of the UV region of the light spectrum. The substrate 101 may be formed from any suitable material, as long as it can adequately transmit light of the operating wavelength and can function as a suitable support for at least the arrangement of the waveguide structure 106 and the sealing layer 104. In some embodiments, which can be combined with other embodiments described herein, the material of the substrate 101 has a relatively low refractive index compared to the refractive index of the material used in each of the waveguide structures 106. The selection of the substrate can include any suitable material substrate, including but not limited to semiconductors, doped semiconductors, amorphous dielectrics, non-amorphous dielectrics, crystalline dielectrics, silicon oxide, polymers, and combinations thereof. In some embodiments, which can be combined with other embodiments described herein, the substrate 101 includes a transparent material. The substrate 101 is transparent and has an absorption coefficient of less than 0.001. Examples include, but are not limited to, oxides, sulfides, phosphides, tellurides, and combinations thereof. For example, the substrate 101 may include, but is not limited to, silicon (Si), silicon dioxide (SiO2), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), sapphire, glass, or combinations thereof.

[0013]

[0017] Waveguide 100 includes an input coupler 102. The input coupler 102 includes a first arrangement of waveguide structure 106. Waveguide structure 106 may have any shape suitable for transmitting and / or guiding incident light to the substrate 101. For example, but not limited to, waveguide structure 106 may have a square or rectangular cross-section. In further non-limiting examples, waveguide structure 106 may have a circular, triangular, elliptical, regular polygon, irregular polygon, and / or irregular cross-section. The cross-sections of waveguide structure 106 on substrate 101 may vary.

[0014]

[0018] The waveguide structure 106 can include, but is not limited to, titanium dioxide (TiO2), zinc oxide (ZnO), tin dioxide (SnO2), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), cadmium stannate (cadmium tin oxide) (CTO), zinc stannate (zinc tin oxide) (SnZnO3), and silicon-containing materials. The silicon-containing materials can include at least one of silicon nitride (Si3N4) or an amorphous silicon (a-Si)-containing material. The waveguide structure 106 can have a refractive index of about 1.8 or more and an absorption coefficient of less than 0.001.

[0015]

[0019] The mirror 103 is disposed on the input coupler 102 of the waveguide structure 106 and not on the output coupler 105. The mirror 103 is a coating capable of reflecting light of one or more wavelengths incident on the substrate 101 and traveling toward the input coupler 102. The mirror 103 is not disposed on the output coupler 105. The mirror 103 can be any suitable material capable of reflecting 90% or more of the light, for example, about 90%, about 91%, about 92%, about 93%, about 94%, about 95%, about 96%, about 97%, about 98%, about 99%, or about 100%. For example, without limitation, the mirror 103 can be silver, aluminum, gold, nanocrystalline oxides such as titanium dioxide, zinc oxide, magnesium oxide, aluminum oxide, etc. For example, the mirror 103 can be silver. For example, the mirror 103 can be aluminum.

[0016]

[0020] The input coupler 102 includes a sealing layer 104 disposed on the mirror 103, and the sealing layer 104 is disposed on the mirror 103 that is disposed only on the input coupler 102. In some embodiments that can also be combined with other embodiments, the sealing layer 104 is disposed only on the upper surface of the mirror 103. In other embodiments that can also be combined with other embodiments, the sealing layer 104 is disposed on the upper surface and one or more sidewalls of the mirror 103.

[0017]

[0021] The encapsulation layer 104 includes one or more materials for encapsulating or protecting the underlying layer (i.e., the mirror 103 and the substrate 101 of the waveguide 100). For example, the encapsulation layer 104 can include chromium, silicon nitride, silicon oxide (e.g., silicon dioxide), aluminum oxide, magnesium oxide, their dopants, or any combination thereof. The encapsulation layer 104 can be formed using one or more vapor deposition processes that do not utilize plasma, such as polymer printing (e.g., inkjet printing or screen printing). The encapsulation layer 104 may be formed using one or more vapor deposition processes that utilize plasma, such as a PVD or sputtering process, a furnace CVD (FCVD) process, a PE-CVD process, a PE-ALD process, or other plasma processes.

[0018]

[0022] In one or more examples, the encapsulation layer 104 may be deposited by a PVD process that includes generating ozone or oxygen plasma during deposition of the encapsulation layer 104. For example, silicon oxide can be deposited in a magnetron sputtering PVD chamber using a silicon target and reacting with a plasma containing argon and oxygen (Ar / O2). In other examples, the encapsulation layer 104 is deposited by inkjet printing one or more polymers or metals onto the mirror 103.

[0019]

[0023] The thickness of the sealing layer 104 is approximately 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or approximately 50 nm to 55 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, 120 nm, 135 nm, 150 nm, 180 nm, 200 nm, or greater. For example, the thickness of the encapsulation layer 104 is approximately 10nm to 200nm, 10nm to 180nm, 10nm to 150nm, 10nm to 120nm, 10nm to 100nm, 10nm to 80nm, 10nm to 60nm, 10nm to 50nm, 10nm to 40nm, 10nm to 20nm, 15nm to 50nm, 20nm to 200nm, 20nm to 180nm, 20nm to 150nm, 20nm to 120nm, 20nm to 100nm, These ranges are approximately 20nm to 80nm, 20nm to 60nm, 20nm to 50nm, 20nm to 40nm, 20nm to 30nm, 40nm to 200nm, 40nm to 180nm, 40nm to 150nm, 40nm to 120nm, 40nm to 100nm, 40nm to 80nm, 40nm to 60nm, 40nm to 50nm, 50nm to 60nm, 50nm to 150nm, 80nm to 120nm, or 90nm to 110nm. In some embodiments, the refractive index of the sealing layer 104 is about 1.0 to about 1.5, for example, about 1.0 to about 1.4, about 1.1 to about 1.4, about 1.2 to about 1.4, or about 1.2 to about 1.3.

[0020]

[0024] Waveguide 100 includes an output coupler 105. The output coupler 105 includes a second arrangement of waveguide structures 106 as described herein. Waveguide structures 106 in the second arrangement guide refracted or reflected light into the substrate 101 when it exits the substrate 101 and / or waveguide 100. Waveguide structures 106 may have a cross-section of a square, rectangular, circular, triangular, elliptical, regular polygon, irregular polygon, and / or irregular shape. Waveguide structures 106 in the second arrangement have depth and critical dimensions as described herein. In some embodiments, a medium fills one or more gaps between the waveguide structures 106 of the second arrangement of output coupler 105. In some embodiments, the medium has a refractive index of about 1. For example, the medium filling one or more gaps between the waveguide structures 106 of the second arrangement of output coupler may be air. The waveguide structure 106 in the second configuration has a structural refractive index as described herein.

[0021]

[0025] The plurality of waveguide structures 106 include, but are not limited to, one or more materials containing silicon (e.g., amorphous silicon), silicon carbide (SiC), silicon oxycarbide (SiOC), titanium dioxide (TiO2), silicon dioxide (SiO2), vanadium(IV) oxide (VOx), aluminum oxide (Al2O3), aluminum-doped zinc oxide (AZO), indium tin oxide (ITO), tin dioxide (SnO2), zinc oxide (ZnO), tantalum pentoxide (Ta2O5), silicon nitride (Si3N4), zirconium dioxide (ZrO2), niobium oxide (Nb2O5), cadmium stannate (Cd2SnO4), or silicon carbonitride (SiCN).

[0022]

[0026] Referring to Figure 2, Method 200 includes depositing mirrors 103 on a waveguide 100. The waveguide 100 includes an input coupler 102 and an output coupler 105. The mirrors 103 are deposited on a plurality of waveguide structures 106 of the waveguide 100. The mirrors 103 can be deposited by PVD or another vapor deposition process (such as CVD or ALD). The mirrors 103 can be deposited or formed by one or more processes or techniques such as CVD, plasma CVD (PE-CVD), near-atmospheric pressure CVD (SA-CVD), high-density plasma CVD (HDP-CVD), fluid CVD, ALD, furnace or thermal ALD, thermal ALD, plasma ALD (PE-ALD), PVD, sputtering, evaporation, ion beam deposition, inkjet printing, screen printing, or any combination thereof.

[0023]

[0027] Method 200 includes, in operation 202, depositing a sealing layer 104 on the mirror 103 as shown in Figure 3A. As shown in Figure 3A, the sealing layer 104 is located on the mirror 103. An anti-reflective coating layer 107 is located beneath the substrate 101. The sealing layer 104 is chromium or silicon nitride.

[0024]

[0028] In operation 203, a resist 302 is formed on the input coupler, as shown in Figure 3B. As shown in Figure 3B, the remaining sealing portion of the sealing layer 104 on the non-input coupler area is exposed. The resist 302 prevents the sealing layer 104 from being removed during subsequent processing steps.

[0025]

[0029] The resist 302 can be deposited by block photolithography procedures, such as spin-coating the resist, baking it, exposing it with a pattern, developing the area, and removing the resist in areas where no input couplers are present on the waveguide.

[0026]

[0030] In operation 204, as shown in Figure 3C, the remaining sealing portion of the sealing layer 104 is removed, exposing the remaining mirror portion of the mirror 103 on the exposed non-input coupler region. The etching process in operation 204 may include a wet etching process that etches the remaining portion of the sealing layer 104 using tetramethylammonium, potassium iodide, or iodine. For example, the etching process may be a dry etching process, which provides good selectivity between the sealing layer 104 and the mirror 103. As a further non-limiting example, the etching process may be a wet etching process that avoids oxidation of the mirror 103 and potential contamination of the chamber. The etching process can etch all of the remaining portion of the sealing layer 104 that is not covered by the resist 302 down to the mirror 103.

[0027]

[0031] In operation 205, an etching process is used to etch the remaining mirror portion of the mirror 103 of the input coupler 102, exposing the output coupler 105 of the waveguide 100, as shown in Figure 3D. The etching process includes a wet etching process using tetramethylammonium, potassium iodide, or iodine. The wet etching process can etch all of the remaining portion of the mirror 103 that is not covered by the resist 302 or the sealing layer 104 down to the multiple optical structures 301.

[0028]

[0032] In operation 206, the resist 302 is removed from the input coupler 102, as shown in Figure 3E. The waveguide has a mirror 103 only on the input coupler 102 and a sealing layer 104 only on the mirror 103. The resist 302 is removed according to one or more etching processes. The etching process in operation 206 may include a dry etching process using O2 plasma, an organic solvent such as propylene glycol methyl ether acetate (PGMEA), or a process that etches the remaining portion of the sealing layer 104 using a tetramethylammonium hydroxide (TMAH) solvent after a flood exposure procedure. The etching process can remove the resist 302 so that the input coupler 102 includes a sealing layer 104 placed on a mirror 103 placed on multiple waveguide structures 106 on the substrate 101. This process enables a single-block lithography process that forms a sealed mirror only on the input coupler of the waveguide and not on the output coupler, improving device efficiency and extending the lifespan of the silver-containing mirror.

[0029]

[0033] Referring to Figure 4, Method 400 includes, in Operation 401, depositing a mirror 103 on a waveguide 100, the waveguide having an input coupler 102 and an output coupler 105. The mirror 103 is deposited on a plurality of waveguide structures 106 of the waveguide 100. The mirror 103 can be deposited by PVD or another vapor deposition process (such as CVD or ALD). The mirror 103 can be deposited or formed by one or more processes or techniques such as CVD, plasma CVD (PE-CVD), near-atmospheric pressure CVD (SA-CVD), high-density plasma CVD (HDP-CVD), fluid CVD, ALD, furnace or thermal ALD, thermal ALD, plasma ALD (PE-ALD), PVD, sputtering, evaporation, ion beam deposition, inkjet printing, screen printing, or any combination thereof.

[0030] In operation 402, as shown in Figure 5A, a first resist 501 is formed on the input coupler, and the first resist is placed on the mirror 103. The remaining mirror portion of the mirror 103 is exposed on the output coupler 105. An anti-reflective coating layer 107 is placed beneath the substrate 101. The first resist 501 includes the optional resist 302 described above.

[0031]

[0034] In operation 403, the residual mirror portion of mirror 103 on the output coupler is removed, as shown in Figure 5B. The residual mirror portion of mirror 103 can be removed using a wet etching process. The wet etching process may include a process using tetramethylammonium, potassium iodide, or iodine. The wet etching process can etch all of the residual portion of mirror 103 that is not covered by the first resist 501.

[0032]

[0035] In operation 404, the first resist 302 is removed, as shown in Figure 5C. The resist 302 is removed according to one or more etching processes. The etching process in operation 404 may include a wet etching process using tetramethylammonium, a dry etching process using an organic solvent such as O2 plasma or propylene glycol methyl ether acetate (PGMEA), or a process to etch the remaining portion of the encapsulation layer 104 using tetramethylammonium hydroxide (TMAH) solvent after a flood exposure procedure. As shown in Figure 5C, the etching process can remove the first resist 501 such that the mirror 103 remains only where the first resist 501 remained.

[0033]

[0036] In operation 405, a sealing layer 104 is deposited on the mirror 103 and output coupler 105, as shown in Figure 5D. The sealing layer 104 can be deposited by PVD or another vapor deposition process (such as CVD or ALD). The sealing layer 104 can be deposited or formed by one or more processes or techniques such as CVD, plasma CVD (PE-CVD), near-atmospheric pressure CVD (SA-CVD), high-density plasma CVD (HDP-CVD), fluid CVD (FCVD® process), ALD, furnace or thermal ALD, thermal ALD, plasma ALD (PE-ALD), PVD, sputtering, evaporation, ion beam deposition, or any combination thereof.

[0034]

[0037] In operation 406, as shown in Figure 5E, a second resist 502 is formed on the mirror 103, and the remaining sealing portion of the sealing layer 104 over the non-input coupler region is exposed by the second resist 502. The second resist 502 prevents the sealing layer 104 from being etched during subsequent processing steps. The second resist 502 is formed to be wider than the mirror 103 in order to protect the sidewalls of the mirror 103 during later processing steps. The resist 502 may include, for example, any resist 302 or resist 501 described herein. The second resist 502 may be formed by a block photolithography procedure, for example, spin-coating the resist, baking it, exposing it in a pattern, developing the area, and removing the resist in areas on the waveguide where no input couplers are present.

[0035]

[0038] In operation 407, as shown in Figure 5F, the remaining sealing portion of the sealing layer 104 is removed, exposing the output coupler 105 of the waveguide 100. For example, the etching process in operation 407 could include etching the chromium layer using a chromium etchant (e.g., cerium ammonium / acetic acid) to etch the remaining portion of the sealing layer 104. Since the second resist 502 is wider than the mirror 103, the sealing layer 104 can be left both on the sides of the mirror 103 and on top of the mirror, as shown in Figure 5F. This protects the mirror 103 from oxidizing agents and potential etching problems.

[0036]

[0039] In operation 408, as shown in Figure 5G, the second resist 502 is removed from the waveguide 100, and the waveguide 100 has the mirror 103 only on the input coupler 102, and the sealing layer 104 is on the mirror 103 only, or on the mirror 103 and on the outer portion of the input coupler 102 surrounding the grating of the input coupler 102. The sealing layer 104 may remain on one or more sidewalls of the mirror 103. The second resist 502 is removed according to one or more etching processes. The etching process in operation 408 may include a wet etching process using tetramethylammonium, or a dry etching process using an organic solvent such as O2 plasma or propylene glycol methyl ether acetate (PGMEA), or a process to etch the remaining portion of the sealing layer 104 using tetramethylammonium hydroxide (TMAH) solvent after a flood exposure procedure. The etching process can remove the second resist 502 such that only the input coupler 102 includes the sealing layer 104 placed on the mirror 103, and the top layer of the mirror 103 and the side walls of the mirror 103 are protected.

[0037]

[0040] Overall, the methods described herein provide waveguides having a mirror only on the input coupler, or having a sealing layer only on the mirror, or on the mirror and on the outer portion of the input coupler surrounding the grating of the input coupler. The mirror layer only on the input coupler and the sealing layer provide a barrier against the ingress of oxygen, sulfur, and moisture. The sealing layer protects the mirror from corrosion in the ambient atmosphere.

[0038]

[0041] The foregoing relates to embodiments of the present disclosure, but other embodiments and further embodiments of the present disclosure can be devised without departing from its basic scope, the scope of which is determined by the appended claims.

Claims

1. It is a substrate, An input coupler comprising a waveguide structure in a first configuration, wherein the waveguide structure in the first configuration has critical dimensions defining one or more gaps between each waveguide structure of the waveguide structure in the first configuration, An output coupler comprising a second arrangement of waveguide structures, wherein the second arrangement of waveguide structures has critical dimensions defining one or more gaps between each waveguide structure of the second arrangement of waveguide structures, A substrate including, A mirror disposed on the input coupler, wherein the mirror is disposed in one or more gaps between each waveguide structure of the first waveguide structure, A sealing layer disposed on the mirror, wherein the sealing layer has a refractive index of about 1.0 to about 1.5, A medium having a refractive index of approximately 1.0, placed on the output coupler, and a medium placed in one or more gaps between each waveguide structure of the second arrangement of waveguide structures, A device equipped with the following features.

2. The device according to claim 1, wherein the sealing layer is disposed only on the upper surface of the mirror.

3. The device according to claim 2, wherein the sealing layer is further disposed on one or more side walls of the mirror.

4. The device according to claim 1, wherein the mirror has a reflectance greater than 90%.

5. Attaching mirrors to a waveguide having an input coupler and an output coupler, Depositing a sealing layer on the aforementioned mirror, Forming a resist on the input coupler such that the residual sealing portion of the sealing layer on the non-input coupler region is exposed. Removing the remaining sealing portion of the sealing layer, such that the remaining mirror portion of the mirror on the non-input coupler region is exposed, Removing the remaining mirror portion of the mirror of the input coupler, such that the non-input coupler region of the waveguide is exposed, Removing the resist on the input coupler, wherein the waveguide has the mirror only on the input coupler and the sealing layer only on the mirror, A method that includes this.

6. Forming the resist on the input coupler means Depositing a resist layer on the aforementioned sealing layer, The resist layer is patterned so that the remaining sealed portion is exposed. The method according to claim 5, including the method described in claim 5.

7. The method according to claim 5, wherein depositing the sealing layer comprises performing one or more gas-phase deposition processes.

8. The method according to claim 7, wherein performing one or more gas-phase deposition processes includes generating an oxygen plasma.

9. The method according to claim 5, wherein the sealing layer is chromium or silicon nitride.

10. The method according to claim 5, wherein the mirror is made of silver or aluminum.

11. The method of claim 5, wherein removing the residual sealing portion of the sealing layer includes etching the residual sealing portion of the sealing layer using an etching process.

12. The method according to claim 11, wherein the etching process is a wet etching process or a dry etching process.

13. Attaching mirrors to a waveguide having an input coupler and an output coupler, Forming a first resist on the input coupler, wherein the remaining mirror portion of the mirror on the non-input coupler region is exposed. Removing the remaining mirror portion of the mirror on the non-input coupler region, Removing the first resist, Depositing a sealing layer on the mirror and on the non-input coupler region, Forming a second resist on the mirror such that the remaining sealing portion of the sealing layer on the non-input coupler region is exposed by the second resist, Removing the remaining sealing portion, such that the non-input coupler region of the waveguide is exposed, Removing the second resist, wherein the waveguide has the mirror only on the input coupler and the sealing layer, Having only on the aforementioned mirror, or The mirror and the outer portion of the input coupler surrounding the grating of the input coupler are provided. Removing the second resist, A method that includes this.

14. Forming the resist on the input coupler means Depositing a resist layer on the aforementioned sealing layer, The resist layer is patterned so that the remaining sealed portion is exposed. The method according to claim 13, including the method described in claim 13.

15. The method according to claim 14, wherein the deposition of the sealing layer comprises performing one or more gas-phase deposition processes.

16. The method according to claim 15, wherein performing one or more gas-phase deposition processes includes generating an oxygen plasma.

17. The method according to claim 13, wherein the sealing layer is chromium or silicon nitride.

18. The method according to claim 13, wherein the mirror is made of silver or aluminum.

19. The method according to claim 13, wherein removing the residual sealing portion of the sealing layer includes etching the sealing layer using an etching process.

20. The method according to claim 19, wherein the etching process is a wet etching process or a dry etching process.

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