Display panel

Abstract

This invention provides a display panel in which, in at least one inverter unit, the active pattern of a first transistor is provided corresponding to a shield layer, and the potential of the shield layer is smaller than the potential of the low-potential line, thereby causing the threshold voltage of the first transistor to be positively biased, thereby avoiding the generation of leakage current when the oxide semiconductor transistor is turned off, reducing the power consumption of the gate drive unit, and enabling the display panel to operate normally.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to display panels.

Background Art

[0002] With the development of display technology, the requirements for the display effect of conventional display devices are becoming increasingly high. In order to improve the display effect, conventional display devices use LTPO (Low Temperature Polysilicon Oxide) pixel circuits. However, since the LTPO pixel driving circuit requires more GOA (Gate On Array, a gate driving circuit provided on the array substrate) circuit output signals, it causes an increase in the power consumption of the display device. In order to reduce the power consumption of the display device, a CMOS (Complementary Metal Oxide Semiconductor) GOA circuit is used to reduce the number of GOA circuits. In the CMOS GOA circuit, the input of different signals is controlled by an inverter to realize the control of the output signal for the CMOS GOA circuit. Specifically, the inverter is composed of one oxide semiconductor transistor and one silicon semiconductor transistor. The gate of the oxide semiconductor transistor is connected to the gate of the silicon semiconductor transistor, and the source of the oxide semiconductor transistor and the source of the low-temperature polysilicon are connected to a low potential and a high potential, respectively, so that the inverter outputs signals of different potentials with different control signals. However, in the actual use process, when the inverter is operating, it is found that the oxide semiconductor transistor cannot be turned off and there is a leakage current in the oxide semiconductor transistor. As a result, the output of the inverter does not reach the expectation, and the only option is to increase the output voltage. Thereby, the power consumption of the GOA circuit increases, the power consumption of the display device increases, and there is a possibility of causing an output abnormality of the GOA circuit.

[0003] Therefore, conventional CMOS GOA circuits have a technical challenge: when oxide semiconductor transistors are turned off, leakage current is generated, causing an increase in the power consumption of the display device. [Overview of the project] [Problems that the invention aims to solve]

[0004] Embodiments of the present invention provide a display panel to solve the technical problem in conventional CMOS GOA circuits, in which leakage current is generated when oxide semiconductor transistors are turned off, causing an increase in the power consumption of the display device. [Means for solving the problem]

[0005] To solve the above problems, the technical solution provided by this application is as follows:

[0006] Embodiments of the present application provide a display panel comprising a display unit and a gate drive circuit located on at least one side of the display unit, wherein the gate drive circuit comprises a plurality of gate drive units connected in cascade.

[0007] The gate drive unit includes at least three inverter units, each inverter unit including one high-potential line, one low-potential line, and a first transistor and a second transistor connected in series between the high-potential line and the low-potential line, wherein the first transistor is an oxide semiconductor transistor and the second transistor is a silicon semiconductor transistor, and the gates of the first transistor and the gates of the second transistor are electrically connected to the same node.

[0008] Here, the display panel further includes a shielding layer, and in at least one of the inverter units, the active pattern of the first transistor is provided corresponding to the shielding layer, and the potential of the shielding layer is less than the potential of the low-potential line. [Brief explanation of the drawing]

[0009] The following will clarify the technical proposal and the effects of the invention by providing a detailed explanation of specific embodiments of the present application with reference to the drawings.

[0010] [Figure 1] This is a circuit diagram showing the CMOS GOA circuit of a conventional display device.

[0011] [Figure 2] This is a timing diagram of each transistor and signal terminal in a conventional CMOS GOA circuit for a display device.

[0012] [Figure 3] This is a first schematic diagram showing a display panel provided by an embodiment of the present application.

[0013] [Figure 4] This is a first circuit diagram showing a gate drive unit of a display panel provided by an embodiment of the present application.

[0014] [Figure 5] This is a circuit diagram showing a pixel driving circuit provided by an embodiment of the present application.

[0015] [Figure 6] This is a line graph showing the relationship between the voltage offset amount and current with respect to the threshold voltage of the first control transistor provided by the embodiment of the present application.

[0016] [Figure 7] This is a second circuit diagram showing the gate drive unit of a display panel provided by an embodiment of the present application.

[0017] [Figure 8] This is a second schematic diagram showing a display panel provided by an embodiment of the present application.

[0018] [Figure 9]It is a first laminated diagram showing each film layer of the gate drive circuit provided by an embodiment of the present application.

[0019] [Figure 10] It is an exploded view showing a first active layer and a first metal layer in the gate drive circuit of FIG. 9.

[0020] [Figure 11] It is an exploded view showing a second metal layer and a second active layer in the gate drive circuit of FIG. 9.

[0021] [Figure 12] It is an exploded view showing a third metal layer and a first source-drain layer in the gate drive circuit of FIG. 9.

[0022] [Figure 13] It is an exploded view showing a second source-drain layer in the gate drive circuit of FIG. 9.

[0023] [Figure 14] It is an exploded view showing a first via and a second via in the gate drive circuit of FIG. 9.

[0024] [Figure 15] It is an exploded view showing a third via in the gate drive circuit of FIG. 9.

[0025] [Figure 16] It is a second laminated diagram showing each film layer of the gate drive circuit provided by an embodiment of the present application.

[0026] [Figure 17] It is an exploded view showing a shield layer and a first active layer in the gate drive circuit of FIG. 16.

[0027] [Figure 18] It is an exploded view showing a first metal layer and a second metal layer in the gate drive circuit of FIG. 16.

[0028] [Figure 19] Figure 16 is an exploded view showing the second active layer and the third metal layer in the gate drive circuit.

[0029] [Figure 20] Figure 16 is an exploded view showing the first source-drain layer in the gate drive circuit.

[0030] [Figure 21] Figure 16 is an exploded view showing the second source-drain layer in the gate drive circuit.

[0031] [Figure 22] Figure 16 is an exploded view showing the first and second vias in the gate drive circuit.

[0032] [Figure 23] Figure 16 is an exploded view showing the third via in the gate drive circuit.

[0033] [Figure 24] This is a third schematic diagram showing a display panel provided by an embodiment of the present application.

[0034] [Figure 25] This is a fourth schematic diagram showing a display panel provided by an embodiment of the present application.

[0035] [Figure 26] This is a third circuit diagram showing the gate drive unit of a display panel provided by an embodiment of the present application.

[0036] [Figure 27] This is a schematic diagram showing a display device provided by an embodiment of the present application. [Modes for carrying out the invention]

[0037] The technical proposal in the embodiments of this application will be described clearly and completely below with reference to the drawings of the embodiments. It is clear that the embodiments described are only a selection of embodiments of this application, and not all embodiments. All other embodiments that a person skilled in the art could obtain without inventive effort based on the embodiments of this application are within the scope of protection of this application.

[0038] In the description of this application, terms indicating orientation or positional relationships such as “center,” “vertical,” “horizontal,” “length,” “width,” “thickness,” “top,” “bottom,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” “outside,” “clockwise,” and “counterclockwise” are based on the orientation or positional relationships shown in the figures and are for the purpose of describing and simplifying the description of this application. It should be understood that these terms do not indicate or suggest that the referred device or element should have a particular orientation, is configured in a particular orientation, or operates in a particular orientation. Therefore, they should not be interpreted as limitations on this application. Furthermore, the terms “first” and “second” are for descriptive purposes only and should not be interpreted as indicating or suggesting relative importance or the number of technical features shown. Therefore, features defined as “first” and “second” may explicitly or implicitly include one or more such features. In the description of this application, the term “multiple” means two or more unless otherwise specifically defined.

[0039] In the description of this application, unless otherwise clearly defined and limited, the term “connected” means that two parties are directly connected, and the term “electrically connected” means that two parties may be directly connected or indirectly connected by an intermediate medium. A person skilled in the art will be able to understand the specific meaning of the above terms in this application in accordance with the specific embodiment.

[0040] In this application, unless otherwise specifically defined and limited, the position of a first feature "above" or "below" a second feature may include the first feature being in direct contact with the second feature, or it may include the first feature not being in direct contact with the second feature but being in contact with it by other features between them. Furthermore, the position of a first feature "above," "above," or "upper side" a second feature may include the first feature being directly above or diagonally above the second feature, or it may simply mean that the height of the first feature is greater than that of the second feature. The position of a first feature "below," "below," or "below side" a second feature may include the first feature being directly below or diagonally below the second feature, or it may simply mean that the height of the first feature is lower than that of the second feature.

[0041] The following description provides various different embodiments or examples of the present application to realize different configurations of the present application. For the sake of brevity of the description of the present application, elements and configurations of specific embodiments are described below. Needless to say, these are merely illustrative and are not intended to limit the present application. Furthermore, for the purposes of simplification and clarity, the present application may repeat reference numerals and / or reference numerals in different examples. These in themselves do not indicate relationships between the various embodiments and / or configurations described. Also, the present application provides examples of various specific processes and materials, but those skilled in the art can conceive of applying other processes and / or using other materials based on them.

[0042] As shown in Figure 1, in a conventional CMOS GOA circuit of a display device, two scanning signals are output within a single-stage GOA unit, realizing a frequency division function. As shown in Figure 1, the GOA circuit consists of a first transistor To1, a second transistor To2, a third transistor To3, a fourth transistor To4, a fifth transistor To5, a sixth transistor To6, a seventh transistor To7, an eighth transistor To8, a ninth transistor To9, a tenth transistor To10, an eleventh transistor To11, a twelfth transistor To12, a thirteenth transistor To13, a fourteenth transistor To14, a fifteenth transistor To15, a sixteenth transistor To16, a seventeenth transistor To17, an eighteenth transistor To18, a nineteenth transistor To19, and a twenty-tenth transistor To20. The GOA circuit includes a 21st transistor To21, a 22nd transistor To22, a first capacitor Co1, a second capacitor Co2, and a third capacitor Co3. The GOA circuit is controlled by a control line Ctl, a start line STV1, a first clock line CK1, and a second clock line XCK1, and receives high and low potentials via a first high potential line PVGH1, a second high potential line NVGH1, a first low potential line PVGL1, and a second low potential line NVGL1 to realize the outputs of the first output terminal Nout(n)1 and the second output terminal Pout(n)1. The first frequency division line NLF1 and the second frequency division line PLF1 realize the display of the frequency division of the display device. Here, the start line STV1 is connected to the third output terminal Nout(n-1)1 in the GOA unit one stage prior, the gate of the seventh transistor To7 is connected to the gate of the sixteenth transistor To16, the gate of the twentyth transistor To20, and node P1(n) of the current stage, and the gate of the eighth transistor To8 is connected to node P1(n-2) two stages prior.

[0043] Specifically, as can be seen from Figure 1, the 13th transistor To13 is an oxide semiconductor transistor, and the 12th transistor To12 is a silicon semiconductor transistor. When the third output terminal Nout(n-1)1 in the GOA unit one stage prior outputs a low potential, the potential difference between the gate and source of the 13th transistor To13 is 0. At that time, the 13th transistor To13 is normally turned off. However, in actual use, due to manufacturing process biases, the threshold voltage of the 13th transistor To13 becomes negatively biased, and in the worst case, the threshold voltage becomes negatively biased to -1 volt, preventing the 13th transistor To13 from being turned off. This causes a certain amount of leakage current in the 13th transistor To13, resulting in an abnormality in the output signal of the connected node O1. It was discovered that this abnormality manifests as an output abnormality at the first output terminal Nout(n)1 and the second output terminal Pout(n)1.

[0044] As shown in Figure 2, Figure 2 is a timing diagram of the voltage for each signal line and a timing diagram of the current for each transistor. In Figure 2, the horizontal coordinate represents time, the vertical coordinate of the timing diagram for each transistor represents current in microamperes, and the vertical coordinate of the timing diagram for each signal line represents voltage in volts. As can be seen from Figure 2, when the first transistor To1 and the tenth transistor To10 are operating and outputting a low potential from the third output terminal Nout(n-1)1 of the GOA unit one stage prior, and inputting a low potential to the start line STV1, the thirteenth transistor To13 is turned off, and at that time the twelfth transistor To12 is turned on, and normally outputs a predetermined high potential (for example, the potential input by the first high potential line PVGH1) from the first output terminal Nout(n)1. However, as can be seen from Figure 2, the potential output from the first output terminal Nout(n)1 does not reach the predetermined high potential, and an abnormality occurs in the potential output from the first output terminal Nout(n)1. On the other hand, the second output terminal Pout(n)1 is controlled by the potential of the connected node O1, so there is a risk of an abnormality occurring there as well. In other words, the thirteenth transistor To13 cannot be turned off, so a leakage current is generated and an output abnormality occurs in the GOA unit. Therefore, conventional CMOS GOA circuits have a technical challenge: when oxide semiconductor transistors are turned off, leakage current is generated, causing an increase in the power consumption of the display device.

[0045] The embodiment of this application provides a display panel to address the above technical problem and is used to solve the above technical problem.

[0046] Figure 3 is a first schematic diagram showing a display panel provided by an embodiment of the present application. Figure 4 is a first circuit diagram showing a gate drive unit of a display panel provided by an embodiment of the present application. Figure 5 is a circuit diagram showing a pixel drive circuit provided by an embodiment of the present application. Figure 6 is a piecewise line graph of voltage offset and current with respect to threshold voltage of a first control transistor provided by an embodiment of the present application. Figure 7 is a second circuit diagram showing a gate drive unit of a display panel provided by an embodiment of the present application. Figure 8 is a second schematic diagram showing a display panel provided by an embodiment of the present application. Figure 9 is a first stacked diagram showing each film layer of the gate drive circuit provided by an embodiment of the present application. Figure 10 is an exploded view showing the first active layer and the first metal layer in the gate drive circuit of Figure 9. Here, Figure 10(a) is an exploded view showing the first active layer in the gate drive circuit of Figure 9, and Figure 10(b) is an exploded view showing the first metal layer in the gate drive circuit of Figure 9. Figure 11 is an exploded view showing the second metal layer and the second active layer in the gate drive circuit of Figure 9. Here, Figure 11(a) is an exploded view showing the second metal layer in the gate drive circuit of Figure 9, and Figure 11(b) is an exploded view showing the second active layer in the gate drive circuit of Figure 9. Figure 12 is an exploded view showing the third metal layer and the first source-drain layer in the gate drive circuit of Figure 9. Here, Figure 12(a) is an exploded view showing the third metal layer in the gate drive circuit of Figure 9, and Figure 12(b) is an exploded view showing the first source-drain layer in the gate drive circuit of Figure 9. Figure 13 is an exploded view showing the second source-drain layer in the gate drive circuit of Figure 9. Figure 14 is an exploded view showing the first via and the second via in the gate drive circuit of Figure 9. Here, Figure 14(a) is an exploded view showing the first via in the gate drive circuit of Figure 9, and Figure 14(b) is an exploded view showing the second via in the gate drive circuit of Figure 9. Figure 15 is an exploded view showing the third via in the gate drive circuit of Figure 9. Figure 16 is a second stacked view showing each film layer of the gate drive circuit provided by the embodiment of the present application. Figure 17 is an exploded view showing the shield layer and the first active layer in the gate drive circuit of Figure 16.Here, Figure 17(a) is an exploded view showing the shield layer in the gate drive circuit of Figure 16, and Figure 17(b) is an exploded view showing the first active layer in the gate drive circuit of Figure 16. Figure 18 is an exploded view showing the first and second metal layers in the gate drive circuit of Figure 16. Here, Figure 18(a) is an exploded view showing the first metal layer in the gate drive circuit of Figure 16, and Figure 18(b) is an exploded view showing the second metal layer in the gate drive circuit of Figure 16. Figure 19 is an exploded view showing the second active layer in the gate drive circuit of Figure 16. Here, Figure 19(a) is an exploded view showing the second active layer in the gate drive circuit of Figure 16, and Figure 19(b) is an exploded view showing the third metal layer in the gate drive circuit of Figure 16. Figure 20 is an exploded view showing the first source-drain layer in the gate drive circuit of Figure 16. Figure 21 is an exploded view showing the second source-drain layer in the gate drive circuit of Figure 16. Figure 22 is an exploded view showing the first and second vias in the gate drive circuit of Figure 16. Here, Figure 22(a) is an exploded view showing the first via in the gate drive circuit of Figure 16, and Figure 22(b) is an exploded view showing the second via in the gate drive circuit of Figure 16. Figure 23 is an exploded view showing the third via in the gate drive circuit of Figure 16. Figure 24 is a third schematic diagram showing a display panel provided by an embodiment of the present application. Figure 25 is a fourth schematic diagram showing a display panel provided by an embodiment of the present application. Figure 26 is a third circuit diagram showing the gate drive unit of the display panel provided by an embodiment of the present application. Figure 27 is a schematic diagram showing a display device provided by an embodiment of the present application.

[0047] As shown in Figures 3 to 26, an embodiment of the present invention provides a display panel 1 which includes a display unit 11 and a gate drive circuit 12 located on at least one side of the display unit 11, the gate drive circuit 12 which includes a plurality of gate drive units 120 connected in cascade, the gate drive units 120 which include at least three inverter units (for example, a first inverter unit 10, a second inverter unit 30, and a third inverter unit 20), each of the inverter units which includes one high-potential line, one low-potential line, and a first transistor and a second transistor connected in series between the high-potential line and the low-potential line (for example, the first... The converter unit 10 includes a first control transistor T13, a second control transistor T12, a second high-potential signal line PVGH, and a second low-potential signal line PVGL. The first transistor is an oxide semiconductor transistor (for example, the first control transistor T13 is an oxide semiconductor transistor), the second transistor is a silicon semiconductor transistor (for example, the second control transistor T12 is a silicon semiconductor transistor), and the gates of the first and second transistors are electrically connected to the same node (for example, the first control transistor T13 and the second control transistor T12 are electrically connected to the same node).

[0048] Here, in at least one of the inverter units, when the first transistor is in the off state, the voltage difference between the gate of the first transistor and the second electrode of the first transistor is smaller than the threshold voltage of the first transistor (for example, in the first inverter unit 10, when the first control transistor T13 is in the off state, the voltage difference between the gate T13G of the first control transistor T13 and the second electrode T13S of the first control transistor T13 is smaller than the threshold voltage of the first control transistor T13).

[0049] An embodiment of the present invention provides a display panel in which, in at least one inverter unit, when the first transistor is in the off state, the voltage difference between the gate of the first transistor and the second electrode of the first transistor is smaller than the threshold voltage of the first transistor, thereby preventing leakage current from occurring in the first transistor when the first transistor is in the off state, thereby reducing the power consumption of the gate drive unit, reducing the power consumption of the display panel without affecting the output signal of the gate drive unit, and allowing the display panel to operate normally.

[0050] Specifically, to make it easier to understand, if the gate drive unit includes three inverter units, when the first transistor in one of the inverter units is in the off state, the voltage difference between the gate of the first transistor and the second electrode of the first transistor may be less than the threshold voltage of the first transistor; when the first transistor in two of the inverter units is in the off state, the voltage difference between the gate of the first transistor and the second electrode of the first transistor may be less than the threshold voltage of the first transistor; or when the first transistor in three of the inverter units is in the off state, the voltage difference between the gate of the first transistor and the second electrode of the first transistor may be less than the threshold voltage of the first transistor.

[0051] In some embodiments, as shown in Figures 3 to 26, the display panel 1 includes a display unit 11 and a gate drive circuit 12 located on at least one side of the display unit 11, the gate drive circuit 12 includes a plurality of cascaded gate drive units 120, the gate drive unit 120 includes at least three inverter units (for example, a first inverter unit 10, a second inverter unit 30, and a third inverter unit 20), each inverter unit includes one high-potential line, one low-potential line, and a first transistor and a second transistor connected in series between the high-potential line and the low-potential line (for example, the first inverter... Unit 10 includes a first control transistor T13, a second control transistor T12, a second high-potential signal line PVGH, and a second low-potential signal line PVGL, wherein the first transistor is an oxide semiconductor transistor (for example, the first control transistor T13 is an oxide semiconductor transistor), the second transistor is a silicon semiconductor transistor (for example, the second control transistor T12 is a silicon semiconductor transistor), and the gates of the first transistor and the gates of the second transistor are electrically connected to the same node (for example, the first control transistor T13 and the second control transistor T12 are electrically connected to the same node).

[0052] Here, the display panel 1 further includes a shield layer 202, and in at least one of the inverter units (for example, in the first inverter unit 10), the active pattern of the first transistor is provided corresponding to the shield layer (for example, the active pattern T13A of the first control transistor T13 is provided corresponding to the shield layer 202), and the potential of the shield layer is smaller than the potential of the low-potential line.

[0053] An embodiment of the present invention provides a display panel in which, in at least one inverter unit, the active pattern of a first transistor is provided corresponding to a shield layer, and the potential of the shield layer is smaller than the potential of the low-potential line, thereby causing the threshold voltage of the first transistor to be positively biased, thereby avoiding the generation of leakage current when the oxide semiconductor transistor is turned off, reducing the power consumption of the gate drive unit, and reducing the power consumption of the display panel without affecting the output signal of the gate drive unit, allowing the display panel to operate normally.

[0054] In some embodiments, as shown in Figures 3 to 26, the display panel 1 includes a display unit 11 and a gate drive circuit 12 located on at least one side of the display unit 11, the gate drive circuit 12 includes a plurality of cascaded gate drive units 120, the gate drive unit 120 includes at least three inverter units (for example, a first inverter unit 10, a second inverter unit 30, and a third inverter unit 20), each inverter unit includes one high-potential line, one low-potential line, and a first transistor and a second transistor connected in series between the high-potential line and the low-potential line (for example, the first inverter... Unit 10 includes a first control transistor T13, a second control transistor T12, a second high-potential signal line PVGH, and a second low-potential signal line PVGL, wherein the first transistor is an oxide semiconductor transistor (for example, the first control transistor T13 is an oxide semiconductor transistor), the second transistor is a silicon semiconductor transistor (for example, the second control transistor T12 is a silicon semiconductor transistor), and the gates of the first transistor and the gates of the second transistor are electrically connected to the same node (for example, the first control transistor T13 and the second control transistor T12 are electrically connected to the same node).

[0055] Here, the display unit 11 further includes a pixel driving circuit 110, in which an oxide semiconductor transistor (for example, the compensation transistor T33 is an oxide semiconductor transistor) is provided within an oxide semiconductor transistor, and the channel length of the first transistor is greater than the channel length of the oxide semiconductor transistor (for example, the channel length of the first control transistor T13 is greater than the channel length of the compensation transistor T33).

[0056] The embodiment of the present invention provides a display panel in which the channel length of the first transistor is greater than the channel length of the oxide semiconductor transistor of the display unit, thereby causing the threshold voltage of the first transistor to be positively biased. This reduces the difference between the potential difference between the gate and the second electrode of the first transistor and the threshold voltage of the first transistor, thereby avoiding leakage current of the first transistor and reducing the power consumption of the display panel.

[0057] Specifically, the above-described embodiment is explained using the design of the first inverter unit as an example, but the embodiment of the present application is not limited thereto, and the second inverter unit may also use the above-described design, and the third inverter unit may also use the above-described design.

[0058] In some embodiments, as shown in Figures 3-26, at least three inverter units are provided.

[0059] A first inverter unit 10 includes a first control transistor T13 and a second control transistor T12, wherein the first control transistor T13 is an oxide semiconductor transistor, the second control transistor T12 is a silicon semiconductor transistor, the gate T13G of the first control transistor T13 and the gate T12G of the second control transistor T12 are connected to an initial signal line STV, and the first electrode T13D of the first control transistor T13 and the first electrode T12D of the second control transistor T12 are electrically connected to a first node K.

[0060] A second inverter unit 30 includes a first output transistor T10, a second output transistor T9, a first low-potential signal line NVGL, and a first high-potential signal line NVGH, wherein the first output transistor T10 is an oxide semiconductor transistor, the second output transistor T9 is a silicon semiconductor transistor, the gate T10G of the first output transistor T10 is connected to the first node K, the gate T9G of the second output transistor T9 is electrically connected to the first node K, the first electrode T10D of the first output transistor T10 and the first electrode T9D of the second output transistor T9 are connected to the first signal output terminal Nout(n), the second electrode of the first output transistor T10 is connected to the first low-potential signal line NVGL, and the second electrode T9S of the second output transistor T9 is connected to the first high-potential signal line NVGH.

[0061] The third inverter unit 20 includes a third control transistor T1, a fourth control transistor T3, a second low-potential signal line PVGL, and a second high-potential signal line PVGH, wherein the third control transistor T1 is an oxide semiconductor transistor, the fourth control transistor T3 is a silicon semiconductor transistor, the gate T1G of the third control transistor T1 and the gate T3G of the fourth control transistor T3 are connected to the first node K, the first electrode T1D of the third control transistor T1 and the first electrode T3D of the fourth control transistor T3 are connected to the internal node P(n) of the current stage, the second electrode T1S of the third control transistor T1 is connected to the second low-potential signal line PVGL, and the second electrode T3S of the fourth control transistor T3 is connected to the second high-potential signal line PVGH.

[0062] Specifically, for the first inverter unit, the first transistor is the first control transistor, the second transistor is the second control transistor, the high-potential line is the second high-potential signal line, and the low-potential line is a different low-potential signal line depending on the different embodiment, and may also be the first low-potential signal line. For the second inverter unit, the first transistor is the first output transistor, the second transistor is the second output transistor, the high-potential line is the first high-potential signal line, and the low-potential line is the first low-potential signal line. For the third inverter unit, the first transistor is the third control transistor, the second transistor is the fourth control transistor, the high-potential line is the second high-potential line, and the low-potential line is the second low-potential signal line.

[0063] In some embodiments, when the first control transistor T13 is in the off state, the voltage difference between the gate T13G of the first control transistor T13 and the second electrode T13S of the first control transistor T13 is smaller than the threshold voltage of the first control transistor T13.

[0064] In the embodiment of the present invention, when the first control transistor is in the off state, the voltage difference between the gate of the first control transistor and the second electrode of the first control transistor is smaller than the threshold voltage of the first control transistor. As a result, when the first control transistor is in the off state, no leakage current is generated in the first control transistor, which in turn reduces the power consumption of the gate drive unit, does not affect the output signal of the gate drive unit, reduces the power consumption of the display panel, and allows the display panel to operate normally.

[0065] In some embodiments, as shown in Figure 4, when the third control transistor T1 is in the off state, the voltage difference between the gate T1G of the third control transistor T1 and the second electrode T1S of the third control transistor T1 is smaller than the threshold voltage of the third control transistor T1.

[0066] And / or, when the first output transistor T10 is in the off state, the voltage difference between the gate T10G of the first output transistor T10 and the second electrode T10S of the first output transistor T10 is smaller than the threshold voltage of the first output transistor T10. When the third control transistor is in the off state, the voltage difference between the gate of the third control transistor and the second electrode of the third control transistor is smaller than the threshold voltage of the third control transistor. As a result, when the third control transistor is in the off state, no leakage current is generated in the third control transistor, which in turn reduces the power consumption of the gate drive unit, does not affect the output signal of the gate drive unit, reduces the power consumption of the display panel, and allows the display panel to operate normally. When the first output transistor is in the off state, the voltage difference between the gate of the first output transistor and the second electrode of the first output transistor is smaller than the threshold voltage of the first output transistor. As a result, when the first output transistor is in the off state, no leakage current is generated in the first output transistor, which in turn reduces the power consumption of the gate drive unit, does not affect the output signal of the gate drive unit, reduces the power consumption of the display panel, and allows the display panel to operate normally.

[0067] Specifically, the gate drive unit further includes a first signal output terminal Nout(n).

[0068] Specifically, in the gate drive unit, the output signals of the first signal output terminal Nout(n) and the second signal output terminal Pout(n) are affected by the potential of the first node K, while the first node K is affected by the output of the first inverter unit. Therefore, the potential of the first node K is affected by the leakage current of the first control transistor T13. In this embodiment of the present invention, by avoiding the leakage current of the first control transistor, the output signals of the first output signal line and the second signal output terminal can be made normal, and power consumption can be reduced. Furthermore, considering that the output signals of the third inverter unit and the second inverter unit also affect the output signals of the first signal output terminal Nout(n) and the second signal output terminal Pout(n), and thus increase power consumption, the embodiment of the present invention further avoids the generation of leakage current in each transistor by ensuring that the voltage difference between the gate of the third control transistor and the second electrode of the third control transistor is smaller than the threshold voltage of the third control transistor, and / or the voltage difference between the gate of the first output transistor T10 and the second electrode of the first output transistor T10 is smaller than the threshold voltage of the first output transistor T10, thereby reducing the power consumption of the gate drive unit.

[0069] Specifically, the second control transistor T12 is a silicon semiconductor transistor, it is a P-type transistor, and the first control transistor T13 is an N-type transistor.

[0070] Specifically, as shown in Figure 3, the display panel 1 includes a display area AA and a non-display area NA, the display unit 11 is provided in the display area AA, and the gate drive circuit 12 is provided in the non-display area NA.

[0071] Specifically, in the embodiments of this application, since some thin-film transistors employ a dual-gate design, if the first and second gates of such thin-film transistors are not explicitly distinguished, the term "gate of this thin-film transistor" refers to both gates of this thin-film transistor. For example, in some embodiments of this application, the gate of the first control transistor T13 includes a first gate T13Ga and a second gate T13Gb, and the statement that the gate of the first control transistor is connected to the gate of another transistor means that both the first and second gates of the first control transistor are connected to the gates of other transistors. Similarly, if other thin-film transistors include dual gates, refer to the above description, which is omitted here.

[0072] Specifically, in the display panel 1 provided by the embodiment of the present application, the gate drive circuit 12 includes a plurality of overlapping units, each overlapping unit includes at least four gate drive units 120. Hereinafter, the case in which four gate drive units 120 are used as one overlapping unit will be used as an example, and the plurality of overlapping units will be arranged in a first direction.

[0073] As shown in Figures 9 to 15, the duplicate unit includes a first gate drive unit 121, a second gate drive unit 122, a third gate drive unit 123, and a fourth gate drive unit 124 arranged sequentially along the first direction, and the display panel includes a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4 arranged along the second direction, with every two clock signal lines connected to one gate drive unit 120.

[0074] In this embodiment, the first clock signal line PCK1 and the second clock signal line PCK2 are connected to the first gate drive unit 121. The first clock signal line PCK1 is the first clock signal line CK of the first gate drive unit 121, and the second clock signal line PCK2 is the second clock signal line XCK of the first gate drive unit 121. Specifically, the first clock signal line PCK1 is connected to the second electrode of the third output transistor T6 in the first gate drive unit 121, and the second clock signal line PCK2 is connected to the gate of the seventh control transistor T21 in the first gate drive unit 121.

[0075] In this embodiment, the second clock signal line PCK2 and the third clock signal line PCK3 are connected to the second gate drive unit 122. The second clock signal line PCK2 is the first clock signal line CK of the second gate drive unit 122, and the third clock signal line PCK3 is the second clock signal line XCK of the second gate drive unit 122. Specifically, the second clock signal line PCK2 is connected to the second electrode of the third output transistor T6 in the second gate drive unit 122, and the third clock signal line PCK3 is connected to the gate of the seventh control transistor T21 in the second gate drive unit 122.

[0076] In this embodiment, the third clock signal line PCK3 and the fourth clock signal line PCK4 are connected to the third gate drive unit 123. The third clock signal line PCK3 is the first clock signal line CK of the third gate drive unit 123, and the fourth clock signal line PCK4 is the second clock signal line XCK of the third gate drive unit 123. That is, the third clock signal line PCK3 is connected to the second electrode of the third output transistor T6 in the third gate drive unit 123, and the fourth clock signal line PCK4 is connected to the gate of the seventh control transistor T21 in the third gate drive unit 123.

[0077] In this embodiment, the fourth clock signal line PCK4 and the first clock signal line PCK1 are connected to the fourth gate drive unit 124. The fourth clock signal line PCK4 is the first clock signal line CK of the fourth gate drive unit 124, and the first clock signal line PCK1 is the second clock signal line XCK of the fourth gate drive unit 124. That is, the fourth clock signal line PCK4 is connected to the second electrode of the third output transistor T6 in the fourth gate drive unit 124, and the first clock signal line PCK1 is connected to the gate of the seventh control transistor T21 in the fourth gate drive unit 124.

[0078] As shown in Figures 8 to 15, the first source-drain layer 215 includes a third connection line L3 connected to the second electrode T6S of the third output transistor T6, and the third connection line L3 is provided along the second direction. In this embodiment, since the third output transistor T6 of the first gate drive unit 121, the second gate drive unit 122, the third gate drive unit 123, and the fourth gate drive unit 124 are connected to different clock signal lines, in the overlapping units, the lengths of the third connection lines L3 in each gate drive unit 120 differ from each other in the second direction, i.e., there is a difference in the lengths of the third connection lines L3 in the first gate drive unit 121, the second gate drive unit 122, the third gate drive unit 123, and the fourth gate drive unit 124. For example, the length of the third connection lines L3 in the first gate drive unit 121, the second gate drive unit 122, the third gate drive unit 123, and the fourth gate drive unit 124 gradually increases.

[0079] In the embodiments of the present invention, the first source-drain layer 215 includes a second connection line L2 connected to the gate of the seventh control transistor T21, the second connection line L2 being provided along a second direction. In these embodiments, the seventh control transistor T21 of the first gate drive unit 121, the second gate drive unit 122, the third gate drive unit 123, and the fourth gate drive unit 124 are connected to different clock signal lines. Therefore, in the overlapping units, the lengths of the second connection lines L2 in each gate drive unit 120 differ from each other in the second direction, i.e., there are differences in the lengths of the second connection lines L2 in the first gate drive unit 121, the second gate drive unit 122, the third gate drive unit 123, and the fourth gate drive unit 124. For example, the length of the second connection line L2 in the fourth gate drive unit 124, the first gate drive unit 121, the second gate drive unit 122, and the third gate drive unit 123 gradually decreases.

[0080] Specifically, the first electrode T13D of the first control transistor T13 and the first electrode T12D of the second control transistor T12 are connected to the second node O, and the second electrode T12S of the second control transistor T12 is connected to the second high-potential signal line PVGH.

[0081] Specifically, as shown in Figure 4, the second electrode of the second output transistor T9 is connected to the first high-potential signal line NVGH, and the second electrode of the fourth control transistor T3 is connected to the second high-potential signal line PVGH.

[0082] In some embodiments, at least one active pattern among the first control transistor T13, the first output transistor T10, and the third control transistor T1 is provided corresponding to the shield layer 202. By providing at least one active pattern among the first control transistor, the first output transistor, and the third control transistor corresponding to the shield layer, the threshold voltage of at least one of the first control transistor, the first output transistor, and the third control transistor is made positively biased, thereby preventing leakage current from occurring when at least one of the first control transistor, the first output transistor, and the third control transistor is turned off, and consequently reducing the power consumption of the gate drive unit, reducing the power consumption of the display panel without affecting the output signal of the gate drive unit, and allowing the display panel to operate normally.

[0083] In some embodiments, as shown in Figures 8, 16 to 26, the display panel 1 is,

[0084] Circuit board 201 and,

[0085] A first active layer 205 is provided on one side of the substrate 201,

[0086] A first metal layer 207 provided on the side of the first active layer 205 away from the substrate 201,

[0087] A second metal layer 209 is provided on the side of the first metal layer 207 away from the first active layer 205,

[0088] A second active layer 211 is provided on the side of the second metal layer 209 away from the first metal layer 207,

[0089] The second active layer 211 includes a third metal layer 213 provided on the side away from the second metal layer 209,

[0090] Here, the shield layer 202 is provided between the substrate 201 and the first active layer 205.

[0091] In some embodiments, the orthographic projection on the substrate 201 of the active patterns T13A of the first control transistor T13, T10A of the first output transistor T10, and T1A of the third control transistor T1, which are provided in correspondence with the shield layer 202, does not overlap with the orthographic projection on the substrate 201 of the second metal layer 209. By ensuring that the orthographic projection on the substrate of the active patterns provided in correspondence with the shield layer does not overlap with the orthographic projection on the substrate of the second metal layer, the potential of the shield layer can be adjusted with respect to the performance of the transistors. As a result, the transistors become positively biased, reducing or eliminating leakage current and reducing the power consumption of the display panel.

[0092] In some embodiments, the second active layer 211 includes an active pattern T13A for the first control transistor T13, an active pattern T10A for the first output transistor T10, and an active pattern T1A for the third control transistor T1.

[0093] In some embodiments, the third metal layer 213 includes the gate T13G of the first control transistor T13, the gate T10G of the first output transistor T10, and the gate T1G of the third control transistor T1.

[0094] In some embodiments, the orthographic projection of the second metal layer 209 on the substrate 201 does not overlap with the orthographic projection of the active pattern T13A of the first control transistor T13 on the substrate 201, the shield layer 202 includes a first shield pattern B1, the orthographic projection of the first shield pattern B1 on the substrate 201 overlaps with the orthographic projection of the active pattern T13A of the first control transistor T13 on the substrate 201, and the potential of the first shield pattern B1 is smaller than the potential of the second electrode T13S of the first control transistor T13. The first control transistor is changed from the original dual-gate transistor to a top-gate transistor, the active pattern of the first control transistor is provided corresponding to the first shield pattern, and the potential of the first shield pattern is smaller than the potential of the second electrode of the first control transistor. As a result, the potential difference between the potential of the first shield pattern and the second electrode of the first control transistor becomes a negative voltage, causing the threshold voltage of the first control transistor to be more positively biased compared to the threshold voltage of the dual-gate transistor, thereby reducing or eliminating leakage current and lowering the power consumption of the display panel.

[0095] Specifically, when the first control transistor T13 is in the off state, the potential of the first shield pattern B1 may be made lower than the potential of the second electrode T13S of the first control transistor T13.

[0096] In some embodiments, as shown in Figures 16 to 26, the orthographic projection of the active pattern T13A of the first control transistor T13 on the substrate 201 lies within the orthographic projection of the first shield pattern B1 on the substrate 201, with a gap between the boundary of the active pattern T13A of the first control transistor T13 and the boundary of the first shield pattern B1. By having the orthographic projection of the active pattern of the first control transistor on the substrate located within the orthographic projection of the first shield pattern on the substrate, and by having a gap between the boundary of the active pattern of the first control transistor and the boundary of the first shield pattern, each side of the first shield pattern protrudes from the side of the active pattern of the first control transistor, thereby shielding the active pattern of the first control transistor from light and preventing light from affecting the performance of the first control transistor.

[0097] Specifically, each side of the first shield pattern may protrude by 2.5 μm or more from the side corresponding to the first control transistor.

[0098] In some embodiments, as shown in Figures 16 to 26, the shield layer 202 further includes a second shield pattern B2, the orthographic projection of the second metal layer 209 on the substrate 201 does not overlap with the orthographic projection of the active pattern T1A of the third control transistor T1 on the substrate 201, the orthographic projection of the third control transistor T1 on the substrate 201 overlaps with the orthographic projection of the second shield pattern B2 on the substrate 201, and the potential of the second shield pattern B2 is smaller than the potential of the second electrode T1S of the third control transistor T1. The third control transistor is changed from the original dual-gate transistor to a top-gate transistor, and the active pattern of the third control transistor is provided corresponding to the second shield pattern. Because the potential of the second shield pattern is smaller than the potential of the second electrode of the third control transistor, the potential difference between the potential of the second shield pattern and the second electrode of the third control transistor becomes a negative voltage. This causes the threshold voltage of the second control transistor to be more positively biased compared to the threshold voltage of the dual-gate transistor, thereby reducing or eliminating leakage current and lowering the power consumption of the display panel.

[0099] Specifically, when the third control transistor T1 is in the off state, the potential of the second shield pattern B2 may be made lower than the potential of the second electrode T1S of the third control transistor T1.

[0100] In some embodiments, as shown in Figures 16 to 26, the orthographic projection of the active pattern T1A of the third control transistor T1 on the substrate 201 lies within the orthographic projection of the second shield pattern B2 on the substrate 201, and there is a gap between the boundary of the active pattern T1A of the third control transistor T1 and the boundary of the second shield pattern B2. By having the orthographic projection of the active pattern of the third control transistor on the substrate lie within the orthographic projection of the second shield pattern on the substrate, and by having a gap between the boundary of the active pattern of the third control transistor and the boundary of the second shield pattern, each side of the second shield pattern protrudes from the side of the active pattern of the third control transistor, thereby shielding the active pattern of the third control transistor from light and preventing light from affecting the performance of the third control transistor.

[0101] Specifically, each side of the second shield pattern may protrude by 2.5 μm or more from the side corresponding to the third control transistor.

[0102] In some embodiments, as shown in Figures 16 to 26, the shield layer 202 further includes a third shield pattern B3, the orthographic projection of the second metal layer 209 on the substrate 201 does not overlap with the orthographic projection of the active pattern T10A of the first output transistor T10 on the substrate 201, the orthographic projection of the first output transistor T10 on the substrate 201 overlaps with the orthographic projection of the third shield pattern B3 on the substrate 201, and the potential of the third shield pattern B3 is smaller than the potential of the second electrode T10S of the first output transistor T10. The first output transistor is changed from the original dual-gate transistor to a top-gate transistor, the active pattern of the first output transistor is provided corresponding to the third shield pattern, and the potential of the third shield pattern is smaller than the potential of the second electrode of the first output transistor. As a result, the potential difference between the potential of the third shield pattern and the second electrode of the first output transistor becomes a negative voltage, causing the threshold voltage of the first output transistor to be more positively biased compared to the threshold voltage of the dual-gate transistor, thereby reducing or eliminating leakage current and lowering the power consumption of the display panel.

[0103] Specifically, when the first output transistor T10 is in the off state, the potential of the third shield pattern B3 may be made lower than the potential of the second electrode T10S of the first output transistor T10.

[0104] In some embodiments, as shown in Figures 16 to 26, the orthographic projection of the active pattern T10A of the first output transistor T10 on the substrate 201 lies within the orthographic projection of the third shield pattern B3 on the substrate 201, with a gap between the boundary of the active pattern T10A of the first output transistor T10 and the boundary of the third shield pattern B3. By having the orthographic projection of the active pattern of the first output transistor on the substrate located within the orthographic projection of the third shield pattern on the substrate, and by having a gap between the boundary of the active pattern of the first output transistor and the boundary of the third shield pattern, each side of the third shield pattern protrudes from the side of the active pattern of the first output transistor, thereby shielding the active pattern of the first output transistor from light and preventing light from affecting the performance of the first output transistor.

[0105] Specifically, each side of the third shield pattern may protrude by 2.5 μm or more from the side corresponding to the first output transistor.

[0106] In some embodiments, the orthographic projection of the shield layer 202 on the substrate 201 does not overlap with the orthographic projection of the first active layer 205 on the substrate 201. By ensuring that the orthographic projection of the shield layer 202 on the substrate does not overlap with the orthographic projection of the first active layer 205 on the substrate 201, it is possible to avoid the potential of the shield layer affecting the first active layer and thus avoid the shield layer affecting the performance of the silicon semiconductor transistor.

[0107] Specifically, in this embodiment, a low potential is provided in the shield layer. If the shield layer is provided in correspondence with the first active layer, the potential of the shield layer will affect the channel in the first active layer, and consequently affect the performance of the silicon semiconductor transistor. Therefore, the embodiment of this application avoids affecting the performance of the silicon semiconductor transistor by ensuring that the shield layer does not overlap with the orthographic projection of the first active layer on the substrate. Specifically, for example, if the second control transistor T12 is a silicon semiconductor transistor, the active pattern of the second control transistor T12 may be made so as not to overlap with the projection of the shield layer on the substrate.

[0108] In some embodiments, as shown in Figure 4, the first inverter unit 10 includes a first low-potential signal line NVGL and a second high-potential signal line PVGH, the second electrode T13S of the first control transistor T13 is connected to the first low-potential signal line NVGL, the second electrode T12S of the second control transistor T12 is connected to the second high-potential signal line PVGH, the initial signal line STV is connected to the previous stage transmission node P(n-1), and the potential of the first low-potential signal line NVGL is greater than the potential of the second low-potential signal line PVGL. When the second electrode of the first control transistor is connected to the first low-potential signal line, and the initial signal line is connected to the internal node one stage prior, and the potential of the first low-potential signal line is greater than the potential of the second low-potential signal line, and the first control transistor is in the off state, the potential difference between the gate and the second electrode of the first control transistor is negative, and even if the threshold voltage of the first control transistor is negatively biased, leakage current can be reduced or eliminated, reducing the power consumption of the display panel and improving the yield of the display panel.

[0109] Specifically, in the conventional case where the initial signal line STV is connected to the third signal output terminal Nout(n-1), and the third signal output terminal is the first signal output terminal of the drive unit one stage prior, when the third signal output terminal Nout(n-1) outputs a low potential, STV outputs the potential of the first low-potential signal line NVGL, and the second electrode of the first control transistor T13 is connected to the second low-potential signal line PVGL, so that the potential difference between the gate and the second electrode of the first control transistor T13 becomes 0. In contrast, the embodiment of the present invention is, When the signal line STV is connected to the internal node P(n-1) of the gate drive unit one stage prior, and a low potential is input to the initial signal line STV, the input is the potential of the second low-potential signal line PVGL, and the second electrode of the first control transistor T13 is connected to the first low-potential signal line NVGL, the potential difference between the gate and the second electrode of the first control transistor T13 becomes less than 0, thereby improving the issue of leakage current due to the negative bias of the threshold voltage of the first control transistor T13.

[0110] Specifically, taking the case where the voltage of the first low-potential signal line NVGL is -8 volts and the voltage of the second low-potential signal line PVGL is -9 volts, the potential difference between the gate and the second electrode of the first control transistor T13 is -1 volt. However, in the manufacturing process of the display panel, the degree of negative bias with respect to the threshold voltage of the first control transistor T13 is usually less than -1 volt, thereby avoiding the generation of leakage current in the first control transistor and reducing the power consumption of the display panel. Furthermore, simulation verification shows that when the first control transistor T13 is in the off state, the current between the gate and the second electrode of the first control transistor T13 can be reduced from 60 nA (nanoamperes) to 52 fA (femtoamperes), thereby reducing leakage current and power consumption.

[0111] In some embodiments, as shown in Figure 7, the first inverter unit 10 includes the second low-potential signal line PVGL and the second high-potential signal line PVGH, the second electrode T13S of the first control transistor T13 is connected to the second low-potential signal line PVGL, the second electrode T12S of the second control transistor T12 is connected to the second high-potential signal line PVGH, and the initial signal line STV is connected to the first output signal terminal of the gate drive unit one stage prior.

[0112] In some embodiments, as shown in Figures 3 to 5, the display unit 11 includes a pixel driving circuit 110, the pixel driving circuit 110 includes an oxide semiconductor transistor (for example, the compensation transistor T33 is an oxide semiconductor transistor), and the channel length of at least one of the first control transistor T13, the first output transistor T10, and the third control transistor T1 is greater than the channel length of the oxide semiconductor transistor. By having a channel length of at least one of the first control transistor, the first output transistor, and the third control transistor greater than the channel length of the oxide semiconductor transistor of the display unit, the threshold voltage of at least one of the first control transistor, the first output transistor, and the third control transistor becomes positively biased, reducing the difference between the potential difference between the gate and the second electrode of at least one of the first control transistor, the first output transistor, and the third control transistor and its threshold voltage, thereby avoiding leakage current in at least one of the first control transistor, the first output transistor, and the third control transistor and reducing the power consumption of the display panel.

[0113] Specifically, as shown in Figures 3 to 5, the display unit 11 includes a pixel driving circuit 110, the compensation transistor T33 is an oxide semiconductor transistor, and the channel length of the first control transistor T13 is greater than the channel length of the compensation transistor T33. Because the channel length of the first control transistor is greater than that of the compensation transistor, the threshold voltage of the first control transistor becomes positively biased, reducing the difference between the potential difference between the gate and the second electrode of the first control transistor and the threshold voltage of the first control transistor, thereby avoiding leakage current of the first control transistor and reducing the power consumption of the display panel.

[0114] Specifically, taking the gate drive unit shown in Figure 7 as an example, the current when the first control transistor T13 is in the off state and the threshold voltage of the first control transistor T13 is offset is tested to obtain the graph shown in Figure 6. In Figure 6, the horizontal axis represents the amount of voltage offset related to the threshold voltage of the first control transistor T13, in units of V (volts), and the vertical axis represents the current between the gate of the first control transistor T13 and the second electrode, in units of nA (nanoamperes). As can be seen from Figure 6, when the threshold voltage of the first control transistor T13 is negatively biased, the leakage current of the first control transistor T13 is relatively serious, and as a result, the power consumption of the display panel becomes relatively high. For example, if the voltage offset amount related to the threshold voltage of the first control transistor T13 is -0.5V, the output power loss of the first inverter unit will be approximately 12mW (milliwatts). On the other hand, if the voltage offset amount related to the threshold voltage of the first control transistor T13 is 0.5V, the output power gain of the first inverter unit will be approximately 4mW (milliwatts), thereby reducing the power consumption of the display panel.

[0115] Specifically, in the embodiment of the present invention, by increasing the channel length of the first control transistor T13, the threshold voltage of the first control transistor T13 can be positively biased, thereby preventing leakage current from occurring in the first control transistor.

[0116] Specifically, as shown in Figure 5, the pixel driving circuit 110 includes a driving transistor T31, a pixel switching transistor T32, a compensation transistor T33, a first initialization transistor T34, a first light-emitting transistor T35, a second light-emitting transistor T36, a second initialization transistor T37, and a third initialization transistor T38. The gate of the pixel switching transistor T32 is connected to the third scan signal line Pscan1, the first electrode of the pixel switching transistor T32 is connected to the data signal line Data, the second electrode of the pixel switching transistor T32 is connected to the first electrode of the driving transistor T31, the gate of the compensation transistor T33 is connected to the first scan signal line Nscan1, the first electrode of the compensation transistor T33 is connected to the second electrode of the first initialization transistor T34, the second electrode of the compensation transistor T33 is connected to the second electrode of the driving transistor T31, the gate of the first initialization transistor T34 is connected to the second scan signal line Nscan2, and the first electrode of the first initialization transistor T34 is connected to the second electrode of the first initialization transistor T34. The first initialization line Vi1 is connected, the gate of the first light-emitting transistor T35 is connected to the light emission control line EM, the first electrode of the first light-emitting transistor T35 is connected to the power supply high-potential signal line VDD, the second electrode of the first light-emitting transistor T35 is connected to the first electrode of the drive transistor T31, the gate of the second light-emitting transistor T36 is connected to the light emission control line EM, the first electrode of the second light-emitting transistor T36 is connected to the second electrode of the drive transistor T31, and the second electrode of the second light-emitting transistor T36 is connected to the light-emitting element LED. The gate of the second initialization transistor T37 is connected to the fourth scan signal line Pscan2, the first electrode of the second initialization transistor T37 is connected to the second initialization line Vi2, the second electrode of the second initialization transistor T37 is connected to the light-emitting element LED, the gate of the third initialization transistor T38 is connected to the fourth scan signal line Pscan2, the first electrode of the third initialization transistor T38 is connected to the third initialization line Vi3, and the second electrode of the third initialization transistor T38 is connected to the first electrode of the drive transistor T31.

[0117] Specifically, as shown in Figure 5, the light-emitting element LED is connected to the power supply low-potential signal line VSS, and the pixel driving circuit includes a storage capacitor Cst and a boost capacitor Cboost. One end of the storage capacitor Cst is connected to the power supply high-potential signal line VDD, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor T31. One end of the boost capacitor Cboost is connected to the gate of the pixel switching transistor T32, and the other end of the boost capacitor Cboost is connected to the gate of the driving transistor T31.

[0118] Specifically, the signal of the first scan signal line Nscan1 may be a signal output from the first signal output terminal Nout(n) of the gate drive unit of the current stage, the signal of the second scan signal line Nscan2 may be a signal output from the first signal output terminal of the gate drive unit of the previous five stages, the signal of the third scan signal line Pscan1 may be a signal output from the second signal output terminal Pout(n) of the gate drive unit of the current stage, and the signal of the fourth scan signal line Pscan2 may be a signal output from the second signal output terminal of the gate drive unit of the stage before the current stage.

[0119] Specifically, the drive transistor T31, pixel switching transistor T32, first light-emitting transistor T35, second light-emitting transistor T36, second initialization transistor T37, and third initialization transistor T38 are silicon semiconductor transistors, while the compensation transistor T33 and first initialization transistor T34 are oxide semiconductor transistors.

[0120] Specifically, the drive transistor T31, pixel switching transistor T32, first light-emitting transistor T35, second light-emitting transistor T36, second initialization transistor T37, and third initialization transistor T38 are P-type transistors, while the compensation transistor T33 and first initialization transistor T34 are N-type transistors.

[0121] Specifically, the third control transistor T1 is an oxide semiconductor transistor, and the channel length of the third control transistor T1 is greater than the channel length of the compensation transistor T33. Because the channel length of the third control transistor is greater than that of the compensation transistor, the threshold voltage of the third control transistor becomes positively biased, reducing the difference between the potential difference between the gate and the second electrode of the third control transistor and the threshold voltage of the third control transistor, thereby avoiding leakage current of the third control transistor and reducing the power consumption of the display panel.

[0122] Specifically, the fourth control transistor T3 is a silicon semiconductor transistor, it is a P-type transistor, and the third control transistor T1 is an N-type transistor.

[0123] Specifically, the first output transistor T10 is an oxide semiconductor transistor, and the channel length of the first output transistor T10 is greater than the channel length of the compensation transistor T33. Because the channel length of the first output transistor is greater than that of the compensation transistor, the threshold voltage of the first output transistor is positively biased, reducing the difference between the potential difference between the gate and the second electrode of the first output transistor and the threshold voltage of the first output transistor, thereby avoiding leakage current of the first output transistor and reducing the power consumption of the display panel.

[0124] Specifically, the second output transistor T9 is a silicon semiconductor transistor, it is a P-type transistor, and the first output transistor T10 is an N-type transistor.

[0125] Specifically, when changing the channel lengths of the first control transistor, the third control transistor, and the first output transistor to make the threshold voltage of each transistor positively biased, it is not necessary to change the circuit design within the gate drive unit or the film layer design. The gate drive unit design shown in Figure 7 may be used, or the gate drive unit design shown in Figure 4 may be used, or the film layer design shown in Figure 8 may be used, or the film layer design shown in Figure 24 may be used.

[0126] In some embodiments, as shown in Figure 8, the display panel 1 includes a substrate 201, a first active layer 205, a first metal layer 207, a second metal layer 209, a second active layer 211, and a third metal layer 213, wherein the first active layer 205 is provided on one side of the substrate 201, the first metal layer 207 is provided on the side of the first active layer 205 away from the substrate 201, the second metal layer 209 is provided on the side of the first metal layer 207 away from the first active layer 205, the second active layer 211 is provided on the side of the second metal layer 209 away from the first metal layer 207, and the third metal layer 213 is provided on the side of the second active layer 211 away from the second metal layer 209.

[0127] In some embodiments, as shown in Figures 8 to 15, the gate drive unit 120 further includes an output control unit 60, a first control unit 801, and a second control unit 802, wherein the output control unit 60 includes a first switching transistor T4, a second switching transistor T5, and a third switching transistor T14, the gate T4G of the first switching transistor T4 being connected to a second clock signal line XCK, and the first electrode T4D of the first switching transistor T4 being connected to the first electrode T5D of the second switching transistor T5, and The second electrode T4S of the first switching transistor T4 is connected to the first node K, the gate T5G of the second switching transistor T5 and the gate T14G of the third switching transistor T14 are connected to the first electrode T1D of the third control transistor T1, the second electrode T5S of the second switching transistor T5 is connected to the second high-potential signal line PVGH, the first electrode T14D of the third switching transistor T14 is connected to the first node K, and the second electrode T14S of the third switching transistor T14 is connected to the first low-potential signal line NVGL.

[0128] The first control unit 801 includes a fifth control transistor T17 and a sixth control transistor T18, wherein the gate T17G of the fifth control transistor T17 is connected to a second clock signal line XCK, the first electrode 17D of the fifth control transistor T17 is connected to the first electrode T18D of the sixth control transistor T18, the second electrode T17S of the fifth control transistor T17 is electrically connected to the first node K, the gate T18G of the sixth control transistor T18 is connected to the gate T14G of the third switching transistor T14, and the second electrode T18S of the sixth control transistor T18 is connected to a second high-potential signal line PVGH.

[0129] The second control unit 802 includes a seventh control transistor T21 and an eighth control transistor T22. The gate T21G of the seventh control transistor T21 is connected to the second clock signal line XCK, the first electrode T21D of the seventh control transistor T21 is connected to the first electrode T22D of the eighth control transistor T22, the second electrode T21S of the seventh control transistor T21 is electrically connected to the first node K, the gate T22G of the eighth control transistor T22 is connected to the gate T14G of the third switching transistor T14, and the second electrode T22S of the eighth control transistor T22 is connected to the second high-potential signal line PVGH. By providing the output control unit, the first control unit, and the second control unit, control can be performed on the signals output from the first signal output terminal and the second signal output terminal.

[0130] Specifically, as shown in Figures 4 to 26, the first switching transistor T4 is an oxide semiconductor transistor, the second switching transistor T5 is a silicon semiconductor transistor, and the third switching transistor T14 is an oxide semiconductor transistor. The fifth control transistor T17 is an oxide semiconductor transistor, and the sixth control transistor T18 is a silicon semiconductor transistor. The seventh control transistor T21 is an oxide semiconductor transistor, and the eighth control transistor T22 is a silicon semiconductor transistor.

[0131] In some embodiments, as shown in Figures 4 to 26, when the first switching transistor T4 is in the off state, the voltage difference between the gate T4G of the first switching transistor T4 and the second electrode T4S of the first switching transistor T4 is smaller than the threshold voltage of the first switching transistor T4.

[0132] And / or, when the third switching transistor T14 is in the off state, the voltage difference between the gate T14G of the third switching transistor T14 and the second electrode T14S of the third switching transistor T14 is smaller than the threshold voltage of the third switching transistor T14.

[0133] And / or, when the fifth control transistor T17 is in the off state, the voltage difference between the gate T17G of the fifth control transistor T17 and the second electrode T17S of the fifth control transistor T17 is smaller than the threshold voltage of the fifth control transistor T17.

[0134] And / or, when the seventh control transistor T21 is in the off state, the voltage difference between the gate T21G of the seventh control transistor T21 and the second electrode T21S of the seventh control transistor T21 is smaller than the threshold voltage of the seventh control transistor T21.

[0135] Specifically, when the first switching transistor is in the off state, the voltage difference between the gate of the first switching transistor and the second electrode of the first switching transistor is smaller than the threshold voltage of the first switching transistor. This prevents leakage current from occurring in the first switching transistor when it is off, thereby reducing the power consumption of the gate drive unit, and without affecting the output signal of the gate drive unit, it reduces the power consumption of the display panel and allows the display panel to operate normally.

[0136] Specifically, if the gate drive unit includes a first switching transistor, a third switching transistor, a fifth control transistor, and a seventh control transistor, the channel lengths of the first switching transistor, the third switching transistor, the fifth control transistor, and the seventh control transistor are equal, and the channel length of the first control transistor is greater than the channel length of the first switching transistor, thereby causing the threshold voltage of the first control transistor to be positively biased. And / or, the channel length of the third control transistor is greater than the channel length of the first switching transistor, thereby causing the threshold voltage of the third control transistor to be positively biased. And / or, the channel length of the first output transistor is greater than the channel length of the first switching transistor, thereby causing the threshold voltage of the first output transistor to be positively biased.

[0137] Specifically, the channel length of the first switching transistor may be equal to the channel length of the compensation transistor, or it may be greater than the channel length of the compensation transistor.

[0138] Specifically, when the third switching transistor is in the off state, the voltage difference between the gate of the third switching transistor and the second electrode of the third switching transistor is smaller than the threshold voltage of the third switching transistor. This prevents leakage current from occurring in the third switching transistor when it is off, thereby reducing the power consumption of the gate drive unit, and without affecting the output signal of the gate drive unit, it reduces the power consumption of the display panel and allows the display panel to operate normally.

[0139] Specifically, when the fifth control transistor is in the off state, the voltage difference between the gate of the fifth control transistor and the second electrode of the fifth control transistor is smaller than the threshold voltage of the fifth control transistor. This prevents leakage current from occurring in the fifth control transistor when it is off, thereby reducing the power consumption of the gate drive unit, and without affecting the output signal of the gate drive unit, it reduces the power consumption of the display panel and allows the display panel to operate normally.

[0140] Specifically, when the seventh control transistor is in the off state, the voltage difference between the gate of the seventh control transistor and the second electrode of the seventh control transistor is smaller than the threshold voltage of the seventh control transistor. This prevents leakage current from occurring in the seventh control transistor when it is off, thereby reducing the power consumption of the gate drive unit, and without affecting the output signal of the gate drive unit, it reduces the power consumption of the display panel and allows the display panel to operate normally.

[0141] Specifically, the second switching transistor T5 is a P-type transistor, while the first switching transistor T4 and the third switching transistor T14 are N-type transistors.

[0142] Specifically, the sixth control transistor T18 is a P-type transistor, and the fifth control transistor T17 is an N-type transistor.

[0143] Specifically, the 8th control transistor T22 is a P-type transistor, and the 7th control transistor T21 is an N-type transistor.

[0144] In some embodiments, the display panel is

[0145] Circuit board 201 and,

[0146] A first active layer 205 is provided on one side of the substrate 201,

[0147] A first metal layer 207 provided on the side of the first active layer 205 away from the substrate 201,

[0148] A second metal layer 209 is provided on the side of the first metal layer 207 away from the first active layer 205,

[0149] A second active layer 211 is provided on the side of the second metal layer 209 away from the first metal layer 207, and includes the active pattern T4A of the first switching transistor T4, the active pattern T14A of the third switching transistor T14, the active pattern T17A of the fifth control transistor T17, and the active pattern T21A of the seventh control transistor T21.

[0150] The second active layer 211 includes a third metal layer 213 provided on the side away from the second metal layer 209, which includes the gate T4H of the first switching transistor T4, the gate T14G of the third switching transistor T14, the gate T17G of the fifth control transistor T17, and the gate T21G of the seventh control transistor T21.

[0151] Here, the shield layer 202 is provided between the substrate 201 and the first active layer 205, and the shield layer 202 includes a fourth shield pattern B4. The orthographic projection of the second metal layer 209 on the substrate 201 does not overlap with the orthographic projection of the active pattern T4A of the first switching transistor T4 on the substrate 201, and the orthographic projection of the active pattern T4A of the first switching transistor T4 on the substrate 201 overlaps with the orthographic projection of the fourth shield pattern B4 on the substrate 201. When the first switching transistor T4 is in the off state, the potential of the fourth shield pattern B4 is smaller than the potential of the second electrode T4S of the first switching transistor T4.

[0152] and / or, the shield layer 202 includes a fifth shield pattern B5, wherein the orthographic projection of the second metal layer 209 on the substrate 201 does not overlap with the orthographic projection of the active pattern T14A of the third switching transistor T14 on the substrate 201, the orthographic projection of the active pattern T14A of the third switching transistor T14 on the substrate 201 overlaps with the orthographic projection of the fifth shield pattern B5 on the substrate 201, and when the third switching transistor T14 is in the off state, the potential of the fifth shield pattern B5 is smaller than the potential of the second electrode T14S of the third switching transistor T14.

[0153] and / or, the shield layer 202 includes a sixth shield pattern B6, wherein the orthographic projection of the second metal layer 209 on the substrate 201 does not overlap with the orthographic projection of the active pattern T17A of the fifth control transistor T17 on the substrate 201, and the orthographic projection of the active pattern T17A of the fifth control transistor T17 on the substrate 201 overlaps with the orthographic projection of the sixth shield pattern B6 on the substrate 201, and when the fifth control transistor T17 is in the off state, the potential of the sixth shield pattern B6 is smaller than the potential of the second electrode T17S of the fifth control transistor T17.

[0154] and / or, the shield layer 202 includes a seventh shield pattern B7, wherein the orthographic projection of the second metal layer 209 on the substrate 201 does not overlap with the orthographic projection of the active pattern T21A of the seventh control transistor T21 on the substrate 201, and the orthographic projection of the active pattern T21A of the seventh control transistor T21 on the substrate 201 overlaps with the orthographic projection of the seventh shield pattern B7 on the substrate 201, and when the seventh control transistor T21 is in the off state, the potential of the seventh shield pattern B7 is smaller than the potential of the second electrode T21S of the seventh control transistor T21.

[0155] Specifically, the first switching transistor is changed from the original dual-gate transistor to a top-gate transistor, the active pattern of the first switching transistor is provided corresponding to the fourth shield pattern, and the potential of the fourth shield pattern is smaller than the potential of the second electrode of the first switching transistor. As a result, the potential difference between the potential of the fourth shield pattern and the second electrode of the first switching transistor becomes a negative voltage, causing the threshold voltage of the first switching transistor to be more positively biased than the threshold voltage of the dual-gate transistor, thereby reducing or eliminating leakage current and lowering the power consumption of the display panel.

[0156] Specifically, the third switching transistor is changed from the original dual-gate transistor to a top-gate transistor, the active pattern of the third switching transistor is provided corresponding to the fifth shield pattern, and the potential of the fifth shield pattern is smaller than the potential of the second electrode of the third switching transistor. As a result, the potential difference between the potential of the fifth shield pattern and the second electrode of the third switching transistor becomes a negative voltage, causing the threshold voltage of the third switching transistor to be more positively biased compared to the threshold voltage of the dual-gate transistor, thereby reducing or eliminating leakage current and lowering the power consumption of the display panel.

[0157] Specifically, the fifth control transistor is changed from the original dual-gate transistor to a top-gate transistor, the active pattern of the fifth control transistor is provided corresponding to the sixth shield pattern, and the potential of the sixth shield pattern is smaller than the potential of the second electrode of the fifth control transistor. As a result, the potential difference between the potential of the sixth shield pattern and the second electrode of the fifth control transistor becomes a negative voltage, causing the threshold voltage of the fifth control transistor to be more positively biased compared to the threshold voltage of the dual-gate transistor, thereby reducing or eliminating leakage current and lowering the power consumption of the display panel.

[0158] Specifically, the seventh control transistor is changed from the original dual-gate transistor to a top-gate transistor, the active pattern of the seventh control transistor is provided corresponding to the seventh shield pattern, and the potential of the seventh shield pattern is smaller than the potential of the second electrode of the seventh control transistor. As a result, the potential difference between the potential of the seventh shield pattern and the second electrode of the seventh control transistor becomes a negative voltage, causing the threshold voltage of the seventh control transistor to be more positively biased compared to the threshold voltage of the dual-gate transistor, thereby reducing or eliminating leakage current and lowering the power consumption of the display panel.

[0159] In some embodiments, the orthographic projection of the active pattern T4A of the first switching transistor T4 on the substrate 201 lies within the orthographic projection of the fourth shield pattern B4 on the substrate 201, and there is a gap between the boundary of the active pattern T4A of the first switching transistor T4 and the boundary of the fourth shield pattern B4. By having the orthographic projection of the active pattern of the first switching transistor on the substrate lie within the orthographic projection of the fourth shield pattern on the substrate, and having a gap between the boundary of the active pattern of the first switching transistor and the boundary of the fourth shield pattern, each side of the fourth shield pattern protrudes from the side of the active pattern of the first switching transistor, thereby shielding the active pattern of the first switching transistor from light and preventing light from affecting the performance of the first switching transistor.

[0160] Specifically, each side of the fourth shield pattern may protrude by 2.5 μm or more from the side corresponding to the first switching transistor.

[0161] In some embodiments, the orthographic projection of the active pattern T14A of the third switching transistor T14 on the substrate 201 lies within the orthographic projection of the fifth shield pattern B5 on the substrate 201, with a gap between the boundary of the active pattern T14A of the third switching transistor T14 and the boundary of the fifth shield pattern B5. By having the orthographic projection of the active pattern of the third switching transistor on the substrate lie within the orthographic projection of the fifth shield pattern on the substrate, and with a gap between the boundary of the active pattern of the third switching transistor and the boundary of the fifth shield pattern, each side of the fifth shield pattern protrudes from the side of the active pattern of the third switching transistor, thereby shielding the active pattern of the third switching transistor from light and preventing light from affecting the performance of the third switching transistor.

[0162] Specifically, each side of the fifth shield pattern may protrude by 2.5 μm or more from the side corresponding to the third switching transistor.

[0163] In some embodiments, the orthographic projection of the active pattern T17A of the fifth control transistor T17 on the substrate 201 lies within the orthographic projection of the sixth shield pattern B6 on the substrate 201, with a gap between the boundary of the active pattern T17A of the fifth control transistor T17 and the boundary of the sixth shield pattern B6. By having the orthographic projection of the active pattern of the fifth control transistor on the substrate lie within the orthographic projection of the sixth shield pattern on the substrate, and with a gap between the boundary of the active pattern of the fifth control transistor and the boundary of the sixth shield pattern, each side of the sixth shield pattern protrudes from the side of the active pattern of the fifth control transistor, thereby shielding the active pattern of the fifth control transistor from light and preventing light from affecting the performance of the fifth control transistor.

[0164] Specifically, each side of the sixth shield pattern may protrude by 2.5 μm or more from the side corresponding to the fifth control transistor.

[0165] Specifically, when each oxide semiconductor transistor uses a top-gate design and is provided in accordance with the shield pattern, the potential of the shield pattern may be 3 volts lower than the potential of the second electrode of each oxide semiconductor transistor. Compared to a dual-gate metal thin-film transistor, this results in a positive bias threshold voltage of approximately 0.4 volts for the oxide semiconductor transistor, and an improvement of 0.4 volts in the PBTS (Positive Bias Temperature Stress) curve.

[0166] Specifically, the potential of the shield pattern may be -12 volts.

[0167] In some embodiments, the orthographic projection of the active pattern T21A of the seventh control transistor T21 on the substrate 201 lies within the orthographic projection of the seventh shield pattern B7 on the substrate 201, with a gap between the boundary of the active pattern T21A of the seventh control transistor T21 and the boundary of the seventh shield pattern B7. By having the orthographic projection of the active pattern of the seventh control transistor on the substrate lie within the orthographic projection of the seventh shield pattern on the substrate, and with a gap between the boundary of the active pattern of the seventh control transistor and the boundary of the seventh shield pattern, each side of the seventh shield pattern protrudes from the side of the active pattern of the seventh control transistor, thereby shielding the active pattern of the seventh control transistor from light and preventing light from affecting the performance of the seventh control transistor.

[0168] Specifically, each side of the seventh shield pattern may protrude by 2.5 μm or more from the side corresponding to the seventh control transistor.

[0169] As shown in Figure 25, it can be seen that the shield layer 202 includes a shield pattern corresponding to each gate drive unit 120, and each shield pattern is connected by connecting lines. In some embodiments, as shown in Figures 4 to 26, the display unit 11 includes a pixel drive circuit 110, the pixel drive circuit 110 includes oxide semiconductor transistors (for example, the compensation transistor T33 is an oxide semiconductor transistor), where the channel length of the first switching transistor T4 is greater than the channel length of the oxide semiconductor transistor, and / or the channel length of the third switching transistor T14 is greater than the channel length of the oxide semiconductor transistor, and / or the channel length of the fifth control transistor T17 is greater than the channel length of the oxide semiconductor transistor, and / or the channel length of the seventh control transistor T21 is greater than the channel length of the oxide semiconductor transistor. By having a channel length greater than the channel length of the oxide semiconductor transistor at least one of the first switching transistor, third switching transistor, fifth control transistor, and seventh control transistor, the threshold voltage of at least one of the first switching transistor, third switching transistor, fifth control transistor, and seventh control transistor is made positively biased. This reduces the difference between the potential difference between the gate and the second electrode of at least one of the first switching transistor, third switching transistor, fifth control transistor, and seventh control transistor and its threshold voltage, thereby avoiding leakage current in at least one of the first switching transistor, third switching transistor, fifth control transistor, and seventh control transistor and reducing the power consumption of the display panel.

[0170] Specifically, as shown in Figures 4 to 26, the display unit 11 includes a pixel driving circuit 110, the pixel driving circuit 110 includes a compensation transistor T33, and the compensation transistor T33 is an oxide semiconductor transistor.

[0171] Here, the channel length of the first switching transistor T4 is greater than the channel length of the compensation transistor T33. And / or, the channel length of the third switching transistor T14 is greater than the channel length of the compensation transistor T33. And / or, the channel length of the fifth control transistor T17 is greater than the channel length of the compensation transistor T33. And / or, the channel length of the seventh control transistor T21 is greater than the channel length of the compensation transistor T33.

[0172] Specifically, by making the channel length of the first switching transistor greater than the channel length of the compensation transistor, the threshold voltage of the first switching transistor is made positively biased. This reduces the difference between the potential difference between the gate and the second electrode of the first switching transistor and the threshold voltage of the first switching transistor, thereby avoiding leakage current of the first switching transistor and reducing the power consumption of the display panel.

[0173] Specifically, by making the channel length of the third switching transistor greater than the channel length of the compensation transistor, the threshold voltage of the third switching transistor is made positively biased. This reduces the difference between the potential difference between the gate and the second electrode of the third switching transistor and the threshold voltage of the third switching transistor, thereby avoiding leakage current in the third switching transistor and reducing the power consumption of the display panel.

[0174] Specifically, by making the channel length of the fifth control transistor greater than the channel length of the compensation transistor, the threshold voltage of the fifth control transistor is made positively biased. This reduces the difference between the potential difference between the gate and the second electrode of the fifth control transistor and the threshold voltage of the fifth control transistor, thereby avoiding leakage current in the fifth control transistor and reducing the power consumption of the display panel.

[0175] Specifically, by making the channel length of the seventh control transistor greater than the channel length of the compensation transistor, the threshold voltage of the seventh control transistor is made positively biased. This reduces the difference between the potential difference between the gate and the second electrode of the seventh control transistor and the threshold voltage of the seventh control transistor, thereby avoiding leakage current in the seventh control transistor and reducing the power consumption of the display panel.

[0176] In some embodiments, as shown in Figures 8 to 26, the display panel 1 is,

[0177] Circuit board 201 and,

[0178] A first active layer 205 is provided on one side of the substrate 201 and includes the active pattern T9A of the second output transistor T9,

[0179] A first metal layer 207 provided on the side of the first active layer 205 away from the substrate 201,

[0180] A second metal layer 209 is provided on the side of the first metal layer 207 away from the first active layer 205,

[0181] A second active layer 211 is provided on the side of the second metal layer 209 away from the first metal layer 207 and includes the active pattern T10A of the first output transistor T10,

[0182] A third metal layer 213 is provided on the side of the second active layer 211 away from the second metal layer 209,

[0183] The third metal layer 213 is provided on the side away from the second active layer 211 and includes a first source-drain layer 215 which includes the first electrode T10D of the first output transistor T10 and the first electrode T9D of the second output transistor T9.

[0184] Here, the active pattern T9A of the second output transistor T9 includes a plurality of first protrusions 311 and a first groove 312 located between the plurality of first protrusions 311, the active pattern T10A of the first output transistor T10 includes a plurality of second protrusions 313 and a second groove 314 located between the plurality of second protrusions 313, the first protrusions 311 are provided corresponding to the second groove 314 and the second protrusions 313 are provided corresponding to the first groove 312, the first electrode T10D of the first output transistor T10 is connected to the second protrusion 313 and the first electrode T9D of the second output transistor T9 is connected to the first protrusion 311. When a first via and a second via are formed by providing a second protrusion and a second groove in the active pattern of the first output transistor, and a first protrusion and a first groove in the active pattern of the second output transistor, with the first protrusion corresponding to the second groove and the second protrusion corresponding to the first groove, the first via and the second via can be provided alternately, and when the metal formed in the first source-drain layer is connected to the active pattern of the first output transistor and the active pattern of the second output transistor, respectively, via the first via and the second via, the vertical space occupied can be reduced, and the bezel of the display panel can be reduced.

[0185] Specifically, the shape of the active pattern of the first output transistor includes a comb shape, and the shape of the active pattern of the second output transistor includes a comb shape.

[0186] Specifically, as shown in Figure 3, the display panel 1 further includes a terminal section 13.

[0187] Specifically, as shown in Figure 4, the first inverter unit 10 further includes a ninth control transistor T2, the gate T2G of the ninth control transistor T2 is connected to the second clock signal line XCK, the first electrode T2D of the ninth control transistor T2 is connected to the first node K, and the second electrode T2S of the ninth control transistor T2 is connected to the second node O.

[0188] Specifically, the ninth control transistor is a silicon semiconductor transistor, and the ninth control transistor is a P-type transistor.

[0189] Specifically, as shown in Figure 4, the gate drive unit 120 further includes a second output unit 40, the second output unit 40 includes a third output transistor T6, a fourth output transistor T7, and a first capacitor C1, the gate T6G of the third output transistor T6 is connected to the third node Q, the first electrode T6D of the third output transistor T6 is connected to the first electrode T7D of the fourth output transistor T7, and the first electrode T6D of the third output transistor T6 is connected to the second signal output terminal Pout( The second electrode T6S of the third output transistor T6 is connected to the first clock signal line CK, the gate T7G of the fourth output transistor T7 is connected to the internal node P(n) of the current stage, the second electrode T7S of the fourth output transistor T7 is connected to the second high potential signal line PVGH, the first electrode plate C1a of the first capacitor C1 is connected to the gate of the third output transistor T6, and the second electrode plate C1b of the first capacitor C1 is connected to the second signal output terminal Pout(n).

[0190] Specifically, the third output transistor T6 and the fourth output transistor T7 are silicon semiconductor transistors, and both the third output transistor T6 and the fourth output transistor T7 are P-type transistors.

[0191] Specifically, as shown in Figure 4, the gate drive unit 120 further includes a frequency division module 50, which includes a first frequency division module 501 and a second frequency division module 502, the first frequency division module 501 includes a first frequency division transistor T16, a second frequency division transistor T11 and a second capacitor C2, the gate T16G of the first frequency division transistor T16 is connected to the internal node P(n) of the current stage, and the first frequency division The first electrode T16D of transistor T16 and the first electrode plate C2a of second capacitor C2 are connected to the gate T11G of second frequency division transistor T11, the second electrode T16S of first frequency division transistor T16 is connected to the first frequency division signal line NLF, the first electrode T11D of second frequency division transistor T11 and the second electrode plate C2b of second capacitor C2 are connected to the fourth node W, and the second electrode T11S of second frequency division transistor T11 is connected to the first node K. The second frequency division module 502 includes a third frequency division transistor T20, a fourth frequency division transistor T19, and a third capacitor C3. The gate T20G of the third frequency division transistor T20 is connected to the internal node P(n) of the current stage. The first electrode T20D of the third frequency division transistor T20 and the first electrode plate C3a of the third capacitor C3 are connected to the gate T19G of the fourth frequency division transistor T19. The second electrode T20S of the third frequency division transistor T20 is connected to the second frequency division signal line PLF. The first electrode T19D of the fourth frequency division transistor T19 and the second electrode plate C3b of the third capacitor C3 are connected to the fifth node M. The second electrode T19S of the fourth frequency division transistor T19 is connected to the first node K.

[0192] Specifically, the first frequency division transistor T16 and the second frequency division transistor T11 are silicon semiconductor transistors, and the first frequency division transistor T16 and the second frequency division transistor T11 are P-type transistors.

[0193] Specifically, the third frequency division transistor T20 and the fourth frequency division transistor T19 are silicon semiconductor transistors, and the third frequency division transistor T20 and the fourth frequency division transistor T19 are P-type transistors.

[0194] Specifically, as shown in Figure 4, the gate drive unit 120 further includes a reset module 70, which includes a reset transistor T15, the gate T15G of the reset transistor T15 is connected to the control signal line Control, the first electrode T15D of the reset transistor T15 is connected to the first node K, and the second electrode T15S of the reset transistor T15 is connected to the high-potential signal line PVGH.

[0195] Specifically, reset transistor T15 is a silicon semiconductor transistor, and reset transistor T15 is a P-type transistor.

[0196] Specifically, as shown in Figure 4, the gate drive unit 120 further includes a switching module 90, which includes a fourth switching transistor T8, the gate T8G of the fourth switching transistor T8 connected to a switching signal line SC, the switching signal line SC connected to an internal node P(n-2) two stages prior, the first electrode T8D of the fourth switching transistor T8 connected to a third node Q, and the second electrode T8S of the fourth switching transistor T8 connected to a fifth node M.

[0197] Specifically, the fourth switching transistor T8 is a silicon semiconductor transistor, and the fourth switching transistor T8 is a P-type transistor.

[0198] Specifically, when the oxide semiconductor transistor in the embodiment of the present application has a dual-gate structure, its circuit configuration can be seen in Figure 4, its film layer configuration in Figure 24, and its stacked structure in Figures 9 to 15. When the oxide semiconductor transistor in the embodiment of the present application has a top-gate structure, its circuit configuration can be seen in Figure 26, its film layer configuration in Figure 8, and its stacked structure in Figures 16 to 23.

[0199] Specifically, although each embodiment in the present invention includes a shielding layer, the embodiments of the present invention are not limited to this, and in some embodiments, a shielding layer may not be provided if it is not necessary to adjust the electrical properties of the oxide semiconductor transistor by the shielding layer. For example, if the first control transistor T13 has a dual-gate structure, a shielding layer may not be provided.

[0200] Specifically, when adjusting the channel length of an oxide semiconductor transistor or adjusting the threshold voltage of an oxide semiconductor transistor by a shielding pattern, the second electrode T13S of the first control transistor T13 may be connected to PVGL, as shown in Figure 7. Accordingly, the initial signal line STV is connected to the third signal output terminal Nout(n-1), and the third signal output terminal Nout(n-1) is the first signal output terminal of the gate drive unit one stage prior.

[0201] Specifically, the oxide semiconductor transistor may be a metal oxide transistor, and the silicon semiconductor transistor may be a low-temperature polysilicon transistor.

[0202] Specifically, as shown in Figure 8, the display panel 1 includes a drive circuit layer 22 and a light-emitting layer 23.

[0203] Specifically, as shown in Figure 8, the drive circuit layer 22 includes a shield layer 202, a barrier layer 203, a buffer layer 204, a first active layer 205, a first gate insulating layer 206, a first metal layer 207, a second gate insulating layer 208, a second metal layer 209, a third gate insulating layer 210, a second active layer 211, a fourth gate insulating layer 212, a third metal layer 213, a first interlayer insulating layer 214, a first source-drain layer 215, a first planarization layer 216, a second source-drain layer 217, and a second planarization layer 218. The shield layer 202 is provided on one side of the substrate 201, the barrier layer 203 is provided on the side of the shield layer 202 away from the substrate 201, the buffer layer 204 is provided on the side of the barrier layer 203 away from the shield layer 202, the first gate insulating layer 206 is provided between the first active layer 205 and the first metal layer 207, the second gate insulating layer 208 is provided between the first metal layer 207 and the second metal layer 209, and the third gate insulating layer 210 is provided between the second metal layer 2 The fourth gate insulating layer 212 is provided between the second active layer 211 and the third metal layer 213, the first interlayer insulating layer 214 is provided between the third metal layer 213 and the first source-drain layer 215, the first planarization layer 216 is provided between the first source-drain layer 215 and the second source-drain layer 217, and the second planarization layer 218 is provided between the second source-drain layer 217 and the pixel electrode layer 219.

[0204] Specifically, as shown in Figure 8, the light-emitting layer 23 includes a pixel electrode layer 219, a pixel definition layer 220, a light-emitting material layer, and a common electrode layer.

[0205] In some embodiments, the first electrode of the transistor in the above-described embodiment is the source and the second electrode is the drain. Alternatively, the first electrode of the transistor in the above-described embodiment is the drain and the second electrode is the source.

[0206] In some embodiments, the material of the first active layer includes low-temperature polysilicon, and the material of the second active layer includes a metal oxide, specifically indium gallium zinc oxide.

[0207] In some embodiments, as shown in Figure 10(a), the first active layer 205 includes the active pattern T2A of the ninth control transistor T2, the active pattern T3A of the fourth control transistor T3, the active pattern T5A of the second switching transistor T5, the active pattern T6A of the third output transistor T6, the active pattern T7A of the fourth output transistor T7, the active pattern T8A of the fourth switching transistor T8, the active pattern T9A of the second output transistor T9, and the second frequency division transistor This includes the active pattern T11A of transistor T11, the active pattern T12A of the second control transistor T12, the active pattern T15A of the reset transistor T15, the active pattern T16A of the first frequency division transistor T16, the active pattern T18A of the sixth control transistor T18, the active pattern T19A of the fourth frequency division transistor T19, the active pattern T20A of the third frequency division transistor T20, and the active pattern T22A of the eighth control transistor T22.

[0208] In some embodiments, as shown in Figure 10(b), the first metal layer 207 is connected to the gate T2G of the ninth control transistor T2, the gate T3G of the fourth control transistor T3, the gate T5G of the second switching transistor T5, the gate T6G of the third output transistor T6, the gate T7G of the fourth output transistor T7, the gate T8G of the fourth switching transistor T8, the gate T9G of the second output transistor T9, the gate T11G of the second frequency division transistor T11, and the gate T12G of the second control transistor T12. It includes the gate T15G of the reset transistor T15, the gate T16G of the first frequency division transistor T16, the gate T18G of the sixth control transistor T18, the gate T19G of the fourth frequency division transistor T19, the gate T20G of the third frequency division transistor T20, the gate T22G of the eighth control transistor T22, the first electrode plate C1a of the first capacitor C1, the first electrode plate C2a of the second capacitor C2, the first electrode plate C3a of the third capacitor C3, and the second signal output terminal Pout(n).

[0209] In some embodiments, as shown in Figure 11(a), the second metal layer 209 includes the first gate T1Ga of the third control transistor T1, the first gate T4Ga of the first switching transistor T4, the first gate T10Ga of the first output transistor T10, the first gate T13Ga of the first control transistor T13, the first gate T4Ga of the third switching transistor T14, the first gate T17Ga of the fifth control transistor T17, the first gate T21Ga of the seventh control transistor T21, the second electrode plate C1b of the first capacitor C1, the second electrode plate C2b of the second capacitor C2, and the second electrode plate C3b of the third capacitor C3.

[0210] In some embodiments, as shown in Figure 11(b), the second active layer 211 includes an active pattern T1A for the third control transistor T1, an active pattern T4A for the first switching transistor T4, an active pattern T10A for the first output transistor T10, an active pattern T13A for the first control transistor T13, an active pattern T14A for the third switching transistor T14, an active pattern T17A for the fifth control transistor T17, and an active pattern T21A for the seventh control transistor T21.

[0211] In some embodiments, as shown in Figure 12(a), the third metal layer 213 includes the second gate T1Gb of the third control transistor T1, the second gate T4Gb of the first switching transistor T4, the second gate T10Gb of the first output transistor T10, the second gate T13Gb of the first control transistor T13, the second gate T14Gb of the third switching transistor T14, the second gate T17Gb of the fifth control transistor T17, the second gate T21Gb of the seventh control transistor T21, an internal node P(n-2) two stages prior, and a first connection line L1, the first connection line L1 being connected to the first signal output terminal.

[0212] In some embodiments, as shown in Figure 12(b), the first source-drain layer 215 includes the first electrode T2D and second electrode T2S of the ninth control transistor T2, the first electrode T3D and second electrode T3S of the fourth control transistor T3, the first electrode T5D and second electrode T5S of the second switching transistor T5, the first electrode T6D and second electrode T6S of the third output transistor T6, the first electrode T7D and second electrode T7S of the fourth output transistor T7, and the fourth switching The first electrode T8D and second electrode T8S of the transistor T8, the first electrode T9D and second electrode T9S of the second output transistor T9, the first electrode T11D and second electrode T11S of the second frequency division transistor T11, the first electrode T12D and second electrode T12S of the second control transistor T12, the first electrode T15D and second electrode T15S of the reset transistor T15, the first electrode T16D and second electrode T16S of the first frequency division transistor T16, and the sixth control transistor The first electrode T18D and second electrode T18S of the zista T18, the first electrode T19D and second electrode T19S of the fourth frequency division transistor T19, the first electrode T20D and second electrode T20S of the third frequency division transistor T20, the first electrode T22D and second electrode T22S of the eighth control transistor T22, the first electrode T1D and second electrode T1S of the third control transistor T1, the first electrode T4D and second electrode T4S of the first switching transistor T4, and the first output transistor It includes the first electrode T10D and second electrode T10S of the transistor T10, the first electrode T13D and second electrode T13S of the first control transistor T13, the first electrode T14D and second electrode T14S of the third switching transistor T14, the first electrode T17D and second electrode T17S of the fifth control transistor T17, the first electrode T21D and second electrode T21S of the seventh control transistor T21, a second connection line L2, a third connection line L3, and a first output signal line Nout(n).

[0213] In some embodiments, as shown in Figure 13, the second source-drain layer 217 includes a first low-potential signal line NVGL, a first high-potential signal line NVGH, a second low-potential signal line PVGL, a second high-potential signal line PVGH, a first frequency division signal line NLF, an initial signal line STV, a control signal line Control, a second frequency division signal line PLF, a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4.

[0214] In some embodiments, as shown in Figure 14(a), the position of the first via 321 is shown, and the first via 321 refers to a via that is etched from the first source-drain layer to the first active layer, the first metal layer, and the second metal layer.

[0215] In some embodiments, as shown in Figure 14(b), the position of the second via 322 is shown, and the second via 322 refers to a via that is etched from the first source-drain layer to the second active layer and the third metal layer.

[0216] In some embodiments, as shown in Figure 15, the position of the third via 323 is shown, and the third via 323 refers to a via that is etched from the second source-drain layer to the first source-drain layer.

[0217] In some embodiments, as shown in Figure 17(a), the shield layer 202 includes a first shield pattern B1, a second shield pattern B2, a third shield pattern B3, a fourth shield pattern B4, a fifth shield pattern B5, a sixth shield pattern B6, and a seventh shield pattern B7.

[0218] In some embodiments, as shown in Figure 17(b), the first active layer 205 has an active pattern T2A for the ninth control transistor T2, an active pattern T3A for the fourth control transistor T3, an active pattern T5A for the second switching transistor T5, an active pattern T6A for the third output transistor T6, an active pattern T7A for the fourth output transistor T7, an active pattern T8A for the fourth switching transistor T8, an active pattern T9A for the second output transistor T9, and a second frequency division transistor This includes the active pattern T11A of transistor T11, the active pattern T12A of the second control transistor T12, the active pattern T15A of the reset transistor T15, the active pattern T16A of the first frequency division transistor T16, the active pattern T18A of the sixth control transistor T18, the active pattern T19A of the fourth frequency division transistor T19, the active pattern T20A of the third frequency division transistor T20, and the active pattern T22A of the eighth control transistor T22.

[0219] In some embodiments, as shown in Figure 18(a), the first metal layer 207 is connected to the gate T2G of the ninth control transistor T2, the gate T3G of the fourth control transistor T3, the gate T5G of the second switching transistor T5, the gate T6G of the third output transistor T6, the gate T7G of the fourth output transistor T7, the gate T8G of the fourth switching transistor T8, the gate T9G of the second output transistor T9, the gate T11G of the second frequency division transistor T11, and the gate T12G of the second control transistor T12. It includes the gate T15G of the reset transistor T15, the gate T16G of the first frequency division transistor T16, the gate T18G of the sixth control transistor T18, the gate T19G of the fourth frequency division transistor T19, the gate T20G of the third frequency division transistor T20, the gate T22G of the eighth control transistor T22, the first electrode plate C1a of the first capacitor C1, the first electrode plate C2a of the second capacitor C2, the first electrode plate C3a of the third capacitor C3, and the second signal output terminal Pout(n).

[0220] In some embodiments, as shown in Figure 18(b), the second metal layer 209 includes the second electrode plate C1b of the first capacitor C1, the second electrode plate C2b of the second capacitor C2, and the second electrode plate C3b of the third capacitor C3.

[0221] In some embodiments, as shown in Figure 19(a), the second active layer 211 includes an active pattern T1A for the third control transistor T1, an active pattern T4A for the first switching transistor T4, an active pattern T10A for the first output transistor T10, an active pattern T13A for the first control transistor T13, an active pattern T14A for the third switching transistor T14, an active pattern T17A for the fifth control transistor T17, and an active pattern T21A for the seventh control transistor T21.

[0222] In some embodiments, as shown in Figure 19(b), the third metal layer 213 includes the gate T1G of the third control transistor T1, the gate T4G of the first switching transistor T4, the gate T10G of the first output transistor T10, the gate T13G of the first control transistor T13, the gate T14G of the third switching transistor T14, the gate T17G of the fifth control transistor T17, the gate T21G of the seventh control transistor T21, an internal node P(n-2) two stages prior, and a first connection line L1, the first connection line L1 being connected to the first signal output terminal.

[0223] In some embodiments, as shown in Figure 20, the first source-drain layer 215 includes the first electrode T2D and second electrode T2S of the ninth control transistor T2, the first electrode T3D and second electrode T3S of the fourth control transistor T3, the first electrode T5D and second electrode T5S of the second switching transistor T5, the first electrode T6D and second electrode T6S of the third output transistor T6, the first electrode T7D and second electrode T7S of the fourth output transistor T7, and the fourth switching transistor The first electrode T8D and second electrode T8S of transistor T8, the first electrode T9D and second electrode T9S of the second output transistor T9, the first electrode T11D and second electrode T11S of the second frequency division transistor T11, the first electrode T12D and second electrode T12S of the second control transistor T12, the first electrode T15D and second electrode T15S of reset transistor T15, the first electrode T16D and second electrode T16S of the first frequency division transistor T16, and the sixth control transistor The first electrode T18D and second electrode T18S of transistor T18, the first electrode T19D and second electrode T19S of the fourth frequency division transistor T19, the first electrode T20D and second electrode T20S of the third frequency division transistor T20, the first electrode T22D and second electrode T22S of the eighth control transistor T22, the first electrode T1D and second electrode T1S of the third control transistor T1, the first electrode T4D and second electrode T4S of the first switching transistor T4, and the first output transistor It includes the first electrode T10D and second electrode T10S of the transistor T10, the first electrode T13D and second electrode T13S of the first control transistor T13, the first electrode T14D and second electrode T14S of the third switching transistor T14, the first electrode T17D and second electrode T17S of the fifth control transistor T17, the first electrode T21D and second electrode T21S of the seventh control transistor T21, a second connection line L2, a third connection line L3, and a first output signal line Nout(n).

[0224] In some embodiments, as shown in Figure 21, the second source-drain layer 217 includes a first low-potential signal line NVGL, a first high-potential signal line NVGH, a second low-potential signal line PVGL, a second high-potential signal line PVGH, a first frequency division signal line NLF, an initial signal line STV, a control signal line Control, a second frequency division signal line PLF, a first clock signal line PCK1, a second clock signal line PCK2, a third clock signal line PCK3, and a fourth clock signal line PCK4.

[0225] In some embodiments, as shown in Figure 22(a), the position of the first via 321 is shown, and the first via 321 refers to a via that is etched from the first source-drain layer to the first active layer, the first metal layer, and the second metal layer.

[0226] In some embodiments, as shown in Figure 22(b), the position of the second via 322 is shown, and the second via 322 refers to a via that is etched from the first source-drain layer to the second active layer and the third metal layer.

[0227] In some embodiments, as shown in Figure 23, the position of the third via 323 is shown, and the third via 323 refers to a via that is etched from the second source-drain layer to the first source-drain layer.

[0228] Specifically, the embodiments described above will be explained in detail with respect to the display panel from the perspective of each circuit, each film layer, each structure and its combination, but each embodiment can be combined if it is not contradictory, so as can be understood. For example, the second electrode of the first control transistor is connected to the first low-potential signal line, the initial signal line is connected to the internal node one stage prior, the potential of the first low-potential signal line is greater than the potential of the second low-potential signal line, the display unit includes a pixel driving circuit, the pixel driving circuit includes a compensation transistor, the compensation transistor is an oxide semiconductor transistor, and the channel length of the first control transistor is greater than the channel length of the compensation transistor.

[0229] Furthermore, embodiments of the present application provide a display device, which includes a display panel described in any one of the embodiments described above.

[0230] Specifically, as shown in Figure 27, the display device includes a display panel 1, a flexible circuit board 41, and a drive chip 42. The signal from the shield layer 202 can be input by the flexible circuit board 41, with connection terminals 43 connected to the flexible circuit board 41.

[0231] As can be seen from the above examples,

[0232] Embodiments of the present invention provide a display panel comprising a display unit and a gate drive circuit located on at least one side of the display unit, wherein the gate drive circuit comprises a plurality of cascaded gate drive units, each gate drive unit comprising at least three inverter units, each inverter unit comprising one high-potential line, one low-potential line, and a first transistor and a second transistor connected in series between the high-potential line and the low-potential line, the first transistor being an oxide semiconductor transistor and the second transistor being a silicon semiconductor transistor, the gates of the first transistor and the gates of the second transistor being electrically connected to the same node. Herein, the display panel further comprises a shielding layer, and in at least one inverter unit, the active pattern of the first transistor is provided corresponding to the shielding layer, the potential of the shielding layer being less than the potential of the low-potential line. In this invention, in at least one inverter unit, the active pattern of the first transistor is provided corresponding to the shield layer, and the potential of the shield layer is smaller than the potential of the low-potential line, so that the threshold voltage of the first transistor becomes positively biased, thereby avoiding the generation of leakage current when the oxide semiconductor transistor is turned off, reducing the power consumption of the gate drive unit, and reducing the power consumption of the display panel without affecting the output signal of the gate drive unit, allowing the display panel to operate normally.

[0233] In the embodiments described above, the emphasis differs for each embodiment, and for parts of one embodiment that are not described in detail, you can refer to descriptions related to other embodiments.

[0234] The display panels provided by the embodiments of this application have been described in detail above, and the principles and embodiments of this application have been explained using specific examples in this specification. The above descriptions of embodiments are intended to aid in understanding the technical proposal and its core concept. Those skilled in the art may modify the technical proposals described in the above embodiments or substitute some of their technical features with equivalent ones, but it should be understood that these modifications or substitutions do not cause the essence of the corresponding technical proposal to deviate from the scope of the technical proposals of the various embodiments of this application. [Explanation of symbols]

[0235] 1: Display Panel 10: First Inverter Unit 11:Display section 12: Gate drive circuit 13:Terminal section 17D: 1st electrode 20: Third Inverter Unit 22: Drive circuit layer 23: Emitting layer 30: Second Inverter Unit 40: Second output unit 41: Flexible circuit board 42: Drive Chip 43: Connection terminals 50: Frequency division module 60: Output control unit 70: Reset Module 90: Switching module 110: Pixel driving circuit 120: Gate drive unit 121: First gate drive unit 122: Second gate drive unit 123: Third gate drive unit 124: Fourth gate drive unit 201: Circuit board 202: Shield layer 203: Barrier layer 204: Buffer layer 205: 1st active layer 206: First gate insulating layer 207: 1st metal layer 208: Second gate insulating layer 209: Second metal layer 210: Third gate insulating layer 211: 2nd active layer 212: Fourth gate insulating layer 213:Third metal layer 214: First interlayer insulating layer 215: First source-drain layer 216: First planarization layer 217: Second source-drain layer 218: Second planarization layer 219: Pixel electrode layer 220: Pixel definition layer 311: 1st protrusion 312: 1st groove 313:Second protrusion 314: 2nd groove 321: First Via 322: Second Beer 323: Third Beer 501: First frequency division module 502: Second frequency division module 801: First control unit 802: Second control unit

Claims

1. A display panel comprising a display unit and a gate drive circuit located on at least one side of the display unit, wherein the gate drive circuit comprises a plurality of gate drive units connected in cascade, each gate drive unit comprises at least three inverter units, each inverter unit comprising one high-potential line, one low-potential line, and a first transistor and a second transistor connected in series between the high-potential line and the low-potential line, wherein the first transistor is an oxide semiconductor transistor, and the second transistor is a silicon semiconductor transistor, and the gates of the first transistor and the gates of the second transistor are electrically connected to the same node. Here, the display panel further includes a shielding layer, and in at least one of the inverter units, the active pattern of the first transistor is provided corresponding to the shielding layer, and the potential of the shielding layer is less than the potential of the low-potential line. Display panel.

2. At least three of the inverter units are A first inverter unit comprising a first control transistor and a second control transistor, wherein the first control transistor is an oxide semiconductor transistor and the second control transistor is a silicon semiconductor transistor, the gates of the first control transistor and the gates of the second control transistor are connected to an initial signal line, and the first electrode of the first control transistor and the first electrode of the second control transistor are electrically connected to a first node, A second inverter unit comprising a first output transistor, a second output transistor, a first low-potential signal line, and a first high-potential signal line, wherein the first output transistor is an oxide semiconductor transistor, the second output transistor is a silicon semiconductor transistor, the gate of the first output transistor and the gate of the second output transistor are electrically connected to the first node, the first electrode of the first output transistor is connected to the first electrode of the second output transistor, the second electrode of the first output transistor is connected to the first low-potential signal line, and the second electrode of the second output transistor is connected to the first high-potential signal line, A third inverter unit comprising a third control transistor, a fourth control transistor, a second low-potential signal line, and a second high-potential signal line, wherein the third control transistor is an oxide semiconductor transistor, the fourth control transistor is a silicon semiconductor transistor, the gates of the third control transistor and the gates of the fourth control transistor are connected to the first node, the first electrode of the third control transistor and the first electrode of the fourth control transistor are connected to the internal node of the current stage, the second electrode of the third control transistor is connected to the second low-potential signal line, and the second electrode of the fourth control transistor is connected to the second high-potential signal line, Here, at least one active pattern among the first control transistor, the first output transistor, and the third control transistor is provided corresponding to the shield layer. The display panel according to claim 1.

3. The aforementioned display panel is circuit board and A first active layer provided on one side of the substrate, A first metal layer provided on the side of the first active layer away from the substrate, A second metal layer provided on the side of the first metal layer away from the first active layer, A second active layer is provided on the side of the second metal layer away from the first metal layer and includes an active pattern for a first control transistor, an active pattern for a first output transistor, and an active pattern for a third control transistor. The second active layer is provided on the side away from the second metal layer and includes a third metal layer comprising the gate of the first control transistor, the gate of the first output transistor, and the gate of the third control transistor. Here, the shield layer is provided between the substrate and the first active layer, and the orthographic projection on the substrate of the active pattern of the first control transistor, the active pattern of the first output transistor, and the active pattern of the third control transistor, which is provided in accordance with the shield layer, does not overlap with the orthographic projection on the substrate of the second metal layer. The display panel according to claim 2.

4. The orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the active pattern of the first control transistor on the substrate, the shield layer includes a first shield pattern, the orthographic projection of the first shield pattern on the substrate overlaps with the orthographic projection of the active pattern of the first control transistor on the substrate, and the potential of the first shield pattern is smaller than the potential of the second electrode of the first control transistor. The display panel according to claim 3.

5. The orthographic projection of the active pattern of the first control transistor on the substrate lies within the orthographic projection of the first shield pattern on the substrate, and there is a gap between the boundary of the active pattern of the first control transistor and the boundary of the first shield pattern. The display panel according to claim 4.

6. The shield layer further includes a second shield pattern, wherein the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the active pattern of the third control transistor on the substrate, the orthographic projection of the third control transistor on the substrate overlaps with the orthographic projection of the second shield pattern on the substrate, and the potential of the second shield pattern is smaller than the potential of the second electrode of the third control transistor. The display panel according to claim 3.

7. The orthographic projection of the active pattern of the third control transistor on the substrate lies within the orthographic projection of the second shield pattern on the substrate, and there is a gap between the boundary of the active pattern of the third control transistor and the boundary of the second shield pattern. The display panel according to claim 6.

8. The shield layer further includes a third shield pattern, wherein the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the active pattern of the first output transistor on the substrate, the orthographic projection of the first output transistor on the substrate overlaps with the orthographic projection of the third shield pattern on the substrate, and the potential of the third shield pattern is smaller than the potential of the second electrode of the first output transistor. The display panel according to claim 3.

9. The orthographic projection of the active pattern of the first output transistor on the substrate lies within the orthographic projection of the third shield pattern on the substrate, and there is a gap between the boundary of the active pattern of the first output transistor and the boundary of the third shield pattern. The display panel according to claim 8.

10. The orthographic projection of the shield layer on the substrate does not overlap with the orthographic projection of the first active layer on the substrate. The display panel according to claim 3.

11. The first inverter unit includes a first low-potential signal line and a second high-potential signal line, the second electrode of the first control transistor is connected to the first low-potential signal line, the second electrode of the second control transistor is connected to the second high-potential signal line, the initial signal line is connected to the internal node one stage prior, and the potential of the first low-potential signal line is greater than the potential of the second low-potential signal line. The display panel according to claim 2.

12. The first inverter unit includes the second low-potential signal line and the second high-potential signal line, the second electrode of the first control transistor is connected to the second low-potential signal line, the second electrode of the second control transistor is connected to the second high-potential signal line, and the initial signal line is connected to the first output signal terminal of the gate drive unit one stage prior. The display panel according to claim 2.

13. The display unit includes a pixel driving circuit, the pixel driving circuit includes an oxide semiconductor transistor, and the channel length of at least one of the first control transistor, the first output transistor, and the third control transistor is greater than the channel length of the oxide semiconductor transistor. The display panel according to claim 2.

14. The gate drive unit further includes an output control unit, a first control unit, and a second control unit, the output control unit includes a first switching transistor, a second switching transistor, and a third switching transistor, the first switching transistor and the third switching transistor being oxide semiconductor transistors, the second switching transistor being a silicon semiconductor transistor, the first electrode of the first switching transistor being connected to the first electrode of the second switching transistor, the second electrode of the first switching transistor being connected to the first node, the gate of the second switching transistor and the gate of the third switching transistor being connected to the first electrode of the third control transistor, and the first electrode of the third control transistor being connected to the first node. The first control unit includes a fifth control transistor and a sixth control transistor, wherein the fifth control transistor is an oxide semiconductor transistor, the sixth control transistor is a silicon semiconductor transistor, the first electrode of the fifth control transistor is connected to the first electrode of the sixth control transistor, the second electrode of the fifth control transistor is electrically connected to the first node, and the gate of the sixth control transistor is connected to the gate of the third switching transistor. The second control unit includes a seventh control transistor and an eighth control transistor, wherein the seventh control transistor is an oxide semiconductor transistor, the eighth control transistor is a silicon semiconductor transistor, the first electrode of the seventh control transistor is connected to the first electrode of the eighth control transistor, the second electrode of the seventh control transistor is electrically connected to the first node, and the gate of the eighth control transistor is connected to the gate of the third switching transistor. The display panel according to claim 2.

15. The aforementioned display panel is circuit board and A first active layer provided on one side of the substrate, A first metal layer provided on the side of the first active layer away from the substrate, A second metal layer provided on the side of the first metal layer away from the first active layer, A second active layer is provided on the side of the second metal layer away from the first metal layer and includes the active pattern of the first switching transistor, the active pattern of the third switching transistor, the active pattern of the fifth control transistor, and the active pattern of the seventh control transistor. The second active layer is provided on the side away from the second metal layer and includes a third metal layer which includes the gate of the first switching transistor, the gate of the third switching transistor, the gate of the fifth control transistor, and the gate of the seventh control transistor. Here, the shield layer is provided between the substrate and the first active layer, the shield layer includes a fourth shield pattern, the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the active pattern of the first switching transistor on the substrate, the orthographic projection of the active pattern of the first switching transistor on the substrate overlaps with the orthographic projection of the fourth shield pattern on the substrate, and when the first switching transistor is in the off state, the potential of the fourth shield pattern is smaller than the potential of the second electrode of the first switching transistor. and / or, the shield layer includes a fifth shield pattern, wherein the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the active pattern of the third switching transistor on the substrate, the orthographic projection of the active pattern of the third switching transistor on the substrate overlaps with the orthographic projection of the fifth shield pattern on the substrate, and when the third switching transistor is in the off state, the potential of the fifth shield pattern is less than the potential of the second electrode of the third switching transistor. and / or, the shield layer includes a sixth shield pattern, wherein the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the active pattern of the fifth control transistor on the substrate, the orthographic projection of the active pattern of the fifth control transistor on the substrate overlaps with the orthographic projection of the sixth shield pattern on the substrate, and when the fifth control transistor is in the off state, the potential of the sixth shield pattern is less than the potential of the second electrode of the fifth control transistor. and / or, the shield layer includes a seventh shield pattern, wherein the orthographic projection of the second metal layer on the substrate does not overlap with the orthographic projection of the active pattern of the seventh control transistor on the substrate, the orthographic projection of the active pattern of the seventh control transistor on the substrate overlaps with the orthographic projection of the seventh shield pattern on the substrate, and when the seventh control transistor is in the off state, the potential of the seventh shield pattern is less than the potential of the second electrode of the seventh control transistor. The display panel according to claim 14.

16. The display unit includes a pixel driving circuit, and the pixel driving circuit includes an oxide semiconductor transistor. Here, the channel length of the first switching transistor is greater than the channel length of the oxide semiconductor transistor, and / or the channel length of the third switching transistor is greater than the channel length of the oxide semiconductor transistor, and / or the channel length of the fifth control transistor is greater than the channel length of the oxide semiconductor transistor, and / or the channel length of the seventh control transistor is greater than the channel length of the oxide semiconductor transistor. The display panel according to claim 15.

17. The aforementioned display panel is circuit board and A first active layer is provided on one side of the substrate and includes an active pattern for the second output transistor, A first metal layer provided on the side of the first active layer away from the substrate, A second metal layer provided on the side of the first metal layer away from the first active layer, A second active layer is provided on the side of the second metal layer away from the first metal layer and includes the active pattern of the first output transistor, A third metal layer provided on the side of the second active layer away from the second metal layer, The third metal layer includes a first source-drain layer provided on the side away from the second active layer, which includes the first electrode of the first output transistor and the first electrode of the second output transistor, Here, the active pattern of the second output transistor includes a plurality of first protrusions and a first groove located between the plurality of first protrusions, the active pattern of the first output transistor includes a plurality of second protrusions and a second groove located between the plurality of second protrusions, the first protrusions are provided corresponding to the second grooves, the second protrusions are provided corresponding to the first grooves, the first electrode of the first output transistor is connected to the second protrusions, and the first electrode of the second output transistor is connected to the first protrusions. The display panel according to claim 2.

18. The active pattern shape of the first output transistor includes a comb shape, and the active pattern shape of the second output transistor includes a comb shape. The display panel according to claim 17.

19. The oxide semiconductor transistor is a metal oxide transistor, and the silicon semiconductor transistor is a low-temperature polysilicon transistor. The display panel according to claim 2.

20. The first electrode is the source and the second electrode is the drain, or the first electrode is the drain and the second electrode is the source. The display panel according to claim 2.

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