Array substrate and display device

Abstract

The array substrate includes a plurality of pixel driver circuits and a plurality of gate lines. Each pixel driver circuit includes a driver transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Each gate line is configured to provide a gate scan signal to the data writing transistor in the corresponding pixel driver circuit. The gate electrode of the driver transistor is connected to the third capacitor electrode. The first node connection line connects the second electrode of the first reset transistor to the third capacitor electrode. The orthographic projection of the corresponding gate lines onto the base substrate does not substantially overlap with the orthographic projection of the first node connection line onto the base substrate.

Description

Technical Field

[0001] The present invention relates to display technology, and more specifically, to an array substrate and a display device.

Background Art

[0002] Organic light-emitting diode (OLED) displays have received particular attention in today's research field of flat panel displays. Different from thin-film transistor liquid crystal displays (TFT-LCDs) that control brightness with a stable voltage, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes a plurality of pixel units in which pixel driving circuits arranged in a plurality of rows and columns are disposed. Each pixel driving circuit includes a driving transistor having a gate terminal connected to one gate line for each row and a drain terminal connected to one data line for each column. When the row in which the pixel unit is gated is turned on, the switching transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line to the driving transistor through the switching transistor, and a current corresponding to the data voltage is output to the OLED device by the driving transistor. The OLED device is driven to emit light with a corresponding brightness.

Summary of the Invention

Means for Solving the Problems

[0003] In one respect, the present disclosure provides an array substrate comprising a plurality of pixel drive circuits and a plurality of gate lines, each of the plurality of pixel drive circuits comprising a drive transistor, a data write transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line, each of the plurality of gate lines configured to provide a gate scan signal to the data write transistor in the corresponding pixel drive circuit, the gate electrode of the drive transistor being connected to the third capacitor electrode, the first node connection line connecting the second electrode of the first reset transistor to the third capacitor electrode, and the orthographic projection of the corresponding gate lines onto a base substrate substantially overlaps with the orthographic projection of the first node connection line onto the base substrate.

[0004] Optionally, the orthographic projection of the corresponding gate line onto the base substrate and the orthographic projection of the first node connection line onto the base substrate may be separated by the orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate.

[0005] Optionally, the orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate may not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate, nor may it substantially overlap with the orthographic projection of the first node connection line onto the base substrate.

[0006] Optionally, the orthographic projection of the corresponding gate line onto the base substrate and the orthographic projection of the third capacitor electrode of the second capacitor onto the base substrate may be separated by the orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate.

[0007] Optionally, the orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate may not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate, nor may it substantially overlap with the orthographic projection of the third capacitor electrode of the second capacitor onto the base substrate.

[0008] Optionally, the orthographic projection of the corresponding gate line onto the base substrate does not have to substantially overlap with the orthographic projection of the active layer of the first reset transistor and the second electrode onto the base substrate.

[0009] Optionally, the second electrode of the first reset transistor may cross the second capacitor electrode.

[0010] Optionally, the array substrate includes a plurality of second capacitor electrode lines extending in a direction substantially parallel to a second direction, each of the plurality of second capacitor electrode lines includes a second capacitor electrode connected to each other of a pixel drive circuit in the same row, each pixel drive circuit further includes a light emission control transistor and a third reset transistor, wherein the second electrode of the light emission control transistor is separated from the second electrode of the third reset transistor by a connecting line connecting two adjacent second capacitor electrodes of two adjacent pixel drive circuits in the same row in the corresponding second capacitor electrode line, and the second electrode of the light emission control transistor is separated from the first electrode of the drive transistor.

[0011] Optionally, each pixel driving circuit further includes a second node connection line connected via a third via to the second electrode of the light emission control transistor, via a fourth via to the first electrode of the driving transistor, and via a fifth via to the second electrode of the third reset transistor, wherein the second electrode of the light emission control transistor and the first electrode of the driving transistor are located in a first semiconductor material layer, the corresponding second capacitor electrode line is located in a first gate metal layer located away from the base substrate of the first semiconductor material layer, the second electrode of the third reset transistor is located in a second semiconductor material layer located away from the base substrate of the first gate metal layer, and the second node connection line is located in a first signal line layer located away from the base substrate of the second semiconductor material layer.

[0012] Optionally, the second node connection line may intersect with the corresponding second capacitor electrode line.

[0013] Optionally, the array substrate further includes a plurality of voltage supply lines, each pixel driving circuit further includes a light emission control transistor and a voltage supply connection line, a corresponding voltage supply line among the plurality of voltage supply lines is connected to the voltage supply connection line via an eighth via, the voltage supply connection line is connected to the first electrodes of two adjacent light emission control transistors of two adjacent pixel driving circuits in the same row via a ninth via, the first electrodes of the two adjacent light emission control transistors of two adjacent pixel driving circuits in the same row are part of a single structure, and each voltage supply connection line may be connected to the second capacitor electrode of the first capacitor of the two adjacent pixel driving circuits in the same row via a different via.

[0014] Optionally, the voltage supply connection line includes a main line portion extending substantially parallel to the second direction, and a first extension, a second extension, and a third extension portion extending away from the main line portion, each of which extends substantially parallel to the first direction, and the corresponding voltage supply line of the plurality of voltage supply lines is connected to the first extension via the eighth via, the first extension is connected via the ninth via to the first electrode of the two adjacent light emission control transistors of the two adjacent pixel drive circuits in the same row, the second extension is connected to the second capacitor electrode of the first capacitor of the first adjacent pixel drive circuit, and the third extension is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel drive circuit.

[0015] Optionally, the voltage supply connection lines may be substantially parallel to the first direction and substantially mirror-symmetric with respect to a plane substantially perpendicular to the light-emitting surface of the array substrate.

[0016] Optionally, each pixel driver circuit further includes a compensating transistor, wherein the orthographic projection of the voltage supply connection line onto the base substrate at least partially encloses the orthographic projection onto the base substrate of two adjacent compensating transistors of two adjacent pixel driver circuits in the same row, and the portion of the line may intersect with the active layers of two adjacent data writing transistors of two adjacent pixel driver circuits in the same row.

[0017] Optionally, each pixel driving circuit further includes a compensation transistor, wherein at least a portion of the orthographic projection of the second extension onto the base substrate separates the orthographic projection of at least the active layer of the first reset transistor in the first adjacent pixel driving circuit from the orthographic projection of at least the active layer of the compensation transistor in the first adjacent pixel driving circuit from the orthographic projection of at least the active layer of the compensation transistor in the first adjacent pixel driving circuit from the orthographic projection of at least the active layer of the first reset transistor in the second adjacent pixel driving circuit from the orthographic projection of at least the active layer of the compensation from the base substrate.

[0018] Optionally, the array substrate further includes a plurality of first reset signal lines and a plurality of data lines, wherein at least a portion of the orthographic projection of each of the plurality of first reset signal lines onto the base substrate may separate the orthographic projection onto the base substrate of at least a portion of the plurality of data lines configured to provide data signals to a first adjacent pixel drive circuit and the orthographic projection onto the base substrate of at least a portion of the plurality of data lines configured to provide data signals to a second adjacent pixel drive circuit.

[0019] Optionally, the array substrate further includes a plurality of first reset signal lines, each of the plurality of first reset signal lines including a plurality of loops arranged substantially parallel to the first direction, and each of the plurality of loops being connected to the first electrodes of two adjacent first reset transistors of two adjacent pixel drive circuits in the same row.

[0020] Optionally, the array substrate further includes an interconnection voltage supply network, the interconnection voltage supply network includes a plurality of voltage supply lines, a plurality of second capacitor electrode lines, and a plurality of voltage supply connection lines, wherein the plurality of voltage supply lines extend in a direction substantially parallel to a first direction, the plurality of second capacitor electrode lines extend in a direction substantially parallel to a second direction, each of the plurality of second capacitor electrode lines includes a second capacitor electrode of a pixel driving circuit in the same row, and each of the plurality of voltage supply connection lines connects a corresponding voltage supply line of the plurality of voltage supply lines to a corresponding second capacitor electrode line of the plurality of second capacitor electrode lines.

[0021] Optionally, each pixel driving circuit further includes a compensating transistor and a third node connection line, the third node connection line connected via a sixth via to the second electrodes of the compensating transistor and the data writing transistor, and connected via a seventh via to the first capacitor electrode of the first capacitor and the fourth capacitor electrode of the second capacitor, the orthographic projection of the third node connection line onto the base substrate at least partially overlapping with the orthographic projection of the active layer of the compensating transistor onto the base substrate, and the third node connection line may extend in a direction substantially parallel to the extending direction of the active layer of the compensating transistor.

[0022] In another aspect, the present disclosure provides a display device comprising an array substrate described herein and one or more integrated circuits connected to the array substrate. [Brief explanation of the drawing]

[0023] The following drawings are for illustrative purposes only and are not intended to limit the scope of the invention. [Figure 1] This is a plan view of a display substrate in some embodiments of the present disclosure. [Figure 2A]It is a circuit diagram showing the configuration of a pixel driving circuit in some embodiments according to the present disclosure. [Figure 2B] It is a circuit diagram showing the configuration of a pixel driving circuit in some embodiments according to the present disclosure. [Figure 3] It is a timing chart showing the operation of a pixel driving circuit in some embodiments according to the present disclosure. [Figure 4A] It shows the current path in the phase t1 of an image frame in a pixel driving circuit of some embodiments according to the present disclosure. [Figure 4B] It shows the current path in the phase t2 of an image frame in a pixel driving circuit of some embodiments according to the present disclosure. [Figure 4C] It shows the current path in the phase t3 of an image frame in a pixel driving circuit of some embodiments according to the present disclosure. [Figure 4D] It shows the current path in the phase t4 of an image frame in a pixel driving circuit of some embodiments according to the present disclosure. [Figure 4E] It shows the current path in the phase t5 of an image frame in a pixel driving circuit of some embodiments according to the present disclosure. [Figure 5A] It is a schematic diagram showing the configuration of a pixel driving circuit in an array substrate of some embodiments according to the present disclosure. [Figure 5B] It is a schematic diagram showing the arrangement of pixel driving circuits in the array substrate shown in FIG. 5A. [Figure 5C] It is a schematic diagram showing the configuration of the first semiconductor material layer in the array substrate shown in FIG. 5A. [Figure 5D] It is a schematic diagram showing the configuration of the first gate metal layer in the array substrate shown in FIG. 5A. [Figure 5E] It is a schematic diagram showing the configuration of the second gate metal layer in the array substrate shown in FIG. 5A. [Figure 5F] It is a schematic diagram showing a via penetrating the first interlayer dielectric layer in the array substrate shown in FIG. 5A. [Figure 5G]Figure 5A is a schematic diagram showing the configuration of the second semiconductor material layer in the array substrate. [Figure 5H] Figure 5A is a schematic diagram showing vias penetrating the second interlayer dielectric layer in the array substrate. [Figure 5I] Figure 5A is a schematic diagram showing the configuration of the third gate metal layer in the array substrate. [Figure 5J] Figure 5A is a schematic diagram showing vias penetrating the passivation layer in the array substrate. [Figure 5K] Figure 5A is a schematic diagram showing the configuration of the first signal line layer in the array substrate. [Figure 5L] Figure 5A is a schematic diagram showing vias penetrating the first planarization layer in the array substrate. [Figure 5M] Figure 5A is a schematic diagram showing the configuration of the second signal line layer in the array substrate. [Figure 5N] Figure 5A is a schematic diagram showing vias penetrating the second planarization layer in the array substrate. [Figure 5O] Figure 5A is a schematic diagram showing the configuration of the anode layer in the array substrate. [Figure 6A] This is a cross-sectional view along the line A-A' in Figure 5A. [Figure 6B] This is a cross-sectional view along the line B-B' in Figure 5A. [Figure 6C] This is a cross-sectional view along the line C-C' in Figure 5A. [Figure 6D] This is a cross-sectional view along the line D-D' in Figure 5A. [Figure 7A] Figure 5A is a schematic diagram showing the configuration of the second semiconductor material layer and the first signal line layer in the array substrate. [Figure 7B] This is a schematic diagram showing the configuration of the reset signal line network in some embodiments of the present disclosure. [Figure 7C] This is a schematic diagram showing the configuration of a voltage supply network in some embodiments of the present disclosure. [Figure 7D]This is a schematic diagram showing the configuration of a second signal line layer in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure. [Figure 8A] This is a schematic diagram showing the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. [Figure 8B] Figure 8A is a schematic diagram showing the arrangement of pixel driving circuits in the array substrate. [Figure 8C] Figure 8A is a schematic diagram showing the configuration of the first semiconductor material layer in the array substrate. [Figure 8D] Figure 8A is a schematic diagram showing the configuration of the first gate metal layer in the array substrate. [Figure 8E] Figure 8A is a schematic diagram showing the configuration of the second gate metal layer in the array substrate. [Figure 8F] Figure 8A is a schematic diagram showing vias penetrating the first interlayer dielectric layer in the array substrate. [Figure 8G] Figure 8A is a schematic diagram showing the configuration of the second semiconductor material layer in the array substrate. [Figure 8H] Figure 8A is a schematic diagram showing vias penetrating the second interlayer dielectric layer in the array substrate. [Figure 8I] Figure 8A is a schematic diagram showing the configuration of the third gate metal layer in the array substrate. [Figure 8J] Figure 8A is a schematic diagram showing vias penetrating the passivation layer in the array substrate. [Figure 8K] Figure 8A is a schematic diagram showing the configuration of the first signal line layer in the array substrate. [Figure 8L] Figure 8A is a schematic diagram showing vias penetrating the first planarization layer in the array substrate. [Figure 8M] Figure 8A is a schematic diagram showing the configuration of the second signal line layer in the array substrate. [Figure 8N] Figure 8A is a schematic diagram showing vias penetrating the second planarization layer in the array substrate. [Figure 8O]Figure 8A is a schematic diagram showing the configuration of the anode layer in the array substrate. [Figure 9] This is a schematic diagram showing the layout of the gate lines corresponding to the first node connection lines in the array substrate shown in Figure 5A or Figure 8A. [Figure 10] This is a schematic diagram showing the layout of the second capacitor electrode wires corresponding to the second node connection lines in the array substrate shown in Figure 5A or Figure 8A. [Figure 11] This is a schematic diagram showing the configuration of voltage supply connection lines in some embodiments of the present disclosure. [Figure 12] This is a schematic diagram showing the layout of voltage supply connection lines to the second semiconductor material layer in the array substrate shown in Figure 5A or Figure 8A. [Figure 13] This is a schematic diagram showing the layout of multiple first reset signal lines for multiple data lines in four adjacent pixel driving circuits in the same row of an array substrate according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0024] The present disclosure will be described in more detail below with reference to embodiments. Note that the following descriptions of some embodiments are illustrative and descriptive, and are not intended to be exhaustive or to limit the disclosure to the exact form.

[0025] This disclosure provides array substrates and display devices that substantially eliminate one or more problems arising from limitations and drawbacks in related technologies. In one aspect, this disclosure provides array substrates. In some embodiments, the array substrate includes a plurality of pixel driver circuits and a plurality of gate lines. Optionally, each of the plurality of pixel driver circuits may include a drive transistor, a data write transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Optionally, each of the plurality of gate lines may be configured to provide a gate scan signal to the data write transistor in the corresponding pixel driver circuit. Optionally, the gate electrode of the drive transistor may be connected to a third capacitor electrode. Optionally, the second electrode of the first reset transistor may be connected to a third capacitor electrode by a first node connection line. Optionally, the orthographic projection of the corresponding gate line onto the base substrate does not have to substantially overlap with the orthographic projection of the first node connection line onto the base substrate.

[0026] The array substrate in this disclosure may use a variety of suitable pixel driving circuits. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, one of each of the multiple pixel driving circuits is a 7T2C driving circuit. In some embodiments, one of each of the multiple pixel driving circuits is an 8T2C driving circuit. The array substrate in this disclosure may use a variety of suitable light-emitting elements. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes, and microlight-emitting diodes. Optionally, the light-emitting element may be a microlight-emitting diode. Optionally, the light-emitting element may be an organic light-emitting diode including an organic light-emitting layer.

[0027] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Referring to Figure 1, the array substrate includes an array of subpixels Sp. Each subpixel includes an electronic component, such as a light-emitting element. For example, the light-emitting element is driven by a corresponding pixel driver circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, and a plurality of voltage supply lines Vdd. Each subpixel Sp is driven to emit light by a corresponding pixel driver circuit PDC. For example, a high-voltage signal (e.g., a VDD signal) is input to the corresponding pixel driver circuit PDC connected to the anode of the light-emitting element via each of the voltage supply lines Vdd, and a low-voltage signal (e.g., a VSS signal) is input to the cathode of the light-emitting element via a low-voltage supply line. The voltage difference between the high-voltage signal (e.g., a VDD signal) and the low-voltage signal (e.g., a VSS signal) is the drive voltage ΔV that drives the light-emitting element to emit light.

[0028] Figure 2A is a schematic diagram showing the configuration of a pixel driving circuit in some embodiments of the present disclosure. Referring to Figure 2A, the pixel driving circuit includes a driving transistor T3, a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2, a second capacitor C2 having a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4, and a data writing transistor T4 having an electrode gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The electrode gate of the driving transistor T3 is connected to the third capacitor electrode Ce3.

[0029] In some embodiments, the pixel driving circuit further includes a gate electrode connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a first electrode of a driving transistor T3, and a compensation transistor T2 having a first capacitor electrode Ce1, a fourth capacitor electrode Ce4, and a second electrode connected to a second electrode of a data writing transistor T4.

[0030] In some embodiments, the first capacitor electrode Ce1 of the first capacitor C1 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the fourth capacitor electrode Ce4. The second capacitor electrode Ce2 of the first capacitor C1 is connected to a corresponding voltage supply line (e.g., a high-voltage signal line) among a plurality of voltage supply lines Vdd.

[0031] In some embodiments, the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the first capacitor electrode Ce1. The third capacitor electrode Ce3 of the second capacitor C2 is connected to the gate electrode of the drive transistor T3.

[0032] In some embodiments, the pixel driving circuit further includes a light emission control transistor T5 having a gate electrode connected to a corresponding light emission control signal line among a plurality of light emission signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to a first electrode of the driving transistor T3 and a first electrode of the compensating transistor T2.

[0033] In some embodiments, the pixel driving circuit further includes at least one reset transistor. In some embodiments, the pixel driving circuit further includes a first reset transistor T1 having a gate electrode connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the gate electrode of the driving transistor T3 and the third capacitor electrode Ce3 of the second capacitor C2.

[0034] In some embodiments, the pixel driving circuit further includes a second reset transistor T7 having a gate electrode connected to a corresponding second control signal line among a plurality of second control signal lines SL2, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the anode of the driving transistor T3 and the light-emitting element LE.

[0035] In some embodiments, the pixel driving circuit further includes a third reset transistor T6 having a gate electrode connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to a third reset signal line Vint3, and a second electrode connected to a first electrode of the driving transistor T3, a second electrode of the light emission control transistor T5, and a second electrode of the compensation transistor T2.

[0036] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor T3, the third capacitor electrode Ce3, and the second electrode of the first reset transistor T1. The second node N2 is connected to the first electrode of the driving transistor T3, the second electrode of the light emission control transistor T5, the first electrode of the compensation transistor T2, and the second electrode of the third reset transistor T6. The third node N3 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, the first capacitor electrode Ce1, and the fourth capacitor electrode Ce4. The fourth node N4 is connected to the second electrode of the driving transistor T3, the second electrode of the second reset transistor T7, and the anode of the light-emitting element LE.

[0037] In this specification, the first electrode or the second electrode refers to either the first terminal or the second terminal of the transistor, which is connected to the active layer of the transistor. The direction of the current flowing through the transistor may be configured to flow from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, for example, the first electrode may be configured to receive an input signal and the second electrode may be configured to output an output signal; for other examples, the second electrode may be configured to receive an input signal and the first electrode may be configured to output an output signal.

[0038] The present disclosure may be implemented in a pixel driving circuit having various transistors, including a pixel driving circuit having a p-type transistor, a pixel driving circuit having an n-type transistor, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. Referring to Figure 2A, the data writing transistor T4, the compensation transistor T2, the first reset transistor T1, and the third reset transistor T6 are n-type transistors such as metal oxide transistors, and the driving transistor T3, the light emission control transistor T5, and the second reset transistor T7 are p-type transistors such as polysilicon transistors. In the case of a p-type transistor, the active control signal (e.g., on control signal) is a low-voltage signal, and the inactive control signal (e.g., off control signal) is a high-voltage signal. In the case of an n-type transistor, the active control signal (e.g., on control signal) is a high-voltage signal, and the inactive control signal (e.g., off control signal) is a low-voltage signal.

[0039] Figure 2B is a schematic diagram showing the configuration of a pixel driving circuit in some embodiments of the present disclosure. Referring to Figure 2B, the pixel driving circuit includes a driving transistor T3, a first capacitor C1 having a first capacitor electrode Ce1 and a second capacitor electrode Ce2, a second capacitor C2 having a third capacitor electrode Ce3 and a fourth capacitor electrode Ce4, and a data writing transistor T4 having an electrode gate connected to a corresponding gate line among a plurality of gate lines GL, a first electrode connected to a corresponding data line among a plurality of data lines DL, and a second electrode connected to the first capacitor electrode Ce1 and the fourth capacitor electrode Ce4. The electrode gate of the driving transistor T3 is connected to the third capacitor electrode Ce3.

[0040] In some embodiments, the pixel driving circuit further includes a gate electrode connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a first electrode of a driving transistor T3, and a compensation transistor T2 having a first capacitor electrode Ce1, a fourth capacitor electrode Ce4, and a second electrode connected to a second electrode of a data writing transistor T4.

[0041] In some embodiments, the first capacitor electrode Ce1 of the first capacitor C1 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the fourth capacitor electrode Ce4. The second capacitor electrode Ce2 of the first capacitor C1 is connected to a corresponding voltage supply line (e.g., a high-voltage signal line) among a plurality of voltage supply lines Vdd.

[0042] In some embodiments, the fourth capacitor electrode Ce4 of the second capacitor C2 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, and the first capacitor electrode Ce1. The third capacitor electrode Ce3 of the second capacitor C2 is connected to the gate electrode of the drive transistor T3.

[0043] In some embodiments, the pixel driving circuit further includes a light emission control transistor T5 having a gate electrode connected to a corresponding light emission control signal line among a plurality of light emission signal lines em, a first electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a second electrode connected to a first electrode of the driving transistor T3 and a first electrode of the compensating transistor T2.

[0044] In some embodiments, the pixel driving circuit further includes at least one reset transistor. In some embodiments, the pixel driving circuit further includes a first reset transistor T1 having a gate electrode connected to a corresponding first control signal line among a plurality of first control signal lines SL1, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the gate electrode of the driving transistor T3 and the third capacitor electrode Ce3 of the second capacitor C2.

[0045] In some embodiments, the pixel driving circuit further includes a control transistor T8 having a gate electrode connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to a second electrode of a driving transistor T3, and a second electrode connected to the anode of a light-emitting element LE.

[0046] The inventors of this disclosure have found that in the pixel driving circuit shown in Figure 2A, there is a problem of leakage current through the driving transistor T3. For example, the voltage level of the reset signal provided by the corresponding third reset signal line Vint3 is 6V, and the voltage level of the reset signal provided by the corresponding first reset signal line Vint1 is -3V. The reset signal provided by the corresponding third reset signal line Vint3 may flow through the driving transistor T3 and the second reset transistor T7. The inventors of this disclosure have found that by providing a control transistor T8, leakage current through the driving transistor T3 and the second reset transistor T7 can be prevented or avoided.

[0047] In some embodiments, the pixel driving circuit further includes a second reset transistor T7 having a gate electrode connected to a corresponding second control signal line among a plurality of second control signal lines SL2, a first electrode connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a second electrode connected to the second electrode of the control transistor T8 and the anode of the light-emitting element LE.

[0048] In some embodiments, the pixel driving circuit further includes a third reset transistor T6 having a gate electrode connected to a corresponding third control signal line among a plurality of third control signal lines SL3, a first electrode connected to a third reset signal line Vint3, and a second electrode connected to a first electrode of the driving transistor T3, a second electrode of the light emission control transistor T5, and a second electrode of the compensation transistor T2.

[0049] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor T3, the third capacitor electrode Ce3, and the second electrode of the first reset transistor T1. The second node N2 is connected to the first electrode of the driving transistor T3, the second electrode of the light emission control transistor T5, the first electrode of the compensation transistor T2, and the second electrode of the third reset transistor T6. The third node N3 is connected to the second electrode of the data writing transistor T4, the second electrode of the compensation transistor T2, the first capacitor electrode Ce1, and the fourth capacitor electrode Ce4. The fourth node N4 is connected to the second electrode of the control transistor T8, the second electrode of the second reset transistor T7, and the anode of the light-emitting element LE.

[0050] This disclosure may be implemented in a pixel driving circuit having various transistors, including a pixel driving circuit having a p-type transistor, a pixel driving circuit having an n-type transistor, and a pixel driving circuit having one or more p-type transistors and one or more n-type transistors. Referring to Figure 2B, the data writing transistor T4, the compensation transistor T2, the first reset transistor T1, and the third reset transistor T6 are n-type transistors such as metal oxide transistors, while the driving transistor T3, the light emission control transistor T5, the second reset transistor T7, and the control transistor T8 are p-type transistors such as polysilicon transistors. In the case of a p-type transistor, the active control signal (e.g., on control signal) is a low-voltage signal, and the inactive control signal (e.g., off control signal) is a high-voltage signal. In the case of an n-type transistor, the active control signal (e.g., on control signal) is a high-voltage signal, and the inactive control signal (e.g., off control signal) is a low-voltage signal.

[0051] Figure 3 is a timing chart showing the operation of a pixel drive circuit in some embodiments of the present disclosure. Referring to Figures 2A, 2B and 3, over the duration of one frame image, the operation of the pixel drive circuit includes a first phase t1, a second phase t2, a third phase t3, a fourth phase t4, and a fifth phase t5.

[0052] In the first phase t1, an ON control signal is provided to the gate electrode of the first reset transistor T1 via the corresponding first control signal line among the plurality of first control signal lines SL1, turning on the first reset transistor T1. This causes the reset signal from the first reset signal line Vint1 to be transmitted from the first electrode of the first reset transistor T1 to the second electrode of the first reset transistor T1, and further to the third capacitor electrode Ce3 and the gate electrode of the drive transistor T3. Node N1 (gate electrode of drive transistor T3) is reset. The ON control signal is also provided to the gate electrode of the compensation transistor T2 via the corresponding first control signal line among the plurality of first control signal lines SL1, turning on the compensation transistor T2. An ON control signal is provided to the gate electrode of the second reset transistor T7 via the corresponding second control signal line among the multiple second control signal lines SL2, turning on the second reset transistor T7. This causes the reset signal from the corresponding first reset signal line among the multiple first reset signal lines Vint1 to be transmitted from the first electrode of the second reset transistor T7 to the second electrode of the second reset transistor T7, and further transmitted to the anode of the light-emitting element LE. Node N4 (the anode of the light-emitting element LE) is reset. An OFF light emission control signal is provided to the gate electrode of the light-emitting control transistor T5 via each of the multiple light emission control signal lines em, turning off the light-emitting control transistor T5. An OFF control signal is provided to the gate electrode of the third reset transistor T6 via the corresponding third control signal line among the multiple third control signal lines SL3, turning off the third reset transistor T6. A gate OFF signal is provided to the gate electrode of the data writing transistor T4 via the corresponding gate line among the multiple gate lines GL, turning off the data writing transistor T4. Figure 4A shows the current path in phase t1 of an image frame in a pixel driving circuit of several embodiments of the present disclosure. The shaded arrows in Figure 4A indicate the current in phase t1.

[0053] In the second phase t2, an on-control signal is provided to the gate electrode of the first reset transistor T1 via a corresponding first control signal line among the plurality of first control signal lines SL1 to turn on the first reset transistor T1, and is also provided to the gate electrode of the compensation transistor T2 via a corresponding first control signal line among the plurality of first control signal lines SL1 to turn on the compensation transistor T2. An on-control signal is provided to the gate electrode of the second reset transistor T7 via a corresponding second control signal line among the plurality of second control signal lines SL2 to turn on the second reset transistor T7. An on-control signal is provided to the gate electrode of the third reset transistor T6 via a corresponding third control signal line among the plurality of third control signal lines SL3 to turn on the third reset transistor T6, whereby a reset signal from a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is transmitted from the first electrode of the third reset transistor T6 to the second electrode of the third reset transistor T6, and further transmitted to the first electrode of the driving transistor T3, the second electrode of the emission control transistor T5, and the second electrode of the compensation transistor T2. The node N2 (the first electrode of the driving transistor T3) is charged by the voltage of a corresponding third reset signal line among the plurality of third reset signal lines Vint3. In some embodiments, the voltage level of a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is increased (for example, to 6V) to ensure Vgs<Vth, so that the driving transistor T3 is surely maintained in the on state. FIG. 4B shows the current path in the phase t2 of the image frame in the pixel driving circuit according to some embodiments of the present disclosure. The shaded arrows in FIG. 4B indicate the current in the phase t2.

[0054] In the third phase t3 (Vth compensation phase), an off control signal is applied to the gate electrode of the third reset transistor T6 via the corresponding third control line among the multiple third control line SL3, thereby turning off the third reset transistor T6. In the third phase t3, the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the second reset transistor T7, and the control transistor T8 remain ON. The first reset signal is provided via the corresponding first reset signal line among the multiple first reset signal line Vint1, and charges node N2 (the first electrode of the drive transistor T3) via the second reset transistor T7 and the drive transistor T3. When node N2 is charged to the point where Vgs = Vth, the drive transistor T3 is turned OFF. Vgs = VN1 - VN2, where VN1 is the voltage level of node N1 and VN2 is the voltage level of node N2. In the third phase t3, VN1 is the voltage level of the first reset signal provided by the first reset signal line Vint1. Thus, VN2 = VN1 - Vgs = VN1 - Vth, i.e., VN2 = Vint1 - Vth. In the third phase t3, the compensating transistor T2 is turned on, so VN3 = VN2 = VN1 - Vth, where VN3 is the voltage level of node N3. Figure 4C shows the current path in phase t3 of an image frame in a pixel driving circuit of some embodiments of the present disclosure. The shaded arrows in Figure 4C indicate the current in phase t3.

[0055] In phase t4 (data writing phase), an off control signal is provided to the gate electrode of the first reset transistor T1 via the corresponding first control line among the multiple first control line SL1, thereby turning off the first reset transistor T1, and also to the gate electrode of the compensation transistor T2 via the corresponding first control line among the multiple first control line SL1, thereby turning off the compensation transistor T2. An off control signal is provided to the gate electrode of the second reset transistor T7 via the corresponding second control line among the multiple second control line SL2, thereby turning off the second reset transistor T7. A gate on signal is provided to the gate electrode of the data writing transistor T4 via the corresponding gate line among the multiple gate lines GL, thereby turning on the data writing transistor T4, and the data signal provided via the data line DL is transmitted from the first electrode of the data writing transistor T4 to the second electrode of the data writing transistor T4, and further transmitted to node N3. In phase t3, VN1 = the voltage level of the first reset signal provided by the first reset signal line Vint1 (denoted as Vre1). In phase t4, the voltage level at node N3 changes from (Vre1-Vth) to the voltage level of the data signal Vdata. The amount of change is ΔVN3 = Vdata - Vre1 + Vth. The second capacitor C2 induces voltage coupling at node N1 by ΔVN3. Due to the voltage coupling, VN1 changes to (Vre1 + ΔVN3) = (Vre1 + Vdata - Vre1 + Vth) = (Vdata + Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction of the driving transistor T3. Figure 4D shows the current path in phase t4 of an image frame in a pixel driving circuit of several embodiments of the present disclosure. The shaded arrows in Figure 4D indicate the current in phase t4.

[0056] In phase t5 (light emission phase), an ON light emission control signal is provided to the gate electrode of the light emission control transistor T5 via each of the multiple light emission control signal lines em, thereby turning on the light emission control transistor T5. As a result, a voltage supply voltage signal provided via the corresponding voltage supply line among the multiple voltage supply lines Vdd is transmitted from the first electrode of the light emission control transistor T5 to the second electrode of the light emission control transistor T5, further transmitted from the first electrode of the drive transistor T3 to the second electrode of the drive transistor T3, further transmitted from the first electrode of the control transistor T8 to the second electrode of the control transistor T8, and also transmitted to the anode of the light-emitting element LE. The light-emitting element is configured to emit light. Figure 4E shows the current path in phase t5 of an image frame in a pixel driving circuit of several embodiments of the present disclosure. The shaded arrows in Figure 4E indicate the current in phase t5.

[0057] Figure 5A is a schematic diagram showing the configuration of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 5B is a schematic diagram showing the arrangement of the pixel driving circuits in the array substrate shown in Figure 5A. Figures 5A and 5B show portions of an array substrate having two adjacent pixel driving circuits (including PDC1 and PDC2).

[0058] Figure 5C is a schematic diagram showing the configuration of the first semiconductor material layer in the array substrate shown in Figure 5A. Figure 5D is a schematic diagram showing the configuration of the first gate metal layer in the array substrate shown in Figure 5A. Figure 5E is a schematic diagram showing the configuration of the second gate metal layer in the array substrate shown in Figure 5A. Figure 5F is a schematic diagram showing vias penetrating the first interlayer dielectric layer in the array substrate shown in Figure 5A. Figure 5G is a schematic diagram showing the configuration of the second semiconductor material layer in the array substrate shown in Figure 5A. Figure 5H is a schematic diagram showing vias penetrating the second interlayer dielectric layer in the array substrate shown in Figure 5A. Figure 5I is a schematic diagram showing the configuration of the third gate metal layer in the array substrate shown in Figure 5A. Figure 5J is a schematic diagram showing vias penetrating the passivation layer in the array substrate shown in Figure 5A. Figure 5K is a schematic diagram showing the configuration of the first signal line layer in the array substrate shown in Figure 5A. Figure 5L is a schematic diagram showing vias penetrating the first planarization layer in the array substrate shown in Figure 5A. Figure 5M is a schematic diagram showing the configuration of the second signal line layer in the array substrate shown in Figure 5A. Figure 5N is a schematic diagram showing vias penetrating the second planarization layer in the array substrate shown in Figure 5A. Figure 5O is a schematic diagram showing the configuration of the anode layer in the array substrate shown in Figure 5A. Figure 6A is a cross-sectional view along the line A-A' in Figure 5A. Figure 6B is a cross-sectional view along the line B-B' in Figure 5A. Figure 6C is a cross-sectional view along the line C-C' in Figure 5A. Figure 6D is a cross-sectional view along the line D-D' in Figure 5A.

[0059] Referring to Figures 5A to 5O and Figures 6A to 6D, in some embodiments, the array substrate comprises a base substrate BS, a buffer layer BUF located on the base substrate BS, a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the base substrate BS, a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the base substrate BS, a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1, an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI, a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1, a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN, and a second semiconductor material layer SML1 located on the side of the first interlayer dielectric layer ILD1 away from the second gate metal layer Gate2. 2, a second interlayer dielectric layer ILD2 located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1, a third gate metal layer Gate3 located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2, a passivation layer PVX located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2, and a passivation layer PVX located on the side of the passivation layer PVX away from the third gate metal layer Gate3 It includes a first signal line layer SD1, a first flattening layer PLN1 located on the side of the first signal line layer SD1 away from the passivation layer PVX, a second signal line layer SD2 located on the side of the first flattening layer PLN1 away from the first signal line layer SD1, a second flattening layer PLN2 located on the side of the second signal line layer SD2 away from the first flattening layer PLN1, and an anode layer ADL located on the side of the second flattening layer PLN2 away from the second signal line layer SD2.

[0060] Referring to Figures 2B, 5A, 5C, and 6A to 6D, in some embodiments, the first semiconductor material layer SML1 includes at least the active layers of a plurality of transistors in the pixel driving circuit (including a driving transistor T3, a light emission control transistor T5, a second reset transistor T7, and a control transistor T8). Optionally, the first semiconductor material layer SML1 may further include at least corresponding portions of the first electrodes of the plurality of transistors in the pixel driving circuit (including a driving transistor T3, a light emission control transistor T5, a second reset transistor T7, and a control transistor T8). Optionally, the first semiconductor material layer SML1 may further include at least corresponding portions of the second electrodes of the plurality of transistors in the pixel driving circuit (including a driving transistor T3, a light emission control transistor T5, a second reset transistor T7, and a control transistor T8). Optionally, the first semiconductor material layer SML1 may include the active layers of multiple transistors in the pixel driving circuit (including the driving transistor T3, the light emission control transistor T5, the second reset transistor T7, and the control transistor T8), the first electrode, and the second electrode. Various suitable semiconductor materials may be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials such as polysilicon, single-crystal silicon, and amorphous silicon.

[0061] In Figure 5C, the pixel driving circuit corresponding to PDC2 in Figure 5B is given a reference number, and the components of each of the multiple transistors (T3, T5, T7, and T8) in the pixel driving circuit are shown. For example, the driving transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The light emission control transistor T5 includes an active layer ACT5, a first electrode S5, and a second electrode D5. The second reset transistor T7 includes an active layer ACT7, a first electrode S7, and a second electrode D7. The control transistor T8 includes an active layer ACT8, a first electrode S8, and a second electrode D8.

[0062] Optionally, the active layers (ACT3, ACT5, ACT7, and ACT8) of each transistor (T3, T5, T7, and T8), the first electrodes (S3, S5, S7, and S8), and the second electrodes (D3, D5, D7, and D8) may be located on the same layer.

[0063] In some embodiments, the active layers (ACT3, ACT7, and ACT8), at least a portion of the first electrodes (S3, S7, and S8), and at least a portion of the second electrodes (D3, D7, and D8) of multiple transistors (T3, T7, and T8) in a pixel driving circuit are part of an integrated structure. Optionally, in the same pixel driving circuit, the portion of the light emission control transistor T5 located in the first semiconductor material layer (ACT5, S5, D5) may be separated from the integrated structure (T3, T7, and T8).

[0064] In some embodiments, the active layers of two adjacent light emission control transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) and at least a portion of the first electrode are part of a single integrated structure. Optionally, the active layers of two adjacent light emission control transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row), at least a portion of the first electrode, and at least a portion of the second electrode may be part of a single integrated structure. Optionally, the first electrodes of two adjacent light emission control transistors in two adjacent pixel drive circuits in the same row may be directly connected to each other.

[0065] Referring to Figures 2B, 5A, 5D and 6A to 6D, in some embodiments, the first gate metal layer Gate1 includes a plurality of light emission control lines em, a plurality of second control lines SL2, at least a portion of a plurality of third control lines (e.g., a corresponding third control line first branch line SL3-1), a second capacitor electrode Ce2 of the first capacitor C1, and a third capacitor electrode Ce3 of the second capacitor C2.

[0066] Various suitable electrode materials and various suitable manufacturing methods may be used to fabricate the first gate metal layer Gate1. For example, a conductive material may be deposited on a substrate by plasma-enhanced chemical vapor deposition (PECVD) and then patterned. Examples of conductive materials suitable for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, and copper-molybdenum-aluminum alloy. Optionally, in the pixel driving circuit, a plurality of light emission control lines em, a plurality of second control lines SL2, at least a portion of a plurality of third control lines (e.g., a corresponding third control line first branch line SL3-1), the second capacitor electrode Ce2 of the first capacitor C1, and the third capacitor electrode Ce3 of the second capacitor C2 may be located in the same layer.

[0067] In this specification, "same layer" refers to the relationship between layers formed simultaneously in the same step. For example, multiple light-emitting control signals em and a second capacitor electrode Ce2 are located in the same layer when they are formed as a result of one or more steps of the same patterning process performed in the same material layer. As another example, multiple light-emitting control signals em and a second capacitor electrode Ce2 can be formed in the same layer by simultaneously performing the steps of forming multiple light-emitting control signals em and forming the second capacitor electrode Ce2. "Same layer" does not necessarily mean that the thickness or height of the layers in a cross-sectional view is the same.

[0068] Referring to Figure 5D, the multiple second capacitor electrodes in the multiple pixel driving circuits are connected to each other and form part of an integrated structure. By connecting the second capacitor electrodes to each other, the second capacitor electrodes are electrically connected to the multiple voltage supply lines Vdd, thereby reducing the resistance of the multiple voltage supply lines Vdd. The inventors of this disclosure have found that this configuration improves the display uniformity of the array substrate.

[0069] Referring to Figures 2B, 5A, 5E, and 6A to 6D, in some embodiments, the second gate metal layer Gate 2 includes at least a portion of a plurality of gate lines (e.g., corresponding gate line first branch line GL-1), at least a portion of a plurality of first control signal lines (e.g., corresponding first control signal line first branch line SL1-1), at least a portion of a plurality of third control signal lines (e.g., corresponding third control signal line second branch line SL3-2), the first capacitor electrode Ce1 of the first capacitor C1, and the fourth capacitor electrode Ce4 of the second capacitor C2. Various suitable electrode materials and various suitable manufacturing methods may be used to fabricate the second gate metal layer Gate 2. For example, a conductive material may be deposited on a substrate by plasma-enhanced chemical vapor deposition (PECVD) and then patterned. Examples of conductive materials suitable for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, and copper-molybdenum-aluminum alloy. Optionally, at least a portion of a plurality of gate lines (e.g., the corresponding first gate line branch line GL-1), at least a portion of a plurality of first control signal lines (e.g., the corresponding first control signal line first branch line SL1-1), at least a portion of a plurality of third control signal lines (e.g., the corresponding third control signal line second branch line SL3-2), the first capacitor electrode Ce1 of the first capacitor C1, and the fourth capacitor electrode Ce4 of the second capacitor C2 may be located on the same layer in the pixel driving circuit.

[0070] Optionally, the first capacitor electrode Ce1 of the first capacitor C1 and the fourth capacitor electrode Ce4 of the second capacitor C2 in the pixel driving circuit may be part of an integrated structure.

[0071] Figure 5F shows vias that penetrate the first interlayer dielectric layer ILD1.

[0072] Referring to Figures 2B, 5A, 5G, and 6A to 6D, in some embodiments, the second semiconductor material layer SML2 includes at least the active layer ACT1 of the first reset transistor T1, the active layer ACT2 of the compensation transistor T2, the active layer ACT4 of the data writing transistor T4, and the active layer ACT6 of the third reset transistor T6 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 may further include at least a portion of the first electrode S1 of the first reset transistor T1, at least a portion of the first electrode S2 of the compensation transistor T2, at least a portion of the first electrode S4 of the data writing transistor T4, and at least a portion of the first electrode S6 of the third reset transistor T6 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 may further include at least a portion of the second electrode D1 of the first reset transistor T1, at least a portion of the second electrode D2 of the compensation transistor T2, at least a portion of the second electrode D4 of the data writing transistor T4, and at least a portion of the second electrode D6 of the third reset transistor T6 in the pixel driving circuit. Optionally, the second semiconductor material layer SML2 may further include the active layer ACT1, first electrode S1 and second electrode D1 of the first reset transistor T1, the active layer ACT2, first electrode S2 and second electrode D2 of the compensation transistor T2, the active layer ACT4, first electrode S4 and second electrode D4 of the data writing transistor T4, and the active layer ACT6, first electrode S6 and second electrode D6 of the third reset transistor T6 in the pixel driving circuit. In this array substrate, at least the active layer ACT1 of the first reset transistor T1, the active layer ACT2 of the compensation transistor T2, the active layer ACT4 of the data writing transistor T4, and the active layer ACT6 of the third reset transistor T6 are located in layers different from at least the active layers of the other transistors in the pixel driving circuit. Various suitable semiconductor materials may be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride semiconductor materials (e.g., zinc oxynitride).

[0073] In Figure 5G, the pixel driving circuit corresponding to PDC2 in Figure 5B is given a reference number, and the components of each of the multiple transistors (T1, T2, T4, and T6) in the pixel driving circuit are shown. For example, the first reset transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The compensation transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2. The data writing transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The third reset transistor T6 includes an active layer ACT6, a first electrode S6, and a second electrode D6.

[0074] In some embodiments, the active layers (ACT2, ACT4, and ACT6) of a plurality of transistors (T2, T4, and T6) in a pixel driving circuit, at least a portion of the first electrodes (S2, S4, and S6), and at least a portion of the second electrodes (D2, D4, and D6) are part of an integrated structure. Optionally, in the same pixel driving circuit, at least a portion of the first reset transistor T1 located in the second semiconductor material layer (ACT1, S1, D1) may be separated from the integrated structure (T2, T4, and T6).

[0075] In some embodiments, the active layers of two adjacent third reset transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) and at least a portion of the first electrode are part of an integrated structure. Optionally, the active layers of two adjacent third reset transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row), at least a portion of the first electrode, and at least a portion of the second electrode may be part of an integrated structure. Optionally, in the integrated structure, the first electrodes of two adjacent third reset transistors in two adjacent pixel drive circuits in the same row may be directly connected to each other.

[0076] In some embodiments, the active layers, at least a portion of the first electrode and at least a portion of the second electrode of two adjacent third reset transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row), the active layers, at least a portion of the first electrode and at least a portion of the second electrode of two adjacent compensation transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row), and the active layers, at least a portion of the first electrode and at least a portion of the second electrode of two adjacent data write transistors in two adjacent pixel drive circuits (e.g., two adjacent pixel drive circuits in the same row) are part of an integrated structure. Optionally, in the integrated structure, the first electrodes of the two adjacent third reset transistors in two adjacent pixel drive circuits in the same row may be directly connected to each other.

[0077] Figure 5H shows vias that penetrate the second interlayer dielectric layer ILD2.

[0078] Referring to Figures 2B, 5A, 5I, and 6A to 6D, in some embodiments, the third gate metal layer Gate 3 includes at least a portion of a plurality of gate lines (e.g., corresponding gate line second branch line GL-2), at least a portion of a plurality of first control signal lines (e.g., corresponding first control signal second branch line SL1-2), at least a portion of a plurality of third control signal lines (e.g., corresponding third control signal third branch line SL3-3), and a plurality of second reset signal lines Vint2 and a plurality of third reset signal lines Vint3. Various suitable electrode materials and various suitable manufacturing methods may be used to fabricate the third gate metal layer Gate 3. For example, a conductive material may be deposited on a substrate by plasma-enhanced chemical vapor deposition (PECVD) and then patterned. Examples of conductive materials suitable for fabricating the third gate metal layer (Gate 3) include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, and copper-molybdenum-aluminum alloys.

[0079] Figure 5J shows vias that penetrate the passivation layer PVX.

[0080] Referring to Figures 2B, 5A, 5K, and 6A to 6D, in some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines Vint1, a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a data connection line Cld, a voltage supply connection line Clv, a reset signal connection line Cli, and a relay electrode RE.

[0081] Various suitable conductive materials and various suitable manufacturing methods may be used to fabricate the first signal line layer. For example, the conductive material may be deposited on a substrate by plasma-enhanced chemical vapor deposition (PECVD) and then patterned. Examples of conductive materials suitable for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, and copper-molybdenum-aluminum alloy. In some embodiments, the first signal line layer includes a plurality of stacked sublayers. As an example, the first signal line layer includes a stacked titanium / aluminum / titanium multilayer structure. As another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer structure. Optionally, multiple first reset signal lines Vint1, a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a data connection line Cld, a voltage supply connection line Clv, a reset signal connection line Cli, and a relay electrode RE may be located on the same layer.

[0082] In some embodiments, a first node connection line Cln1 connects multiple components of the pixel driving circuit to node N1. Referring to Figure 6A, in the pixel driving circuit, the first node connection line Cln1 is connected via a first via v1 to the third capacitor electrode Ce3 of a second capacitor C2 and via a second via v2 to a first reset transistor T1 (e.g., the second electrode D1 of the first reset transistor T1). Optionally, the first node connection line Cln1 may correspond to node N1 shown in Figure 2B. As an example, the first via v1 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN. As another example, the second via v2 penetrates the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0083] In some embodiments, a second node connection line Cln2 connects multiple components of the pixel driving circuit to node N2. Referring to Figure 6B, in the pixel driving circuit, the second node connection line Cln2 is connected to the second electrode D5 of the light emission control transistor T5 via a third via v3, to the first electrode S3 of the driving transistor T3 via a fourth via v4, and to the second electrode D6 of the third reset transistor T6 via a fifth via v5. Optionally, the second node connection line Cln2 may correspond to node N2 as shown in Figure 2B. As an example, the third via v3 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. As another example, the fourth via v4 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. As yet another example, the fifth via v5 penetrates the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0084] In some embodiments, a third node connection line Cln3 connects multiple components of the pixel driver circuit to node N3. Referring to Figure 6C, in the pixel driver circuit, the third node connection line Cln3 is connected via a sixth via v6 to the second electrodes of the compensation transistor T2 and the data writing transistor T4, and via a seventh via v7 to the first capacitor electrode Ce1 of the first capacitor C1 and / or the fourth capacitor electrode Ce4 of the second capacitor C2. Optionally, the third node connection line Cln3 may correspond to node N3 as shown in Figure 2B. As an example, the sixth via v6 penetrates the passivation layer PVX and the second interlayer dielectric layer ILD2. As another example, the seventh via v7 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1.

[0085] In some embodiments, voltage supply connection lines Clv connect multiple components of a pixel driving circuit to corresponding voltage supply lines among multiple voltage supply lines Vdd. Referring to Figure 6D, in the pixel driving circuit, corresponding voltage supply lines among multiple voltage supply lines Vdd are connected to voltage supply connection line Clv via an eighth via v8. Voltage supply connection line Clv is connected to the second electrode S5 of the light emission control transistor T5 via a ninth via v9 and to the second capacitor electrode Ce2 of the first capacitor C1 via a tenth via v10. As an example, the eighth via v8 penetrates the first planarization layer PLN1. As another example, the ninth via v9 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. As another example, the tenth via v10 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN.

[0086] In some embodiments, referring to Figure 6A, a corresponding first reset signal line among a plurality of first reset signal lines Vint1 is connected to the first electrode S1 of the first reset transistor T1 via an eleventh via v11. For example, the eleventh via v11 penetrates the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0087] Figure 7A is a schematic diagram showing the configuration of the second semiconductor material layer and the first signal line layer in the array substrate shown in Figure 5A. In some embodiments, referring to Figure 7A, the orthographic projection of the third node connection line Cln3 onto the base substrate BS overlaps at least partially (e.g., at least 5%, at least 10%, at least 15%, at least 20%, at least 25%, at least 30%, at least 35%, at least 40%, at least 45%, at least 50%, at least 55%, at least 60%, at least 65%, at least 70%, at least 75%, at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) with the orthographic projection of the active layer ACT2 of the compensating transistor T2 onto the base substrate. Optionally, the third node connection line Cln3 may extend in a direction substantially parallel to the extending direction of the active layer ACT2 of the compensating transistor T2. Optionally, the orthographic projection of the third node connection line Cln3 onto the base substrate BS may at least partially overlap with the orthographic projection of the first electrode S2 of the compensating transistor T2 onto the base substrate. Optionally, the orthographic projection of the third node connection line Cln3 onto the base substrate BS may at least partially overlap with the orthographic projection of the second electrode D2 of the compensating transistor T2 onto the base substrate.

[0088] Referring to Figures 5K and 6D, in some embodiments, a voltage supply connection line Clv connects multiple components of two adjacent pixel drive circuits in the same row to corresponding voltage supply lines among multiple voltage supply lines Vdd. In some embodiments, corresponding voltage supply lines among multiple voltage supply lines Vdd are connected to the voltage supply connection line Clv, for example, via an eighth via v8. The voltage supply connection line Clv is connected via a ninth via v9 to the first electrodes of two adjacent light emission control transistors of two adjacent pixel drive circuits in the same row. The first electrodes of the two adjacent light emission control transistors of two adjacent pixel drive circuits in the same row are part of a single structure. Each voltage supply connection line Clv is connected via a different via to the second capacitor electrode of the first capacitor of the two adjacent pixel drive circuits in the same row.

[0089] Figure 7B is a schematic diagram showing the configuration of a reset signal line network in some embodiments of the present disclosure. Referring to Figure 7B, in some embodiments, the array substrate includes an interconnected reset signal line network. In some embodiments, the interconnected reset signal line network includes a plurality of first reset signal lines Vint1 and a plurality of second reset signal lines Vint2 that are connected to each other. Optionally, the plurality of first reset signal lines Vint1 may extend in a direction substantially parallel to a first direction DR1. Optionally, the plurality of second reset signal lines Vint2 may extend in a direction substantially parallel to a second direction DR2. Optionally, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 may be located in different layers. For example, the plurality of first reset signal lines Vint1 may be located in a first signal line layer, and the plurality of second reset signal lines Vint2 may be located in a third gate metal layer. In some embodiments, each of the multiple first reset signal lines Vint1 is connected to one or more of the multiple second reset signal lines Vint2. In some embodiments, each of the multiple second reset signal lines Vint2 is connected to one or more of the multiple first reset signal lines Vint1 to form an interconnected reset signal line network.

[0090] Referring to Figure 7B, in some embodiments, each of the multiple first reset signal lines Vint1 includes a plurality of loops LP arranged substantially parallel to the first direction DR1. Each of the loops LP is connected to the first electrode of two adjacent first reset transistors of two adjacent pixel drive circuits in the same row.

[0091] Referring to Figures 5A, 5G, 5I, and 5K, in some embodiments, the reset signal connection line Cli in the first signal line layer is connected to the corresponding third reset signal line among a plurality of third reset signal lines Vint3 in the third gate metal layer, and also to the first electrode S6 of the third reset transistor T6 in the second semiconductor material layer. Optionally, the reset signal connection line Cli may be connected to the first electrodes of two adjacent third reset transistors in two adjacent pixel drive circuits in the same row.

[0092] Figure 5L shows vias that penetrate the first flattening layer PLN1.

[0093] Referring to Figures 2B, 5A, 5M, and 6A to 6D, in some embodiments, the second signal line layer SD2 includes a plurality of voltage supply lines Vdd, a plurality of data lines DL, and an anode connection pad ACP. Various suitable conductive materials and various suitable manufacturing methods may be used to fabricate the second signal line layer. For example, the conductive material may be deposited on a substrate by plasma-enhanced chemical vapor deposition (PECVD) and then patterned. Examples of conductive materials suitable for fabricating the second signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloys, copper-molybdenum alloys, molybdenum-aluminum alloys, aluminum-chromium alloys, copper-chromium alloys, molybdenum-chromium alloys, and copper-molybdenum-aluminum alloys. In some embodiments, the second signal line layer includes a plurality of stacked sublayers. As an example, the second signal line layer includes a stacked titanium / aluminum / titanium multilayer configuration. As another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multilayer configuration. Optionally, multiple voltage supply lines Vdd, multiple data lines DL, and anode connection pad ACP may be located on the same layer.

[0094] Referring to Figures 5A, 5G, 5K, and 5M, in some embodiments, each data line among a plurality of data lines DL in the second signal line layer is connected to a data connection line Cld in the first signal line layer, and the data connection line Cld is connected to a first electrode S4 located in the second semiconductor material layer of the data writing transistor T4.

[0095] In some embodiments, each data line among a plurality of data lines DL includes a plurality of branch lines BL provided in a direction substantially parallel to a first direction DR1. Each branch line among the plurality of branch lines BL extends away from the body MB of the corresponding data line. In some embodiments, each branch line among the plurality of branch lines BL is connected to a data connection line Cld in the first signal line layer. In some embodiments, the body MB of the corresponding data line extends in a direction substantially parallel to the first direction DR1, and each branch line extends in a direction substantially parallel to a second direction DR. The second direction DR2 is different from the first direction DR1. The second direction DR2 intersects the first direction DR1.

[0096] Referring to Figures 5A, 5C, 5K, and 5M, in some embodiments, an anode connection pad ACP in the second signal line layer is connected to a relay electrode RE in the first signal line layer, and the relay electrode RE is connected to a second reset transistor T7 and the second electrode of a control transistor T8. The anode connection pad ACP is connected to a corresponding anode among a plurality of anodes.

[0097] Figure 5N shows the vias that penetrate the second planarization layer PLN2.

[0098] Referring to Figures 5A, 5O and 6A to 6D, in some embodiments, the anode layer ADL includes multiple anodes AD.

[0099] Figure 7C is a schematic diagram showing the configuration of a voltage supply network in some embodiments of the present disclosure. Referring to Figure 7C, in some embodiments, the array substrate includes an interconnect voltage supply network. In some embodiments, the interconnect voltage supply network includes a plurality of voltage supply lines Vdd, a plurality of second capacitor electrode lines Ce2L, and a plurality of voltage supply connection lines Clvs. Optionally, the plurality of voltage supply lines Vdd may extend in a direction substantially parallel to a first direction DR1. Optionally, the plurality of second capacitor electrode lines Ce2L may extend in a direction substantially parallel to a second direction DR2. Each of the plurality of second capacitor electrode lines Ce2L includes a second capacitor electrode of a pixel driving circuit in the same row. Each of the plurality of voltage supply connection lines Clvs connects a corresponding voltage supply line of the plurality of voltage supply lines Vdd to a corresponding second capacitor electrode line of the plurality of second capacitor electrode lines Ce2L. Optionally, the multiple voltage supply lines Vdd, the multiple second capacitor electrode lines Ce2L, and the multiple voltage supply connection lines Clvs may be located in different layers. For example, the multiple second capacitor electrode lines Ce2L are located in the first gate metal layer, the multiple voltage supply connection lines Clvs are located in the first signal line layer, and the multiple voltage supply lines Vdd are located in the second signal line layer. In some embodiments, each of the multiple voltage supply lines Vdd is connected to one or more of the multiple second capacitor electrode lines Ce2L via one or more of the multiple voltage supply connection lines Clvs. In some embodiments, each of the multiple second capacitor electrode lines Ce2L is connected to one or more of the multiple voltage supply lines Vdd via one or more of the multiple voltage supply connection lines Clvs.

[0100] Referring to Figure 5A, in some embodiments, the array substrate includes a transparent region TR where no conductive components of the pixel driving circuit are present. Referring to Figure 7B, corresponding loops of multiple loops of each first reset signal line surround the transparent region TR. Accessories may be attached to the transparent region TR. An example of an accessory is a photoelectric sensor.

[0101] Referring to Figure 5M, each of the multiple data lines DL includes a body MB and multiple branch lines BL extending away from the body MB. The body MB includes multiple alternately connected first segments SG1 and multiple second segments SG2. Figure 7D is a schematic diagram showing the configuration of a second signal line layer in four adjacent pixel driver circuits in the same row of an array substrate in some embodiments of the present disclosure. Referring to Figures 5M and 7D, in some embodiments, a transparent region TR is substantially surrounded by second segments of two adjacent data lines configured to provide data signals to two adjacent pixel driver circuits in the same row. In some embodiments, the first segment SG1 is substantially linear, and the second segment SG2 is a curved segment that curves and surrounds the transparent region TR. In some embodiments, a virtual extension of the first segment SG1 penetrates the transparent region TR.

[0102] Figure 8A is a schematic diagram showing the configuration of a pixel driving circuit in an array substrate of several embodiments according to the present disclosure. Figure 8B is a schematic diagram showing the arrangement of the pixel driving circuit in the array substrate shown in Figure 8A. Figure 8C is a schematic diagram showing the configuration of a first semiconductor material layer in the array substrate shown in Figure 8A. Figure 8D is a schematic diagram showing the configuration of a first gate metal layer in the array substrate shown in Figure 8A. Figure 8E is a schematic diagram showing the configuration of a second gate metal layer in the array substrate shown in Figure 8A. Figure 8F is a schematic diagram showing vias penetrating the first interlayer dielectric layer in the array substrate shown in Figure 8A. Figure 8G is a schematic diagram showing the configuration of a second semiconductor material layer in the array substrate shown in Figure 8A. Figure 8H is a schematic diagram showing vias penetrating the second interlayer dielectric layer in the array substrate shown in Figure 8A. Figure 8I is a schematic diagram showing the configuration of a third gate metal layer in the array substrate shown in Figure 8A. Figure 8J is a schematic diagram showing vias penetrating the passivation layer in the array substrate shown in Figure 8A. Figure 8K is a schematic diagram showing the configuration of the first signal line layer in the array substrate shown in Figure 8A. Figure 8L is a schematic diagram showing vias penetrating the first planarization layer in the array substrate shown in Figure 8A. Figure 8M is a schematic diagram showing the configuration of the second signal line layer in the array substrate shown in Figure 8A. Figure 8N is a schematic diagram showing vias penetrating the second planarization layer in the array substrate shown in Figure 8A. Figure 8O is a schematic diagram showing the configuration of the anode layer in the array substrate shown in Figure 8A.

[0103] The array substrates shown in Figures 8A to 8O differ from those shown in Figures 5A to 5O in that the main body MB of each data line extends substantially linearly in a direction substantially parallel to the first direction DR1. Optionally, the array substrates shown in Figures 8A to 8O do not need to include a transparent region TR.

[0104] The inventors of this disclosure have found that the presence of resistance and parasitic capacitance in signal lines causes a resistive-capacitive delay in the associated array substrate. This resistive-capacitive delay becomes particularly pronounced as the signal transmission distance of the signal line increases. The inventors of this disclosure have found that control signals (e.g., gate scan signals) output from a scanning circuit to sub-pixel rows far from the integrated circuit have a longer delay than control signals output to sub-pixel rows closer to the integrated circuit. The inventors of this disclosure have found that this is at least in part due to a resistive-capacitive delay in the signal line transmitting signals (e.g., clock signals) from the integrated circuit to a multi-stage scanning circuit.

[0105] The inventors of this disclosure have found that in a related array substrate, the falling edge time of a signal changes with changes in the signal transmission distance of a signal line. The change in falling edge time becomes particularly pronounced as the signal transmission distance of the signal line increases. The inventors of this disclosure have found that the falling edge time of the gate scan signal output from the scanning circuit to a subpixel far from the scanning circuit is longer than that of the control signal output to a subpixel close to the scanning circuit. When a gate-off scan signal is output from the scanning circuit, due to the change in falling edge time, the voltage at node N1 in the pixel driving circuit far from the scanning circuit is lowered to be smaller than the voltage at node N1 in the pixel driving circuit close to the scanning circuit. As a result, the display uniformity of the subpixels far from the scanning circuit and the subpixels close to the scanning circuit is inferior.

[0106] The inventors of this disclosure have surprisingly and unexpectedly found that the array substrate according to this disclosure reduces the problem of display unevenness. The inventors of this disclosure have found that the problem of display unevenness can be eliminated by reducing the parasitic capacitance between the corresponding gate line and the N1 node. Figure 9 is a schematic diagram showing the layout of the corresponding gate lines to the first node connection line in the array substrate shown in Figure 5A or Figure 8A. Referring to Figure 9, the inventors of this disclosure have found that the problem of display unevenness can be improved by reducing the parasitic capacitance between the corresponding gate line among the multiple gate lines GL and the first node connection line Cln1.

[0107] Referring to Figure 9, in some embodiments, the orthographic projection of the corresponding gate line onto the base substrate does not substantially overlap with the orthographic projection of the first node connection line Cln1 onto the base substrate (e.g., at least 80% overlap, at least 90% overlap, at least 95% overlap, at least 99% overlap, or no overlap at all). Parasitic capacitance between the corresponding gate line among the multiple gate lines GL and the first node connection line Cln1 can be minimized. The first node connection line Cln1 corresponds at least partially to node N1.

[0108] In some embodiments, the orthographic projection of the corresponding gate line onto the base substrate and the orthographic projection of the first node connection line Cln1 onto the base substrate are separated by the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate. Optionally, the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate may not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all), and may not substantially overlap with the orthographic projection of the first node connection line Cln1 onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all). By orthogonally projecting the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate, the orthogonal projection of the corresponding gate line onto the base substrate and the orthogonal projection of the first node connection line Cln1 onto the base substrate are separated, thereby further minimizing the parasitic capacitance (e.g., lateral parasitic capacitance) between the corresponding gate line among the multiple gate lines GL and the node N1.

[0109] In some embodiments, the orthographic projection of the corresponding gate line onto the base substrate and the orthographic projection of the third capacitor electrode Ce3 of the second capacitor C2 onto the base substrate are separated by the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate. Optionally, the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate may not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all), and may not substantially overlap with the orthographic projection of the third capacitor electrode Ce3 of the second capacitor C2 onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all).

[0110] The array substrate according to this disclosure is compared to an array substrate related to which the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate and the orthographic projection of the corresponding gate line onto the base substrate are separated by the orthographic projection of the third capacitor electrode Ce3 onto the base substrate (thus bringing node N1 closer to the corresponding gate line). The parasitic capacitance between the corresponding gate line and node N1 is 1.33f in the array substrate according to this disclosure and 2.72f in the array substrate related to this disclosure. The voltage difference between the first node located in the pixel drive circuit far from the scanning circuit and the first node located in the pixel drive circuit close to the scanning circuit is 0.08V in the array substrate according to this disclosure and 0.16V in the array substrate related to this disclosure. The array substrate according to this disclosure shows a significant improvement in display uniformity.

[0111] In some embodiments, a first node connection line Cln1 is connected to a second electrode D1 of a first reset transistor T1 via a second via v2. The inventors of this disclosure have found that because the first reset transistor T1 is connected to the first node connection line Cln1, the parasitic capacitance between the first reset transistor T1 and the corresponding gate line is minimized, thereby further improving the problem of display unevenness.

[0112] In some embodiments, the orthographic projection of the corresponding gate line onto the base substrate does not substantially overlap with the orthographic projection of the second electrode D1 of the first reset transistor T1 onto the base substrate (e.g., at least 80% overlap, at least 90% overlap, at least 95% overlap, at least 99% overlap, or no overlap at all). Optionally, the orthographic projection of the corresponding gate line onto the base substrate may not substantially overlap with the orthographic projection of the active layer ACT1 and the second electrode D1 of the first reset transistor T1 onto the base substrate (e.g., at least 80% overlap, at least 90% overlap, at least 95% overlap, at least 99% overlap, or no overlap at all). Optionally, the orthographic projection of the corresponding gate line onto the base substrate may not substantially overlap with the orthographic projection of the first electrode S1, active layer ACT1 and the second electrode D1 of the first reset transistor T1 onto the base substrate (e.g., at least 80% overlap, at least 90% overlap, at least 95% overlap, at least 99% overlap, or no overlap at all).

[0113] In some embodiments, the second electrode D1 of the first reset transistor T1 intersects with the second capacitor electrode Ce2. Optionally, the orthographic projection of the second electrode D1 of the first reset transistor T1 onto the base substrate may partially overlap with the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate.

[0114] In some embodiments, the orthographic projection of a corresponding gate line onto the base substrate and the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate are separated by the orthographic projection of the corresponding light-emitting control line among a plurality of light-emitting control lines em onto the base substrate. Optionally, the orthographic projection of each light-emitting control line among a plurality of light-emitting control lines em onto the base substrate may not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all), and may not substantially overlap with the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all).

[0115] In some embodiments, the orthographic projection of a corresponding gate line onto the base substrate and the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate are separated by the orthographic projection of the corresponding first control signal line among a plurality of first control signal lines SL1 onto the base substrate. Optionally, the orthographic projection of each first control signal line among a plurality of first control signal lines SL1 onto the base substrate may not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all), and may not substantially overlap with the orthographic projection of the second capacitor electrode Ce2 of the first capacitor C1 onto the base substrate (e.g., not overlapping by at least 80%, not overlapping by at least 90%, not overlapping by at least 95%, not overlapping by at least 99%, or not overlapping at all).

[0116] As described above with reference to Figure 7C, in some embodiments, the array substrate includes a plurality of second capacitor electrode lines Ce2L as part of an interconnection voltage supply network. The plurality of second capacitor electrode lines Ce2L extend in a direction substantially parallel to the second direction DR2. Each of the plurality of second capacitor electrode lines Ce2L includes a second capacitor electrode connected to each other in a pixel driving circuit in the same row.

[0117] Figure 10 is a schematic diagram showing the layout of the corresponding second capacitor electrode lines to the second node connection lines in the array substrate shown in Figure 5A or Figure 8A. Referring to Figures 10 and 6B, the connection line CL connecting two adjacent second capacitor electrodes of two adjacent pixel drive circuits in the same row separates the second electrode D5 of the light emission control transistor T5 from the second electrode D6 of the third reset transistor T6, and separates the second electrode D5 of the light emission control transistor T5 from the first electrode S3 of the drive transistor T3. Since each second capacitor electrode line is located in the first gate metal layer, the second node connection line Cln2 cannot be located in the first gate metal layer.

[0118] In some embodiments, each second capacitor electrode wire is located in the first gate metal layer, the second electrode D5 of the light emission control transistor T5 and the first electrode S3 of the drive transistor T3 are located in the first semiconductor material layer, and the second electrode D6 of the third reset transistor T6 is located in the second semiconductor material layer. In some embodiments, in the pixel drive circuit, the second node connection wire Cln2 is connected to the second electrode D5 of the light emission control transistor T5 via a third via v3, to the first electrode S3 of the drive transistor T3 via a fourth via v4, and to the second electrode D6 of the third reset transistor T6 via a fifth via v5. As an example, the third via v3 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. As another example, the fourth via v4 penetrates the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the insulating layer IN, and the gate insulating layer GI. As yet another example, the fifth via v5 penetrates the passivation layer PVX and the second interlayer dielectric layer ILD2.

[0119] In some embodiments, the second node connection line Cln2 intersects the corresponding second capacitor electrode line. Optionally, the orthographic projection of the second node connection line Cln2 onto the base substrate may partially overlap the orthographic projection of the corresponding second capacitor electrode line onto the base substrate.

[0120] Referring to Figures 5A to 5O, Figures 6A to 6D, and Figures 8A to 8O, in some embodiments, the corresponding layers of a first pixel driver circuit (e.g., PDC1 in Figure 5B) and the corresponding layers of a second pixel driver circuit (e.g., PDC2 in Figure 5B), which are directly adjacent to each other and located in the same row, are substantially mirror-symmetric to each other with respect to a plane that is perpendicular to the main surface of the array substrate and substantially parallel to the plurality of data lines.

[0121] In this specification, “corresponding layers of the first pixel drive circuit and corresponding layers of the second pixel drive circuit” is not intended to include layers that are not part of the pixel drive circuit. For example, “corresponding layers of the first pixel drive circuit and corresponding layers of the second pixel drive circuit” does not include an anode layer or a pixel definition layer. In some embodiments, “corresponding layers of the first pixel drive circuit and corresponding layers of the second pixel drive circuit” does not include a light-shielding layer or a first signal line layer. As an example, “corresponding layers of the first pixel drive circuit and corresponding layers of the second pixel drive circuit” means at least one conductive layer of the first pixel drive circuit and a conductive layer of the second pixel drive circuit. As a specific example, “corresponding layer” includes at least one of a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, or a second signal line layer. As another specific example, the "corresponding layer" further includes at least one of a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, or a second planarization layer. As yet another specific example, the "corresponding layer" includes a first semiconductor material layer, a first gate metal layer, a second gate metal layer, a second semiconductor material layer, a third gate metal layer, a first signal line layer, and a second signal line layer. As yet another specific example, the "corresponding layer" further includes a gate insulating layer, an insulating layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a passivation layer, a first planarization layer, and a second planarization layer.

[0122] Referring to Figures 5A to 5O, Figures 6A to 6D, and Figures 8A to 8O, in some embodiments, a voltage supply connection line Clv connects multiple components of two adjacent pixel drive circuits in the same row to corresponding voltage supply lines among multiple voltage supply lines Vdd. In some embodiments, corresponding voltage supply lines among multiple voltage supply lines Vdd are connected to the voltage supply connection line Clv, for example, via an eighth via v8. The voltage supply connection line Clv is connected via a ninth via v9 to the first electrodes of two adjacent light emission control transistors of two adjacent pixel drive circuits in the same row. The first electrodes of the two adjacent light emission control transistors of two adjacent pixel drive circuits in the same row are part of a single structure. The voltage supply connection line Clv is connected via different vias to the second capacitor electrode of a first capacitor of two adjacent pixel drive circuits in the same row.

[0123] Figure 11 is a schematic diagram showing the configuration of a voltage supply connection line in some embodiments of the present disclosure. Referring to Figure 11, in some embodiments, the voltage supply connection line includes a main line portion MLP extending in a direction substantially parallel to a second direction DR2, and a first extension portion E1, a second extension portion E2, and a third extension portion E3 extending away from the main line portion MLP. The first extension portion E1, the second extension portion E2, and the third extension portion E3 each extend in a direction substantially parallel to the first direction DR1. In some embodiments, a corresponding voltage supply line among a plurality of voltage supply lines Vdd is connected to the first extension portion E1, for example, via an eighth via v8. The first extension portion E1 is connected via a ninth via v9 to the first electrodes of two adjacent light emission control transistors of two adjacent pixel drive circuits in the same row. The second extension E2 is connected to the second capacitor electrode of the first capacitor of the first adjacent pixel driving circuit, and the third extension E3 is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel driving circuit.

[0124] In some embodiments, the voltage supply connection line Clv is substantially mirror-symmetric with respect to a plane that is substantially parallel to the first direction DR1 and substantially perpendicular to the light-emitting surface of the array substrate. Optionally, this plane may intersect with the first extension. Optionally, this plane may intersect with the eighth via v8 and the ninth via v9.

[0125] Figure 12 is a schematic diagram showing the layout of voltage supply connection lines to the second semiconductor material layer in the array substrate shown in Figure 5A or Figure 8A. Referring to Figures 11 and 12, in some embodiments, the orthographic projection of the voltage supply connection line Clv onto the base substrate at least partially encloses the orthographic projection onto the base substrate of two adjacent compensating transistors of two adjacent pixel driver circuits in the same row. The main line portion MLP of the voltage supply connection line Clv intersects the active layers of two adjacent data write transistors of two adjacent pixel driver circuits in the same row. Optionally, the orthographic projection of the voltage supply connection line Clv onto the base substrate may partially overlap the orthographic projection onto the base substrate of the active layers of two adjacent data write transistors of two adjacent pixel driver circuits in the same row.

[0126] In some embodiments, the orthographic projection of the first extension E1 onto the base substrate separates the orthographic projection of the second electrode of the compensation transistor in the first adjacent pixel driving circuit from the orthographic projection of the second electrode of the compensation transistor in the second adjacent pixel driving circuit onto the base substrate.

[0127] In some embodiments, at least a portion of the orthographic projection of the second extension E2 onto the base substrate separates the orthographic projection of at least the active layer of the first reset transistor in the first adjacent pixel drive circuit from the orthographic projection of at least the active layer of the compensation transistor in the first adjacent pixel drive circuit. In this layout, a constant voltage is provided to the voltage supply connection line Clv, thereby effectively preventing signal interference between the first reset transistor and the compensation transistor.

[0128] In some embodiments, at least a portion of the orthographic projection of the third extension E3 onto the base substrate separates the orthographic projection of at least the active layer of the first reset transistor in the second adjacent pixel drive circuit from the orthographic projection of at least the active layer of the compensation transistor in the second adjacent pixel drive circuit. In this layout, a constant voltage is provided to the voltage supply connection line Clv, thereby effectively preventing signal interference between the first reset transistor and the compensation transistor.

[0129] Figure 13 is a schematic diagram showing the layout of a plurality of first reset signal lines for a plurality of data lines in four adjacent pixel drive circuits in the same row of an array substrate in some embodiments of the present disclosure. Referring to Figures 13, 5K and 5M, in some embodiments, at least a portion of the orthographic projection onto the base substrate of each of the plurality of first reset signal lines Vint1 separates the orthographic projection onto the base substrate of at least a portion of the plurality of data lines DL configured to provide data signals to a first adjacent pixel drive circuit, and the orthographic projection onto the base substrate of at least a portion of the plurality of data lines DL configured to provide data signals to a second adjacent pixel drive circuit. Optionally, at least a portion of the orthographic projection onto the base substrate of each of the multiple first reset signal lines Vint1 may separate the orthographic projection onto the base substrate of the second segment of a first corresponding data line configured to provide a data signal to a first adjacent pixel drive circuit, and the orthographic projection onto the base substrate of the second segment of a second corresponding data line configured to provide a data signal to a second adjacent pixel drive circuit, among the multiple data lines DL. In this layout, a constant voltage is provided to each first reset signal line, thereby effectively preventing interference between data signals in two adjacent data lines configured to provide data signals to two adjacent pixel drive circuits.

[0130] In some embodiments, each gate line among a plurality of gate lines includes a plurality of branch lines. Referring to Figures 5A to 5O and Figures 8A to 8O, in some embodiments, each gate line includes a corresponding gate line first branch line GL-1 and a corresponding gate line second branch line GL-2. Optionally, the orthographic projection of the corresponding gate line first branch line GL-1 onto the base substrate may at least partially overlap the orthographic projection of the corresponding gate line second branch line GL-2 onto the base substrate. As an example, the corresponding gate line first branch line GL-1 is located in the second gate metal layer. As another example, the corresponding gate line second branch line GL-2 is located in the third gate metal layer.

[0131] In some embodiments, each of the multiple first control signal lines SL1 includes multiple branch lines. Referring to Figures 5A to 5O and Figures 8A to 8O, each first control signal line includes a corresponding first control signal line first branch line SL1-1 and a corresponding first control signal line second branch line SL1-2. Optionally, the orthographic projection of the corresponding first control signal line first branch line SL1-1 onto the base substrate may at least partially overlap the orthographic projection of the corresponding first control signal line second branch line SL1-2 onto the base substrate. As an example, the corresponding first control signal line first branch line SL1-1 is located in a second gate metal layer. As another example, the corresponding first control signal line second branch line SL1-2 is located in a third gate metal layer.

[0132] In some embodiments, each of the multiple third control lines includes multiple branch lines. Referring to Figures 5A to 5O and Figures 8A to 8O, each third control line includes a corresponding third control line first branch line SL3-1, a corresponding third control line second branch line SL3-2, and a corresponding third control line third branch line SL3-3. Optionally, the orthographic projection of the corresponding third control line first branch line SL3-1 onto the base substrate may at least partially overlap the orthographic projection of the corresponding third control line second branch line SL3-2 onto the base substrate, and at least partially overlap the orthographic projection of the corresponding third control line third branch line SL3-3 onto the base substrate. Optionally, the orthographic projection of the corresponding third control line second branch line SL3-2 onto the base substrate may at least partially overlap the orthographic projection of the corresponding third control line third branch line SL3-3 onto the base substrate. As an example, the corresponding third control signal line, first branch line SL3-1, is located in the first gate metal layer. As another example, the corresponding third control signal line, second branch line SL3-2, is located in the second gate metal layer. As yet another example, the corresponding third control signal line, third branch line SL3-3, is located in the third gate metal layer.

[0133] In another aspect, the present invention provides a display device comprising an array substrate described herein or an array substrate manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Suitable examples of display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital albums, GPS, etc. Optionally, the display device may be an organic light-emitting diode display device. Optionally, the display device may be a micro light-emitting diode display device. Optionally, the display device may be a mini light-emitting diode display device.

[0134] In another aspect, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a plurality of pixel drive circuits and forming a plurality of gate lines. Optionally, forming each of the plurality of pixel drive circuits may include forming a drive transistor, forming a data write transistor, forming a first reset transistor, forming a first capacitor having a first capacitor electrode and a second capacitor electrode, forming a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and forming a first node connection line. Optionally, each of the plurality of gate lines may be configured to provide a gate scan signal to the data write transistor in the corresponding pixel drive circuit. Optionally, the gate electrode of the drive transistor may be connected to a third capacitor electrode. Optionally, the second electrode of the first reset transistor may be connected to a third capacitor electrode by a first node connection line. Optionally, the orthographic projection of the corresponding gate line onto the base substrate may not substantially overlap with the orthographic projection of the first node connection line onto the base substrate.

[0135] The above description relating to embodiments of the present invention is for illustrative and explanatory purposes only. The above description is not intended to be exhaustive or to limit the present invention to the exact form or exemplary embodiment disclosed. Therefore, the above description should be considered illustrative rather than limiting, and many changes and modifications will be obvious to those skilled in the art. Many modifications and modifications will be obvious to those skilled in the art. These embodiments have been selected and described to illustrate the practical application of the principles of the present invention and its best mode, thereby enabling those skilled in the art to understand that the present invention is applicable to various embodiments and various modifications of a particular use or assumed embodiment. The scope of the present invention is intended to be defined by the claims and equivalents attached to this disclosure, and unless otherwise indicated, all language is to be interpreted most broadly within reasonable limits. Accordingly, the words “the present invention,” “this disclosure,” or similar language do not necessarily limit the claims to specific embodiments, and references to exemplary embodiments of the present invention do not imply a limitation to the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. Furthermore, these claims may use expressions such as “first,” “second,” etc., followed by nouns or elements. Unless otherwise specified, such terms should be understood as proprietary terms and should not be interpreted as limiting the quantity of the modified element. None of the effects or advantages described may apply to all embodiments of the present invention. Those skilled in the art will understand that the described embodiments can be modified without departing from the scope of the present invention as defined by the following claims. Furthermore, none of the elements and components of this disclosure, whether or not they are explicitly stated in the following claims, are intended for the public.

Claims

1. An array substrate including multiple pixel driving circuits and multiple gate lines, Each of the plurality of pixel driving circuits includes a driving transistor, a data writing transistor, a first reset transistor, a first capacitor having a first capacitor electrode and a second capacitor electrode, a second capacitor having a third capacitor electrode and a fourth capacitor electrode, and a first node connection line. Each of the plurality of gate lines is configured to provide a gate scanning signal to the data writing transistor in the corresponding pixel driving circuit. The gate electrode of the drive transistor is connected to the third capacitor electrode, The first node connection line connects the second electrode of the first reset transistor and the third capacitor electrode. The orthographic projection of the corresponding gate line onto the base substrate does not substantially overlap with the orthographic projection of the first node connection line onto the base substrate. Array substrate.

2. The orthographic projection of the corresponding gate line onto the base substrate and the orthographic projection of the first node connection line onto the base substrate are separated by the orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate. The array substrate according to claim 1.

3. The orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate does not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate, nor does it substantially overlap with the orthographic projection of the first node connection line onto the base substrate. The array substrate according to claim 2.

4. The orthographic projection of the corresponding gate line onto the base substrate and the orthographic projection of the third capacitor electrode of the second capacitor onto the base substrate are separated by the orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate. The array substrate according to claim 3.

5. The orthographic projection of the second capacitor electrode of the first capacitor onto the base substrate does not substantially overlap with the orthographic projection of the corresponding gate line onto the base substrate, and does not substantially overlap with the orthographic projection of the third capacitor electrode of the second capacitor onto the base substrate. The array substrate according to claim 4.

6. The orthographic projection of the corresponding gate line onto the base substrate does not substantially overlap with the orthographic projection of the active layer of the first reset transistor and the second electrode onto the base substrate. The array substrate according to any one of claims 1 to 5.

7. The second electrode of the first reset transistor intersects with the second capacitor electrode. The array substrate according to any one of claims 1 to 6.

8. It includes a plurality of second capacitor electrode wires extending in a direction substantially parallel to the second direction, Each of the plurality of second capacitor electrode lines includes a second capacitor electrode connected to each other in the same row of the pixel driving circuit. Each of the aforementioned pixel driving circuits further includes a light emission control transistor and a third reset transistor, The second electrode of the light emission control transistor is separated from the second electrode of the third reset transistor by a connecting line that connects two adjacent second capacitor electrodes of two adjacent pixel drive circuits in the same row in the corresponding second capacitor electrode line, and the second electrode of the light emission control transistor is separated from the first electrode of the drive transistor. The array substrate according to any one of claims 1 to 7.

9. Each of the aforementioned pixel driving circuits further includes a second node connection line connected via a third via to the second electrode of the light emission control transistor, connected via a fourth via to the first electrode of the driving transistor, and connected via a fifth via to the second electrode of the third reset transistor. The second electrode of the light-emitting control transistor and the first electrode of the drive transistor are located in the first semiconductor material layer. The corresponding second capacitor electrode wire is located in the first gate metal layer, which is located on the side of the first semiconductor material layer away from the base substrate. The second electrode of the third reset transistor is located in a second semiconductor material layer that is located on the side of the first gate metal layer away from the base substrate. The second node connection line is located in the first signal line layer, which is located on the side of the second semiconductor material layer away from the base substrate. The array substrate according to claim 8.

10. The second node connection line intersects with the corresponding second capacitor electrode line. The array substrate according to claim 8.

11. It further includes multiple voltage supply lines, Each of the aforementioned pixel driving circuits further includes a light emission control transistor and a voltage supply connection line, The corresponding voltage supply line among the plurality of voltage supply lines is connected to the voltage supply connection line via an eighth via. The voltage supply connection line is connected via a ninth via to the first electrodes of two adjacent light emission control transistors of two adjacent pixel drive circuits in the same row. The first electrodes of the two adjacent light-emitting control transistors of the two adjacent pixel driving circuits in the same row are part of an integrated structure. Each of the aforementioned voltage supply connection lines is connected via different vias to the second capacitor electrode of the first capacitor of two adjacent pixel drive circuits in the same row. The array substrate according to any one of claims 1 to 7.

12. The voltage supply connection line includes a main line portion extending in a direction substantially parallel to the second direction, and a first extension portion, a second extension portion, and a third extension portion extending away from the main line portion. The first, second, and third extensions each extend in a direction substantially parallel to the first direction. The corresponding voltage supply line among the plurality of voltage supply lines is connected to the first extension via the eighth via, The first extension is connected via the ninth via to the first electrode of the two adjacent light-emitting control transistors of the two adjacent pixel driving circuits in the same row. The second extension is connected to the second capacitor electrode of the first capacitor of the first adjacent pixel driving circuit. The third extension is connected to the second capacitor electrode of the first capacitor of the second adjacent pixel driving circuit. The array substrate according to claim 11.

13. The voltage supply connection line is substantially parallel to the first direction and substantially mirror-symmetric with respect to a plane substantially perpendicular to the light-emitting surface of the array substrate. The array substrate according to claim 12.

14. Each of the aforementioned pixel driving circuits further includes a compensation transistor, The orthographic projection of the voltage supply connection line onto the base substrate at least partially encloses the orthographic projection of two adjacent compensation transistors of two adjacent pixel drive circuits in the same row onto the base substrate. The aforementioned main line portion intersects with the active layers of two adjacent data writing transistors of two adjacent pixel driving circuits in the same row. The array substrate according to claim 12.

15. Each of the aforementioned pixel driving circuits further includes a compensation transistor, At least a portion of the orthographic projection of the second extension onto the base substrate separates the orthographic projection of at least the active layer of the first reset transistor in the first adjacent pixel driving circuit onto the base substrate from the orthographic projection of at least the active layer of the compensation transistor in the first adjacent pixel driving circuit onto the base substrate. At least a portion of the orthographic projection of the third extension onto the base substrate separates the orthographic projection of at least the active layer of the first reset transistor in the second adjacent pixel driving circuit onto the base substrate from the orthographic projection of at least the active layer of the compensation transistor in the second adjacent pixel driving circuit onto the base substrate. The array substrate according to claim 12.

16. Further including multiple first reset signal lines and multiple data lines, At least a portion of the orthographic projection of each of the plurality of first reset signal lines onto the base substrate is such that the orthographic projection of at least a portion of the first corresponding data lines configured to provide data signals to a first adjacent pixel drive circuit, and the orthographic projection of at least a portion of the second corresponding data lines configured to provide data signals to a second adjacent pixel drive circuit, are separated. The array substrate according to any one of claims 1 to 15.

17. It further includes multiple first reset signal lines, Each of the plurality of first reset signal lines includes a plurality of loops arranged in a direction substantially parallel to the first direction, Each of the multiple loops is connected to the first electrode of two adjacent first reset transistors in two adjacent pixel drive circuits in the same row. The array substrate according to any one of claims 1 to 15.

18. Further including an interconnected voltage supply network, The interconnected voltage supply network includes a plurality of voltage supply lines, a plurality of second capacitor electrode lines, and a plurality of voltage supply connection lines. The aforementioned plurality of voltage supply lines extend in a direction substantially parallel to the first direction, The plurality of second capacitor electrode wires extend in a direction substantially parallel to the second direction, Each of the plurality of second capacitor electrode lines includes a second capacitor electrode of a pixel driving circuit in the same row. Each of the plurality of voltage supply connection lines connects a corresponding voltage supply line among the plurality of voltage supply lines to a corresponding second capacitor electrode line among the plurality of second capacitor electrode lines. The array substrate according to any one of claims 1 to 10.

19. Each of the aforementioned pixel driving circuits further includes a compensation transistor and a third node connection line, The third node connection line is connected via a sixth via to the second electrode of the compensation transistor and the data writing transistor, and via a seventh via to the first capacitor electrode of the first capacitor and the fourth capacitor electrode of the second capacitor. The orthographic projection of the third node connection line onto the base substrate overlaps at least partially with the orthographic projection of the active layer of the compensation transistor onto the base substrate. The third node connection line extends in a direction substantially parallel to the extending direction of the active layer of the compensation transistor. The array substrate according to any one of claims 1 to 14 and 16 to 18.

20. The array substrate is as described in any one of claims 1 to 19, and includes one or more integrated circuits connected to the array substrate. Display device.

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