Three-dimensional (3D) dual complementary circuit structure and related fabrication methods

Abstract

A 3D dual complementary circuit structure includes a first fork sheet structure stacked on the first side of a second fork sheet structure in a first direction to provide two complementary circuits within the space of a single fork sheet structure. A dividing wall divides at least one semiconductor slab within the first fork sheet structure into a first slab portion having a first semiconductor type and a second slab portion having a second semiconductor type, and also divides at least one semiconductor slab within the second fork sheet structure into a third slab portion having a third semiconductor type and a fourth slab portion having a fourth semiconductor type. One of the second, third, and fourth semiconductor types may be the same semiconductor type as the first semiconductor type. Two complementary metal-oxide-semiconductor (CMOS) circuits can be formed within the region of a single fork sheet structure.

Description

Technical Field

[0001] (Priority Application)

[0001] This application claims priority to U.S. Patent Application No. 18 / 314,245, filed May 9, 2023, titled "THREE-DIMENSIONAL (3D) DUAL COMPLEMENTARY CIRCUIT STRUCTURES AND RELATED FABRICATION METHODS," which is hereby incorporated by reference in its entirety.

Background Art

[0002] I. Field of the Disclosure

[0002] The technology of this disclosure generally relates to transistors within integrated circuits, and more particularly to three-dimensional transistor circuits.

[0003] II. Background

[0003] Consumer demand for higher electronic device performance is a driving force behind technological progress. For example, in response to consumer demand for devices with higher functionality and performance in smaller packages, there is a continuing trend to increase the number of transistors in integrated circuits (ICs) within electronic devices such as cellular phones, laptops, and tablets. Reducing the size of transistors allows more transistors to fit on a chip of the same area, or the same number of transistors to fit on a smaller chip. One method for reducing the area of ​​individual transistors involves exchanging horizontal area for vertical height. This has spurred the development of three-dimensional (3D) transistors and circuits. For example, a complementary circuit employing two different types of transistors can be reduced by vertically stacking the first type of transistor on top of the second type of transistor. However, in addition to the size of individual transistors, another contributing factor to the area of ​​an IC is the minimum lateral spacing distance between transistors, which is due to limitations in the manufacturing process. Due to this spacing distance, a large proportion of the area of ​​the IC chip is wasted. Methods are needed to further reduce the area occupied by multiple transistors. [Overview of the project]

[0004]

[0004] The embodiments disclosed in “Modes for Carrying Out the Invention” include a three-dimensional (3D) dual complementary circuit structure. Related manufacturing methods for the 3D dual complementary circuit structure are also disclosed. An exemplary 3D dual complementary circuit structure includes a first fork sheet structure stacked on the first side in a first direction of a second fork sheet structure to provide two complementary circuits within the space of a single fork sheet structure. The fork sheet structure includes at least one semiconductor slab used as a transistor channel, which is bifurcated by a dividing wall to form a first circuit device in the first slab portion and a second circuit device in the second slab portion to provide two circuit devices in a region smaller than two separate circuit device structures. The dividing wall divides at least one semiconductor slab in the first fork-sheet structure into a first slab portion having a first semiconductor type and a second slab portion having a second semiconductor type, and also divides at least one semiconductor slab in the second fork-sheet structure into a third slab portion having a third semiconductor type and a fourth slab portion having a fourth semiconductor type. In this way, two CMOS circuits can be formed in one of several configurations within the region of a single fork-sheet structure in order to significantly increase circuit density and reduce the area of ​​the integrated circuit.

[0005]

[0005] Any of the second, third, and fourth semiconductor types may be the same semiconductor type as the first semiconductor type. In some examples, only one of the second, third, and fourth semiconductor types may be the same semiconductor type as the first semiconductor type, while the others may be opposite semiconductor types. In such examples, where the 3D dual complementary circuit structure has two semiconductor devices of each semiconductor type, two complementary metal oxide semiconductor (CMOS) circuits may be formed within a region of the first fork sheet structure, which is a region smaller than the region of the two separate device structures.

[0006]

[0006] In this regard, one embodiment discloses a 3D dual circuit structure. The 3D dual circuit structure includes a first fork sheet structure comprising at least one first semiconductor slab, a second fork sheet structure comprising at least one second semiconductor slab and disposed on the first side of the first fork sheet structure in a first direction, and a dividing wall comprising a dividing wall that, in a second direction perpendicular to the first direction, divides at least one first semiconductor slab into a first slab portion comprising a first semiconductor type on the first side of the dividing wall and a second slab portion comprising a second semiconductor type on the second side of the dividing wall, and also divides at least one second semiconductor slab into a third slab portion comprising a third semiconductor type on the first side of the dividing wall and a fourth slab portion comprising a fourth semiconductor type on the second side of the dividing wall, wherein the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

[0007]

[0007] In another embodiment, a method for fabricating a 3D dual circuit structure is disclosed. A method for fabricating a 3D dual circuit structure includes forming a first fork sheet structure including at least one first semiconductor slab; forming a second fork sheet structure including at least one second semiconductor slab and disposed on the first side of the first fork sheet structure in a first direction; and forming a dividing wall that, in a second direction perpendicular to the first direction, divides at least one first semiconductor slab into a first slab portion including a first semiconductor type on the first side of the dividing wall and a second slab portion including a second semiconductor type on the second side of the dividing wall, and also divides at least one second semiconductor slab into a third slab portion including a third semiconductor type on the first side of the dividing wall and a fourth slab portion including a fourth semiconductor type on the second side of the dividing wall, wherein the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

[0008]

[0008] In another embodiment, an integrated circuit (IC) is disclosed. The IC includes a complementary logic circuit comprising a plurality of 3D dual circuit structures, each of which comprises a first fork sheet structure comprising at least one first semiconductor slab, a second fork sheet structure comprising at least one second semiconductor slab disposed on the first side of the first fork sheet structure in a first direction, and a dividing wall comprising at least one first semiconductor slab in a second direction perpendicular to the first direction, on the first side of the dividing wall The semiconductor slab comprises a dividing wall that divides the slab into a first slab portion containing a semiconductor type and a second slab portion containing a second semiconductor type on the second side of the dividing wall, and also divides at least one second semiconductor slab in a second direction into a third slab portion containing a third semiconductor type on the first side of the dividing wall and a fourth slab portion containing a fourth semiconductor type on the second side of the dividing wall, wherein the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type. [Brief explanation of the drawing]

[0009] [Figure 1A]

[0009] This is a top view of an example of an exemplary three-dimensional (3D) dual complementary circuit structure, which includes a stacked fork-sheet structure in which two complementary metal-oxide-semiconductor (CMOS) circuits are formed within the region of the fork-sheet structure. [Figure 1B]

[0010] Figure 1A is a cross-sectional side view of an exemplary 3D dual complementary circuit structure, showing the fork sheet structure divided into separate slab sections. [Figure 1C]

[0011] Figure 1A is a cross-sectional side view along the channel direction of the first and second fork seats in an exemplary 3D dual complementary circuit structure. [Figure 2]

[0012] This flowchart shows an exemplary fabrication process for creating an exemplary 3D dual complementary circuit structure, including, but not limited to, the dual complementary circuit structure shown in Figures 1A to 1C, which includes a stacked fork sheet structure in which two CMOS circuits are formed within a reduced region. [Figure 3A]

[0013] Figure 3A is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3B] Figure 3B is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3C] Figure 3C is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-seat structure in which two CMOS circuits are formed within the region of the fork-seat structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3D] Figure 3D is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3E] Figure 3E is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-seat structure in which two CMOS circuits are formed within the region of the fork-seat structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3F]Figure 3F is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3G] Figure 3G is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3H] Figure 3H is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 3I] Figure 3I is a flowchart illustrating another exemplary fabrication process for creating an exemplary dual complementary circuit structure, including, but not limited to, a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, including the dual complementary circuit structure in Figures 1A-1C. [Figure 4A]

[0014] Figure 4A shows an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, which includes a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, relating to the exemplary fabrication process in Figures 1A to 1C. [Figure 4B] Figure 4B shows an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, which includes a stacked fork-sheet structure in which two CMOS circuits are formed within the region of the fork-sheet structure, relating to the exemplary fabrication process in Figures 1A to 1C. [Figure 4C]FIG. 4C is an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, including a stacked fork sheet structure with two CMOS circuits formed within the region of the fork sheet structure, according to the exemplary fabrication process in FIGS. 1A-1C. [Figure 4D] FIG. 4D is an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, including a stacked fork sheet structure with two CMOS circuits formed within the region of the fork sheet structure, according to the exemplary fabrication process in FIGS. 1A-1C. [Figure 4E] FIG. 4E is an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, including a stacked fork sheet structure with two CMOS circuits formed within the region of the fork sheet structure, according to the exemplary fabrication process in FIGS. 1A-1C. [Figure 4F] FIG. 4F is an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, including a stacked fork sheet structure with two CMOS circuits formed within the region of the fork sheet structure, according to the exemplary fabrication process in FIGS. 1A-1C. [Figure 4G] FIG. 4G is an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, including a stacked fork sheet structure with two CMOS circuits formed within the region of the fork sheet structure, according to the exemplary fabrication process in FIGS. 1A-1C. [Figure 4H] FIG. 4H is an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, including a stacked fork sheet structure with two CMOS circuits formed within the region of the fork sheet structure, according to the exemplary fabrication process in FIGS. 1A-1C. [Figure 4I] FIG. 4I is an exemplary fabrication stage during the fabrication of an exemplary 3D dual complementary circuit structure, including a stacked fork sheet structure with two CMOS circuits formed within the region of the fork sheet structure, according to the exemplary fabrication process in FIGS. 1A-1C. [Figure 5]

[0015] A cross-sectional side view of another example of a 3D dual complementary circuit structure, including a stacked fork sheet structure in which two CMOS circuits are formed within the region of the fork sheet structure, having a gate in the first fork sheet structure coupled to a gate in the second fork sheet structure, and having gate contacts on only one side. [Figure 6]

[0016] A cross-sectional side view of another example of a 3D dual complementary circuit structure, including a stacked fork sheet structure in which two CMOS circuits are formed within the region of the fork sheet structure, having a gate in the first fork sheet structure coupled to a gate in the second fork sheet structure, and having gate contacts on both sides. [Figure 7]

[0017] A cross-sectional side view of another example of a 3D dual complementary circuit structure, including a stacked fork sheet structure in which two CMOS circuits are formed within the region of the fork sheet structure, having gates in the first fork sheet structure coupled to each other and gates in the second fork sheet structure coupled to each other. [Figure 8]

[0018] An exemplary block diagram of a wireless communication device including a radio-frequency (RF) component that can include a 3D dual complementary circuit structure, including a stacked fork sheet structure in which two CMOS circuits are formed within the region of the fork sheet structure, including the 3D dual circuit structures in FIGS. 1A-1C and FIGS. 5-7, and optionally relating to any of the exemplary fabrication processes in FIGS. 2 and 3A-3I. [Figure 9]

[0019] An exemplary block diagram of a processor-based system that can include a �D dual complementary circuit structure, including a stacked fork sheet structure in which two CMOS circuits are formed within a reduced region, including the dual circuit structures in FIGS. 1A-1C and FIGS. 5-7, and optionally relating to any of the exemplary fabrication processes in FIGS. 2 and 3A-3I.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]

[0020] Several exemplary embodiments of this disclosure are described with reference to the drawings. The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” No embodiment described herein as “exemplary” should be construed as necessarily preferable or advantageous to any other embodiment.

[0011]

[0021] The embodiments disclosed in “Modes for Carrying Out the Invention” include a three-dimensional (3D) dual complementary circuit structure. Related methods for fabricating the 3D dual complementary circuit structure are also disclosed. An exemplary 3D dual complementary circuit structure includes a first fork-sheet structure stacked on the first side in a first direction of a second fork-sheet structure to provide two complementary circuits within the space of a single fork-sheet structure. The fork-sheet structure includes at least one semiconductor slab used as a transistor channel, bifurcated by a dividing wall to form a first circuit device in the first slab portion and a second circuit device in the second slab portion, to provide two circuit devices within a region smaller than two separate circuit device structures. The dividing wall divides at least one semiconductor slab in the first fork-sheet structure into a first slab portion having a first semiconductor type and a second slab portion having a second semiconductor type, and also divides at least one semiconductor slab in the second fork-sheet structure into a third slab portion having a third semiconductor type and a fourth slab portion having a fourth semiconductor type. In this way, two CMOS circuits can be formed in one of several configurations within the region of a single fork-sheet structure in order to significantly increase circuit density and reduce the area of ​​the integrated circuit.

[0012]

[0022] Any of the second, third, and fourth semiconductor types may be the same semiconductor type as the first semiconductor type. In some examples, only one of the second, third, and fourth semiconductor types may be the same semiconductor type as the first semiconductor type, while the others may be opposite semiconductor types. In such examples, where the 3D dual complementary circuit structure has two semiconductor devices of each semiconductor type, two complementary metal-oxide-semiconductor (CMOS) circuits may be formed within a region of the first fork-sheet structure, which is a region smaller than the regions of the two separate device structures.

[0013]

[0023] In this regard, Figure 1A shows an exemplary three-dimensional (3D) dual complementary circuit structure ("dual circuit structure") 100 on an integrated circuit chip (IC) 101, and a first fork seat structure 102Y, with fork seat region A extending in the second horizontal direction (X-axis direction) and the third horizontal direction (Y-axis direction). 100 This is a top view of an example of a first fork sheet structure 102Y, stacked on a second fork sheet structure 102X (not shown in Figure 1A) in a first vertical direction (Z-axis direction) to provide first and second complementary metal-oxide-semiconductor (CMOS) circuits 104A and 104B within it. A semiconductor slab is a thin layer having two opposite flat planes and two edges. A semiconductor slab bisected by a dividing wall is divided or separated by two planes into a first slab portion on the first side of the dividing wall and a second slab portion on the second side of the dividing wall, which are separated from each other. The first and second slab portions are electrically isolated from each other due to the bisection, but could otherwise be coupled. The first and second portions may be of different sizes. A bisected semiconductor slab within a fork sheet structure provides two circuit devices within a smaller area than two circuit device structures having separately formed transistor channel regions. Figures 1A, 1B, and 1C, respectively, which are diagrams of the dual circuit structure 100, show features referred to herein, and in some cases, the features may be shown in only one of Figures 1A, 1B, and 1C.

[0014]

[0024] The second X-axis direction and the third Y-axis direction are orthogonal to the first direction and to each other. The respective parts of the first and second laminated fork sheet structures 102Y and 102X are separated by a dividing wall 106 that is narrower than the minimum separation distance, so that region A 100 The region can be smaller than the region of two separate device structures (e.g., complementary field-effect transistor, CFET) structures) separated by a minimum separation distance determined by the limits of the fabrication process. As an example, the first CMOS circuit 104A may be formed on the first side S1 of the partition wall 106, and the second CMOS circuit 104B may be formed on the second side S2 of the partition wall 106. However, other configurations are also possible. The CMOS circuit includes a first circuit device having a first semiconductor type and a second circuit device having the opposite semiconductor type, as will be further described below.

[0015]

[0025] The first fork sheet structure 102Y includes at least one first semiconductor slab (e.g., nanosheet) 108, which is divided by a dividing wall 106 into a first slab portion 110A and a second slab portion 110B, also referred to herein as a first portion 110A and a second portion 110B. The dual circuit structure 100 also includes a first gate 112A disposed around the first portion 110A of at least one first semiconductor slab 108, and a second gate 112B disposed around the second portion 110B of at least one first semiconductor slab 108. The first gate 112A and the second gate 112B may initially be formed as a single structure but are separated by the addition of the dividing wall 106. The first gate 112A controls the flow of current in the second X-axis direction within the first channel region 114A of the first portion 110A of the first semiconductor slab 108. The second gate 112B controls the flow of current in the second channel region 114B within the second portion 110B of the first semiconductor slab 108. Therefore, circuit devices such as metal-oxide-semiconductor (MOS) transistors can be formed within the first portion 110A and the second portion 110B of the first fork-seat structure 102Y. The dual circuit structure 100 also includes spacers 116 on each side of the first fork-seat structure 102Y.

[0016]

[0026] In the second direction, on both sides of the first gate 112A, the first portion 110A of the first semiconductor slab 108 is coupled to source / drain regions 118J and 118K, and the second portion 110B of the semiconductor slab 108 is coupled to source / drain regions 120J and 120K. The currents in the first portion 110A and the second portion 110B of the semiconductor slab 108 are partially based on the voltage differences between the source / drain regions 118J and 118K, and between the source / drain regions 120J and 120K, respectively. The dual circuit structure 100 also includes dummy gates 122J and 122K at both ends (in the second direction) of the first portion 110A and the second portion 110B of the semiconductor slab 108. In some examples, the dummy gates 122J and 122K are inactive gates that isolate the dual circuit structure 100 from other circuit structures and may be active gates for controlling the flow of current in other channel regions.

[0017]

[0027] Figure 1B is a cross-sectional side view of the dual circuit structure 100 taken at section B-B' in Figure 1A, extending in the third Y-axis direction through gates 112A and 112B and across the dividing wall 106 (for example, perpendicular to it). Section B-B' is taken in a plane extending in the third direction (Y-axis direction) and the first direction (Z-axis direction). The top view of Figure 1A is of section A-A' shown in Figure 1B.

[0018]

[0028] Figure 1B shows that at least one first semiconductor slab 108 in the first fork sheet structure 102Y includes three first semiconductor slabs in this example. The current-driving capability of the first channel region 114A of the first portion 110A and the second channel region 114B of the second portion 110B is at least partially determined by the number of at least one first semiconductor slab 108, which may be more or less than the number shown herein.

[0019]

[0029] Figure 1B also shows a second fork seat structure 102X disposed on the first side (e.g., below) of the first fork seat structure 102Y in a first direction. The second fork seat structure 102X is structurally similar in many embodiments but is inverted with respect to the first fork seat structure 102Y. In other words, the first fork seat structure 102Y and the second fork seat structure 102X may be mirror images of each other in a first direction on the opposite side of the bonding layer 124 separating them. In some examples, the bonding layer 124 may include a shallow trench isolation (STI) material layer.

[0020]

[0030] The second fork seat structure 102X includes at least one (e.g., three in this example) second semiconductor slab 126 divided into a third portion 128A and a fourth portion 128B, electrically isolated from each other by a dividing wall 106. The second fork seat structure 102X also includes a third gate 130A and a fourth gate 130B, also electrically isolated from each other by a dividing wall 106. The first and second gates 112A, 112B and the third and fourth gates 130A, 130B are made of a conductive material such as metal.

[0021]

[0031] At least one first semiconductor slab 108 and at least one second semiconductor slab 126 are formed from a semiconductor material such as silicon (Si). Within the first portion 110A of the first fork-sheet structure 102Y, the semiconductor material is doped with a first dopant DP1 to have a first semiconductor type PN1. Within the third portion 128A of the second fork-sheet structure 102X, the semiconductor material is doped with a third dopant DP3 to have a third semiconductor type PN3, which in this example is the opposite of the first semiconductor type PN1. For example, the first semiconductor type PN1 may be doped with a pentavalent dopant, and the third semiconductor type PN3 may be doped with a trivalent dopant. In another example, the first semiconductor type PN1 is doped with a trivalent dopant, and the third semiconductor type is doped with a pentavalent dopant. In another example, the first semiconductor type PN1 in the first section 110A and the third semiconductor type PN3 in the third section 128A are the same semiconductor type.

[0022]

[0032] Depending on the type of dopant, the semiconductor material in each of the at least one first semiconductor slab 108 in the first section 110A and the at least one second semiconductor slab 126 in the third section 128A is either an N-type semiconductor or a P-type semiconductor. Thus, in this example, a first CMOS circuit 104A can be formed, where the first semiconductor type PN1 in the first section 110A and the third semiconductor type PN3 in the third section 128A are opposite semiconductor types. In this example, the at least one first semiconductor slab 108 in the second section 110B of the first fork sheet structure 102Y is doped with a second dopant DP2 for a second semiconductor type PN2, which is opposite to the first semiconductor type PN1 and also opposite to the fourth semiconductor type PN4 of the at least one second semiconductor slab 126B in the fourth section 128B that is doped with a fourth dopant DP4. Thus, the second portion 110B and the fourth portion 128B can be used to form the second CMOS circuit 104B.

[0023]

[0033] In some examples, the first semiconductor type PN1 of the first section 110A is the same as the second semiconductor type PN2 of the second section 110B. In some examples, the first semiconductor type PN1 of the first section 110A is the same as the third semiconductor type PN3 of the third section 128A. In some examples, the first semiconductor type PN1 of the first section 110A is the same as the fourth semiconductor type PN4 of the fourth section 128B. In some examples, any two of the first semiconductor type PN1, the second semiconductor type PN2, the third conductive type PN3, and the fourth semiconductor type PN4 are P-type semiconductors and the other two are N-type semiconductors, thereby allowing two CMOS circuits to be formed within the dual circuit structure 100.

[0024]

[0034] In Figure 1B, it can be seen that the first gate 112A is arranged around at least one first semiconductor slab 108 within the first portion 110A in a manner similar to a gate-all-around (GAA) transistor, except that the dividing wall 106 abuts against at least one first semiconductor slab 108. The second gate 112B, the third gate 130A, and the fourth gate 130B are also arranged around the sides of at least one semiconductor slab 108 and 126, except where they abut against the dividing wall 106. In addition, work function metal layers 132 and 134 are arranged around at least one first semiconductor slab 108 and 126. Specifically, the work function metal layer 132 is a work function metal of the type corresponding to the first semiconductor type PN1 and the fourth semiconductor type PN4 in the example in Figure 1B. Therefore, the work function metal layer 132 is located between at least one first semiconductor slab 108 and the first gate 112A in the first portion 110A. The work function metal layer 132 is also located between at least one second semiconductor slab 126 and the fourth gate 130B in the fourth portion 128B. The work function metal layer 134 corresponds to the second semiconductor type PN2 and the third semiconductor type PN3, as shown in Figure 1B. Therefore, the work function metal layer 134 is located between at least one first semiconductor slab 108 and the second gate 112B in the second portion 110B, and also between at least one second semiconductor slab 126 and the third gate 130A in the third portion 128A. The work function metal layers 132 and 134 are separated from at least one semiconductor slab 108 and 126 by the dielectric layer 136.

[0025]

[0035] Structurally, the first fork sheet structure 102Y and the second fork sheet structure 102X are disposed within inter-layer dielectric (ILD) layers 138 and 140, respectively, of ILD material 142 or other preferred material. The first and second gates 112A and 112B of the first fork sheet structure 102Y and the third and fourth gates 130A and 130B of the second fork sheet structure 102X are isolated from the ILD material 142 by spacers 116. For example, the dividing wall 106 and the spacers 116 may be formed of silicon nitride (SiN or SiO2). The material used for the work function metal layer 132 and the work function metal layer 134 is selected according to whether the semiconductor types PN1, PN2, PN3, and PN4 are N-type or P-type.

[0026]

[0036] To electrically couple to and from an external circuit, the dual circuit structure 100 includes vias 144 and contacts 146 in the first contact layer 148 for separately supplying control voltages to control the current flow in the first and second channel regions 114A and 114B. Vias 150 and contacts 152 in the second contact layer 154 are used to provide supply voltages to control the current flow in the third portion 128A and the fourth portion 128B. Thus, in this example, each of the first gate 112A, the second gate 112B, the third gate 130A, and the fourth gate 130B is individually controlled by separate control voltages provided at contacts 146 and 152. However, depending on the requirements of the circuit, the control voltages may be applied using different configurations, as shown in the examples in Figures 5 to 7, which will be described later.

[0027]

[0037] Figure 1C is a cross-sectional side view of the cross-section C-C' in Figure 1A of the dual circuit structure 100. Cross-section C-C' extends in a first direction (Z-axis direction) and also in a second direction (X-axis direction), which is the direction of current flow in at least one first semiconductor slab 108 in the second portion 110B and at least one second semiconductor slab 126 in the fourth portion 128B. Features common to Figures 1B and 1C may have the same labels and are not described again here. Some of the features mentioned in this description are shown in Figure 1A or Figure 1B.

[0028]

[0038] Figure 1C is provided to show that source / drain regions 120J and 120K in the second portion 110B extend in the first X-axis direction and are coupled to each of at least one first semiconductor slab 108, and source / drain regions 156J and 156K in the second portion 110B extend in the first X-axis direction and are coupled to each of at least one second semiconductor slab 126. The source / drain regions 120J, 120K, 156J, and 156K are located within the first to fourth source / drain regions of the dual circuit structure 100 on the second side S2 of the dividing wall 106 (see Figure 1A), and it should be understood that there are fifth, sixth, seventh, and eighth source / drain regions (not shown) similarly coupled to at least one first semiconductor slab 108 in the first portion 110A and at least one second semiconductor slab 126 in the third portion 128A. In this example, the 5th to 8th source / drain regions will also be coupled to the 5th to 8th contacts in the first contact layer 148 and the second contact layer 154.

[0029]

[0039] Source / drain regions 120J and 120K are located opposite the channel region 114B and provide the source and drain of the transistor according to the polarity of the voltage applied between source / drain regions 120J and 120K. Source / drain regions 156J and 156K extend in a first direction within a fourth portion 128B and are coupled to each of at least one second semiconductor slab 126. Source / drain regions 156J and 156K provide the source and drain on either of the channel regions 158B within the transistor (e.g., a MOS transistor) according to the polarity of the applied voltage.

[0030]

[0040] The source / drain regions 120J and 120K are coupled to metal via 160 and metal contact 162, and the source / drain regions 156J and 156K are coupled to metal via 164 and metal contact 166. The dual circuit structure 100 in this example includes a via 168 for electrically coupling the source / drain region 120K of the second portion 110B to the source / drain region 156K of the fourth portion 128B, which can be used to configure an inverter circuit or other circuit in which the source / drain region of the first type transistor is coupled to the source / drain region of the second type transistor.

[0031]

[0041] While not limited to the above, fabrication processes for manufacturing dual circuit structures may be used, including a 3D fork-sheet structure in which two CMOS circuits are formed within a reduced region, including the dual circuit structure 100 shown in Figures 1A to 1C. In this regard, Figure 2 is a flowchart illustrating an exemplary fabrication process 200 for manufacturing a dual complementary circuit structure, including a 3D fork-sheet stack in which two CMOS circuits are formed within a reduced region. The fabrication process 200 in Figure 2 is described in relation to the dual circuit structure 100 shown in Figures 1A to 1C, but it should be noted that the fabrication process 200 in Figure 2 is not limited to manufacturing the dual circuit structure 100 shown in Figures 1A to 1C.

[0032]

[0042] In this regard, exemplary steps in fabricating the dual circuit structure 100 include forming a first fork seat structure 102Y including at least one first semiconductor slab 108 (block 202), and forming a second fork seat structure 102X including at least one second semiconductor slab 126 and disposed on the first side of the first fork seat structure 102Y in a first direction (block 204). The method includes forming a dividing wall 106 that bisects at least one first semiconductor slab 108 and at least one second semiconductor slab 126 in a second direction perpendicular to the first direction (block 206), wherein the first semiconductor slab 108 bisected by the dividing wall comprises a first slab portion 110A including a first semiconductor type PN1 on the first side S1 of the dividing wall 106, and a second semiconductor type PN2 on the second side S2 of the dividing wall 106. The second semiconductor slab 126, which includes a second slab portion 110B and is divided by a dividing wall, includes a third slab portion 128A on the first side S1 of the dividing wall 106 that includes a third semiconductor type PN3, and a fourth slab portion 128B on the second side S2 of the dividing wall 106 that includes a fourth semiconductor type PN4, wherein the first of the second semiconductor type PN2, third semiconductor type PN3, and fourth semiconductor type PN4 is the same type as the first semiconductor type PN1.

[0033]

[0043] Other fabrication processes for creating dual circuit structures may also be used, including, but are not limited to, the dual circuit structure 100 shown in Figures 1A to 1C, which includes a 3D fork sheet stack in which two CMOS circuits are formed within a reduced area.

[0034]

[0044] In this regard, Figures 3A to 3I are flowcharts of another exemplary fabrication process 300 for fabricating a dual circuit structure, including a 3D fork sheet stack with two CMOS circuits formed within a reduced area, including the dual circuit structure 100 in Figures 1A to 1C, though not limiting to this. Figures 4A to 4I are exemplary fabrication stages 400A to 400I in the fabrication of a dual circuit structure, including a 3D fork sheet stack with two CMOS circuits formed within a reduced area, relating to the fabrication process 300 in Figures 3A to 3I.

[0035]

[0045] In this regard, as shown in fabrication step 400A in Figure 4A, the first step 302 in fabrication process 300 includes forming a first fork sheet structure 402 on a substrate 404, which includes at least one first semiconductor slab 406 stacked in the first Z-axis direction and surrounded by a dummy polygate 408, and forming spacers 410 on each side of the dummy polygate 408. The at least one first semiconductor slab 406 is formed from a semiconductor material such as Si. The dummy polygate 408 may be formed from a polysilicon material. The spacers 410 may be, for example, SiN.

[0036]

[0046] As shown in fabrication step 400B in Figure 4B, the next step 304 in fabrication process 300 includes forming a dielectric layer 412 around the first fork sheet structure 402, forming a segmented wall mask 414 including an opening 416 on the first fork sheet structure 402, and forming a trench 418 within the first fork sheet structure 402 through the opening 416. For example, the dielectric layer 412 may be an interlayer dielectric (ILD) material formed on the substrate 404 around the first fork sheet structure 402. The first fork sheet structure 402 and the dielectric layer 412 may be planarized by chemical and / or mechanical polishing (CMP) before forming the segmented wall mask 414. The trench 418 corresponding to the opening 416 extends through the first fork sheet structure 402 in the first Z-axis direction into the substrate 404.

[0037]

[0047] As shown in fabrication stage 400C in Figure 4C, the next step 306 in fabrication process 300 includes forming a segment wall 420 within the trench 418 of the first fork seat structure 402 and removing the segment wall mask 414. For example, the segment wall 420 may be formed by depositing SiN within the trench 418, as well as by chemical and / or mechanical polishing (CMP).

[0038]

[0048] As shown in fabrication step 400D in Figure 4D, the next step 308 in fabrication process 300 includes removing the dummy polygate 408, forming a high-K dielectric layer 422 on at least one first semiconductor slab 406 on the first side S1 and second side S2 of the split wall 420, and forming a first-type work function metal layer 424 on the high-K dielectric layer 422 on the first side S1 and second side S2 of the split wall 420. The dummy polygate 408 can be removed by a chemical etching process. The first-type work function metal 424 may be an N-type or P-type work function metal.

[0039]

[0049] As shown in fabrication stage 400E in Figure 4E, the next optional processing step 310 in fabrication process 300 includes removing the first type of work function metal 424 from the semiconductor slab 406 on the first side S1 of the split wall 420 and forming the second type of work function metal 426 on the high-K dielectric layer 422 on at least one of the first semiconductor slabs 406 on the first side S1 of the split wall 420. The first type of work function metal 424 can be removed by forming a mask on the second side S2 of the split wall and performing a chemical etch.

[0040]

[0050] As shown in fabrication stage 400F in Figure 4F, the next step 312 in fabrication process 300 includes forming a first gate 428 on the work function metal 424, 426 on the first side S1 of the split wall 420 and forming a second gate 430 on the first work function metal 424 on the second side S2 of the split wall 420. If the work function metal 424 of the first type is removed from the first side S1 and replaced with the work function metal 426 of the second type, the first gate 428 is formed on the work function metal 426 of the second type on side S1. Otherwise, the first gate 428 is formed on the work function metal 424 of the first type on side S1.

[0041]

[0051] As shown in fabrication step 400G in Figure 4G, the next step 314 in fabrication process 300 includes forming a first contact layer 432 on the first dielectric layer 412 and the first fork sheet structure 402, and forming a first gate contact 434 coupled through the first contact layer 432 to one of the first gate 428 and the second gate 430. The first contact layer 432 may be formed of an intermetallic dielectric material. The first gate contact 434 may be a metal, such as tungsten or copper.

[0042]

[0052] As shown in manufacturing step 400H in Figure 4H, step 316 in manufacturing process 300 includes mounting a carrier wafer 436 onto the first contact layer 432, removing the substrate 404 from the lower side BS of the first fork sheet structure 402, and forming a bonding layer 438 on the lower side BS of the first fork sheet structure 402, which optionally includes inter-gate contacts 440 coupled to the first gate 428 and the second gate 430. In an example where the bonding layer 438 is formed without inter-gate contacts 440, the first gate contact 434 in the first contact layer 432 is coupled to one of the first gate 428 and the second gate 430, and the bonding layer 438 may also include a second gate contact (not shown) coupled to the other of the first gate 428 and the second gate 430.

[0043]

[0053] As shown in fabrication stage 400I in Figure 4I, step 318 in fabrication process 300 includes joining the lower side BS' of the second fork seat structure 402', which was fabricated according to steps 302-316 as shown in fabrication stages 400A-400H, to the joining layer 438 of the first fork seat structure 402. In this regard, the second fork seat structure 402' is positioned on the first side (e.g., downward) of the first fork seat structure 402 in the first Z-axis direction to form a 3D fork seat stack. The dividing walls 420 and 420' of the first fork seat structure 402 and the second fork seat structure 402' are aligned to form a single dividing wall 420 extending in a first direction from the first contact layer 432 of the first fork seat structure 402 to the first contact layer 432' of the second fork seat structure 402'.

[0044]

[0054] Figures 5–7 present additional examples of cross-sectional views of dual-circuit structures, including a 3D forksheet stack with two CMOS circuits formed within a reduced region. Features common to Figures 1A–1C are similarly labeled in Figures 5–7 and may not be described again here.

[0045]

[0055] Figure 5 shows an example of a 3D dual circuit structure 500, which includes a 3D fork-seat structure 502 in which CMOS circuits 504A and 504B are formed within a reduced region. In Figure 5, the first semiconductor type PN1 in the first portion 110A is opposite to the third semiconductor type PN3 in the third portion 128A in this example. In addition, the second semiconductor type PN2 in the second portion 110B is opposite to the fourth semiconductor type PN4 in the fourth portion 128B in this example. Therefore, transistors (not shown) formed in the first portion 110A and the third portion 128A can form a CMOS circuit 504A, and transistors formed in the second portion 110B and the fourth portion 128B can form a CMOS circuit 504B. On the first side S1 of the dividing wall 106, the first gate 112A in the first portion 110A is coupled to the third gate 130A in the third portion 128A by the first inter-gate contact 506A in the junction layer 124, forming a CMOS circuit 504A, and the second gate 112B in the second portion 110B is coupled to the fourth gate 130B in the fourth portion 128B by the second inter-gate contact 506B on the second side S2 of the dividing wall 106, forming a CMOS circuit 504B.

[0046]

[0056] As in this example, the inclusion of inter-gate contacts 506A and 506B allows control voltages for the CMOS circuits on each side S1 and S2 of the split wall 106 to be provided by the inter-gate contact 506A on the first contact layer 148 above the first fork seat structure 102Y (in the Z-axis direction). This eliminates the need for lower contacts or vias to couple the third gate 130A in the third section 128A and the fourth gate 130B in the fourth section 128B to the control voltage.

[0047]

[0057] Similar to the example in Figure 5, the example of the dual circuit structure 600 in Figure 6 includes inter-gate contacts 602A and 602B for coupling the first gate 112A to the third gate 130A on the first side S1 and the second gate 112B to the fourth gate 130B in the fourth section 128B. However, the first contact layer 148 includes only gate contact 604A coupled to the first gate 112A and the third gate 130A for supplying voltage to the CMOS circuit on the first side S1. The second contact layer 154 includes gate contact 604B coupled to the fourth gate 130B and the second gate 112B for supplying voltage to the CMOS circuit on the second side S2.

[0048]

[0058] In the case of Figure 5, the second semiconductor type PN2 and the fourth semiconductor type PN4 are opposite to each other, but in the dual circuit structure 600, the second semiconductor type PN2 and the first semiconductor PN1 in the first fork sheet structure 102Y have the same semiconductor type, and the fourth semiconductor type PN4 and the third semiconductor type PN3 in the second fork sheet structure 102X have the same semiconductor type. Therefore, the dual circuit structure 600 in Figure 6 can provide the same CMOS circuit as the dual circuit structure 500 in Figure 5, but does not require the optional processing step 310 in process 300, which forms opposite semiconductor types on different sides S1 and S2 of the dividing wall 106.

[0049]

[0059] Figure 7 shows another example of a dual circuit structure 700, which includes a 3D fork sheet structure in which CMOS circuits 702A and 702B are formed within a reduced region. A first semiconductor type PN1 in a first portion 110A of at least one semiconductor slab 108 is opposite to a second semiconductor type PN2 in a second portion 110B. In addition, a first gate 112A and a second gate 112B are coupled to each other in a first contact layer 148 by vias 704 and contacts 706. In contrast to Figures 5 and 6, in which the CMOS circuits are formed on each side of the partition wall 106, the dual circuit structure in Figure 7 realizes the CMOS circuits 702A and 702B on each side of the junction layer 124. For example, the first gate 112A and the second gate 112B are coupled to form a CMOS inverter. Similarly, the third semiconductor type PN3 is the opposite of the fourth semiconductor type PN4, and gates 130A and 130B are coupled to each other through vias 708 and contacts 710 in the second contact layer 154.

[0050]

[0060] In all examples in Figures 5 to 7, it should be understood that the source / drain region may also be coupled to an external circuit or another terminal through vias and contacts in the first contact layer 148 and the second contact layer 154.

[0051]

[0061] Electronic devices including a 3D dual complementary circuit structure, such as those shown in Figures 1A-1C and 5-7, and any embodiment disclosed herein, which includes a stacked fork-sheet structure in which two CMOS circuits are formed within a reduced area, may be provided within or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotors.

[0052]

[0062] In this regard, Figure 8 shows an exemplary wireless communication device 800 including radio frequency (RF) components formed from one or more ICs 802. Here, any of the ICs 802 may include integrated circuits including dual complementary circuit structures, including a stacked fork-sheet structure in which two CMOS circuits are formed within the area of ​​a single fork-sheet, as shown in Figures 1A-1C and 5-7, and according to any embodiment disclosed herein. The wireless communication device 800 may, for example, include any of the devices mentioned above, or may be provided within any of those devices. As shown in Figure 8, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 that support bidirectional communication. Generally, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 can be mounted on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0053]

[0063] The transmitter 808 or receiver 810 may be implemented using a superheterodyne or direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted between RF and baseband in multiple stages, for example, from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. In the wireless communication device 800 in Figure 8, the transmitter 808 and receiver 810 are implemented using a direct conversion architecture.

[0054]

[0064] In the transmission path, the data processor 806 processes the data to be transmitted and provides the transmitter 808 with an I analog output signal and a Q analog output signal. In an exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1), 812(2) for converting the digital signals generated by the data processor 806 into an I analog output signal and a Q analog output signal, such as an I output current and a Q output current, for further processing.

[0055]

[0065] Within transmitter 808, low-pass filters 814(1) and 814(2) filter the I analog output signal and the Q analog output signal, respectively, to remove undesirable signals generated by the preceding digital-to-analog conversion. Amplifiers (AMPs) 816(1) and 816(2) amplify the signals from low-pass filters 814(1) and 814(2), respectively, to provide the I baseband signal and the Q baseband signal. Upconverter 818 upconverts the I baseband signal and the Q baseband signal via mixers 820(1) and 820(2) using the I TX LO signal and the Q TX LO signal from the transmit (TX) local oscillator (LO) signal generator 822, to provide the upconverted signal 824. Filter 826 filters the upconverted signal 824 to remove undesirable signals generated by frequency upconversion and noise in the receiving frequency band. A power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain the desired output power level and provides the transmit RF signal. The transmit RF signal is routed through a duplexer or switch 830 and transmitted via antenna 832.

[0056]

[0066] In the receiving path, antenna 832 receives signals transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 830 and provided to a low-noise amplifier (LNA) 834. The duplexer or switch 830 is designed to operate with specific RX vs. TX duplexer frequency separation so that the receive (RX) signal is separated from the TX signal. The received RF signal is amplified by the LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Down-conversion mixers 838(1) and 838(2) mix the output of filter 836 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from the RX LO signal generator 840 to generate the I baseband signal and the Q baseband signal. The I and Q baseband signals are amplified by AMP842(1) and 842(2), and further filtered by low-pass filters 844(1) and 844(2) to obtain the I and Q analog input signals, which are provided to the data processor 806. In this example, the data processor 806 includes analog-to-digital converters (ADCs) 846(1) and 846(2) for converting the analog input signals into digital signals that will be further processed by the data processor 806.

[0057]

[0067] In the wireless communication device 800 shown in Figure 8, the TX LO signal generator 822 generates the I TX LO signal and the Q TX LO signal used for frequency upconversion, while the RX LO signal generator 840 generates the I RX LO signal and the Q RX LO signal used for frequency downconversion. Each LO signal is a periodic signal with a specific fundamental frequency. The TX phase-locked loop (PLL) circuit 848 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 822. Similarly, the RX PLL circuit 850 receives timing information from the data processor 806 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 840.

[0058]

[0068] Figure 9 shows an example of a processor-based system 900 that can employ integrated circuits, including dual complementary circuit structures and stacked fork-sheet structures, in which two CMOS circuits are formed within the region of a single fork-sheet, as shown in Figures 1A to 1C and Figures 5 to 7. In this embodiment, the processor-based system 900 includes one or more CPUs 902, which may also be referred to as central processor units (CPUs) or processor cores, each containing one or more processors 904. The CPU(s) 902 may have a cache memory 906 coupled to the processor(s) 904 for high-speed access to temporarily stored data. The CPU(s) 902 are coupled to a system bus 908, which can interconnect master and slave devices contained within the processor-based system 900. As is well known, the CPU(s) 902 communicate with these other devices by exchanging address information, control information, and data information via the system bus 908. For example, a CPU(s) 902 can communicate bus transaction requests to a memory controller 910, which is an example of a slave device. Although not shown in Figure 9, it is possible to provide multiple system buses 908, each system bus 908 constituting a different fabric.

[0059]

[0069] Other master and slave devices can be connected to the system bus 908. As shown in Figure 9, these devices may include, for example, a memory system 912 including a memory controller 910 and one or more memory arrays 914, one or more input devices 916, one or more output devices 918, one or more network interface devices 920, and one or more display controllers 922. The input device(s) 916 may include any type of input device, including, but not limited to, input keys, switches, and audio processors. The output device(s) 918 may include any type of output device, including, but not limited to, audio, video, and other visual indicators. The network interface device(s) 920 may be any device configured to enable data exchange with the network 924. Network 924 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth® networks, and the Internet. Network interface devices 920 (one or more) can be configured to support any desired type of communication protocol.

[0060]

[0070] The CPU(s) 902 may also be configured to access the display controller(s) 922 via the system bus 908 to control the information sent to one or more displays 926. The display controller(s) 922 sends the information to be displayed to the display(s) 926 via one or more video processors 928, and the one or more video processors 928 process the information to be displayed into a format suitable for the display(s) 926. The display(s) 926 may include, but are not limited to, any type of display, including cathode ray tube (CRT), liquid crystal display (LCD), plasma display, or light-emitting diode (LED) display.

[0061]

[0071] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in relation to the embodiments disclosed herein can be implemented as instructions stored in electronic hardware, in memory, or in another computer-readable medium, and any such instructions can be executed by a processor or other processing device, or as a combination of both. For example, the devices and components described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any desired information. To clearly demonstrate this compatibility, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for specific applications, but such implementation decisions should not be construed as causing a departure from the scope of this disclosure.

[0062]

[0072] Various exemplary logic blocks, modules, and circuits described in relation to the embodiments disclosed herein may be implemented or carried out using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate logic or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors working with a DSP core, or any other such configuration).

[0063]

[0073] The embodiments disclosed herein may be embodied in hardware form, or in the form of instructions stored within hardware, which may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as separate components in a remote station, base station, or server.

[0064]

[0074] Furthermore, it should be noted that the operating steps described in any of the exemplary embodiments of this specification are described for the purpose of providing examples and explanations. The operations described can also be performed in many different orders other than the order shown in the illustrations. Moreover, an operation described in a single operating step can actually be performed in several different steps. Furthermore, one or more operating steps described in the exemplary embodiments can be combined. It should be understood that, as will be readily apparent to those skilled in the art, many different modifications can be made to the operating steps shown in the flowcharts. Those skilled in the art will also understand that information and signals can be represented using various techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0065]

[0075] The above description in this disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to this disclosure will be readily apparent to a person skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not intended to be limited to the embodiments and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0066]

[0076] Implementation examples are described in the following numbered clauses. 1.3-dimensional (3D) dual circuit structure, A first fork seat structure comprising at least one first semiconductor slab, A second fork seat structure comprising at least one second semiconductor slab, disposed on the first side of the first fork seat structure in a first direction, A dividing wall that bisects each of at least one first semiconductor slab and at least one second semiconductor slab in a second direction perpendicular to the first direction, Equipped with, A first semiconductor slab, divided into two by a dividing wall, includes a first slab portion containing a first semiconductor type on the first side of the dividing wall, and a second slab portion containing a second semiconductor type on the second side of the dividing wall. The second semiconductor slab, divided by a dividing wall, includes a third slab portion containing a third semiconductor type on the first side of the dividing wall, and a fourth slab portion containing a fourth semiconductor type on the second side of the dividing wall. A three-dimensional (3D) dual circuit structure in which the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

[0067] 2. The 3D dual circuit structure according to Clause 1, wherein the second of the second, third, and fourth semiconductor types is the same semiconductor type as the third of the second, third, and fourth semiconductor types.

[0068] 3. A 3D dual circuit structure according to Clause 1 or Clause 2, wherein the second semiconductor type is the first of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type.

[0069] 4. The 3D dual circuit structure according to Clause 1 or Clause 2, wherein the third semiconductor type is the first of the second, third, and fourth semiconductor types.

[0070] 5. The 3D dual circuit structure according to Clause 1 or Clause 2, wherein the fourth semiconductor type is the first of the second, third, and fourth semiconductor types.

[0071] 6. The first fork seat structure is, The first gate, and The second gate, It further includes, The first gate is arranged around at least one first semiconductor slab within the first slab portion, A second gate is arranged around at least one first semiconductor slab within the second slab portion. A 3D dual circuit structure according to any one of clauses 1 to 5, wherein the first gate is separated from the second gate by a dividing wall.

[0072] 7. The second fork seat structure is, The third gate, and The fourth gate, It further includes, A third gate is arranged around at least one second semiconductor slab within the third slab portion. A fourth gate is arranged around at least one second semiconductor slab within the fourth slab portion. The 3D dual circuit structure described in Clause 6, wherein the third gate is separated from the fourth gate by a dividing wall.

[0073] 8. The first slab portion further comprises a first type work function metal disposed between the first gate and at least one first semiconductor slab, A 3D dual circuit structure according to Clause 6 or 7, wherein a work function metal of type 1 is disposed within a second slab portion, a third slab portion, and a fourth slab portion, the first of which includes a work function metal of type 2, a work function metal of type 3, and a work function metal of type 4.

[0074] 9. The 3D dual circuit structure according to Clause 8, further comprising a second type of work function metal, different from the first type of work function metal, disposed within the second and third of the second and fourth slab portions.

[0075] 10. Further comprising a bonding layer, A first fork seat structure is disposed within a first dielectric layer. A second fork seat structure is disposed within a second dielectric layer. The 3D dual circuit structure according to Clause 7, wherein the junction layer is disposed between the first dielectric layer and the second dielectric layer.

[0076] 11. The bonding layer is A first gate-to-gate contact electrically couples the first gate to the third gate, and A second gate-to-gate contact electrically couples the second gate to the fourth gate. The 3D dual circuit structure described in Clause 10 further includes the following.

[0077] 12. A 3D dual circuit structure according to Clause 10 or Clause 11, wherein the dividing wall extends through the bonding layer.

[0078] 13. A first contact layer disposed on a first fork seat structure, A first gate contact coupled to the first gate, and A second gate contact coupled to the second gate, The first contact layer includes, A second contact layer disposed on a second fork seat structure, A third gate contact coupled to the third gate, and The fourth gate contact is coupled to the fourth gate, A second contact layer, including A 3D dual circuit structure further comprising any one of clauses 7 to 12.

[0079] 14. A first source / drain coupled to each of at least one first semiconductor slab within the first slab portion on the first side of the first gate, A second source / drain coupled to each of at least one first semiconductor slab within the first slab portion on the second side of the first gate, A third source / drain coupled to each of at least one first semiconductor slab within the second slab portion on the first side of the second gate, A fourth source / drain coupled to each of at least one first semiconductor slab within the second slab portion on the second side of the second gate, A fifth source / drain coupled to each of at least one second semiconductor slab within the third slab portion on the first side of the third gate, A sixth source / drain coupled to each of at least one second semiconductor slab within the third slab portion on the second side of the third gate, A seventh source / drain coupled to each of at least one second semiconductor slab within the fourth slab portion on the first side of the fourth gate, An eighth source / drain coupled to each of at least one second semiconductor slab within the fourth slab portion on the second side of the fourth gate, The 3D dual circuit structure described in Clause 13 further comprises the features described above.

[0080] 15. The first contact layer is A first source / drain contact coupled to the first source / drain, A second source / drain contact coupled to the second source / drain, A third source / drain contact coupled to a third source / drain, and A fourth source / drain contact coupled to the fourth source / drain, It further includes, The second contact layer is A fifth source / drain contact coupled to the fifth source / drain, A sixth source / drain contact coupled to a sixth source / drain, A seventh source / drain contact coupled to a seventh source / drain, and An eighth source / drain contact coupled to the eighth source / drain, The 3D dual circuit structure described in Clause 14 further includes the following.

[0081] 16. A first via connects the first source / drain contact to the fifth source / drain contact, A second via connects the third source / drain contact to the seventh source / drain contact, The 3D dual circuit structure described in Clause 15 further comprises the following:

[0082] 17. The first gate is electrically isolated from the third gate by a bonding layer. A 3D dual circuit structure according to Clause 10 or Clause 12, wherein the second gate is electrically isolated from the fourth gate by a junction layer.

[0083] 18. A 3D dual circuit structure as described in any one of Clauses 1 to 17, integrated into a device selected from the group consisting of set-top boxes, entertainment units, navigation devices, communication devices, fixed-position data units, mobile-position data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0084] 19. A method for fabricating a 3D dual circuit structure, To form a first fork sheet structure including at least one first semiconductor slab, The invention includes at least one second semiconductor slab and forms a second fork seat structure disposed on the first side of the first fork seat structure in a first direction, To form a dividing wall that bisects at least one first semiconductor slab and at least one second semiconductor slab in a second direction perpendicular to the first direction, Includes, A first semiconductor slab, divided into two by a dividing wall, includes a first slab portion containing a first semiconductor type on the first side of the dividing wall, and a second slab portion containing a second semiconductor type on the second side of the dividing wall. The second semiconductor slab, divided by a dividing wall, includes a third slab portion containing a third semiconductor type on the first side of the dividing wall, and a fourth slab portion containing a fourth semiconductor type on the second side of the dividing wall. A method wherein the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

[0085] 20. Integrated circuits (ICs) It features a complementary logic circuit with multiple 3D dual circuit structures, and each of the 3D dual circuit structures is A first fork seat structure comprising at least one first semiconductor slab, A second fork seat structure comprising at least one second semiconductor slab, disposed on the first side of the first fork seat structure in a first direction, A dividing wall comprising: a dividing wall that, in a second direction perpendicular to a first direction, divides at least one first semiconductor slab into a first slab portion including a first semiconductor type on the first side of the dividing wall and a second slab portion including a second semiconductor type on the second side of the dividing wall; and in a second direction, divides at least one second semiconductor slab into a third slab portion including a third semiconductor type on the first side of the dividing wall and a fourth slab portion including a fourth semiconductor type on the second side of the dividing wall; Equipped with, An integrated circuit (IC) in which the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

Claims

1. It is a three-dimensional (3D) dual circuit structure, A first fork seat structure comprising at least one first semiconductor slab, A second fork seat structure comprising at least one second semiconductor slab, disposed on the first side of the first fork seat structure in a first direction, A dividing wall that bisects each of the at least one first semiconductor slab and the at least one second semiconductor slab in a second direction perpendicular to the first direction, Equipped with, The first semiconductor slab, divided by the dividing wall, includes a first slab portion containing a first semiconductor type on the first side of the dividing wall, and a second slab portion containing a second semiconductor type on the second side of the dividing wall. The second semiconductor slab, divided by the dividing wall, includes a third slab portion containing a third semiconductor type on the first side of the dividing wall, and a fourth slab portion containing a fourth semiconductor type on the second side of the dividing wall. A three-dimensional (3D) dual circuit structure in which the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

2. The 3D dual circuit structure according to claim 1, wherein the second of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is the same semiconductor type as the third of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type.

3. The 3D dual circuit structure according to claim 1, wherein the second semiconductor type is the first of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type.

4. The 3D dual circuit structure according to claim 1, wherein the third semiconductor type is the first of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type.

5. The 3D dual circuit structure according to claim 1, wherein the fourth semiconductor type is the first of the second, third, and fourth semiconductor types.

6. The first fork seat structure described above is The first gate, and The second gate, It further includes, The first gate is arranged around the at least one first semiconductor slab within the first slab portion, The second gate is arranged around the at least one first semiconductor slab within the second slab portion. The 3D dual circuit structure according to claim 1, wherein the first gate is separated from the second gate by the dividing wall.

7. The second fork seat structure described above is The third gate, and The fourth gate, It further includes, The third gate is arranged around the at least one second semiconductor slab within the third slab portion. The fourth gate is arranged around the at least one second semiconductor slab within the fourth slab portion. The 3D dual circuit structure according to claim 6, wherein the third gate is separated from the fourth gate by the dividing wall.

8. The first slab portion further comprises a first type work function metal disposed between the first gate and the at least one first semiconductor slab, The 3D dual circuit structure according to claim 6, wherein the work function metal of the first type is disposed within the first of the second, third, and fourth slab portions, which include the first of the second, third, and fourth semiconductor types.

9. The 3D dual circuit structure according to claim 8, further comprising a second type of work function metal, different from the first type of work function metal, disposed within the second and third of the second, third, and fourth slab portions.

10. Further comprising a bonding layer, The first fork seat structure is disposed within the first dielectric layer, The second fork seat structure is disposed within the second dielectric layer. The 3D dual circuit structure according to claim 7, wherein the bonding layer is disposed between the first dielectric layer and the second dielectric layer.

11. The aforementioned bonding layer A first gate-to-gate contact electrically coupling the first gate to the third gate, and A second gate-to-gate contact electrically couples the second gate to the fourth gate, The 3D dual circuit structure according to claim 10, further comprising:

12. The 3D dual circuit structure according to claim 10, wherein the dividing wall extends through the bonding layer.

13. A first contact layer disposed on the first fork seat structure, wherein the first contact layer is A first gate contact coupled to the first gate, and The second gate contact coupled to the second gate, A first contact layer including, A second contact layer disposed on the second fork seat structure, wherein the second contact layer is A third gate contact coupled to the third gate, and The fourth gate contact coupled to the fourth gate, A second contact layer, including The 3D dual circuit structure according to claim 7, further comprising the above.

14. A first source / drain coupled to each of the at least one first semiconductor slab in the first slab portion on the first side of the first gate, A second source / drain coupled to each of the at least one first semiconductor slab in the first slab portion on the second side of the first gate, A third source / drain coupled to each of the at least one first semiconductor slab in the second slab portion on the first side of the second gate, A fourth source / drain coupled to each of the at least one first semiconductor slab within the second slab portion on the second side of the second gate, A fifth source / drain coupled to each of the at least one second semiconductor slab in the third slab portion on the first side of the third gate, A sixth source / drain coupled to each of the at least one second semiconductor slab within the third slab portion on the second side of the third gate, A seventh source / drain coupled to each of the at least one second semiconductor slab in the fourth slab portion on the first side of the fourth gate, An eighth source / drain coupled to each of the at least one second semiconductor slab in the fourth slab portion on the second side of the fourth gate, The 3D dual circuit structure according to claim 13, further comprising the above.

15. The first contact layer is The first source / drain contacts coupled to the first source / drain, The second source / drain contact coupled to the second source / drain, A third source / drain contact coupled to the third source / drain, and A fourth source / drain contact coupled to the fourth source / drain, It further includes, The second contact layer is A fifth source / drain contact coupled to the fifth source / drain, The sixth source / drain contact coupled to the sixth source / drain, A seventh source / drain contact coupled to the seventh source / drain, and The eighth source / drain contact coupled to the eighth source / drain, The 3D dual circuit structure according to claim 14, further comprising:

16. A first via connecting the first source / drain contact to the fifth source / drain contact, A second via connects the third source / drain contact to the seventh source / drain contact, The 3D dual circuit structure according to claim 15, further comprising the above.

17. The first gate is electrically isolated from the third gate by the bonding layer. The 3D dual circuit structure according to claim 10, wherein the second gate is electrically isolated from the fourth gate by the junction layer.

18. Set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters The 3D dual circuit structure according to claim 1, which is integrated into a device selected from the group consisting of the following.

19. A method for fabricating a 3D dual circuit structure, To form a first fork sheet structure including at least one first semiconductor slab, To include at least one second semiconductor slab and form a second fork seat structure disposed on the first side of the first fork seat structure in a first direction, A dividing wall is formed in a second direction perpendicular to the first direction, dividing the at least one first semiconductor slab and the at least one second semiconductor slab in two. Includes, The first semiconductor slab, divided by the dividing wall, includes a first slab portion containing a first semiconductor type on the first side of the dividing wall, and a second slab portion containing a second semiconductor type on the second side of the dividing wall. The second semiconductor slab, divided by the dividing wall, includes a third slab portion containing a third semiconductor type on the first side of the dividing wall, and a fourth slab portion containing a fourth semiconductor type on the second side of the dividing wall. A method wherein the first of the second semiconductor type, the third semiconductor type, and the fourth semiconductor type is the same semiconductor type as the first semiconductor type.

20. Integrated circuits (ICs) It comprises a complementary logic circuit having multiple 3D dual circuit structures, and each of the 3D dual circuit structures is A first fork seat structure comprising at least one first semiconductor slab, A second fork seat structure comprising at least one second semiconductor slab, disposed on the first side of the first fork seat structure in a first direction, A dividing wall, wherein in a second direction perpendicular to the first direction, the at least one first semiconductor slab is divided into a first slab portion including a first semiconductor type on the first side of the dividing wall and a second slab portion including a second semiconductor type on the second side of the dividing wall, and in the second direction, the at least one second semiconductor slab is divided into a third slab portion including a third semiconductor type on the first side of the dividing wall and a fourth slab portion including a fourth semiconductor type on the second side of the dividing wall, Equipped with, An integrated circuit (IC) in which the first of the second, third, and fourth semiconductor types is the same semiconductor type as the first semiconductor type.

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