Integrated cooling assembly for advanced device packaging and method for manufacturing the same

Abstract

A device package including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate includes an upper section and a lower section horizontally adjacent to the upper section. The upper section includes an upper cavity partition extending downward and defining the upper cavity volume. The lower section includes a lower cavity partition extending upward and defining the lower cavity volume. The upper and lower cavity partitions alternate along the horizontal length of the cold plate.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 467,274, filed on May 17, 2023, and U.S. Patent Application No. 18 / 235,271, filed on August 17, 2023, the entire contents of which are hereby incorporated by reference.

[0002] The present disclosure relates to advanced packaging for microelectronic devices, and more particularly, to embedded cooling systems for device packages and methods of manufacturing the same.

Background Art

[0003] Since the world's computing energy requirements are increasing at a rate that most people consider unsustainable, energy consumption poses an important challenge for the future of large - scale computing. In the predictions of some models, the information and communication technology (ICT) ecosystem may exceed 20% of the world's electricity usage by 2030, and direct power consumption by large - scale computing centers accounts for more than one - third of its energy usage. Cooling costs account for a large portion of the energy requirements of computing centers because even a slight increase in operating temperature can adversely affect the performance of microprocessors, memory devices, and other electronic components.

[0004] Improved chip performance, such as increased gate density and multi-core microprocessors, leads to increased power density and correspondingly increased heat flux, which contributes to higher chip temperatures. Therefore, heat dissipation in high-power-density chips (semiconductor devices) is a critical issue. Such temperature increases are undesirable as they degrade the chip's operating performance, efficiency, and reliability. Typically, cooling systems used to maintain the chip at a desired operating temperature use one or more heat dissipation devices, such as thermal spreaders, heat pipes, cold pipes, and heat sinks, to remove heat. Such cooling systems can suffer from reduced cooling efficiency due to the design and manufacturing of the system components. [Overview of the project] [Problems that the invention aims to solve]

[0005] Therefore, in this field, there is a need for improved energy-efficient cooling systems and methods for manufacturing the same. [Means for solving the problem]

[0006] Embodiments of this specification provide an integrated cooling assembly incorporated into an advanced device package. This integrated cooling assembly has the advantage of increasing the internal surface area of ​​the cold plate through which the coolant flows, while controlling the properties and flow characteristics of the coolant as it flows through the cold plate.

[0007] One general embodiment includes a device package comprising an integrated cooling assembly. The integrated cooling assembly comprises a semiconductor device and a cold plate attached to the semiconductor device. The cold plate comprises an upper section and a lower section horizontally adjacent to the upper section. The upper section includes an upper cavity partition extending downward and defining the upper cavity volume. The lower section includes a lower cavity partition extending upward and defining the lower cavity volume. The upper and lower cavity partitions alternate along the horizontal length of the cold plate.

[0008] In some embodiments, the upper cavity partition and the lower cavity partition can be arranged along the horizontal length of the cold plate with a lateral gap between horizontally adjacent upper and lower cavity partitions.

[0009] In some embodiments, the upper cavity partitions may be spaced horizontally across the top by a first lateral spacing, and the lower cavity partitions may be spaced horizontally across the bottom by a second lateral spacing different from the first lateral spacing. The lateral spacing between cavity partitions may be greater than the lateral width of the cavity partitions.

[0010] Another general embodiment includes a device package. The device package includes an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device. The cold plate is spaced apart from the semiconductor device and collectively defines a cooling chamber volume between it and the semiconductor device. The cold plate includes an upper part having an upper cavity partition that extends downward and defines an upper cavity volume. The back surface of the semiconductor device includes a lower cavity partition that extends upward and defines a lower cavity volume. The upper and lower cavity partitions alternate along the horizontal length of the cold plate.

[0011] Another general embodiment includes a method for manufacturing a device package. The method includes directly bonding a first substrate, which includes an upper cavity partition defining an upper cavity, to a second substrate, which includes a lower cavity partition defining a lower cavity. The bonded first and second substrates form a cold plate in which the upper and lower cavity partitions are alternated horizontally. The upper and lower cavity partitions are etched into the first and second substrates by an anisotropic etching process. The method further includes directly bonding the cold plate to a third substrate containing a semiconductor device. The method further includes framing an integrated cooling assembly, which includes the semiconductor device and the cold plate, from the bonded first, second, and third substrates. The method further includes sealing a package cover to the integrated cooling assembly using a layer of material placed between the package cover and the integrated cooling assembly. The package cover includes an inlet opening and an outlet opening. The method further includes forming openings in the material layer before or after attaching the package cover to the cold plate, thereby enabling fluid communication between the inlet and outlet openings and the coolant chamber volume.

[0012] The above and other purposes and advantages of this disclosure will become clear upon review of the following detailed description in conjunction with the attached drawings. [Brief explanation of the drawing]

[0013] [Figure 1A] This is a schematic plan view of an example of a system panel according to an embodiment of the present disclosure. [Figure 1B] This is a schematic partial cross-sectional side view of a device package mounted on a PCB according to an embodiment of the present disclosure. [Figure 2A] Figure 1B is a schematic exploded isometric view of the device package. [Figure 2B] This is a schematic cross-sectional view of the device package shown in Figure 1B according to an embodiment of the present disclosure. [Figure 3A] This is a schematic exploded isometric view of a cold plate according to an embodiment of the present disclosure. [Figure 3B]This is another schematic exploded isometric view of a cold plate according to an embodiment of the present disclosure. [Figure 4A] This figure shows a method that can be used to manufacture the integrated cooling assembly described herein. [Figure 4B] This is a schematic partial cross-sectional side view of an integrated cooling assembly according to an embodiment of the present disclosure. [Figure 4C] This is another schematic partial cross-sectional side view of an integrated cooling assembly according to an embodiment of the present disclosure. [Figure 4D] This is another schematic partial cross-sectional side view of an integrated cooling assembly according to an embodiment of the present disclosure. [Figure 4E] This is another schematic partial cross-sectional side view of an integrated cooling assembly according to an embodiment of the present disclosure. [Figure 5] This is a schematic cross-sectional view of a device package according to an embodiment of the present disclosure. [Modes for carrying out the invention]

[0014] The figures in this specification illustrate various embodiments of the disclosure for illustrative purposes only. It will be understood that further or other structures, assemblies, systems, and methods can also be implemented within the scope of the principles shown in this disclosure.

[0015] Embodiments of this specification provide an integrated cooling assembly embedded within a device package. The integrated cooling assembly increases the surface area of ​​the cold plate through which the coolant flows, while controlling the properties and flow characteristics of the coolant as it flows within the cold plate.

[0016] As used herein, the term "substrate" means any workpiece, wafer or article that provides a base material or support surface on which components, elements, devices, assemblies, modules, systems or features of the heating devices, packaging components and cooling assembly components described herein can be formed, including these. The term "substrate" also includes a "semiconductor substrate" that provides a support material on which elements of a semiconductor device are fabricated or attached, and any material layer, feature and / or electronic device formed on, within or through it.

[0017] As described later, a semiconductor substrate as used herein generally has a "device side," such as the side on which semiconductor device elements like transistors, resistors, and capacitors are fabricated, and a "back side" opposite the device side. The term "active side" includes the device-side surface of the substrate and can be understood to include the device-side surface of the semiconductor substrate and / or any material layer formed thereon or extending outward from there, the surface of any device element or feature, and / or any opening formed thereon. Therefore, it can be understood that the (single or multiple) materials forming the active side can vary depending on the manufacturing and assembly stages of the device. Similarly, the term "non-active side" (opposite to the active side) includes the non-active side of the substrate at any stage of device manufacturing, including the surface of any material layer, any feature formed thereon or extending outward from there, and / or any opening formed thereon. Therefore, the terms "active side" or "non-active side" can include the respective surfaces of the semiconductor substrate at the start of device manufacturing and any surfaces formed during material removal, such as after substrate thinning operations. The terms “active side” and “inactive side” are also used to describe the surface of a material layer or feature formed on, within, or through a semiconductor substrate, depending on the device manufacturing or assembly stage, regardless of whether such material layer or feature ultimately exists in the manufactured or assembled device.

[0018] In this specification, spatially relative terms, such as the relationships between elements, such as the relationship between a substrate, a heating device, a cooling assembly component, a device packaging component, and other features described hereinafter, are used to describe the relationships between elements. Unless otherwise defined, terms such as "above", "over", "upper", "upwardly", "outwardly", "on", "below", "under", "beneath", "lower", "top", and "bottom" are generally used with reference to the X, Y, and Z directions shown by the X, Y, and Z directions shown in the drawings. Therefore, it should be understood that the spatially relative terms used in this specification are intended to cover different orientations of the substrate and are not limited by the direction of gravity unless otherwise indicated. Unless otherwise defined, terms representing the relationships between elements, such as "disposed on", "embedded in", "coupled to", "connected by", "attached to", "bonded to", etc., alone or in combination with spatially relative terms, include both relationships with intervening elements and direct relationships without intervening elements. Further, the terms "horizontal" and "vertical" are generally used with reference to the X direction and the Z direction shown in the drawings, respectively.

[0019] Unless otherwise specified, the terms “cooling assembly” and “integrated cooling assembly” generally refer to a semiconductor device and a cold plate attached to the semiconductor device. Typically, the cold plate has a concave surface that defines a fluid cavity (e.g., coolant chamber volume) between the cold plate and the semiconductor device. The cold plate may contain polymer materials. The cold plate can be attached to the semiconductor device using a compliant adhesive layer 242 or by direct dielectric bonding or hybrid bonding. For example, the cold plate may contain material layers and / or metallic features that facilitate direct dielectric bonding or hybrid bonding with the semiconductor device. The back surface of the semiconductor device is directly exposed to the coolant flowing through the integrated cooling assembly, thus having the advantage of achieving direct heat transfer between them. Unless otherwise specified, the integrated cooling assemblies described herein can be used with any desired fluid, such as a liquid, gas, or vapor-phase coolant, such as water and / or glycol. In some embodiments, the coolant may contain additives that enhance the conductivity of the coolant within the integrated cooling assembly. The additives may include, for example, carbon nanotube nanoparticles, graphene nanoparticles, and metal oxide nanoparticles. The concentration of these nanoparticles can be less than 1%, less than 0.2%, or even less than 0.05%. The coolant may also contain small amounts of one or more glycols (e.g., propylene glycol, ethylene glycol, etc.) to reduce the frictional shear stress and drag coefficient of the coolant within the integrated cooling assembly.

[0020] As will be discussed later, the temperature of a semiconductor device can be controlled using a coolant flowing through a cold plate. The fluid flowing over the surface of the semiconductor device absorbs heat and displaces it from the device. Unfortunately, the effectiveness of heat transfer from the semiconductor device to the cold plate fluid can be limited by the dimensions of the cold plate cavity (e.g., the amount of surface area exposed to the fluid). Fluid properties and flow characteristics (e.g., turbulence) can also hinder the efficiency of heat transfer.

[0021] Figure 1A is a schematic plan view of an example of a system panel 100 according to an embodiment of the present disclosure. Generally, the system panel 100 includes a printed circuit board, here referred to as a PCB 102, a plurality of device packages 201 mounted on the PCB 102, and a plurality of coolant lines 108 that fluidly connect each of the device packages 201 to a coolant source 110. The coolant can be supplied to each of the device packages 201 in any desired fluid phase, such as liquid, vapor, gas, or a combination thereof, and is assumed to be able to flow out of the device packages 201 in the same phase or a different phase. In some embodiments, the coolant is supplied to the device packages 201 and returned there as a liquid, and the coolant source 110 may include a heat exchanger or chiller to maintain the coolant at a desired temperature. In other embodiments, the coolant is supplied to the device packages 201 as a liquid, vaporizes within the device packages to become a liquid, and returns to the coolant source 110 as vapor. In these embodiments, the device package 201 can be fluidly coupled in parallel to the coolant source 110, which includes, or may further include, a compressor (not shown) for condensing the received vapor into a liquid form.

[0022] Figure 1B is a schematic partial cross-sectional side view of a portion of the system panel 100 of Figure 1A. As shown, each device package 201 is positioned within a socket 114 on the PCB 102 and connected to the socket 114 using a number of pins 116 or by other preferred connection methods such as solder bumps (not shown). The device package 201 can be seated within the socket 114 and secured to the PCB 102 using a mounting frame 106 and a number of fasteners 112, such as compression screws, collectively configured to exert a relatively uniform downward force on the upward edge of the device package 201. This uniform downward force ensures correct pin contact between the device package 201 and the socket 114.

[0023] Figure 2A is a schematic exploded isometric view of an example device package 201 according to an embodiment of the present disclosure. Figure 2B is a schematic cross-sectional view of the device package 201 cut along line A-A' in Figure 2A. Generally, the device package 201 includes a package substrate 202, an integrated cooling assembly 203 disposed on the package substrate 202, and a package cover 208 disposed on the periphery of the package substrate 202. The package cover 208 extends over the integrated cooling assembly 203 so that the integrated cooling assembly 203 is positioned between the package substrate 202 and the package cover 208. As shown, the device package 201 further includes a sealing material layer 222 that forms a coolant-impermeable barrier between the package cover 208 and the integrated cooling assembly 203. Coolant is supplied to the integrated cooling assembly 203 through an inlet / outlet opening 212 in the package cover 208 and a corresponding opening 222A formed through the sealing material layer 222. In some embodiments, the device package 201 may further include a support member 207 attached to an integrated cooling assembly.

[0024] Generally, the package substrate 202 includes a rigid material such as an epoxy or resin-based laminate that supports the integrated cooling assembly 203 and the package cover 208. The package substrate 202 may include conductive features, located within or on the rigid material, that electrically connect the integrated cooling assembly 203 to a system panel such as a PCB 102.

[0025] Typically, the integrated cooling assembly 203 includes a semiconductor device, here a device 204, and a cold plate 206 bonded to the device 204. Here, the device 204 includes an active side 218 on which device components such as transistors, resistors, and capacitors are formed on top or inside, and a non-active side opposite to the active side 218, here a device back side 220. As shown in the figure, the active side 218 is adjacent to the package substrate 202 and is positioned facing the package substrate 202. The active side 218 can be electrically connected to the package substrate 202 by using conductive bumps 219 encased in a first underfill layer 221 positioned between the device 204 and the package substrate 202. The first underfill layer 221 may include a curing polymer resin or epoxy that provides mechanical support to the conductive bumps 219 and protects them from thermal fatigue. The cold plate 206 can be placed on the package substrate 202 with the semiconductor device 204 attached to the package substrate 202. For example, a semiconductor device 204 can be placed between the cold plate 206 and the package substrate 202.

[0026] As shown in Figure 2B, the cold plate 206 includes an upper section 230 and a lower section 240 perpendicularly adjacent to the upper section 230. For example, the upper section 230 can be stacked on the lower section 240 in the Z-axis direction such that the upper section 230 is perpendicularly adjacent to the lateral portion 208B of the package cover 208 and the lower section 240 is perpendicularly adjacent to the package substrate 202. The upper section 230 includes upper cavity dividers 224 that extend downward (e.g., facing the lower section 240) and define the upper cavity volume 213. The lower section 240 includes lower cavity dividers 226 that extend upward (e.g., facing the upper section 230) and define the lower cavity volume 217. As shown, the cold plate 206 has a substantially horizontal orientation so as to extend in the X-axis direction. As will be explained in more detail below with reference to Figure 3A, the upper cavity partitions 224 and lower cavity partitions 226 can each define multiple upper and lower cavity volumes, each having various different shapes, sizes, and arrangements. The upper cavity partitions 224 and lower cavity partitions 226 alternate along the horizontal length of the cold plate 206. The horizontal length can be understood as the length in the X-axis direction. "Alternating along the horizontal length" can be understood as meaning that adjacent pairs of upper cavity partitions 224 are positioned on both sides above the lower cavity partitions 226, and adjacent pairs of lower cavity partitions 226 are positioned on both sides below the upper cavity partitions 224. In other words, the cavity partitions are positioned such that the downward-extending upper cavity partitions 224 do not directly face (e.g., do not face) the upward-extending lower cavity partitions 226. Furthermore, as will be explained in more detail below, the cavity partitions are spaced apart from each other so that the coolant can flow between them across the opposing surfaces of the cavity partitions. The confined coolant flow formed by the cavity partitions can be called an irregular flow path (e.g., a zigzag flow path), and the confined coolant chamber volume 210 can be called an irregular channel.

[0027] A "cavity partition" can be understood as a structure formed for the purpose of dividing a sealed volume into at least two separate volumes (e.g., compartments or partial volumes) so that a fluid can flow between them.

[0028] In some embodiments, the upper cavity partition 224 and the lower cavity partition 226 are arranged along the horizontal length of the cold plate 206 with lateral spacing between adjacent upper and lower cavity partitions. The horizontal length can be considered, for example, the length of the cold plate 206 parallel to the back surface 220 of the device 204.

[0029] The lateral spacing between adjacent upper and lower cavity partitions provides space through which the coolant can flow. For example, as shown in Figure 2B, the upper section 230 includes two upper cavity partitions 224, and the lower section 240 includes one lower cavity partition 226. The lower cavity partition 226 in the center of the lower section 240 is located below the two upper cavity partitions 224 of the upper section 230 and is adjacent to the upper cavity partitions 224 with a lateral spacing between them. The lateral spacing between the two upper cavity partitions 224 and the lower cavity partition 226 ensures that none of these cavity partitions touch each other and that the coolant can flow through the cavity volume between these cavity partitions.

[0030] In some embodiments, the upper cavity partition 224 is horizontally spaced across the upper part 230 by a first lateral spacing (e.g., in the X-axis direction), and the lower cavity partition 226 is horizontally spaced across the lower part 240 by a second lateral spacing (e.g., in the X-axis direction) that is different from the first lateral spacing. The difference between the first and second lateral spacings ensures that the upper cavity partition 224 is offset from the lower cavity partition. Ensuring that the upper and lower cavity partitions are offset from each other prevents them from aligning in the Z-axis direction, thus avoiding contact between opposing cavity partitions. As described above, maintaining space between the cavity partitions ensures that coolant can flow between the partitions. Here, the first lateral spacing includes a relatively long gap (e.g., 5 mm) between the two upper cavity partitions 224 and a relatively short gap (e.g., 2 mm) between each upper cavity partition and the adjacent cold plate sidewall. The second lateral spacing includes a uniform gap (e.g., 5 mm) between the lower cavity partition 226 and the cold plate sidewalls on both sides.

[0031] The minimum spacing between adjacent cavity partitions can be greater than the width of the cavity partition itself. The width of a cavity partition can be considered as the width measured across the widest cross-section of the cavity partition in a plane parallel to the back surface 220 of the device 204 (in the X-axis direction).

[0032] By avoiding overlap and vertical alignment of opposing upper and lower cavity partitions, coolant can be reliably flowed between the cavity partitions.

[0033] Referring to Figure 3, which will be described in more detail below, the upper part 230 includes a top surface 209 attached to the upper side wall 211, the upper side wall 211 extending downward from the top surface 209. The lower part 240 includes a lower side wall 216 attached to either the bottom surface 215 or the back surface 220 of the semiconductor device 204. That is, in some embodiments, as described below in relation to Figure 4B, the lower cavity partition 226 is located directly on the back surface 220 of the device 204, and the lower side wall 216 extends upward from the back surface 220 of the device 204. In such embodiments, the bottom surface 215 (and the cold plate 206 as a whole) is attached to the back surface 220 of the device 204. In other embodiments, as described below in relation to Figure 4C, the lower cavity partition 226 is located on the bottom surface 215 of the lower part 240, and the lower side wall 216 extends upward from the bottom surface 215.

[0034] To provide a watertight seal between the upper 230 and the lower 240, in some embodiments, the upper cavity partition 224 may extend downward from the top surface 209 to a depth substantially equal to the depth of the upper side wall 211, and the lower cavity partition 226 may extend upward from the bottom surface 215 (or the back surface 220 of the device 204) to a depth substantially equal to the depth of the lower side wall 216. The depth can be considered as the thickness in the Z-axis direction. In such embodiments, the upper and lower side walls intersect in a single horizontal plane so that the top surfaces of the side walls contact this horizontal plane to form a watertight seal between the upper 230 and the lower 240 (for example, the top surfaces and side walls of the cavity partitions are coplanar and vertically aligned in the same plane). The opposing upper surfaces of the cavity partitions (for example, the upper 230 and lower 240 which are in contact when joined together) can be directly bonded to each other using ZiBond® technology, as will be described in more detail below with reference to Figure 4A, for example. Thus, in such embodiments, the only means by which the coolant can enter and exit the coolant chamber volume 210 is through the opening 206A.

[0035] In some embodiments, an upper cavity partition 224 extends between opposing sides of the upper sidewall 211 to define an upper cavity volume 213, and a lower cavity partition 226 extends between opposing sides of the lower sidewall 216 to define a lower cavity volume 217. As shown in Figure 2B, the upper part 230 may include three upper cavity volumes 213 that extend in the Y-axis direction between opposing sides (not shown) of the upper sidewall 211 to form a rectangular cavity volume. Similarly, the lower part 240 may include two lower cavity volumes 217 that extend in the Y-axis direction between opposing sides of the lower sidewall 216 (not shown) to form a rectangular cavity volume. The upper and lower cavity volumes partially overlap each other, allowing coolant to flow between these volumes. It should be understood that the upper 230 and lower 240 may also contain more or fewer cavity partitions (and therefore more or less cavity volume than shown) than those shown in Figure 2B.

[0036] As will be described below in relation to Figures 3A and 3B, the cavity divider can be a continuous divider that extends continuously between the opposing sides of each side wall. In some embodiments, as will be described below in relation to Figure 4E, the upper cavity divider 224 is a series of first metal posts and the lower cavity divider 226 is a series of second metal posts.

[0037] The coolant chamber volume 210 can be determined as follows when attached to the device 204: The upper side wall 211 and the lower side wall 216 form the periphery of the coolant chamber volume 210. The top surface 209 and the surface of the upper cavity partition 224 form the uppermost surface of the coolant chamber volume 210. The surface of the lower cavity partition and either the back surface 220 or the bottom surface 215 of the device form the bottom surface of the coolant chamber volume 210.

[0038] Therefore, the upper cavity volume 213 and the lower cavity volume 217 collectively define the coolant chamber volume 210 between them. The coolant chamber volume 210 is in fluid communication with the inlet opening 212 and outlet opening 212 of the cold plate 206. The back surface 220 of the device 204 is in direct thermal contact with the coolant flowing through the coolant chamber volume 210, as shown by the coolant flow path 250 in Figure 2B. The lateral spacing between the horizontally adjacent upper and lower cavity partitions has the advantage of ensuring that the fluid flows between the cavities while the cavity partitions themselves obstruct the coolant flow path and create turbulence. Increasing the turbulence of the coolant improves the efficiency of heat transfer from the back surface 220 of the device 204 to the coolant. Furthermore, by providing both upper and lower cavity volumes, the surface area of ​​the coolant chamber volume 210 is increased, further improving the efficiency of heat transfer and the overall cooling of the device 204. For example, a typical coolant flow path may include an unobstructed (e.g., without cavity partitions) flow path through the coolant chamber volume 210. An unobstructed channel through the coolant chamber volume 210 can be called a straight channel. A 0.5 mm thick straight channel can be, for example, 63.32 mm 2 The exposed surface area (e.g., silicon) may be included. Irregular channels having the same thickness according to the embodiments described herein are 98.64 mm 2 The exposed surface area (e.g., silicon) can be included, and the increase in exposed surface area for heat transfer is 56%.

[0039] Generally, the support member 207 extends from the upper surface 209 to the bonding interface with the back surface 220 of the device 204. The support member 207 provides structural support to the integrated cooling assembly 203 and enhances heat transfer between them as a result of disturbing the laminar fluid flow at the interface between the coolant and the back surface 220 of the device.

[0040] Here, the coolant circulates through the cavity volume within the coolant chamber volume 210 through an opening, which is positioned through the cold plate 206 and is shown here as opening 206A. Opening 206A can be positioned between a downward-facing upper surface 209 and an upward-facing surface opposite it. Opening 206A is in fluid communication with the inlet / outlet opening 212 of the package cover 208 through an opening 222A formed in the sealing layer 222 positioned between the package cover 208 and the package cover 208.

[0041] As described below, the cold plate 206 can be etched using an anisotropic etching process that inclines the surfaces of the upper and lower sidewalls, as well as the surfaces of the upper and lower cavity partitions, i.e., forms an angle greater than or less than 90 degrees between them and the bonding surface of the device 204. As shown in Figure 4B below, the surface 402 of the upper cavity partition 224 is inclined toward the lower 240 at an angle greater than 90 degrees (for example, the (sidewall) surface 402 of the upper cavity partition 224 extends downward toward the lower 240 such that the angle between the top surface 209 and the (sidewall) surface 402 is greater than 90 degrees). As shown in Figure 2B, the surface 405 of the lower cavity partition 226 can be inclined toward the upper 230 at an angle of less than 90 degrees (for example, the (sidewall) surface 405 of the lower cavity partition 226 extends upward toward the upper 230 such that the angle between the back surface 220 and the (sidewall) surface 408 of the device 204 is less than 90 degrees). It will be understood that in another embodiment, the surfaces of the upper cavity partition and the lower cavity partition may have different inclinations. For example, as will be explained in relation to Figures 4B to 4D below, the surface 405 of the lower cavity partition 226 can be inclined toward the upper 230 at an angle greater than 90 degrees (for example, the (sidewall) surface 405 of the lower cavity partition 226 extends upward toward the upper 230 such that the angle between the back surface 220 and the (sidewall) surface 408 of the device 204 is greater than 90 degrees).

[0042] This anisotropic etching process gives the cross-sections of the upper and lower cavity partitions a trapezoidal shape. For example, the upper cavity partition 224 can have a wider width at its upper surface 209 than at its interface with the lower surface 240. Similarly, (in embodiments where the angle between the back surface 220 and the (sidewall) surface 408 of the device 204 is greater than 90 degrees) the lower cavity partition 226 can also have a wider width at its lower surface 215 / back surface 220 than at its interface with the upper surface 230.

[0043] This inclined surface can enhance the stability of the upper and lower sidewalls and / or upper and lower cavity partitions during the manufacturing of the integrated cooling assembly 203. The added stability allows for a narrower upper and lower sidewall width and a deeper coolant chamber volume compared to a cold plate with orthogonal surfaces.

[0044] Referring to Figure 2B, the cold plate 206 is attached to the back surface 220 of the device 204 without the use of an intervening adhesive. For example, the cold plate 206 can be directly bonded to the back surface 220 of the device 204, allowing the cold plate 206 and the back surface 220 of the device 204 to be in direct thermal contact. Generally, the package cover 208 includes one or more vertical or inclined sidewall portions 208A and an outer portion 208B that extends to and connects the sidewall portions 208A. The sidewall portions 208A can extend upward from the periphery of the package substrate 202 and surround the device 204 and the cold plate 206 placed thereon. The outer portion 208B is positioned to cover the cold plate 206, and is typically spaced away from the cold plate 206 by a gap corresponding to the thickness of the sealing material layer 222. The coolant circulates within the chamber volume 210 through an inlet / outlet opening 212 formed through the outer portion 208B. In each embodiment described herein, the coolant line 108 can be attached to the device package 201 by using connector features formed on the package cover 208, such as threads formed on the sidewall of the inlet / outlet opening 212 and / or protruding features 214 that surround the opening 212 and extend upward from the surface of the outer portion 208B.

[0045] Typically, the package cover 208 is formed of a semi-rigid or rigid material so that at least a portion of the downward force exerted on the package cover 208 by the mounting frame 106 (Figure 1B) is transmitted to the support surface of the package substrate 202 and not to the cold plate 206 and device 204 below. In some embodiments, the package cover 208 is formed of a thermally conductive metal such as aluminum or copper. In some embodiments, the package cover 208 functions as a heat spreader, redistributing heat from one or more electronic components within a multi-component device package.

[0046] The sealing layer 222 forms an impermeable barrier between the integrated cooling assembly 203 and the package cover 208, preventing coolant from reaching and damaging the active side 218 of the device 204. In some embodiments, the sealing layer 222 includes a polymer or epoxy material that extends upward from the package substrate 202 and encloses and / or surrounds at least a portion of the device 204. In other embodiments, the sealing layer 222 may be positioned only between the upward surface of the cold plate 206 and the portion of the package cover 208 that covers the cold plate 206. In some embodiments, the sealing layer 222 is formed of a molding compound, such as a thermosetting resin, which forms an airtight seal between the package cover 208 and the cold plate 206 during polymerization. Here, coolant is supplied to the cold plate 206 through an opening 222A positioned through the sealing layer 222. As shown in the figure, the opening 222A is aligned with the inlet / outlet opening 212 of the upper package cover 208 and the inlet / outlet opening 206A of the lower cold plate 206, respectively, to communicate with the fluid. Typically, the coolant line is attached to the device package 201 by using connector features formed on the package cover 208, such as threads formed on the side wall of the inlet / outlet opening 212 and / or protruding features 214 that surround the inlet / outlet opening 212 and extend upward from the surface of the outer portion 208B.

[0047] The sealing layer 222 has the advantage of providing mechanical support that enhances system reliability and extends the useful life of the device package 201. For example, the second sealing layer 222 can reduce mechanical stresses that could weaken the interfacial bonds and / or electrical connections between the electrical components of the device package 201, such as stresses caused by vibration, mechanical and thermal shocks, and / or fatigue resulting from repetitive thermal cycling. In some embodiments, the sealing layer 222 may be a thermally conductive material such as a polymer or epoxy having one or more thermally conductive additives such as silver and / or graphite. In some embodiments, the device package 201 further includes a support member 207 attached to the upward surface of the cold plate 206, the support member 207 may be formed of a rigid material such as a metal or ceramic plate that provides mechanical support to the cold plate 206. The support member 207 may be attached to the cold plate 206 using a direct bonding method or using an intervening adhesive layer (not shown).

[0048] Figures 3A and 3B are schematic exploded isometric views of cold plates 306A / 306B according to embodiments of the present disclosure. In Figure 3A, the cold plate 306A includes an upper 230 and a lower 240 as described above in relation to Figure 2B. The upper 230 may include an upper cavity separator 228 mounted between a pair of upper cavity partitions 224 to define a compartment within a particular upper cavity volume 213. A compartment can be considered a subdivision of the cavity volume having the same characteristics as the cavity volume but smaller dimensions. Thus, the upper cavity separator 228 defines adjacent rectangular compartments within individual upper cavity volumes 213. The lower 240 may include a lower cavity separator 232 mounted between a pair of lower cavity partitions 226 to define a compartment within a particular lower cavity volume 217. Accordingly, the lower cavity separator 232 defines adjacent rectangular compartments within each lower cavity volume 217. As shown in Figure 3A, the upper 230 may contain three upper cavity volumes 213, with the central volume being divided into first and second compartments by the upper cavity separator 228. Similarly, the lower 240 may contain two lower cavity volumes 217, both volumes being divided into first and second compartments by the lower cavity separator 232. The corresponding first compartments in the upper 230 and lower 240 define first irregular channels through the coolant chamber volume 210. The corresponding second compartments in the upper 230 and lower 240 (e.g., adjacent to the first compartments) define second irregular channels through the coolant chamber volume 210. As shown, the coolant can flow through the first irregular channels along the first coolant flow path 350A. The coolant can also flow through a second irregular channel along the second coolant passage 350B. By introducing a cavity separator and defining two separate coolant passages through the same coolant chamber volume 210, the exposed surface area of ​​the cold plate 306A is increased, thereby improving the efficiency of heat transfer. The cavity sidewalls also form additional obstacles that increase the turbulence of the coolant, further enhancing the efficiency of heat transfer.Figure 3A shows a single upper cavity separator 228 and a single lower cavity separator 232, but as will be explained later with reference to Figure 3B, it will be understood that more or fewer cavity separators can be provided.

[0049] As shown in Figure 3B, the cold plate 306B includes an upper section 330 containing three upper cavity partitions 324. The cold plate 306B further includes a lower section 340 containing one lower cavity partition 326. The upper cavity partitions 324 can define two longitudinal upper cavity volumes 313 extending between the upper side walls 311. The lower cavity partitions 326 can define three longitudinal lower cavity volumes 317 perpendicular to the longitudinal upper cavity volumes 313. The first lower cavity volume may overlap only with the first upper cavity volume, the second lower cavity volume may overlap only with the second upper cavity volume, and the third lower cavity volume may overlap with both the first and second upper cavity volumes. This arrangement of upper and lower cavity volumes defines a three-dimensional disordered channel having a three-dimensional disordered flow path, as shown by the coolant flow path 360 in Figure 3B. That is, the coolant flow path 360 directs the coolant in the X, Y, and Z axis directions to increase turbulence and further enhance the efficiency of heat transfer. As shown in Figure 3B, the three-dimensional disordered flow path is formed by a third lower cavity partition adjacent to both the first and second lower cavity partitions and in fluid communication with both upper cavity volumes. The function of the opening 206A has been explained above, and therefore, for brevity, this explanation will not be repeated.

[0050] Figure 4A is a flowchart showing a method 40 for forming an integrated cooling assembly according to an embodiment of the present disclosure. Figure 4B schematically shows an integrated cooling assembly 403A formed by method 40 according to several embodiments. The integrated cooling assembly 403A in Figure 4A includes a first substrate 230, a second substrate 470, and a third substrate 404. The first substrate 230 corresponds to the upper part described above, and the second substrate 460 corresponds to the lower part described above.

[0051] Method 40 includes directly bonding a first substrate 230 (e.g., a single-crystal silicon wafer) including an upper cavity partition 224 that defines the upper cavity volume to a second substrate 460 (e.g., a single-crystal silicon wafer) including a lower cavity partition 428 that defines the lower cavity volume, in block 42. The bonded first and second substrates form a cold plate 406 in which the upper and lower cavity partitions alternate horizontally. The upper and lower cavity volumes are etched within the first and second substrates using an anisotropic etching process. For example, the first and second substrates can be etched using a patterned mask layer formed on the surface of each substrate. The anisotropic etching process uses inherently different etching rates for the silicon material exposed to the anisotropic etchant when forming the patterned mask layer. In some embodiments, Method 40 further includes etching an opening 206A within the first substrate 230.

[0052] In Figure 4B, the upper cavity volume is etched through the first substrate 230 in part to form the upper cavity volume defined by the upper cavity partition 224, the upper sidewall 211, and the top surface 209. The depth of the upper cavity volume can be any depth shorter than the depth of the first substrate 230 in the X-axis direction (e.g., 50%, 75%, or 90% of the depth of the first substrate 230). As described above with reference to Figure 2B, the resulting upper cavity partition 224 may have a surface 402 that inclins toward the second substrate 460 at an angle greater than 90 degrees with respect to the top surface 209. In Figure 4B, the lower cavity volume is etched through the second substrate 460 completely (or almost completely) to form the lower cavity volume defined by the lower cavity partition 428, the lower sidewall 416, and the back surface 220 of the device. The depth of the lower cavity volume can be substantially the same as the depth of the second substrate 460 in the X-axis direction. The arrangement of the first and second substrates in Figure 4B is such that the resulting lower cavity partition 428 has a surface 405 that is inclined toward the first substrate 230 at an angle greater than 90 degrees with respect to the back surface 220 of the device 204.

[0053] In some embodiments, the etching process is controlled so that the etching rate of the exposed silicon material has a ratio of approximately 1:10 to 1:200, such as approximately 1:10 to 1:50 or approximately 1:25 to 1:75, including ratios of approximately 1:10 to 1:100. Examples of suitable anisotropic wet etchants include aqueous solutions of potassium hydroxide (KOH), ethylenediamine and pyrocatechol (EPD), ammonium hydroxide (HN4OH), hydrazine (N2H4), or tetramethylammonium hydroxide (TMAH). The actual difference in etching rates depends on the concentration of the etchant in the aqueous solution, the temperature of the aqueous solution, and (if present) the concentration of dopants in the substrate.

[0054] Typically, the mask layer is formed from a material that has higher selectivity for anisotropic etching compared to the underlying single-crystal silicon substrate. Examples of suitable mask materials include silicon oxide (SixOy) or silicon nitride (SixNy). In some embodiments, the mask layer has a thickness of approximately 2 μm or less, such as approximately 1 micrometer (μm) or approximately 0.1 μm or less. The mask layer can be patterned using a preferred combination of lithography and material etching patterning methods.

[0055] In block 44, method 40 includes directly bonding a cold plate 406 to a third substrate 404. The third substrate 404 may contain multiple to-be-singulated dies such as device 204, and the second substrate 460 may contain multiple to-be-singulated cold plates 406.

[0056] As shown in Figure 4B, an exemplary method for forming upper and lower cavity volumes includes etching a first substrate 230 to form an upper cavity volume, etching a second substrate 460 to form a lower cavity volume, joining the first substrate 230 to the second substrate 470 with the etched surfaces facing back to back (for example, "inverting" the second substrate 460 after etching and joining it to the first substrate 230), and joining a third substrate 404 to the surface of the second substrate opposite to the first substrate 230 to form an integrated cooling assembly 403A.

[0057] In other embodiments where the surface 405 of the lower cavity partition 428 is inclined toward the upper 230 at an angle of less than 90 degrees (for example, as described in relation to Figure 2B), exemplary methods for forming the upper and lower cavity volumes include etching the first substrate 230 to form the upper cavity volume; bonding the first substrate 230 to the second substrate 460 with the upper cavity volume facing the second substrate 460; etching the surface of the second substrate 460 opposite to the surface to which the first substrate 230 is bonded to form the lower cavity volume; and bonding the third substrate 404 to the surface of the second substrate opposite to the first substrate 230 to form an integrated cooling assembly.

[0058] The third substrate 404 may include a bulk material and a plurality of material layers disposed on the bulk material. The bulk material may include any semiconductor material suitable for manufacturing semiconductor devices, such as silicon, silicon germanium, germanium, group III-V semiconductor materials, group II-VI semiconductor materials, or combinations thereof. For example, in some embodiments, the third substrate 404 may include a single-crystal wafer, such as a silicon wafer, a plurality of device components formed in or on the silicon wafer, and a plurality of interconnection layers formed on the plurality of device components. In other embodiments, the substrate may include a reconstituted substrate, such as a substrate formed from a plurality of fragmented devices embedded in a support material.

[0059] The bulk material of the third substrate 404 can be thinned after the formation of the device 204 by using one or more backgrinding, etching, and polishing operations to remove material from the back surface. Thinning the third substrate 404 may include reducing the thickness (Z direction) to about 450 μm or less, such as about 201 μm or about 150 μm or less, using a combination of polishing and etching processes. After thinning, the back surface can be polished to a desired smoothness using a chemical mechanical polishing (CMP) process and a dielectric material layer can be deposited thereon. In some embodiments, the dielectric material layer can be polished to a desired smoothness to prepare the third substrate 404 for the bonding process.

[0060] In some embodiments, the active side 218 is temporarily bonded to a carrier substrate (not shown) before or after the thinning process. When a carrier substrate is used, the carrier substrate provides support for the thinning operation and / or thinning material to facilitate handling of the substrate during one or more subsequent manufacturing operations as described herein.

[0061] Here, method 40 may include forming dielectric layers on a first substrate 230 and a second substrate 260, and direct bonding may include forming a dielectric bond between a first dielectric material layer on the first substrate 230 and a second dielectric material layer on the second substrate 260. Furthermore, method 40 may include forming dielectric layers on a cold plate 406 and a third substrate 404, and direct bonding may include forming a dielectric bond between a third dielectric material layer on the cold plate 406 and a fourth dielectric material layer on the third substrate 404.

[0062] In general, directly bonding the surfaces (of the dielectric material layers) in blocks 42 and 44 involves preparing, aligning, and contacting the surfaces. Preparing the surfaces involves smoothing each surface to a desired surface roughness, such as 0.1–3.0 nm RMS, activating the surfaces to weaken or open the chemical bonds of the dielectric material, and terminating the surfaces with desired species. Smoothing the surfaces involves polishing the substrate using a chemical mechanical polishing (CMP) process. Activating the surfaces and terminating them with desired species may involve exposing the surfaces to radical species formed in the plasma.

[0063] In some embodiments, the plasma is formed using a nitrogen-containing gas such as N2, and the terminating species include nitrogen and hydrogen. In some embodiments, the surface can be activated using a wet cleaning process, such as exposing the surface to an aqueous ammonia solution. In some embodiments, dielectric bonding can be formed using dielectric material layers deposited on only one of the substrates, rather than both. In these embodiments, direct dielectric bonding can be formed by bringing the deposited dielectric material layer on one substrate into direct contact with the bulk material surface of the other substrate.

[0064] In block 42, the direct formation of a dielectric bond between the first and second substrates to form a cold plate 406, and in block 44, the direct formation of a dielectric bond between the cold plate 406 and the third substrate 404, involves bringing the prepared and aligned surfaces into direct contact at a temperature below 150°C, such as below 100°C, for example below 30°C, or near room temperature, such as 20°C to 30°C. Although not constrained by theory, it is believed that hydrogen-terminated species diffuse from the interfacial bonding surfaces and chemical bonds are formed between the remaining nitrogen species during the direct bonding process. In some embodiments, the direct bonds are strengthened using an annealing process in which the substrates are heated to a temperature higher than about 30°C and lower than about 450°C, for example higher than about 50°C and lower than about 250°C, or about 150°C and maintained for a period of about 5 minutes or more, such as about 15 minutes. Typically, these bonds are strengthened over time without the application of heat. Therefore, in some embodiments, the method does not involve heating the substrates.

[0065] After dielectric bonds are formed, the substrate can be heated to a temperature of 150°C or higher and maintained at a high temperature for approximately one hour or more, such as 8 to 24 hours, to form direct metallurgical bonds between the metallic features. Suitable direct dielectric bonding and hybrid bonding technologies that can be used to carry out embodiments of the methods described herein include ZiBond® and DBI®, both commercially available from Adeia Holdings, Inc. in San Jose, California, USA.

[0066] In block 46, method 40 includes framing an integrated cooling assembly 403A, which includes a semiconductor device 204 and a cold plate 406, from the bonded first, second, and third substrates.

[0067] Since the bonding surface of each cold plate 406 has the same perimeter as the back surface of the device 204 bonded to the cold plate 406, post-bonding piecework gives the integrated cooling assembly 203 unique structural properties. Therefore, typically, the sidewalls of the cold plate 406 are the same height as the edges of the device 204 along their common perimeter. In some embodiments, the cold plate 406 is pieced from the first and second substrates using a process that cuts or divides the first and second substrates in a vertical plane (i.e., a plane parallel to the Z direction). In these embodiments, the sides of the cold plate 406 are substantially perpendicular to the back surface of the device 204 (i.e., the horizontal (XY) plane of the attachment interface between the device 204 and the cold plate 406). In some embodiments, the cold plate 406 is pieced using a saw or laser dicing process.

[0068] In block 48, method 40 includes sealing the package cover 208 to the integrated cooling assembly 403A by using a material layer placed between the package cover 208 and the integrated cooling assembly 403A (for example, by using a molded compound that forms a sealing material layer 222 when cured). The package cover 208 may include an inlet opening 212 and an outlet opening 212.

[0069] In block 50, method 40 includes forming openings in the material layer before or after attaching the package cover 208 to the cold plate 406 to allow fluid communication between the inlet opening 222a and the outlet opening 222a and the lower cavity and the upper cavity. In some embodiments, the method further includes forming an opening 222A in the material layer.

[0070] Since the inclined surface can also be formed using other methods well known to those skilled in the art, it is assumed that the above method is not limited to crystalline silicon. Accordingly, in some embodiments, the cold plate 406 can be formed from a bulk material having substantially the same coefficient of linear thermal expansion (CTE) as the bulk material of the device, where CTE is the fractional change in the length of the material (in the XY plane) per degree of temperature change. In some embodiments, the CTEs of the first and second substrates are matched such that the CTE of the second substrate is within approximately ±20% of the CTE of the first substrate, such as within ±15%, ±10%, or ±5% when measured over a desired temperature range. In some embodiments, the CTEs are matched over a temperature range of approximately -60°C to approximately 100°C, or approximately 60°C to approximately 175°C. In one embodiment, the matching CTE materials each include silicon.

[0071] Figure 4C schematically shows an integrated cooling assembly 403B formed by Method 40 according to several embodiments. The integrated cooling assembly 403B in Figure 4C includes a first substrate 230, a second substrate 470, and a third substrate 404. The first substrate 230 corresponds to the upper part described above, and the second substrate 470 corresponds to the lower part described above.

[0072] Here, an anisotropic etching process is used to etch upper and lower cavity partitions within the first and second substrates to form a cold plate. As described above in relation to Figure 4B, the upper cavity volume is etched through the first substrate 230 in a partial manner. In Figure 4C, the lower cavity volume is etched through the second substrate 470 in a partial manner to form the lower cavity volume, which is defined by the lower cavity partition 428, the lower sidewall 416, and the bottom surface 415. The depth of the lower cavity volume can be any depth shorter than the depth of the second substrate 470 in the X-axis direction (e.g., 50%, 75%, or 90% of the depth of the second substrate 470). The arrangement of the first and second substrates in Figure 4C is such that the resulting lower cavity partition 428 has a surface 405 that is inclined toward the first substrate 230 at an angle greater than 90 degrees with respect to the bottom surface 415.

[0073] A first substrate 230 (e.g., a single-crystal silicon wafer) including an upper cavity partition 224 that defines the upper cavity volume is directly bonded to a second substrate 470 (e.g., a single-crystal silicon wafer) including a lower cavity partition 428 that defines the lower cavity volume. The bonded first and second substrates form a cold plate in which the upper and lower cavity partitions alternate horizontally.

[0074] As shown in Figure 4C, an exemplary method for forming upper and lower cavity volumes includes etching a first substrate 230 to form an upper cavity volume, etching a second substrate 470 while maintaining the lower surface 415 to form a lower cavity volume, joining the first substrate 230 to the second substrate 470 with the etched surfaces facing back to back (for example, "inverting" the second substrate 470 after etching and joining it to the first substrate 230), and joining a third substrate 404 to the surface of the second substrate opposite to the first substrate 230 to form an integrated cooling assembly 403B.

[0075] The direct bonding of the cold plate to the third substrate, the fragmentation of the integrated cooling assembly 403B 46, and the formation of the opening 50 can be the same as described above in relation to Figure 4B, and are therefore omitted for brevity.

[0076] Figure 4D schematically shows an integrated cooling assembly 403C formed by Method 40 according to several embodiments. The integrated cooling assembly 403C in Figure 4D includes a first substrate 230 and a second substrate 480. The first substrate 230 corresponds to the upper part described above. The second substrate 480 is the substrate for the semiconductor device 204. The second substrate 480 may contain multiple dies intended to be pieced, such as the device 204.

[0077] Here, an anisotropic etching process is used to etch the upper cavity partition 224 into the first substrate 230. As described above in relation to Figure 4B, the upper cavity volume is etched by partially penetrating the first substrate 230. In Figure 4D, the lower cavity volume is etched by partially penetrating the second substrate 480 to form the lower cavity volume, which is determined by the lower cavity partition 430 and the etched back surface of the second substrate 480. The depth of the lower cavity volume can be any depth shorter than the depth of the second substrate 480 in the X-axis direction (e.g., 50%, 75%, or 90% of the depth of the second substrate 480). The arrangement of the first and second substrates in Figure 4D is such that the resulting lower cavity partition 430 has a surface 432 that is inclined toward the first substrate 230 at an angle greater than 90 degrees relative to the etched back surface of the second substrate 480.

[0078] A first substrate 230 (e.g., a single-crystal silicon wafer) including an upper cavity partition 224 that defines the upper cavity volume is directly bonded to a second substrate 480 (e.g., a single-crystal silicon wafer) including a lower cavity partition 430 that defines the lower cavity volume. The first and second substrates are bonded with their etched surfaces facing back to back (for example, the second substrate 480 is "inverted" after etching and bonded to the first substrate 230). The upper and lower cavity partitions alternate along the horizontal length to form a cold plate 426.

[0079] The steps for directly bonding the cold plate 426 to the third substrate, the step 46 for piecewise forming the integrated cooling assembly 403C, and the step 50 for forming the opening can be the same as those described above in relation to Figure 4B, and are therefore omitted for brevity.

[0080] In the embodiment shown in Figure 4D, the semiconductor device substrate itself is used to form the lower cavity partition and the lower cavity volume, which has the advantage that only a single substrate is required to form the cold plate.

[0081] In the integrated cooling assembly 403C of Figure 4D, the cold plate 426 is spaced apart from the semiconductor device 204, and collectively defines the coolant chamber volume between them. As described above, the cold plate 426 includes an upper part 230 having an upper cavity partition 224 that extends downward and defines the upper cavity volume. The back surface 220 of the semiconductor device 204 includes a lower cavity partition 430 that extends upward and defines the lower cavity volume. The upper cavity volume of the cold plate 426 and the lower cavity volume of the semiconductor device 204 define the coolant chamber volume between them. The upper cavity partition 224 and the lower cavity partition 430 alternate along the horizontal length of the cold plate 206, as described above.

[0082] Figure 4E schematically shows an integrated cooling assembly 403D formed by Method 40 according to several embodiments. The integrated cooling assembly 403D in Figure 4E includes a first substrate 490 and a second substrate 492, both of which include metal posts 494. That is, the first substrate 490 includes an upper metal post 494 extending downward toward the second substrate 492, and the second substrate 492 includes a lower metal post extending upward toward the first substrate 490. The first substrate 490 corresponds to the upper part described above, and the second substrate 492 corresponds to the lower part described above. The series of metal posts 494 will be understood to replace the cavity dividers described above in relation to other embodiments.

[0083] The series of metal posts 494 can be spaced apart to allow coolant to flow between them. For example, the metal posts 494 can be arranged in a pattern of M rows and N columns, where N and M are positive integers. Such embodiments further increase the heat transfer efficiency by further increasing the exposed surface area of ​​the cold plate 206. The metal posts may include, for example, aluminum or copper. The metal posts may have a cylindrical or rectangular cross-section. The metal posts may have the advantage of providing structural stability to the cold plate.

[0084] Metal posts can be formed within the first and second substrates. Around the metal posts within the first and second substrates, cavity volumes can be etched using an etching process with high selectivity for the metal posts. The cavity volumes can be etched to the depth of the first and second substrates, as described above in relation to the first and second substrates in Figure 4B.

[0085] As shown in Figure 4E, an exemplary method for forming upper and lower cavity volumes includes selectively etching a first substrate 490 to form a cavity volume around an upper metal post, selectively etching a second substrate 492 to form a cavity volume around a lower metal post, bonding the first substrate 490 to the second substrate 492 with the etched surfaces facing back to back (for example, "inverting" the second substrate 492 after etching and bonding it to the first substrate 490), and bonding a third substrate 404 to the surface of the second substrate opposite to the first substrate 230 to form an integrated cooling assembly.

[0086] The steps for directly bonding the cold plate 426 to the third substrate, the step 46 for piecewise forming the integrated cooling assembly 403D, and the step 50 for forming the opening can be the same as those described above in relation to Figure 4B, and are therefore omitted for brevity.

[0087] Figure 5 is a schematic side cross-sectional view of an example of a multi-component device package 501 including a cold plate 506 directly bonded to the back surface of two or more devices. As shown, the device package 501 includes a package substrate 502, an integrated cooling assembly 503, a package cover 208, and a sealing layer 522. The integrated cooling assembly 503 may include a plurality of devices 504A (one shown) that can be pieced and / or arranged in the form of a vertical device stack 504B (one shown), and a cold plate 506 that is attached to each of the devices 504A and the device stack 504B by, for example, the direct bonding method described herein. In some embodiments, the devices 504A may include a processor, and the device stack 504B may include a plurality of memory devices. Here, the devices 504A and the device stack 504B are arranged side by side on the package substrate 502 and are electrically in communication with each other through conductive elements formed within the package substrate 502, on the package substrate, or through the package substrate 502. Here, the cold plate 506 is sized to provide a bonding surface that adheres to both device 504A and device stack 504B, but in other respects it may be identical or substantially the same as other cold plates described herein. For example, here the cold plate 506 includes an upper part 530 including a top surface 509. From the top surface 509, an upper side wall 511 and an upper cavity partition 524 extend downward to define the upper cavity volume. The cold plate 506 further includes a lower side wall 516 and a lower cavity partition 526 that extend upward from device 504A and device stack 504B to define the lower cavity volume (for example, device 504A and device stack 504B define the respective lower portions of the coolant chamber volume 510). The upper cavity volume and the lower cavity volume together define the coolant chamber volume 510.Here, a second underfill layer 540 or other molding material, positioned in the lower part of the coolant chamber volume 510 and in the gap region between device 504A and device stack 504B, provides the lower part of the coolant chamber volume interposed between device 504A and device stack 504B.

[0088] A sealing layer 522 positioned between the cold plate 506 and the package cover 208 secures the cold plate 506 to the package cover 208, forming a coolant-impermeable barrier between them. The coolant circulates to the device package 501 through the inlet / outlet openings 212 of the package cover 208 and flows through the coolant chamber volume 510 via the opening 506A in the integrated cooling assembly 503 and the corresponding opening 522A formed through the sealing layer 522. Here, the sealing layer 522 can be formed of a polymer or epoxy molding material as described above, or a flexible adhesive layer such as a thermal interface material (TIM) layer.

[0089] The method described above advantageously enhances the efficiency of heat transfer from the back surface of the device to the coolant by increasing the turbulence of the coolant as it passes through the coolant chamber volume. By providing both upper and lower cavity volumes, the surface area of ​​the coolant chamber volume is increased, thereby improving the efficiency of heat transfer and the overall cooling of the device. Furthermore, the method described above provides a means for efficiently etching the cavity of a cold plate for a semiconductor device.

[0090] Cold plates and semiconductor devices can be formed from CTE-matched materials, eliminating the need for an intervening TIM layer. In some embodiments, integrated cooling assemblies and package covers can be formed from CTE-mismatched materials and bonded to each other by forming a sealing layer using a flexible material, or by using a decoupling adhesive layer placed between the sealing layer and the cold plate or package cover. Flexible materials can extend the useful life of the device package by absorbing the difference in linear expansion between the package cover and the cold plate during iterative thermal cycling.

[0091] The embodiments described above are illustrative and not intended to limit the scope. Those skilled in the art will understand that individual embodiments of the cooling assemblies, device packages, and methods described herein can be omitted, modified, combined, and / or rearranged without departing from the scope of this disclosure. Only the following claims are intended to limit the scope of this disclosure.

Claims

1. It is a device package, The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device, The cold plate includes an upper part and a lower part that is vertically adjacent to the upper part. The upper part includes an upper cavity partition that extends downward and defines the volume of the upper cavity, The lower part includes a lower cavity partition that extends upward and defines the volume of the lower cavity, The upper cavity partition and the lower cavity partition are arranged alternately along the horizontal length of the cold plate. Device package.

2. The upper cavity partition and the lower cavity partition are arranged along the horizontal length of the cold plate with a lateral gap between adjacent upper and lower cavity partitions. The device package according to claim 1.

3. The upper cavity partition is spaced horizontally at a first lateral interval across the upper part, and the lower cavity partition is spaced horizontally at a second lateral interval different from the first lateral interval across the lower part. The lateral spacing between the cavity partitions is greater than the horizontal width of the cavity partitions. The device package according to claim 1 or 2.

4. The upper part includes an upper surface attached to the upper side wall, and the upper side wall extends downward from the upper surface. A device package according to any one of claims 1 to 3.

5. The upper cavity partition extends downward from the upper surface to a depth substantially the same as the depth of the upper side wall. The device package according to claim 4.

6. The upper cavity partition extends between opposing sides of the upper side wall and defines the volume of the upper cavity. The device package according to claim 4 or 5.

7. The lower part includes a lower surface attached to the lower side wall, and the lower side wall extends upward from the lower surface. The aforementioned lower surface is attached to the back surface of the semiconductor device. A device package according to any one of claims 1 to 6.

8. The lower cavity partition extends upward from the lower surface to a depth substantially the same as the depth of the lower side wall. The device package according to claim 7.

9. The lower part includes a lower side wall extending upward from the back surface of the semiconductor device. The lower cavity partition is positioned on the back surface of the semiconductor device. A device package according to any one of claims 1 to 6.

10. The lower cavity partition extends upward from the back surface of the semiconductor device to a depth substantially the same as the depth of the lower side wall. The device package according to claim 9.

11. The lower cavity partition extends between opposing sides of the lower side wall and defines the volume of the lower cavity. A device package according to any one of claims 7 to 10.

12. The upper part includes an upper cavity separator that is installed between a pair of upper cavity partitions to define a section within the upper cavity volume. The lower part includes a lower cavity separator that is installed between a pair of lower cavity partitions to define a section within the lower cavity volume. A device package according to any one of claims 1 to 11.

13. The surface of the upper cavity partition is inclined toward the lower part at an angle greater than 90 degrees. A device package according to any one of claims 1 to 12.

14. The surface of the lower cavity partition is inclined toward the upper part at an angle greater than 90 degrees, or The surface of the lower cavity partition is inclined toward the upper part at an angle less than 90 degrees. A device package according to any one of claims 1 to 13.

15. The upper cavity partition is a series of first metal posts, and the lower cavity partition is a series of second metal posts. A device package according to any one of claims 1 to 14.

16. The upper part of the cold plate includes a package cover. The package cover has an inlet opening and an outlet opening that are positioned to penetrate the package cover, The upper cavity volume and the lower cavity volume collectively determine the coolant chamber volume between them. The volume of the coolant chamber is in fluid communication with the inlet opening and the outlet opening. A device package according to any one of claims 1 to 15.

17. The cold plate is attached to the semiconductor device using a flexible adhesive layer. A device package according to any one of claims 1 to 16.

18. The cold plate comprises a polymer material. A device package according to any one of claims 1 to 17.

19. Further equipped with a package substrate, The cold plate is placed on the package substrate, The semiconductor device is attached to the package substrate. A device package according to any one of claims 1 to 18.

20. The device package further comprises a sealing material layer surrounding the interface between the semiconductor device and the package substrate. The device package according to claim 19.

21. The integrated cooling assembly includes a plurality of semiconductor devices, and the cold plate is attached to the plurality of semiconductor devices. A device package according to any one of claims 1 to 20.

22. The aforementioned upper cavity partition defines two longitudinal upper cavity volumes, The aforementioned lower cavity partition defines three longitudinally lower cavity volumes perpendicular to the longitudinally upper cavity volume, The volume of the first lower cavity overlaps only with the volume of the first upper cavity. The volume of the second lower cavity overlaps only with the volume of the second upper cavity. The third lower cavity volume overlaps with both the first upper cavity volume and the second upper cavity volume. The device package according to claim 1.

23. It is a device package, The integrated cooling assembly includes a semiconductor device and a cold plate attached to the semiconductor device, The cold plate is spaced apart from the semiconductor device and collectively defines the cooling chamber volume between it and the semiconductor device. The cold plate includes an upper section having an upper cavity partition that extends downward and defines the upper cavity volume, The back surface of the semiconductor device includes a lower cavity partition that extends upward and defines the volume of the lower cavity. The upper cavity partition and the lower cavity partition are arranged alternately along the horizontal length of the cold plate. Device package.

24. A method for manufacturing a device package according to any one of claims 1 to 23, The method includes directly bonding a first substrate, which includes an upper cavity partition that defines the upper cavity volume, to a second substrate, which includes a lower cavity partition that defines the lower cavity volume, wherein the bonded first and second substrates form a cold plate in which the upper and lower cavity partitions are alternated horizontally, and the upper and lower cavity partitions are etched into the first and second substrates using an anisotropic etching process, and the method is A method further comprising directly bonding the cold plate to a third substrate including the semiconductor device.

25. The method according to claim 24, further comprising framing an integrated cooling assembly, including the semiconductor device and the cold plate, from the bonded first, second, and third substrates.

26. A package cover including an inlet opening and an outlet opening is sealed to the integrated cooling assembly using a material layer placed between the package cover and the integrated cooling assembly. Before or after attaching the package cover to the cold plate, an opening is formed in the material layer to allow fluid communication between the inlet opening and the outlet opening and the lower cavity volume and the upper cavity volume. The method according to claim 24, further comprising:

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