Wide-range switch-mode power amplifier architecture

Abstract

According to one embodiment, the power amplifier includes a plurality of switches and an output tank network. One or more of the plurality of switches are configured to generate one or more first intermediate waveforms having one or more first fundamental frequency components, and one or more of the plurality of switches are configured to generate one or more second intermediate waveforms by chopping one or more of the first intermediate waveforms at a controllable timing. The second intermediate waveforms have one or more second fundamental frequency components that are controllably reduced from the fundamental frequency components of one or more first intermediate waveforms. The output tank network is configured to filter one or more second intermediate waveforms to provide an output waveform having one or more third fundamental frequency components to the load. In some cases, all switches achieve zero-volt switching under different power and load conditions with resistive and reactive loads.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application asserts the interests under Section 119 of U.S. Provisional Patent Application No. 63 / 381,337, filed on 28 October 2022, which is incorporated herein by reference in its entirety. [Background technology]

[0002]

[0002] Switch-mode power amplifiers capable of handling a wide operating range, including resistive load ranges and reactive load ranges, and / or a wide range of power levels, are required for applications such as plasma generation, wireless power transfer, DC-DC converters, communications, battery chargers, induction heating, radio frequency (RF) welding, and RF power transmission. Furthermore, such switch-mode power amplifiers, also known as RF inverters, often need to provide a high control bandwidth (i.e., fast response speed) to changes in load and / or desired power levels. [Overview of the Initiative] [Problems that the invention aims to solve]

[0003]

[0003] Disclosed herein is a switch-mode power amplifier architecture that can efficiently and rapidly control RF power to a variable load impedance, including a load having variable resistive and reactant components. The architecture provides direct RF output voltage modulation for power control and further control means, such as frequency modulation, structural modulation, and phase-switched impedance modulation, to accommodate variations in load impedance. Output power control to a variable load can be achieved while maintaining zero-volt switching (ZVS) of all inverter power equipment, which is often important for high-frequency applications.

[0004]

[0004] The disclosed power amplifier architecture can be adapted to take advantage of other existing modulation methods, including input / drain voltage modulation, load modulation, out-of-phase modulation, and phase-switched impedance modulation. The disclosed wide-range power amplifier architecture provides the ability to perform high-speed response control of power over a wide range to variable load impedance. The disclosed embodiments are intended for DC-to-AC power conversion, but the general techniques may be further applied to AC-to-DC power conversion.

[0005]

[0005] The disclosed power amplifier architecture relates to a controlled-transform matching network technique that can be introduced in various circuit implementations and can be realized through various circuit implementations. As an example of the general concept that is intended to be protected herein, three circuits are described below: a wide-range voltage-mode Class D power amplifier (6-switch or 3-switch), a wide-range current-mode Class D power amplifier, and a wide-range Class E power amplifier, and other related variations may be similarly implemented while maintaining the technique.

[0006]

[0006] The amplifier architecture uses a version of phase control (or "inverse" phase control), hereafter referred to as β-modulation, as the main component for controlling the fundamental RF output amplitude. β-modulation applies one or more zero-state portions to an intermediate AC or DC waveform, including (e.g.) square wave, sinusoidal, and half-sine waveforms, thereby enabling control of the fundamental output. Unlike conventional topologies, the disclosed topology allows for direct output voltage modulation while maintaining zero-volt switching for all equipment and equipment transitions across a wide operating range. In some embodiments, dynamic frequency tuning (DFT) or other secondary control means (e.g., structural modulation or phase-switched impedance modulation) may be utilized to address load impedance variations. The wide control range and fast response capability are derived from the topology, β-modulation, and secondary control means (e.g., dynamic frequency modulation). In fact, the electrical angle β (where β) min <β<β max By introducing a zero state in the intermediate waveform, rapid control of RF power can be achieved over a wide range, including variable resistive and reactance components. Secondary control means (e.g., dynamic frequency tuning) may be used in conjunction with output tanks Ls and Cs to compensate for reactance fluctuations in the load while maintaining the ZVS of the inverter equipment. [Means for solving the problem]

[0007]

[0007] According to one aspect of the present disclosure, a power amplifier includes a plurality of switches and an output tank network. One or more of the plurality of switches are configured to generate one or more first intermediate waveforms having one or more first fundamental frequency components. One or more of the plurality of switches are configured to generate one or more second intermediate waveforms by chopping one or more of the first intermediate waveforms at a controllable timing, the second intermediate waveforms having one or more second fundamental frequency components that are controllably reduced from the fundamental frequency components of one or more first intermediate waveforms. The output tank network is configured to filter one or more second intermediate waveforms to provide an output waveform having one or more third fundamental frequency components to a load.

[0008]

[0008] In some embodiments, one or more switches may be configured to chop one or more first intermediate waveforms at a controllable timing determined by an electrical angle.

[0009]

[0009] In some embodiments, one or more of the plurality of switches may be configured to generate a first intermediate waveform, but different from one or more of the plurality of switches configured to generate one or more second intermediate waveforms. In some embodiments, one or more of the plurality of switches may be configured to generate one or more first intermediate waveforms, and one or more of the plurality of switches configured to generate one or more second intermediate waveforms include one or more switches in common.

[0010]

[0010] In some embodiments, the output tank network may include capacitors and inductors connected in series with the load.

[0011]

[0011] In some embodiments, the plurality of switches may include at least two switches. In some embodiments, at least two switches may be connected in series between the voltage source and ground. In some embodiments, the plurality of switches may include at least six switches. In some embodiments, the first three of the at least six switches may be connected in series between the voltage and ground, and at least three of the at least six switches may also be connected in series between the voltage and ground.

[0012]

[0012] In some embodiments, one or more first intermediate waveforms may include one or more square waves. In some embodiments, one or more second intermediate waveforms may include one or more square waves. In some embodiments, the output waveform may be a sine wave.

[0013]

[0013] In some embodiments, the power amplifier may include one or more inductive networks configured to provide zero-volt switching (ZVS) for a plurality of switches. In some embodiments, the one or more inductive networks may include an output tank network. In some embodiments, the one or more inductive networks may include an inductor connected in parallel with the output tank network. In some embodiments, the one or more inductive networks may include at least two inductive networks.

[0014]

[0014] In some embodiments, one or more switches may include at least two switches arranged as two inverter halves configured to operate out of phase in order to provide a second intermediate waveform obtained differentially between two inverter halves.

[0015]

[0015] In some embodiments, one or more second intermediate waveforms may include at least two coupled second intermediate waveforms such that the DC component cancels out the even harmonics of at least two second intermediate waveforms, and the fundamental components of at least two second intermediate waveforms are amplified to drive the load.

[0016]

[0016] According to one aspect of the present disclosure, the system includes the power amplifier described above and a controller configured to control a plurality of switches of the power amplifier.

[0017]

[0017] In some embodiments, the controller may be configured to use at least one of the following: frequency modulation to adjust for variations in the reactance of the load; frequency modulation to control the power, voltage or current delivered to the load; or beta modulation to control the power, voltage or current delivered to the load.

[0018]

[0018] It should be understood that individual elements of the various embodiments described herein can be combined to form other embodiments not specifically stated above. Various elements described in relation to a single embodiment may be further provided separately or in any preferred subcombination. It should be further understood that other embodiments not specifically described herein are also within the scope of the following claims.

[0019]

[0019] The methods for creating and using the disclosed subject matter can be understood by referring to the detailed descriptions associated with the drawings, where similar reference figures identify similar elements. [Brief explanation of the drawing]

[0020] [Figure 1]

[0020] This is a block diagram showing a wide-range switch-mode power amplifier system according to several embodiments. [Figure 2]

[0021] Figures 2A and 2B are configuration diagrams showing examples of 6-switch wide-range voltage mode Class D power amplifiers according to several embodiments. [Figure 3]

[0022] Figures 3A, 3B, and 3C are graphs showing modulated bipolar square wave waveforms that can be generated in a 6-switch wide-range voltage mode Class D power amplifier according to several embodiments. [Figure 4]

[0023] This is a series of graphs showing control sequences that may be used in a wide-range voltage-mode Class D power amplifier according to several embodiments. [Figure 5A]

[0024] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier according to several embodiments. [Figure 5B] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier according to several embodiments. [Figure 5C] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier according to several embodiments. [Figure 5D] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier according to several embodiments. [Figure 6]

[0025] Figures 6A and 6B are configuration diagrams showing examples of 3-switch wide-range voltage mode Class D power amplifiers according to several embodiments. [Figure 7]

[0026] Figures 7A, 7B, and 7C are graphs showing modulated unipolar square wave waveforms that can be generated within a 3-switch wide-range voltage-mode Class D power amplifier. [Figure 8]

[0027] This diagram shows a configuration of a 6-switch wide-range voltage mode Class D power amplifier including switch capacitance, according to several embodiments. [Figure 9]

[0028] Figures 9A, 9B, and 9C are graphs showing modulated bipolar square wave waveforms that can be generated in a 6-switch wide-range voltage mode Class D power amplifier including switch capacitance, according to several embodiments. [Figure 10]

[0029] This is a series of graphs showing control sequences that may be used with a wide-range voltage-mode Class D power amplifier including a switch capacitance, according to several embodiments. [Figure 10A]

[0030] This is a series of graphs showing additional control sequences that may be used with a wide-range voltage-mode Class D power amplifier including a switch capacitance, according to several embodiments. [Figure 11A]

[0031] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 11B] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 11C] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 11D] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 11E] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 11F] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 11G] This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 11H]This diagram shows the circuit operation of a 6-switch wide-range voltage mode Class D power amplifier, including switch capacitance, according to several embodiments. [Figure 12]

[0032] Figures 12A and 12B are graphs illustrating dynamic frequency modulation that can be used with wide-range switch-mode power amplifiers in several embodiments. [Figure 13]

[0033] This graph shows the relationship between power, beta (β), and resistive load. [Figure 14]

[0034] Figures 14A and 14B are graphs showing further relationships between power, β, resistive load, and reactive load. [Figure 15]

[0035] Figures 15A, 15B, and 15C are graphs showing modulated sinusoidal waveforms that can be used with wide-range switch-mode power amplifiers according to several embodiments. [Figure 16A]

[0036] This graph shows modulated half-sine waveforms that can be used with wide-range switch-mode power amplifiers in several embodiments. [Figure 16B] This graph shows modulated half-sine waveforms that can be used with wide-range switch-mode power amplifiers in several embodiments. [Figure 16C] This graph shows modulated half-sine waveforms that can be used with wide-range switch-mode power amplifiers in several embodiments. [Figure 16D] This graph shows modulated half-sine waveforms that can be used with wide-range switch-mode power amplifiers in several embodiments. [Figure 17]

[0037] Figures 17A and 17B are configuration diagrams showing examples of wide-range Class E power amplifiers without switch capacitance, according to several embodiments. [Figure 18A]

[0038] This figure shows a control sequence and a modulated half-sine waveform that can be used in conjunction with a wide-range Class E power amplifier that does not include switch capacitance, according to an embodiment. [Figure 18B] This figure shows a control sequence and a modulated half-sine waveform that can be used in conjunction with a wide-range Class E power amplifier including a switch capacitance, according to an embodiment. [Figure 19]

[0039] Figures 19A and 19B are configuration diagrams showing examples of wide-range current-mode Class D power amplifiers including switch capacitance, according to several embodiments. [Figure 20]

[0040] This is a series of graphs showing control sequences and modulated sinusoidal waveforms that can be used with wide-range current-mode Class D power amplifiers according to several embodiments. [Figure 21A]

[0041] This diagram illustrates how dynamic frequency tuning can be used to manage the effect of a load reactance that fluctuates by changing the operating frequency, according to several embodiments. [Figure 21B]

[0042] This diagram illustrates how phase-switch impedance modulation may be used to manage the effect of fluctuating load reactance by controlling switch S1, according to several embodiments. [Figure 21C]

[0043] This diagram illustrates how structural modulation can be used to manage the effect of fluctuating load reactance by controlling a switch, according to several embodiments. [Figure 21D]

[0044] This diagram illustrates how combinations of dynamic frequency tuning, phase-switch impedance modulation, and structural modulation may be used in several embodiments to manage the action of fluctuating load reactance by changing the operating frequency and controlling the switch. [Figure 22]

[0045] This is a configuration diagram showing an example of a wide-range voltage mode Class D power amplifier having multiple outputs, according to several embodiments. [Figure 23A]

[0046] This graph shows examples of square wave waveforms modulated in beta modulation using several control strategies. [Figure 23B] This graph shows examples of square wave waveforms modulated in beta modulation using several control strategies. [Figure 23C] This graph shows examples of square wave waveforms modulated in beta modulation using several control strategies. [Figure 23D] This graph shows examples of square wave waveforms modulated in beta modulation using several control strategies. [Figure 23E] This graph shows examples of square wave waveforms modulated in beta modulation using several control strategies. [Modes for carrying out the invention]

[0021]

[0047] The drawings are not necessarily to scale and do not include all elements of the system. Instead, the emphasis is generally on illustrating the concepts, structures, and techniques that are intended to be protected in this specification.

[0022]

[0048] Referring to Figure 1, the exemplary power amplifier system 100 has a DC voltage source 102 (V dc The system may include a load 104, a switch-mode power amplifier 106 coupled between the voltage source 102 and the load 104, and a controller 108 coupled to the amplifier 106. The power amplifier 106 may include one or more switches and other electronic components (e.g., capacitors and inductors) arranged in a specific circuit topology, detailed examples of which are described below in conjunction with several other figures.

[0023]

[0049] The controller 108 can operate the switches of the power amplifier 106 by one or more control sequences and using beta modulation as discussed in detail below. In some cases, the controller 108 can further implement secondary control schemes such as dynamic frequency modulation (i.e., changing the operating frequency of the power amplifier). More generally, the power, voltage, and / or current delivered to the load 104 may be controlled using beta modulation, frequency modulation, or both. The controller 108 may include hardware and / or software configured to implement the disclosed control schemes, and in some embodiments may be provided as an application-specific integrated circuit (ASIC). The disclosed power amplifier topology and control schemes enable a wide operating range, including a resistive load range, a reactive load range, and / or a wide range of power levels.

[0024]

[0050] In some embodiments, and as shown in Figure 1, the controller 108 may be configured to modify the β and / or frequency modulation of the amplifier 106 based on one or more inputs. For example, the controller 108 may be configured to receive commands via the signal path 110 to set the β and / or switching frequency to a desired value. In another example, the controller 108 may be configured to receive feedback from a load via the signal path 112 and modify the β and / or switching frequency based on the feedback. In some cases, the system 100 may include a VI probe or other type of sensor for measuring power, impedance, reactance, and / or other electrical characteristics of the load 104, and the output of such a sensor may be used to supply feedback to the controller 108. In yet another example, an adaptive feedback technique may be used to adjust the β and / or switching frequency.

[0025]

[0051] In some embodiments, the controller 108 may be configured to perform phase switch impedance modulation, structural modulation, or both, using the structures and techniques described below.

[0026]

[0052] Turning to FIGS. 2A and 2B, according to some embodiments, a wide voltage mode class D power amplifier architecture can have six switches for a double-ended (or "differential") version, or three switches for a single-ended version. The double-ended variant provides improved harmonic content at the output and, at the expense of a greater number of components, higher power performance than the single-ended variant.

[0027]

[0053] FIG. 2A shows an example of an inverter 200 according to a six-switch voltage mode class D power amplifier architecture. The load 202 is modeled as a series combination of a resistor R load and an inductor L load and is in series with a first inductor 204 (L s ) and a capacitor 206 (C s ). A second inductor 208 (L ZVS ) is used to achieve zero voltage switching of the switches, which will be described later. The inverter 200 further includes a set of six switches 210a-f (S 1~6 ) having a first set of three switches 210a, 210c, 210e (S1, S3, S5) arranged in series and a second set of three switches 210b, 210d, 210f (S2, S4, S6) arranged in series. A voltage source 220 (V dc ) may be connected as shown.

[0028] ​​The six switches 210a to f may be configured to generate one or more first intermediate waveforms having one or more fundamental frequency components. A subset of switches 210a to f may be configured to chop one or more first intermediate waveforms at a controllable timing to generate one or more second intermediate waveforms having fundamental frequency components that have been controllably reduced from the fundamental frequency components of the first intermediate waveforms.

[0029]

[0055] As shown in the figure, the first voltage v a1 This may be defined between the node connecting switches 210a and 210c (S1, S3) and ground, and the second voltage v b1 This may be defined between the node connecting switches 210b and 210d (S2, S4) and ground, and the third voltage v a2 This may be defined between the node connecting switches 210c and 210e (S3, S5) and ground, and the fourth voltage v b2 This may be defined between the node connecting switches 210d, 210f (S4, S6) and ground. In this configuration, the first intermediate waveform is v ab1 (v a1-b1 )=v a1 -v b1 It can be considered as such, and the second intermediate waveform is v ab2 (v a2-b2 )=v a2 -v b2 It can be considered as such. In other words, v a1 , v b1 , and v ab1 Both are sometimes referred to as the first intermediate waveform, v a2 , v b2 , and v ab2 Both are sometimes referred to as the second intermediate waveform.

[0030]

[0056] Load 202, first inductor 204(L s ), and capacitor 206(C sThese are sometimes collectively referred to as "load branches." In the architecture of Figure 2A, the load branches are close to ground (i.e., they can be connected to ground by a single switch 210e or 210f). In contrast, Figure 2B shows a version of the 6-switch inverter 240, where the load branches are connected to the voltage source 220 (V dc ) is in close proximity to (i.e., by a single switch 210e or 210f) dc (It can be connected to...). Similar elements in Figures 2A and 2B are indicated using the same reference numerals.

[0031]

[0057] Inverter 200 in Figure 2A and inverter 240 in Figure 2B have a voltage v ab1 (v a1-b1 )=v a1 -v b1 However, it may be controlled so that it is ideally a square wave as shown in Figures 3A-C, and in practice approximately trapezoidal as shown in Figures 9A-C. In the figures, v ab1 =v a1 -v b1 and v ab2 =v a2 -v b2 As shown, the phase control angle β has a non-zero duration or duty cycle that depends on β, and the voltage v a1-b1 A phase-controlled (or "chopped") waveform v based on ab2 (v a2-b2 )=v a2 -v b2 It is used to create the following. In other words, β controls the chopping from the first intermediate waveform 302 to the second intermediate waveform 304. a2-b2 Basic component v a2-b2_1st This is controlled by β, which provides a means for controlling the RF output power. In the case of an ideal square wave, v a1-b1 and v a2-b2The rise and fall times of are instantaneous, and β has a usable range of 0° to 180°. The fundamental wave of the second intermediate waveform 304 is filtered by a load branch (or “output tank network”) to produce a sinusoidal output 306. In this and other examples disclosed herein, the output tank is L s and C s This consists of the following. Graphs 300, 320, and 340 show examples for three different control angles β.

[0032]

[0058] A 6-switch wide-range voltage-mode Class D power amplifier is related to a full-bridge voltage-mode Class D power amplifier, but utilizes additional switches to achieve a wide output control range while maintaining efficient operation.

[0033]

[0059] Figure 4 shows the control sequence (switch function) of the 6 switches. Here, the switching function state of (1) indicates that the switch is ON, and the state of (0) indicates that the switch is OFF. Graphs 400a to 400f show the respective switches 210a to f (S) in Figures 2A and 2B. 1~6 The control sequences 402a to f for each of the following are shown.

[0034]

[0060] As shown, S1 and S2 can operate in a complementary manner (e.g., ideally) (i.e., ignoring downtime). In the first half-cycle, S1, S4, and S6 are on. S3 is also energized during the first part of the first half-cycle, but turns off at the control angle β, at which point S5 is turned on and energized (ignoring downtime), while S3 is off. In the second half-cycle, S2, S3, and S5 are held on. S4 is energized during the first part of the second half of the cycle, but turns off at β+180°, at which point S6 is turned on (again, ignoring downtime between S4 and S6).

[0035]

[0061] The circuit operation over this time interval is shown in Figures 5A to 5D. As shown in Figure 5A, with switches S1, S3, S4, and S6 turned on, between 0° and β, v a1 =v a2 =V dc , v b1 =v b2 = 0. As shown in Figure 5B, with switches S1, S4, S5, and S6 turned on, between β and 180°, v a1 =V dc , v a2 =0, v b1 =v b2 = 0. As shown in Figure 5C, with switches S2, S3, S4, and S5 turned on, between 180° and β+180°, v a1 =v a2 =0, v b1 =v b2 =V dc As shown in Figure 5D, with switches S2, S3, S5, and S6 turned on, between β+180° and 360°, v a1 =v a2 =0, v b1 =V dc , v b2 = 0

[0036]

[0062] Other related 6-switch variations providing similar control capabilities may be similarly realized. For example, consider inverter 240 in Figure 2B, where load branches are connected between four top switches. The two top switches are S5 and S6 (210e and 210f), and the four bottom switches are S3, S4, S1, S2 (210c, 210d, 210a, 210b). a2-b2 is, v a1-b1 (v ab1 )=v a1 -v b1 This is a modulated waveform, and here, v a2-b2 (v ab2 )=v a2 -v b2 Furthermore, C s , L s , L load , and R loadis the voltage between both ends of the load branch, and v a1-b1 is the voltage across the inductor L ZVS . Using the control sequence of FIG. 4, the circuit in FIG. 2B further includes v shown in FIG. 3 a1 -v b1 can be modulated as v a2 -v b2 .

[0037]

[0063] A three-switch "single-ended" version of the wide-voltage-mode class D power amplifier may also be constructed as shown in FIGS. 6A and 6B. This implementation creates a unipolar square wave at voltage v1 and a modulated "rectangular" waveform with a different duty ratio at voltage v2

[0038]

[0064] FIG. 6A shows an example of an inverter 600 by a three-switch voltage-mode class D power amplifier architecture. The load 602 is connected in series with a first inductor 604 (L s ) and a first capacitor 606 (C s ). A second inductor 608 (L ZVS ) is used to achieve zero-voltage switching of the switches. The inverter 600 further includes three switches 610a, 610c, 610e (S1, S3, S5) arranged in series as shown. A voltage source 620 (V dc ) may be connected as shown. The inverter 600 may further include second and third capacitors 612a, 612b (C ZVS ) for voltage-second balance of L big .

[0039]

[0065] As shown in the figure, the first voltage v1 may be defined between the node connecting the switches 610a, 610c (S1, S3) and the ground, and the second voltage v2 may be defined between the node connecting the switches 610c, 610e (S3, S5) and the ground. In this arrangement, v1 may correspond to the first intermediate waveform and v2 may correspond to the second intermediate waveform

[0040]

[0066] In the architecture of Figure 6A, the load branch is close to ground. In contrast, Figure 6B shows a version of the 3-switch inverter 640, where the load branch is connected to the voltage source 620 (V dc It is adjacent to ). Similar elements in Figures 6A and 6B are indicated using the same reference numerals.

[0041]

[0067] As shown in Figures 7A and 7C, inverter 600 in Figure 6A and inverter 640 in Figure 6B may be controlled so that the voltage v1 is (ideally) a square wave. As shown, the phase control angle β is used to create a phase-controlled (or "chopped") waveform v2 having a non-zero duration or duty cycle dependent on β. In other words, β controls the chopping from the first intermediate waveform 702 to the second intermediate waveform 704. The fundamental wave of the second intermediate waveform 704 is filtered by the output tank to produce a sinusoidal output 706. Graphs 700, 720, and 740 show examples for three different control angles β.

[0042]

[0068] The 3-switch "single-ended" version of the circuit allows for power control using fewer switches, but it can introduce even-order harmonics into the output voltage waveform, potentially resulting in lower load power.

[0043]

[0069] The control sequences 400, 420, and 440 in Figure 4 can be used to control a 3-switch inverter, such as inverter 600 in Figure 6A or inverter 640 in Figure 6B. That is, the 6-switch version uses all 6 control sequences, while the 3-switch version may use only the sequences corresponding to, for example, S1, S3, and S5.

[0044]

[0070] The following is an analysis of a wide range of switch-mode power amplifiers as disclosed herein. The analysis is presented herein with respect to a 6-switch topology, but the subject matter to be protected herein is extended to several other switch topologies, including, but not limited to, a 3-switch topology.

[0045]

[0071] In the waveforms of Figures 3A to 3C, v a2-b2 The peak amplitude and phase of the k-th harmonic may be calculated as follows:

[0046]

number

[0047] Here, v a2-b2_1st Therefore, the harmonic order k is equal to 1. k is an odd number. a2-b2 The corresponding equation in the fundamental wavetime domain is v a2-b2_1st =|V1|cos(ωt+φ1).

[0048]

[0072] If β = π,

number

[0049]

[0073] The average load power due to the k-th harmonic component may also be calculated as follows:

number

[0050] Here, ω is the operating frequency, and |V k | may be calculated from equation (1). In a high-quality output filter tank, the average load power P may be approximated to the basic power P1.

[0051]

[0074] Given resistive load R loadFor this reason, different values ​​of β will result in different voltages being applied to the load, and therefore to different load powers. Given R load For the power range P min ~P max To maintain the β range β min ~β max There is a specific DC voltage V. dc So, β min ≤β ≤β max For this, the range P from minimum power to maximum power. min ~P max The minimum and maximum load resistance values ​​R are the limits to achieve this. min and R max There is.

[0052]

[0075] High-quality coefficient output tank L s , C s Given that, output tank L s , C s and load inductance L load The switching frequency that allows the net series reactance resulting from this to achieve the desired value is such that β and the power range (R min ~R max The circuit may be selected to depend only on resistive loads (within a certain range). In this way, similar circuit operation and waveforms can be maintained for a given resistive component of the load impedance, regardless of the load reactance. That is, frequency modulation may be used so that the net reactance produced by the tank and load becomes some desired value. Techniques for frequency selection / modulation are described in detail below. Further techniques for achieving a wide operating range are also described in detail below.

[0053]

[0076] Moving on to Figure 8, in some practical applications, the switch is at a voltage v a1-b1 and v a2-b2 It can be non-ideal in that it cannot rise and fall instantaneously. For example, a switch has a capacitance C in parallel with the switch. sw It has an output capacity that can be modeled as follows.

[0054]

[0077] The illustrated inverter 800 is connected to a second inductor 808 (L) to achieve zero-volt switching of the switch. ZVS ) along with the first inductor 804 (L) connected in series with load 802. s ) and the first capacitor 806(C s ) includes. Inverter 800 has each capacitor 810a~f(C sw1~6 ) and six switches 810a~f(S) in parallel 1~6 ) further includes. Voltage source 820(V dc The connections may be as shown. The switch may be operated, for example, using the control sequence in Figure 10.

[0055]

[0078] Switch capacity C sw1~6 As a result, the circuit voltage waveform has a finite rise and fall time. To avoid switching losses at high frequencies, zero-volt switching (ZVS) may be implemented such that the switch voltage remains low when the equipment is turned off, and the equipment is only turned on when the voltage across the equipment is low. Thus, in some cases, each switch can be turned on and off by zero-volt switching, even though a modulated output waveform is supplied. Some variations for ZVS switching in the circuit of Figure 8 involve the second inductor 808 (i.e., LVS inductor L) ZVS It depends on the load series branch (L). Otherwise, it depends on the load series branch (L). s , C s , L load , and R load ) depends on the net inductance. ZVS for this second group of transitions may also be carried out by an additional inductive reactance branch (not shown) placed in parallel with the load series branch.

[0056]

[0079] Figures 9A-C show the waveforms that can be generated inside the inverter 800 in Figure 8. Graphs 900, 920, and 940 show examples for three different control angles β, with the first intermediate waveform 902, the second intermediate waveform 904, and the sinusoidal output 906 plotted in each graph. The modulation variable β is in the range of δ1 to 180°-δ2. ab1 =v a1- v b1 and v ab2 =v a2 -v b2 In Figure 8, L ZVS The following are related to the ZVS switch voltage transition times δ1 and δ'1 in Figures 9A-C, and the net inductance from the series branch of the load is related to the ZVS switch voltage transition times δ1 and δ2 in Figures 9A-C.

[0057]

[0080] The switch capacitance (C) shown in Figure 8 sw1~6 ), the voltage v shown in Figure 9 a1-b1 and v a2-b2 For the finite rise and fall times of v, a1-b1 The voltage rise time δ1 and fall time δ'1 (expressed in electrical angles) may be specified. δ1 and δ'1 may be the same or different, and do not need to depend heavily on the load application conditions. a2-b2 The rise time is v as δ1. a1-b1 Following this, the descent time δ2 depends on the load application conditions.

[0058]

[0081] v a1-b1 , v a2-b2 and v a2-b2_1st The actual waveform is shown in Figures 9A to 9C. Since there are non-zero rise / fall times δ1 and δ2, |V k | and φ k These are as follows:

[0059]

number

[0060]

number

[0061] In the above equation, |V k | and φ k These are, respectively, v a2-b2 This represents the peak amplitude and phase of the k-th harmonic. k is an odd number.

[0062]

[0082] v a2-b2 The corresponding equation in the fundamental wave time domain is as follows:

number

[0063] Here, |V k | and φ1 are the amplitude and phase according to equations (4) and (5), respectively.

[0064]

[0083] The average load power due to the k-th harmonic component may also be calculated as follows:

number

[0065] Here, ω is the operating frequency, and |V k | is given by equation (4).

[0066]

[0084] Figure 10 shows a control sequence that may be used for a wide-range voltage mode Class D power amplifier including switch capacitance, such as the inverter 800 in Figure 8. Figures 11A to 11H show the circuit operation of such an amplifier. In Figure 10, graphs 1000a to 1000f show six switches S with capacitance. 1~6 The control sequences 1002a to f for this are shown.

[0067]

[0085] As shown in Figure 11A, with switches S3 and S6 turned on, between 0° and δ1, v a1 =v a2 , v b2 = 0. As shown in Figure 11B, with switches S1, S3, S4, and S6 turned on, between δ1 and β, va1 =v a2 =V dc , v b1 =v b2 = 0. As shown in Figure 11C, with switches S1, S4, and S6 turned on, between β and β+δ², v a1 =V dc , v b1 =v b2 = 0. As shown in Figure 11D, with switches S1, S4, S5, and S6 turned on, between β+δ2 and 180°, v a1 =V dc , v a2 =0, v b1 =v b2 = 0. As shown in Figure 11E, with switches S4 and S5 turned on, between 180° and 180°+δ1, v a2 =0, v b1 =v b2 As shown in Figure 11F, with switches S2, S3, S4, and S5 turned on, between δ1+180° and β+180°, v a1 =v a2 =0, v b1 =v b2 =V dc As shown in Figure 11G, with switches S2, S3, and S5 turned on, between β+180° and β+δ2+180°, v a1 =v a2 =0, v b1 =V dc As shown in Figure 11H, with switches S2, S3, S5, and S6 turned on, between β + δ² + 180° and 360°, v a1 =v a2 =0, v b1 =V dc , v b2 = 0

[0068]

[0086] In comparison with Figure 4, the control sequences 1002a-f in Figure 10 include a downtime between switches to allow zero-volt switching: S5 turns off under ZVS, and S1 turns on with a delay angle δ1. During the downtime interval 0 < ωt < δ1, v a1 =va2 is, i ZVS By charging C5, V dc It increases to, and as a result S1 can perform ZVS turn-on, which can be confirmed in Figure 11A. Furthermore, during this time interval, i ZVS A discharge occurs from C4, and as a result, S4 can perform ZVS turn-on. S3 is still off at β, but S5 turns on with a downtime delay δ2. During this downtime delay, as shown in Figure 11C, C5 is i load This discharges S5, allowing it to perform the ZVS turn-on. (As previously mentioned, an additional inductive branch (not shown in Figure 8) in parallel with the output network branch can also supply current for ZVS switching.) The turn-off of S1 and S5 maintains invariance without delay compared to the idealized case. The other three switches S2, S4, and S6 operate 180° out of phase with switches S1, S3, and S5, respectively. In Figure 10, as in the control sequence in Figure 4, the AND of S3 and S5 is S2, while the AND of S4 and S6 is S1, which is similar to that using ZVS Class D full-bridge operation.

[0069]

[0087] Input DC voltage V dc Given , an example is 0~ωL load、max Load range R including the reactance component min ~R max For the output power range P min ~P max It is desirable to achieve this. (Maximum C load、max The capacity component for a load represented by its equivalent capacity can also be considered in a similar manner. ) For example, V dc =300V, P min =300W, P max =3000W, 4x resistive load range, i.e., R max / R min =4, reactive load components from j0Ω to +j15Ω, and load branching (C) determined by considerations of waveform purity and / or frequency range. s , Ls , R load , and L load Let's consider an example where the quality factor Q of ) is between 5 and 20. dc =300V and power range P min =300W~P max =3000W, series branch (L s , C s , L load and R load ) vs Q min =5, and the center frequency f c Given a frequency of 13.56MHz, the parameters may be determined as follows.

[0070]

[0088] Figure 10A shows a further control sequence that may be used for a wide-range voltage mode Class D power amplifier including switch capacitance, such as the inverter 800 in Figure 8. In Figure 10A, graphs 1020a-f show six switches S with capacitance. 1~6 The control sequences 1022a to f for this are shown. In contrast to the control sequence in Figure 10, the control sequences 1022a to f in Figure 10A include an additional downtime between switches, i.e., a delay angle δ3. This results in 10 different operating regions labeled (a) to (j) in Figure 10A.

[0071]

[0089] The disclosed wide-range power amplifier architecture can maintain ZVS for all inverter equipment across all load and power conditions, which means that the switch capacitance C during idle times δ1, δ2, and δ3. sw to i zvs and i load This is achieved by charging and discharging.

[0072]

[0090] Modeling i zvs and i load This may be important for predicting the ZVS condition. zvs The voltage across both ends of L is approximately a square wave (although it has non-zero rise and fall times, as can be seen in Figure 5), zvsThe current flow through it is a nearly symmetrical triangular waveform, which can be represented as follows:

[0073]

number

[0074] Herein lies the following:

number

[0075]

[0091] As long as the quality factor Q of the load branch is sufficiently high, for example, Q=5, the load current i load This can be expressed as follows:

[0076]

number

[0077] Herein lies the following:

number

[0078] |V1| is, for example, a fundamental component according to equation (1).

[0079]

[0092] Zero Voltage Shift (ZVS) can be important for high-frequency and ultra-high-frequency power conversion. In actual voltage-mode Class D power amplifiers, the control sequence has idle time, as seen in Figures 10 and 10A, so that the switch capacitance can be charged and discharged without loss, and as a result the switch can turn on at zero volts. In some cases, three idle times δ1, δ2, and δ3 may be considered in a wide-range voltage-mode Class D power amplifier.

[0080]

[0093] For δ1, let's consider the commutation of current from S5 to S1 while S3 is held ON. In δ1, v a1 =v a2 iZVS and i load The combination is C sw5 Charge it, C sw1 Discharge it. a1 =v a2 =V dc In this case, S1 turns on at zero volts. a1 =v a2 Assuming v1(t) = v1(t), the following holds:

[0081]

number

[0082] Herein lies the following:

number

[0083]

[0094] Using integration in δ1, we obtain the following:

[0084]

number

[0085]

[0095] The exact solution may also be derived from the following.

[0086]

number

[0087]

[0096] In δ1, from equations (8) and (9), i ZVS (ωt)≒i ZVS (0) = -I ZVS、pk , and, i load (ωt)≒i load (0) = I load、pk cos(φ1-φ load For ), the linear approximation can be as follows:

[0088]

number

[0089]

[0097] C sw1 =C sw5 =C sw (That is, assuming equal effective switch capacitances), it becomes as follows.

[0090]

Number

[0091] Here, |V1| may be calculated from Equation (1) without considering the dead time for simplicity.

[0092]

[0098] Next, it becomes as follows.

[0093]

Number

[0094]

[0099] For ZVS turn-on in S1, as long as I ZVS、pk >I load、pk cos(φ1 - φ load ), there are no requirements regarding the current direction of i load . δ1 is almost independent of the load.

[0095]

[0100] Regarding δ2, consider the current commutation from S3 to S5 while S1 is held on. i load charges C sw3 and discharges C sw5 . When v a2 = 0, S5 turns on at zero volts. Assuming v a2 = v2(t), it becomes as follows.

[0096]

Number

[0097] Here, it is as follows.

Number

[0098]

[0101] Using integration in δ2, it becomes as follows.

[0099]

Equation

[0100]

[0102] An exact solution can be derived from the following.

[0101]

Equation

[0102]

[0103] In δ2, from equations (8) and (9), i load (ωt) ≈ i load (β) = I load、pk cos(β + φ1 - φ load ), the linear approximation can be as follows.

[0103]

Equation

[0104]

[0104] Similarly, it is as follows.

[0105]

Equation

[0106] Here, again, it is assumed that all switch capacitances are equal.

[0107]

[0105] For the ZVS turn-on of S5, i load (β) must be positive. δ2 is load-independent.

[0108]

[0106] Regarding δ3, consider the current commutation from S1 to S3 while S5 is held on. i ZVS charges C sw1 and discharges C sw3 va1 When = 0, S3 turns on at zero volts. v a1 Assuming = v3(t), it is as follows.

[0109]

Number

[0110] Here, it is as follows.

Number

[0111]

[0107] Using integration in δ3, it becomes as follows.

[0112]

Number

[0113]

[0108] The exact solution can be derived from the following.

[0114]

Number

[0115]

[0109] In δ3, from equations (8) and (9), i ZVS (ωt) ≈ i ZVS (π) = I ZVS、pk Regarding, the linear approximation can be as follows.

[0116]

Number

[0117]

[0110] Similarly, it is as follows.

[0118]

Number

[0119]

[0111] During the ZVS turn-on of S3, i in δ3 load There are no requirements for (t) at all. δ3 is completely load-independent.

[0120]

[0112] In practice, δ1 and δ3 may overlap or encompass each other. a1 The rise and v b1 The decline can occur simultaneously. a1 The descent and v b1 The rise in the other can also occur simultaneously.

[0121]

[0113] The following describes techniques for frequency selection / modulation. Inductive L shown in Figure 8 load , or capacitive C load Because there may be a variable reactive load, the operating frequency is determined by the net reactance X formed by the output tank and load reactance constants. net It may be chosen to keep it constant.

[0122]

number

[0123] Here, X with respect to inductive loading load =ωL load And, or, X for capacitive load load = -1 / ωC load That is. ω c This is the angular center frequency, for example, 2π × 13.56 MHz. The operating frequencies are as follows:

[0124]

number

[0125] Here, ω c L net =ω c L s -1 / ω c C s =Xnet This is used to achieve ZVS on the switch. load and C load The frequency selections under these conditions are shown in Figures 12A and 12B, respectively.

[0126]

[0114] Figures 12 and 12A show constant X net Different L load and C load This shows dynamic frequency modulation under L. In Figure 12A, graph 1200 is L load As a function of, the operating frequency is 1202 and the impedance is X net Plot 1204. In Figure 12B, graph 1220 is C load As a function of frequency 1222 and impedance X net Plot 1224.

[0127]

[0115] The average power due to the k-th harmonic component is given by equation (7) as follows:

[0128]

number

[0129] Here, we are interested in the main component of the average power P1. By selecting the operating frequency as equation (27), P1 in equation (28) is L load or C load It is invariant with respect to R, load It depends on the following. Furthermore, due to high-quality filtering from the output tank, the shape of the problematic operating waveform is determined by a given R. load It remains the same for the other party.

[0130]

[0116] Other modulation methods can be used for the series load branching shown in Figures 21A to 21D, or other frequency selection criteria may be used.

[0131]

[0117] Moving on to Figure 13, first, X netIt can be considered as =0Ω, and this means that the inductive X net along with i load This should apply when the switch's ZVS is realized using an additional ZVS inductive branch placed in parallel with the output network branch, instead of using the k-th harmonic component. The average power due to the k-th harmonic component is as follows:

[0132]

number

[0133]

[0118] Assuming δ1=0 and δ2=0, |V in equation (4) k | becomes equation (1), and the average power due to the k-th harmonic component is as follows.

[0134]

number

[0135]

[0119] Since the quality factor is sufficiently high, if we consider only the basic power, it will be as follows.

[0136]

number

[0137]

[0120] P1, β, and R load The relationship between them is shown in Figure 13 by (31). Figure 13 is X net Power P1, β, and resistive load R when =0, δ1=0, and δ2=0. load This shows the relationship. Figure 13 shows R, which has the maximum power range. max This is equal to 24Ω. In graph 1300, β is plotted by lines 1302 and 1306, and power is plotted by lines 1304 and 1308.

[0138]

[0121]

number

[0139]

[0122] Output load branch (L s , C s , L load , R load The quality factor obtained from equation (32) is Q min It will be higher than =5 and will satisfy the requirement. In some cases, L s and C s This may be selected according to a conservative design with respect to the quality factor.

[0140]

[0123] Moving on to Figures 14A and 14B, given known variables and requirements, X net Taking this into consideration, as shown in equation (7), the powers P1, β, and R load The relationship between X can be plotted. Figures 14A and 14B show X net Power, β, and R, considering δ1 and δ2. load This shows the relationship between them. Graph 1400 in Figure 14A shows the relationship between different β and R according to equation (7). load This shows the power range for a given R. load However, the maximum power range, for example, R load = 1Ω and R load It can be understood that achieving =25Ω is not possible. min =3Ω and R max = 20Ω. Graph 1420 in Figure 14B shows different Rload Under this, the achievable power range for β within the limit is shown. A single point is, for example, different L using dynamic frequency modulation. load This can be obtained from simulations that take this into consideration.

[0141]

[0124] Moving on to Figures 15A to 15C, sine waves or half-sine waves can also be modulated, as can ideal square waves or quasi-square waves, and unipolar square waves which can be modulated or switched as shown in Figures 3, 9, and 7. This can be seen in Figures 15A to 15C for modulated sine waves and in Figures 16A to 16D for modulated half-sine waves in the ideal case where the descent time at β is instantaneous. Modulated half-sine waves have another degree of freedom, where the half-resonance period may be less than or greater than 180°, but modulated sine waves must have a half-resonance period less than 180°. This also applies to square waves and unipolar square waves in 6-switch wide-range voltage-mode Class D power amplifiers and 3-switch wide-range voltage-mode Class D power amplifiers, respectively.

[0142]

[0125] Figures 15A to 15C show modulated sinusoidal waveforms that can be used with a wide-range switch-mode power amplifier according to several embodiments. Graphs 1500, 1520, and 1540 show examples for three different control angles β with respect to a first intermediate waveform 1502, a second intermediate waveform 1504, and a sinusoidal output 1506 plotted in each graph. In Figures 15A to 15C, D × 180° = 180° - 2δ, 0 < β - δ ≤ D × 180°; v ab1 =v a1 -v b1 and v ab2 =v a2 -v b2 That is the case.

[0143]

[0126] Figures 16A to 16D show modulated half-sine waveforms that can be used with a wide-range switch-mode power amplifier according to several embodiments. Graphs 1600, 1620, 1640, and 1660 show examples for three different control angles β with respect to a first intermediate waveform 1602, a second intermediate waveform 1604, and a sinusoidal output 1606 plotted in each graph. In these figures, 0 <D<1および0<β≦(1-D)×360°;v ab1 =v a1 -v b1 and v ab2 =v a2 -v b2 In Figure 16A, (1-D)×360°>180°. In Figure 16B, (1-D)×360°>180°. In Figure 16C, (1-D)×360°<180°. In Figure 16D, (1-D)×360°<180°.

[0144]

[0127] In Figures 16A to 16D, the circuits for achieving waveform modulation may be wide-range Class E power amplifiers such as amplifier 1700 in Figure 17A and / or amplifier 1720 in Figure 17B. In Figures 15A to 15C, the circuits for achieving β-modulation may be wide-range current-mode Class D power amplifiers such as amplifier 1900 in Figure 19A and / or amplifier 1920 in Figure 19B. These are single-ended and double-ended concepts described with respect to wide-range voltage-mode Class D inverters, and at the same time represent the related single-ended and double-ended converter concepts, respectively.

[0145]

[0128] In reality, v2 cannot reach zero instantaneously, and the switch has a switch capacitance C sw It has a similar function to Figures 9 and 11, v a2-b2 And a ZVS turn-off compatible switch for v2 may be implemented.

[0146]

[0129] Figures 18A and 18B show a control sequence and a modulated half - sine waveform where, for 0 < D < 1 and 0° < β ≤ (1 - D)×360°, the graph 1800 in Figure 18A corresponds to the ideal case of the circuit in Figure 17A, and for 0 < D < 1 and 0° < β ≤ (1 - D)×360° - γ, the graph 1820 in Figure 18B corresponds to the actual case of the circuit in Figure 17B.

[0147]

[0130] An example of the circuit operation of a wide - range class - E power amplifier is that C1 and L1 together with the AND of S1 and S2 first form a load - independent half - sine wave v1, and then S1 and S2 modulate v1 to v2. Through the series load branches L s , C s , L load , and R load , the load can obtain different power levels based on different duty ratios D, β, and γ (related to the non - operating time). Figures 18A and 18B show the control sequence and the modulated half - sine waveform in simulations using the ideal and practical wide - range class - E power amplifiers shown in Figures 17A and 17B, for the case of L1 = 109.55 nF, C1 = 740 pF, C sw = 20 pF, L s = 1.17 μF, C s = 117 pF.

[0148]

[0131] As part of the operating function of this technique, variable power can be achieved for a given resistive load, or constant power can be achieved for a variable resistive load. Dynamic frequency modulation may be used to handle the no - load situation.

[0149]

[0132] An example of the circuit operation of a wide - range current - mode class - D power amplifier is that C <> p and L p together with the AND of S1 and S3 and the AND of S2 and S4 first form a load - independent sine wave v a1_b1 , and then the four switches modulate v ab1 (v a1-b1 ) = v a1 - v b1 to vab2 (v a2-b2 )=v a2 -v b2 This involves modulation. Series load branch L s , C s , L load , and R load Through this, the load can acquire different power levels based on different duty cycles D and β (ignoring idle time). In Figure 20, graph 2000 shows the simulation using an ideal wide-range current-mode Class D power amplifier shown in Figures 19A and 19B, L p =97.8nF, C p =978pF, C sw = 0.1pF, L s =3.35μF, C s The control sequence and modulated sinusoidal waveform for the case of =46.94pF are shown.

[0150]

[0133] As part of the operational capabilities of this method, variable power can be realized for a given resistive load, or constant power can be realized for a variable resistive load. Dynamic frequency modulation may be used to deal with reactive loads.

[0151]

[0134] Figures 21A to 21D illustrate additional or alternative structures and techniques for handling / managing fluctuating load reactance according to embodiments of the present disclosure. By managing fluctuations in the reactance component of the load impedance, constant frequency operation may be possible in the variable load reactance phase. As discussed previously, dynamic frequency tuning can be used as an example to manage the behavior of fluctuating load reactance. This is a series load branch C s , L s , L load , and R load The circuit 2100 in Figure 21A relates to the output tank L. s , C s and load inductance L load The net series reactance resulting from this is the desired value X netA switching frequency may be selected to achieve this. As another example, phase-switch modulation may be used, as shown by circuit 2120 in Figure 21B. As yet another example, structural modulation (in the form of a switching network) may be used, as shown by circuit 2140 in Figure 21C. As yet another example, a combination of these techniques (e.g., phase-switch modulation combined with structural modulation) may be used, as shown by circuit 2160 in Figure 21D. In some cases, the load branching may further be parallel branching, or a combination of series and parallel branching.

[0152]

[0135] Moving on to Figure 22, general concepts, structures, and techniques to be protected herein for a wide-range power amplifier having multiple outputs may be provided. An exemplary wide-range voltage-mode Class D power amplifier 2200 has load branches 2204~n a1 and v b1 It includes N sets of four switches 2202a~n arranged in parallel. Each set 2202a~n is v as shown in Figures 3A~3C. a1-b1 Modulated waveform v a2-b2_n It is possible to generate each v a2-b2_n Its basic component v a2-b2_n_1st are the same or different C s_n , L s_n , L load_n , and R load_n For the same or different series load branches that have [the same or different characteristics], they may be the same or different.

[0153]

[0136] Similarly, other broad-range circuits, including 6-switch voltage-mode Class D power amplifiers (Figures 2A, 2B, and 8), 3-switch voltage-mode Class D power amplifiers (Figures 6A and 6B), current-mode Class D power amplifiers (Figures 19A and 19B), and Class E power amplifiers (Figures 17A and 17B), can also have multiple outputs.

[0154]

[0137] Generally, as β modulation suggests, different zero-state portions or more zero-state portions, as shown in Figures 23A to 23E, v a1-b1 ni v a2-b2 It may be applied as follows. Graphs 2300, 2320, 2340, 2360, and 2380 show five different examples of β modulation, with the first intermediate waveform 2302 and the second intermediate waveform 2304 plotted on each graph. Different modulated or chopped v a2-b2 , and from the corresponding β allocation, further, the basic component v a2-b2_1st And the corresponding load power can be calculated.

[0155]

[0138] Publication "Wide-range switched-mode power amplifier architecture," 2023 IEEE 24th Workshop on Control and Modeling for Power Electronics (COMPEL), Ann Arbor, MI, USA, 2023, pp. 1-9, by Xin Zan, Khandoker Nuzhat Rafa Islam, and David Perreault. The entire publication is incorporated here by reference.

[0156]

[0139] As used herein, the terms “processor” and “controller” are used to describe an electronic circuit configuration that performs a function, operation, or sequence of operations. The function, operation, or sequence of operations may be hardcoded in the electronic circuit or softcoded by instructions held in a memory device. The function, operation, or sequence of operations may be performed using digital values ​​or analog signals. In some embodiments, the processor or controller may be implemented in an application-specific integrated circuit (ASIC), which may be an analog ASIC or a digital ASIC, in a microprocessor with associated program memory, in a digital signal processor (DSP), and / or in a separate electronic circuit, which may be analog or digital. The processor or controller may include an internal processor or module that performs a portion of the function, operation, or sequence of operations. Similarly, a module may include an internal processor or internal module that performs a portion of the module’s function, operation, or sequence of operations.

[0157]

[0140] As used herein, the term “predetermined” when referring to a value or signal is used to refer to a value or signal that is set or fixed at the factory during manufacturing or thereafter by external means, for example, by programming. As used herein, the term “predetermined” when referring to a value or signal is used to refer to a value or signal that is identified after manufacturing by the operating circuit.

[0158]

[0141] In this specification, the electronic circuits shown in the figures may be shown in the form of analog blocks or digital blocks, but it will be understood that analog blocks may be replaced by digital blocks that perform the same or similar functions, and that digital blocks may be replaced by analog blocks that perform the same or similar functions. It should be understood that conversions from analog to digital or from digital to analog may not be explicitly shown in the figures.

[0159]

[0142] In the preceding detailed descriptions, various features are grouped together in one or more individual embodiments for the purpose of streamlining the present disclosure. This method of the present disclosure should not be construed to reflect the intention that each claim requires more features than are explicitly stated in each claim. Rather, the aspect of inventiveness lies in fewer features than all the features of each disclosed embodiment combined.

[0160]

[0143] The use of the terms “one embodiment,” “embodiment,” “several embodiments,” or variations of such terms in this disclosure indicates that the described embodiments may include certain features, structures, or characteristics, but all embodiments may include certain features, structures, or characteristics. Furthermore, such terms do not necessarily refer to the same embodiments. Moreover, when certain features, structures, or characteristics are described in the relevant knowledge of the art to affect such features, structures, or characteristics in relation to other embodiments, whether or not they are explicitly described.

[0161]

[0144] The disclosed subject matter is not limited to its application to structural details or arrangement of components as specified in the following description or shown in the drawings. The disclosed subject matter is adaptable to other embodiments and can be practiced and implemented in various ways. A person skilled in the art will therefore understand that the concepts on which this disclosure is based can be readily used as a basis for designing other structures, methods, and systems to accomplish some of the purposes of the subject matter of this disclosure. Accordingly, the claims should be deemed to include such equivalent structures, as long as they do not deviate from the spirit and scope of the disclosed subject matter.

[0162]

[0145] Although the disclosed subject matter has been described and illustrated in the exemplary embodiments described above, it is understood that this disclosure is provided only as an example, and that many changes in the details of the implementation of the disclosed subject matter can be made without departing from the spirit and scope of the disclosed subject matter.

[0163]

[0146] All publications and references cited herein are explicitly incorporated herein by reference in their entirety.

Claims

1. Multiple switches, One or more of the aforementioned switches are configured to generate one or more first intermediate waveforms having one or more first fundamental frequency components. One or more of the plurality of switches are configured to generate one or more second intermediate waveforms by chopping one or more first intermediate waveforms at a controllable timing, wherein the second intermediate waveform has one or more second fundamental frequency components that are controllably reduced from the fundamental frequency components of the one or more first intermediate waveforms. Multiple switches, An output tank network configured to filter the one or more second intermediate waveforms in order to provide the load with an output waveform having one or more third fundamental frequency components, A power amplifier equipped with the following features.

2. The power amplifier according to claim 1, wherein one or more switches are configured to chop one or more first intermediate waveforms at a controllable timing determined by an electrical angle.

3. The power amplifier according to claim 1, wherein one or more of the plurality of switches configured to generate the first intermediate waveform is different from one or more of the plurality of switches configured to generate one or more second intermediate waveforms.

4. The power amplifier according to claim 1, wherein one or more of the plurality of switches are configured to generate one or more first intermediate waveforms, and one or more of the plurality of switches configured to generate one or more second intermediate waveforms include one or more switches in common.

5. The power amplifier according to claim 1, wherein the output tank network comprises a capacitor and an inductor connected in series with the load.

6. The power amplifier according to claim 1, wherein the plurality of switches includes at least two switches.

7. The power amplifier according to claim 6, wherein at least two of the switches are connected in series between a voltage source and ground.

8. The power amplifier according to claim 1, wherein the plurality of switches includes at least six switches.

9. The power amplifier according to claim 8, wherein three of the at least six switches are connected in series between voltage and ground, and at least three of the at least six switches are also connected in series between voltage and ground.

10. The power amplifier according to claim 1, wherein the one or more first intermediate waveforms include one or more square waves.

11. The power amplifier according to claim 1, wherein the one or more second intermediate waveforms include one or more square waves.

12. The power amplifier according to claim 1, wherein the output waveform is a sine wave.

13. The power amplifier according to claim 1, comprising one or more inductive networks configured to achieve zero-volt switching (ZVS) for the plurality of switches.

14. The power amplifier according to claim 13, wherein the one or more inductive networks include the output tank network.

15. The power amplifier according to claim 13, wherein the one or more inductive networks include an inductor connected in parallel with the output tank network.

16. The power amplifier according to claim 13, wherein the one or more inductive networks include at least two inductive networks.

17. The power amplifier according to claim 1, comprising at least four switches arranged as the two inverter halves, the one or more switches configured to operate out of phase to provide a second intermediate waveform differentially acquired between the two inverter halves.

18. The power amplifier according to claim 1, wherein the one or more second intermediate waveforms include the coupled at least two second intermediate waveforms such that the DC component and the even harmonics of at least two second intermediate waveforms cancel each other out, and the fundamental components of the at least two second intermediate waveforms are amplified to drive the load.

19. A power amplifier, Multiple switches, One or more of the aforementioned switches are configured to generate one or more first intermediate waveforms having one or more first fundamental frequency components. The plurality of switches are configured such that one or more of the plurality of switches generate one or more second intermediate waveforms by chopping one or more first intermediate waveforms at a controllable timing, and the second intermediate waveform has one or more second fundamental frequency components that are controllably reduced from the fundamental frequency components of the one or more first intermediate waveforms. An output tank network configured to filter one or more second intermediate waveforms in order to provide a load with an output waveform having one or more third fundamental frequency components, A power amplifier including, A controller configured to control the plurality of switches A system equipped with these features.

20. The aforementioned controller Frequency modulation for adjusting the fluctuations in the reactance of the load, Frequency modulation for controlling the power, voltage, or current delivered to the aforementioned load, or The system according to claim 19, configured to use at least one of beta modulation for controlling the power, voltage, or current delivered to the load.

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