Management of conductive connections for semiconductor devices

Abstract

A system, device, and method for managing conductive connections for semiconductor devices are provided. In one embodiment, the method includes the steps of providing an integrated structure comprising an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, wherein at least a portion of at least one polysilicon layer is located on the conductive connection structure; etching at least a portion of at least one polysilicon layer to expose one or more conductive connections in the conductive connection structure; depositing an insulating material on the array structure and the conductive connection structure; and forming conductive vertical interconnect accesses (VIA) that penetrate the insulating material to contact one or more conductive connections and conductive layers in the array structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and manufacturing processes of semiconductor devices.

Background Art

[0002] Semiconductor devices, such as memory devices, can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers within a similar footprint. However, as more layers are stacked in the same area, it can be difficult to manage conductive connections between different components and / or with external devices or components.

Summary of the Invention

Problems to be Solved by the Invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing conductive connections for semiconductor devices, such as 3D memory devices.

Means for Solving the Problems

[0004] One aspect of the present disclosure is a method comprising the steps of providing an integrated structure including an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, wherein at least a part of at least one polysilicon layer is over the conductive connection structure; etching at least a part of at least one polysilicon layer to expose one or more conductive connections in the conductive connection structure; depositing an insulating material over the array structure and the conductive connection structure; and forming a conductive vertical interconnect access (VIA) that penetrates the insulating material to contact the one or more conductive connections and a conductive layer.

[0005] In some embodiments, the step of forming a conductive via includes etching an insulating material to expose one or more conductive connections in a conductive connection structure together with a portion of the conductive layers in an array structure, and depositing a conductive material on one or more conductive connections in the conductive connection structure and a portion of the conductive layers in an array structure to form a conductive via, wherein each conductive via is bonded to a corresponding one of the one or more conductive connections and portions of the conductive layers.

[0006] In some embodiments, one or more conductive connection parts within a conductive connection structure and a portion of the conductive layer within an array structure are exposed together during etching of the insulating material.

[0007] In some embodiments, the method further includes the steps of depositing a conductive pad layer on a conductive via; depositing at least one cover layer on the conductive pad layer; and forming one or more pad openings penetrating at least one cover layer to expose one or more corresponding portions of the conductive pad layer.

[0008] In some embodiments, the method further includes the step of depositing a dielectric layer on a conductive pad layer, wherein the dielectric layer is located between the conductive pad layer and at least one cover layer. The step of forming one or more pad openings may include the step of etching at least one cover layer and the dielectric layer to form the corresponding pad openings.

[0009] In some embodiments, the conductive pad layer comprises a first conductive material, and the conductive via comprises a second conductive material different from the first conductive material.

[0010] In some embodiments, the conductive via and the conductive pad layer are formed in the same process by depositing the same conductive material.

[0011] In some embodiments, at least one polysilicon layer comprises multiple portions, at least a portion of the at least one polysilicon layer is a first portion of the at least one polysilicon layer, and a second portion of the at least one polysilicon layer rests on an array structure. The steps of providing the integrated structure may include etching the second portion of the at least one polysilicon layer to expose multiple strings of memory cells and gate lines between adjacent groups of strings in the array structure, and forming a conductive layer over a first region, wherein the conductive layer is in contact with the end faces and gate lines of the multiple strings of memory cells.

[0012] In some embodiments, the end faces and gate lines of multiple strings of memory cells form a uniform surface. In some embodiments, the end faces and gate lines of multiple strings of memory cells form a non-uniform surface.

[0013] In some embodiments, the step of forming a conductive via includes forming a conductive via that penetrates an insulating material so as to be in contact with a portion of the conductive layer above the gate wire.

[0014] In some embodiments, the step of etching at least a portion of at least one polysilicon layer includes the step of etching the entirety of at least a portion of at least one polysilicon layer within the etching region. The first and second regions may be arranged along a first direction, and one or more conductive connectors may extend along a second direction perpendicular to the first direction. The etching region may have first and second opposite edges along the first direction, the first edge may extend to the edge of the plane of the integrated structure, and the second edge may extend to the edge of the second region. The etching region may have an etching depth from top to bottom along the second direction, and the distance between the top surface of the etching region and each end face of one or more conductive connectors in the conductive connector structure is less than or equal to the etching depth. The etching depth may be determined based on the etching time.

[0015] In some embodiments, the step of depositing insulating material on an array structure and a conductive connection structure includes depositing insulating material between adjacent conductive connections within the conductive connection structure and on conductive layers within the array structure. The method may further include polishing the surface of the deposited insulating material after the step of depositing insulating material on the array structure and the conductive connection structure.

[0016] In some embodiments, the insulating material comprises tetraethyl orthosilicate (TEOS), and the step of depositing the insulating material may include the step of performing boundary field oxide (BFOX) insulation.

[0017] Another aspect of the present disclosure features a semiconductor device comprising: an array structure including conductive layers coupled to a plurality of strings of memory cells; a conductive connection structure located separately from the array structure, comprising a plurality of conductive connection portions; and a conductive pad layer disposed above the array structure and the conductive connection structure, wherein the conductive pad layer comprises a plurality of conductive pads coupled to a portion of the conductive layer and each of the plurality of conductive connection portions via corresponding conductive vias. The plurality of conductive connection portions are separated by an insulating material filled within the conductive connection structure.

[0018] In some embodiments, the corresponding conductive vias are separated and insulated by an insulating material filled between the conductive pad layer, the array structure, and the conductive connection structure.

[0019] In some embodiments, no conductive material is present between the conductive connection structure and the array structure. In some embodiments, no conductive material is present between multiple conductive connection portions within the conductive connection structure.

[0020] In some embodiments, the connection angle between the conductive pad layer and at least one of the conductive vias is about 90 degrees.

[0021] In some embodiments, the array structure and the conductive connection structure are integrated on a first die. The semiconductor device may further include a second die integrated with the first die, and at least one of a plurality of conductive connection parts may be coupled to a control circuit in the second die.

[0022] In some embodiments, the semiconductor device further includes a cover layer on top of the conductive pad layer. The cover layer may include a plurality of pad openings on top of a plurality of conductive pads in the conductive pad layer, and each of the plurality of conductive pads may be coupled to at least one of the corresponding conductive vias.

[0023] Further aspects of the present disclosure feature a system comprising a memory device and a controller coupled to the memory device and configured to control the memory device. The memory device includes an array structure comprising conductive layers coupled to a plurality of strings of memory cells; a conductive connection structure located separately from the array structure, wherein the conductive connection structure comprises a plurality of conductive connection portions, the plurality of conductive connection portions being separated by an insulating material filled within the conductive connection structure; and a conductive pad layer disposed above the array structure and the conductive connection structure, wherein the conductive pad layer comprises a plurality of conductive pads coupled to a portion of the conductive layer and each of the plurality of conductive connection portions via corresponding conductive vias.

[0024] In some embodiments, the memory device further includes a plurality of conductive interconnects that penetrate a cover layer above the conductive pad layer to contact a plurality of conductive pads within the conductive pad layer, with each of the plurality of conductive pads coupled to at least one of the corresponding conductive vias. A controller can be coupled to the memory device via at least one of the plurality of conductive interconnects.

[0025] Implementations of the present disclosure can provide one or more of the following technical advantages and / or benefits. For example, in some implementations, as one or more final steps of forming a 3D memory device, the 3D memory array and peripheral circuits are conductively coupled to conductive pads for coupling to external components or devices. The techniques implemented herein can manage the conductive connections of 3D memory devices to simplify processing steps, improve etching calibration accuracy, reduce the number of machines used, and reduce manufacturing costs. For example, the present technology can omit a number of process steps (e.g., atomic layer deposition (ALD), oxide deposition, metal removal, through-surface contact (TSC) etching) compared to conventional methods, thereby accelerating the manufacturing process, saving manufacturing costs, and improving manufacturing accuracy and yield.

[0026] In some implementations, for example, the top to bottom polysilicon of the conductive connection structure and the array structure is pre-removed so that the conductive connection structure and the array structure can be processed using the same mask for patterning and / or deposition to form conductive vias and conductive pads together. Further, when the bottom polysilicon is removed, there is no leakage between the conductive connections in the conductive connection structure and silicon (Si), eliminating the problems of through-substrate contact (TSC)-Si leakage and burnout. Further, processing the conductive connection structure and the array structure together increases the processing window. Thus, these techniques can enhance reliability, simplify the manufacturing process, improve pad-coupled input / output (I / O), reduce manufacturing costs, and improve the performance of semiconductor devices and systems.

[0027] In some embodiments, for example, after the gate-induced drain leakage (GIDL) loop process is completed, the bottom polysilicon is directly removed to open the conductive connection using an embedded shallow trench isolation (BSTI) etching process with low requirements for exposure accuracy in patterning and / or etching, and there is no need to perform backside deep trench ringing (BDTI) for isolation. Therefore, these techniques can greatly liberate or increase the processing window and improve pad-coupled input / output. Since the process does not require BDTI insulation, there is no tungsten (W) residue problem, which can reduce W dishing.

[0028] In some embodiments, due to the small aspect ratio of BSTI, TEOS can be used to fill the opening area, replacing the ALD process, eliminating the need to etch back and remove Ti residues, and significantly reducing costs and cycle time. In some embodiments, a metal such as tungsten W can be filled into the trench to form a conductive via, and aluminum (Al) can be easily deposited on the conductive via to form a conductive pad.

[0029] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims.

[0030] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate embodiments of the disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable one skilled in the art to make and use the disclosure.

Brief Description of the Drawings

[0031] [Figure 1] A cross-sectional view of a semiconductor device according to one or more embodiments of this disclosure.

[0032] [Figure 2]This is a flowchart illustrating an exemplary process for forming a semiconductor device according to one or more embodiments of the present disclosure. [Figure 3A] This is a cross-sectional view of the structure of a semiconductor device at various stages of the manufacturing process according to one or more embodiments of the present disclosure. [Figure 3B] This is a cross-sectional view of the structure of a semiconductor device at various stages of the manufacturing process according to one or more embodiments of the present disclosure. [Figure 3C] This is a cross-sectional view of the structure of a semiconductor device at various stages of the manufacturing process according to one or more embodiments of the present disclosure. [Figure 3D] This is a cross-sectional view of the structure of a semiconductor device at various stages of the manufacturing process according to one or more embodiments of the present disclosure. [Figure 3E] This is a cross-sectional view of the structure of a semiconductor device at various stages of the manufacturing process according to one or more embodiments of the present disclosure. [Figure 3F] This is a cross-sectional view of the structure of a semiconductor device at various stages of the manufacturing process according to one or more embodiments of the present disclosure. [Figure 3G] This is a cross-sectional view of the structure of a semiconductor device at various stages of the manufacturing process according to one or more embodiments of the present disclosure. [Figure 4] This is a block diagram of an exemplary system having one or more semiconductor devices according to one or more embodiments of the present disclosure. [Modes for carrying out the invention]

[0033] Similar reference numbers and symbols in various drawings refer to the same elements. It should also be understood that the various exemplary implementations shown in the drawings are merely illustrative and not necessarily drawn to scale.

[0034] Figure 1 shows a cross-sectional view of a semiconductor device 100 according to one or more embodiments of the present disclosure. In some implementations, the semiconductor device 100 is a 3D memory device (e.g., a NAND flash memory device). In some implementations, the semiconductor device 100 is an intermediate structure, and one or more post-processing steps can be performed on the intermediate structure to form a 3D memory device. The semiconductor device 100 can be formed as described in more detail, for example, in Figures 2 and 3A to 3G. For convenience of explanation, Figure 1 shows two cross-sectional views of the semiconductor device 100 in Figure (a) and Figure (b). Figure (a) shows a cross-sectional view of the semiconductor device 100 in the XZ plane, and Figure (b) shows a cross-sectional view of the semiconductor device 100 in the YZ plane. The two Figures (a) and (b) are separated by a dashed line in Figure 1.

[0035] In some implementations, as shown in Figure 1, the semiconductor device 100 includes two dies 110 and 120 facing each other and joined, for example, via a junction layer 102 between them. In the semiconductor device 100, die 120 includes an array structure 130 having a memory cell array which can be called an array die 120, and die 110 includes a peripheral circuit (or control circuit) 114 which can be called a peripheral die 110. The array structure 130 can be formed on the front of the array die 120, and the peripheral circuit 114 can be formed on the front of die 110. The array structure 130 and the peripheral circuit 114 can be electrically coupled to each other by a conductive junction pad 104 (for example, made of a conductive material such as metal) in the junction layer 102. In some examples, the peripheral circuit 114 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the peripheral die 110 is also called a CMOS die 110.

[0036] In some embodiments, the semiconductor device may include a plurality of array dies (e.g., array die 120) and CMOS dies (e.g., CMOS die 110). The plurality of array dies and CMOS dies may be stacked and bonded to each other. The CMOS die may be bonded to each of the plurality of array dies, and each of the plurality of array dies may be driven to operate similarly to the semiconductor device 100. The semiconductor device 100 can be any suitable device. In some examples, the semiconductor device 100 includes at least a first wafer and a second wafer bonded facing each other. The array die 120 may be arranged on the first wafer together with other array dies, and the CMOS die 110 may be arranged on the second wafer together with other CMOS dies. The first wafer and the second wafer can be bonded to each other, and thus the array dies on the first wafer can be bonded to the corresponding CMOS dies on the second wafer. In some examples, the semiconductor device 100 is a chip in which at least the array die 120 and the CMOS die 110 are bonded to each other. In one example, the chips are diced from wafers that are bonded together. In another example, the semiconductor device 100 is a semiconductor package containing one or more semiconductor chips assembled on a package substrate.

[0037] In some implementation configurations, the CMOS die 110 includes a substrate 112, and peripheral circuits 114 are formed on the substrate 112. The substrate 112 can be any suitable semiconductor substrate having any suitable semiconductor material such as single crystal, polycrystalline, or monocrystalline semiconductors. For example, the substrate 112 can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. The substrate 112 can be a bulk wafer or an epitaxial layer. For simplicity, the main plane of the substrate 112 is called the XY plane, and the direction perpendicular to the main plane is called the Z direction. The peripheral circuits 114 can include one or more logic and / or circuits, including address decoding circuits, page buffer circuits or sense amplifiers, data buffers, data I / O circuits, voltage generators, control logic, etc.

[0038] In some implementations, the array die 120 includes a) an array structure 130 and a connection structure 140 in a first region 101, and b) a conductive connection structure 150 in a second region 103. The second region 103 may also be called a connection region, where one or more conductive connections are located to connect the array structure 130 and / or the connection structure 140 to peripheral circuits 114 and / or external components, circuits, and / or devices. The array structure 130 is adjacent to the connection structure 140 in the first region 101. For example, the connection structure 140 may be an extension of the array structure 130. The first region 101 and the second region 103 can be adjacent to each other, for example, as shown in Figure 1. The boundary 141 of the connection structure 140 can be considered the boundary of the first region 101 and / or the boundary of the second region 103.

[0039] The array structure 130, the connection structure 140, and the conductive connection structure 150 can be formed within the substrate, for example, as shown in more detail in Figure 3A. The substrate may be a semiconductor substrate similar to or the same as substrate 112, for example. The substrate can be thinned and at least partially removed during the formation of the semiconductor device 100. For example, the connection structure 140 may include the remaining portion 144 of the substrate.

[0040] As shown in Figure 1, the array structure 130 may include multiple vertical memory cell strings 136, such as 3D NAND memory cell strings, along the Z direction. The array structure 130 may also include multiple alternating pairs of conductive layers (or word lines) 132 and insulating layers 134. The conductive layer 132 may include a metallic material, such as tungsten W, and the insulating layer 134 may include a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The vertical memory cell strings 136 penetrate the conductive layers 132 and insulating layers 134 and are connected to corresponding bit lines 131. The vertical memory cell strings 136 may include either an insulator / trap or trap / insulator combination, or either polysilicon only or polysilicon / insulator combination, within the vertical channel along the Z direction. In some examples, the vertical memory cell string 136 includes multiple layers OX / SIN / OX(ONO) 136a that can be formed on the inner surface of the vertical channel and polysilicon 136b that can be filled in the center of the vertical channel. The outer surface of the vertical channel is in contact with a conductive layer 132 that functions as a gate for the memory cells of the vertical memory cell string 136.

[0041] In some embodiments, the array structure 130 includes gate lines 133 between a plurality of vertical memory cell strings 136. The gate lines 133 are configured to isolate adjacent memory blocks. While forming the array structure 130, the gate lines 133 can be used as channels for etching the sacrificial layer and filling with conductive material to form a conductive layer 132. In some embodiments, for example, as shown in Figure 1, the gate lines 133 have a size (e.g., diameter or width) larger than the size (e.g., diameter or width) of the memory cell strings 136. The array structure 130 may further include a conductive layer 135 formed on the end faces of the plurality of vertical memory cell strings 136 and the gate lines 133, for example, as a common source line (CSL). The common source line can be conductively coupled to an external device (e.g., an external power supply or external control signal) via, for example, a corresponding conductive via 154c and a corresponding conductive pad 164c. The conductive layer 135 can be made of polysilicon or metal. A protective layer 137 can be formed on the conductive layer 135. The protective layer 137 may include an insulating material such as a dielectric material such as silicon nitride or an oxide.

[0042] In some embodiments, for example, as shown in Figure 1, the end faces of the multiple vertical memory cell strings 136 and gate lines 133 form a non-uniform surface, for example, the end face of the gate line 133 may be lower than the end face of the multiple vertical memory cell strings 136. Since the gate line 133 may have a larger size than the vertical memory cell strings 136, the end face of the gate line 133 may have a larger area than the end face of the vertical memory cell strings 136. Therefore, the conductive via 154c can be formed on a portion of the conductive layer 135 on the end face of the gate line 133, which is easier to pattern and deposit to form the conductive via 154c, for example, as described in more detail with respect to Figures 3E to 3F. In some embodiments, the end faces of the multiple vertical memory cell strings 136 and gate lines 133 form a uniform surface. For example, a layer of conductive material can be deposited on the end faces of the multiple vertical memory cell strings 136 and gate lines 133, and then the layer of conductive material can be polished from a non-uniform surface, for example, as shown in Figure 1, to a uniform surface. The polished layer of conductive material forms the conductive layer 135. In this case, the conductive via 154c can be formed on any portion of the conductive layer 135 on a uniform surface.

[0043] The connection structure 140 is used to facilitate the fabrication of conductive connections to, for example, the gates of memory cells in a vertical memory cell string 136 and the gates of selected transistors. The gates of memory cells in a vertical memory cell string 136 correspond to word lines for a NAND memory architecture. The connection structure 140 is configured to conductively connect the conductive layer 132 (or word line) to corresponding contact pads (e.g., at the bottom of the connection structure) by, for example, through-array contacts (TAC) and / or stepped contacts (SCT), and further to a control circuit (e.g., peripheral circuit 114 in a CMOS die 110) via, for example, a conductive bonding pad 104.

[0044] In some embodiments, the connection structure 140 includes a channel structure 142. The channel structure 142 can be cylindrical or pillar-shaped. The channel structure 142 can have the same structure as the vertical memory cell string 136, and the channel structure 142 and the vertical memory cell string 136 can be formed by the same process. In some examples, the channel structure 142 includes multiple layers OX / SIN / OX(ONO) that can be formed on the inner surface of the vertical channel and polysilicon that can be filled in the center of the vertical channel. The channel structure 142 can be a stop line, and the metal layer is not connected to the channel structure 142.

[0045] In some embodiments, the array die 120 is configured to include one or more back metal layers on the back surface of the array die 120. The back metal layers can be used to provide a pad structure and / or routing paths. For example, as shown in Figure 1, the array die 120 includes a pad layer 160 having a plurality of conductive pads 164a, 164b, 164c (commonly referred to as conductive pads 164, and individually referred to as conductive pads 164). The conductive pads 164 can be separated by an insulating material 122 (e.g., oxide) within the pad layer 160. The conductive pads 164 can be formed to facilitate the attachment of bonding wires that can conductively couple the conductive pads 164 to external components or devices, such as power supplies, grounds, other semiconductor devices, or metal wires on a printed circuit board (PCB).

[0046] In some embodiments, as shown in Figure 1, for example, the array die 120 includes one or more cover layers on top of the pad layer 160, such as an insulating layer 162, a dielectric layer 170 (for example, made of silicon nitride), and a protective layer 172. Multiple pad openings 174 can be formed through one or more cover layers, so that the conductive pads 164 are bonded to external components by bonding wires passing through the pad openings 174.

[0047] As described above, in the second region 103 of the array die 120, the conductive connection structure 150 includes a plurality of conductive connection portions 152a, 152b (generally referred to as conductive connection portion 152, and individually as conductive connection portion 152) configured to conductively couple to peripheral circuits 114 (e.g., via bonding conductive pads 104) and / or conductive layers 132 in the array structure 130 (e.g., via connection structures 140). As shown in Figure 1, the conductive connection portions 152 may be through-substrate contacts (TSCs). The conductive connection portions 152a, 152b can couple to corresponding conductive pads 164a, 164b via corresponding conductive vias 154a, 154b in the second region 103. The conductive vias 154a, 154b, 154c can generally be referred to as conductive via 154, and individually as conductive via 154. The conductive vias 154a and 154b in the second region 103 and the conductive via 154c in the first region 101 can be formed using the same process steps, for example, as will be described in more detail in Figures 3D to 3F. As will be described in more detail below, the bottom polysilicon can be removed from the second region 103, and a large processing window can be obtained to form the conductive via 154. In some embodiments, the connection angle between the conductive pad 164 and the conductive via 154 is approximately 90 degrees.

[0048] In some embodiments, the conductive via 154 and the conductive pad 164 are made of different materials; for example, the conductive via 154 can be made of tungsten (W) and the conductive pad 164 can be made of aluminum (Al). The conductive via 154 and the conductive pad 164 can be formed in separate process steps. In some embodiments, the conductive via 154 and the conductive pad 164 are made of the same material, for example, W, Al, or any suitable conductive material, and the conductive via 154 and the conductive pad 164 can be formed in the same process steps.

[0049] The array die 120 includes insulating material 122 filled in different components. For example, the conductive via 154 is separated and insulated by the insulating material 122 filled between the conductive pad layer 160, the array structure 130, and the conductive connection structure 150. Conductive material may not be present between the conductive connection structure 150 and the array structure 130. Conductive material may not be present between the conductive connection portions 152 within the conductive connection structure 150.

[0050] Figure 2 is a flowchart of an exemplary process 200 for forming a semiconductor device (e.g., semiconductor device 100 in Figure 1) according to one or more embodiments of the present disclosure. Figures 3A to 3G show cross-sectional views of the structure of the semiconductor device (e.g., semiconductor device 100 in Figure 1) at various stages of the manufacturing process (e.g., process 200 in Figure 2) according to one or more embodiments of the present disclosure. Process 200 will be described below with reference to the structures shown in Figures 3A to 3G. Note that, as with Figure 1, for illustrative purposes, each of Figures 3A to 3G includes two cross-sectional views of the corresponding structure in Figure (a) and Figure (b), respectively. Figure (a) shows a cross-sectional view of the corresponding structure in the XZ plane, and Figure (b) shows a cross-sectional view of the corresponding structure in the YZ plane. The two Figures (a) and (b) are separated by a dashed line in each of Figures 3A to 3G.

[0051] In step 202, an integrated structure is provided. The integrated structure may include an array structure in a first region and a conductive connection structure in a second region adjacent to the first region.

[0052] For example, as shown in Figure 3A, an integrated structure 300a can be formed by joining a peripheral die 310 (e.g., peripheral die 110 in Figure 1) and an array die 320 (e.g., array die 120 in Figure 1) via a bonding layer 302 (e.g., bonding layer 102 in Figure 1) between them. The bonding layer 302 may include a plurality of conductive bonding pads 304. The peripheral die 310 may be a CMOS die and may include peripheral circuits 314 (e.g., peripheral circuit 114 in Figure 1) formed on a substrate 312 (e.g., substrate 112 in Figure 1).

[0053] Similar to the array die 120 in Figure 1, the array die 320 may include a) an array structure 330 (e.g., the array structure 130 in Figure 1) and a connection structure 340 (e.g., the connection structure 140 in Figure 1) in a first region 301 (e.g., the first region 101 in Figure 1), and b) a conductive connection structure 350 (e.g., the conductive connection structure 150 in Figure 1) in a second region 303 (e.g., the second region 103 in Figure 1). The connection structure 340 is adjacent to the array structure 330 and may be an extension of the array structure 330. The second region 303 is adjacent to the first region 303 by a boundary 341 (e.g., the boundary 141 in Figure 1).

[0054] The array structure 330, the connection structure 340, and the conductive connection structure 350 can be formed in a substrate similar to, for example, the substrate 312. The substrate can be any suitable semiconductor substrate having any suitable semiconductor material such as single crystal, polycrystalline, or monocrystalline semiconductors. For example, the substrate can include silicon, silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium nitride, silicon carbide, III-V compounds, or any combination thereof. In some examples, the substrate includes polysilicon. The substrate can be thinned from the back side. The thinned substrate can include a bottom polysilicon layer 324. One or more layers can be formed on the bottom polysilicon layer 324, such as an insulating layer 326 (made of a dielectric material such as an oxide) and a protective layer 328.

[0055] Similar to the array structure 130 in Figure 1, the array structure 330 includes multiple alternating pairs of conductive layers 332 (e.g., conductive layer 132 in Figure 1) and insulating layers 334 (e.g., insulating layer 134 in Figure 1). The array structure 330 also includes multiple vertical memory cell strings 336 (e.g., vertical memory cell string 136 in Figure 1) that penetrate the conductive layers 332 and insulating layers 334 and are coupled to bit lines 331 (e.g., bit line 131 in Figure 1). Each vertical memory cell string 336 may include multiple layers OX / SIN / OX(ONO) 336a (e.g., ONO 136a in Figure 1) and polysilicon 336b (e.g., polysilicon 136b in Figure 1). The array structure 330 may also include gate lines 333 (e.g., gate line 133 in Figure 1) between the multiple vertical memory cell strings 336. The connection structure 340 may include, for example, a conductive connection portion coupled to the conductive layer 332 by through-array contacts (TACs) and conductive pads. The connection structure 340 may also include a channel structure 342 (for example, channel structure 142 in Figure 1).

[0056] The conductive connection structure 350 is located within a second region 303, which may also be called a connection region or peripheral region. The conductive connection structure 350 includes a plurality of conductive connection parts 352a, 352b (generally referred to as conductive connection parts 352, and individually referred to as conductive connection parts 352). A conductive connection part 352 may be, for example, conductive connection part 152 in Figure 1. The conductive connection parts 352 may be separated and insulated by an insulating material 322 (e.g., an oxide). The conductive connection parts 352 may be conductively coupled to the array structure 340 and / or the conductive layer 332 in the connection structure 340 and coupled to the peripheral circuit 314 in the peripheral die 310.

[0057] In some embodiments, in step 202, an integrated structure 300a is provided, with a bottom polysilicon layer 324 on both the conductive connection structure 350 and the array structure 330. To form a common source line on the array structure 330, the protective layer 328 is first removed, and then the first portions of the bottom polysilicon layer 324 and insulating layer 326 on top of the array structure 330 are etched and removed, exposing multiple vertical memory cell strings 336, for example, along the X direction on the side of the stop line 342. On the other side of the stop line 342, the second portions of the bottom polysilicon layer 324 and insulating layer 326 on the conductive connection structure 350 and at least a portion of the connection structure 340 in the second region 303 remain unchanged or unetched. As shown in Figure 3B, a conductive layer (e.g., a source polysilicon layer) 335 can be deposited over the first region 301 and / or the second region 303 to form an integrated structure 300b. The conductive layer 335 may be the conductive layer 135 in Figure 1 and may be in contact with the end faces and gate lines 333 of the multiple vertical memory cell strings 336. In some implementations, the ends of the vertical memory cell strings 336 (for example, on the back side of the array die 320 away from the peripheral die 310) are etched to expose the polysilicon layer 336b of the vertical memory cell strings 336, and as a result, the conductive layer 335 comes into contact with the poly layer 336 within the vertical memory cell strings 336. The ends of the vertical memory cell strings 336 may include an ONO layer 336a.

[0058] In some embodiments, step 202 provides the integrated structure 300b shown in Figure 3B, where the first portion of the bottom polysilicon layer 324 rests on the conductive connection structure 350 but not on the array structure 330.

[0059] In step 204, at least a portion of at least a portion of the polysilicon layer (e.g., the first portion of the bottom polysilicon layer 324) is etched in order to expose one or more conductive connection portions (e.g., conductive connection portion 352) within the conductive connection structure (e.g., conductive connection structure 350).

[0060] To protect the array structure 330 and the connection structure 340 from etching, first a protective layer 337 (e.g., protective layer 137 in Figure 1) is deposited on top of the array structure 330 and the connection structure 340 in the first region 301, for example, on top of the conductive layer 335. As shown in structure 300c in Figure 3C, the entire first portion of the polysilicon layer 324 in the etching region 327 is etched away, exposing the end faces of the conductive connection portions 352a and 352b. The etching region 327 may have first and second opposite edges X1 and X2 along the X direction. The first edge X1 may extend to the plane edge of the semiconductor device, and the second edge X2 may extend to the edge of the second region 303, for example, the boundary 341. The etching region 327 may have an etching depth from the upper surface Y1 to the lower surface Y2 along the Z direction. The upper surface Y1 may be at the same height as the upper surface of the connection structure 340 with the conductive layer 335 and the protective layer 337. The lower surface Y2 may be at the same height as or lower than the end faces of the conductive connection parts 352a and 352b so that the conductive connection parts 352s and 352b can be exposed for connection. The distance between the upper surface Y1 of the etching region 303 and the end faces of each conductive connection part 352a and 352b in the conductive connection structure 350 is less than or equal to the etching depth. The etching depth can be determined based on the etching time.

[0061] The etching process in step 204 is performed using a buried shallow trench isolation (BSTI) process, which can remove the bottom polysilicon layer 324 and conductive layer 335 (e.g., the source polysilicon layer) within the second region 303. The etching process can be performed by dry etching such as vapor phase etching, reactive ion etching (RIE), or plasmon etching. The etching process has low requirements for exposure accuracy in patterning and / or etching and does not require back-side deep trench ringing (BDTI) for insulation, which can greatly open up or increase the processing window. This can also allow for the formation of conductive vias for coupling to conductive pads for input / output, as shown in detail in Figures 3D to 3G, for example.

[0062] In step 206, insulating material is deposited on the array structure (e.g., array structure 330) and the conductive connection structure (e.g., conductive connection structure 350). For example, as shown in Figure 3D, insulating material 327 is formed on structure 300c to obtain structure 300d, and insulating material 327 can be filled between adjacent conductive connection portions 352a, 352b in conductive connection structure 350 and on the conductive layer 335 on array structure 330.

[0063] In some embodiments, the insulating material 327 includes an oxide that can be deposited by any suitable deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). In some embodiments, since BSTI has a smaller depth-to-width ratio, the insulating material 327 may include tetraethyl orthosilicate (TEOS). TEOS can be deposited by a boundary field oxide (BFOX) insulating process, which can replace other deposition methods such as ALD, without etch-back and removal of residues (e.g., Ti), thereby reducing manufacturing costs and cycle times.

[0064] After depositing insulating material 327 on the array structure 330 and the conductive connection structure 350, the surface of the deposited insulating material 327 or the surface of the structure 300d can be polished, for example, using chemical mechanical polishing (CMP) or planarization to smooth the surface of the structure 300d.

[0065] In step 208, conductive vias are formed that penetrate the insulating material so as to contact one or more conductive connections and conductive layers within the array structure.

[0066] Once the bottom polysilicon layer 324 on the conductive connection structure 350 and the array structure 330 is removed, and after depositing insulating material 327 on the array structure 330 and the conductive connection structure 350, the material etched within the conductive connection structure 350 and the array structure 330 (e.g., insulating material 327) is the same, as shown in Figure 3D, for example. Therefore, the conductive connection structure 350 and the array structure 330 can be processed with the same mask in the same process for patterning to form conductive vias, which can greatly increase the processing window. Furthermore, there is no leakage between the conductive connection portion 352 and the silicon.

[0067] For example, as shown in structure 300e in Figure 3E, the deposited insulating material 327 is patterned and removed using the same mask to form trenches 329a, 329b, and 329c (commonly referred to as trenches 329, and individually referred to as trenches 329) in the same etching process, so that the conductive connection portions 352a, 352b and a portion of the conductive layer 335 in the conductive connection structure 350 can be exposed together, for example, in the same etching step. The portion of the conductive layer 335 may be above the gate line 333 or at any other suitable location within the array structure 330. The size of the trench 329c may be smaller than, the same as, or larger than the size of the end face of the gate line 333. The size of the trench 329c is controlled to be smaller than the space between adjacent vertical memory cell strings 336 so that the vertical memory cell strings 336 are not exposed. In addition, a portion of the protective layer 337 on the portion of the conductive layer 335 is also etched away, exposing a portion of the conductive layer 335. The etching step can be carried out, for example, by wet etching. The etching depth can be controlled, for example, by time, in order to expose the conductive connection portions 352a and 352b. For example, as shown in Figure 3E, the bottom surfaces of the trenches 329a and 329b can be at the same height as or lower than the end surfaces of the conductive connection portions 352a and 352b, and the bottom surface of the trench 329c can be, for example, the top surface of the conductive layer 335 on the gate wire 333.

[0068] Next, conductive material is deposited in the trenches 329 within the conductive connection structure 350 and on the conductive connection parts 352a and 352b, and on portions of the conductive layer 335 on the gate wires 333 within the array structure 330, to form conductive vias 354a, 354b, and 354c (generally called conductive vias 354, and individually referred to as conductive vias 354). Conductive vias 354 may be, for example, conductive via 154 in Figure 1. Each of the conductive vias 354a, 354b, and 354c is coupled to the corresponding conductive connection parts 352a and 352b, and to portions of the conductive layer 335 on the gate wires 333. The conductive material may include a metal such as tungsten W. The components and / or structures between the conductive connector 352 and the connection structure 340 are removed by the etching process in step 204, for example, as shown in Figure 3C, and the insulating material 327 is filled into the first region 301 and the second region 303 (for example, between the conductive connector 352, the connection structure 340, and the array structure 330), for example, as shown in Figure 3D. Components and / or structures within the first region 301 and the second region 303 (e.g., conductive connectors 352, connection structures 340, and array structures 330) can be electrically insulated by the filled insulating material 327. Therefore, process 200 does not require one or more additional processes to form BDTI insulation for insulating components and / or structures within the first region 301 and the second region 303, such as the conductive connectors 352, connection structures 340, and array structures 330. Thus, there is no tungsten residue problem, and tungsten dishing can be reduced. In some embodiments, the conductive material includes aluminum (Al).

[0069] In some embodiments, process 200 further includes the step of depositing a conductive pad layer 360 on the conductive via 354. For example, as shown in structure 300f in Figure 3F, the conductive pad layer 360 is formed on the surface of structure 300e, for example, on the conductive via 354, so as to be in contact with the conductive via 354. The conductive pad layer 360 may include a conductive material, such as a metal such as aluminum (Al).

[0070] In some embodiments, the conductive via 354 and the conductive pad layer 360 are made of different materials; for example, the conductive via 354 may be made of tungsten W and the conductive pad layer 360 may be made of aluminum (Al). The conductive via 354 and the conductive pad layer 360 can be formed in separate process steps. In some embodiments, the conductive via 354 and the conductive pad layer 360 are made of the same material, for example, tungsten W, aluminum (Al), or any suitable conductive material. The conductive via 354 and the conductive pad layer 360 can be formed in the same process steps, for example, by depositing the same material on the structure 300e to fill the trench 329 until the conductive pad layer 360 is formed. In this way, process 200 can be simplified.

[0071] In some embodiments, an insulating layer 362 (for example, the insulating layer 162 in Figure 1) is further formed on the conductive pad layer 360, as shown in structure 300f in Figure 3F, for example.

[0072] In some embodiments, process 200 further includes the step of forming separate conductive pads 364a, 364b, and 364c (generally referred to as conductive pad 364 and individually conductive pad 364) by patterning a conductive pad layer 360. Conductive pad 364 may be, for example, conductive pad 164 in Figure 1. Each conductive pad 364a, 364b, and 364c can be bonded to a corresponding conductive via 354 bonded to a corresponding conductive connection portion 352 and to a portion of the conductive layer 335 on the gate wire 333, respectively. In some embodiments, process 200 further includes the step of filling the space between adjacent conductive pads 364 with an insulating material (e.g., oxide). The surface of the deposited insulating material may be polished, for example, by using CMP.

[0073] In some embodiments, process 200 further includes the step of depositing one or more layers (e.g., a dielectric layer 370 and a protective layer 372) on the conductive pad layer 360. After the insulating material has been filled between adjacent conductive pads 364, the dielectric layer 370 (e.g., dielectric layer 170 in Figure 1) and the protective layer 372 (e.g., protective layer 172 in Figure 1) can be sequentially formed on the structure 300f.

[0074] In some embodiments, as shown in Figure 3G, one or more pad openings 374 (e.g., pad opening 174 in Figure 1) are formed through the protective layer 372 and the dielectric layer 370 to expose one or more corresponding conductive pads 364, and one or more conductive pads 364 can be coupled to one or more external components by bonding wires passing through one or more pad openings 174, such as power, ground, other semiconductor devices, metal wires on a printed circuit board (PCB), etc. Thus, peripheral circuits 314 in peripheral die 310 and / or conductive layers 332 in array die 320 can be conductively coupled to one or more permanent components. The structure 300g in Figure 3G may be the same as or similar to the semiconductor device 100 in Figure 1.

[0075] Figure 4 shows a block diagram of a system 400 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure. System 400 may be a mobile phone, desktop computer, laptop computer, tablet, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having internal storage. As shown in Figure 4, system 400 may include a host device 408 and a memory system 402 having one or more 3D memory devices 404 and a memory controller 406. The host device 408 may include an electronic device processor such as a central processing unit (CPU) or a system-on-a-chip (SoC) such as an application processor (AP). The host device 408 may be configured to transmit or receive data to or from one or more 3D memory devices 404.

[0076] The 3D memory device 404 may be any 3D memory device disclosed herein, such as the 3D memory devices shown in Figures 1 to 3G. In some implementations, the 3D memory device 404 includes NAND flash memory. A memory controller 406 (also known as a controller circuit) is coupled to the 3D memory device 404 and the host device 408. Consistent with the implementations of this disclosure, the 3D memory device 404 may include a plurality of conductive interconnects penetrating a cover layer that contacts conductive pads within a conductive pad layer, and the memory controller 406 may be coupled to the 3D memory device 404 via at least one of the plurality of conductive interconnects. The memory controller 406 is configured to control the 3D memory device 404. For example, the memory controller 406 may be configured to operate a plurality of channel structures via word lines. The memory controller 406 can manage the data stored in the 3D memory device 404 and communicate with the host device 408.

[0077] In some implementations, the memory controller 406 is designed / configured to operate in low-duty-cycle environments such as Secure Digital (SD) cards, CompactFlash (CF)® cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 406 is designed / configured to operate in high-duty-cycle environments such as mobile devices like smartphones, tablets, and laptop computers, and SSDs or embedded multimedia cards (eMMCs) used as data storage in enterprise storage arrays. The memory controller 406 can be configured to control the operation of the 3D memory device 404, including read, erase, and program (or write) operations. The memory controller 406 can also be configured to manage various functions related to data stored in or to be stored in the 3D memory device 404, including but not limited to bad block management, garbage collection, logical-physical address translation, and wear leveling. In some implementations, the memory controller 406 is further configured to handle error correction codes (ECC) for data read from and written to the 3D memory device 404. Any other appropriate function, such as formatting the 3D memory device 404, may also be performed by the memory controller 406.

[0078] The memory controller 406 can communicate with an external device (e.g., a host device 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with an external device via at least one of various interface protocols, such as the USB protocol, MMC protocol, Peripheral Interconnection (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Extended Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, or Firewire protocol.

[0079] The memory controller 406 and one or more 3D memory devices 404 can be integrated into various types of storage devices, for example, in the same package such as a Universal Flash Storage (UFS) package or an eMMC package. In other words, the memory system 402 can be implemented and packaged in different types of final electronic products. In one example shown in Figure 4, the memory controller 406 and a single 3D memory device 404 may be integrated into a memory card 402. The memory card 402 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0080] The subject matter and embodiments of operations and behavior described in this disclosure can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware including structures disclosed in this disclosure and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or for controlling the operation of a data processing device. The carrier may be a tangible, non-transient computer storage medium. Alternatively or additionally, the carrier may be an artificially generated propagating signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by a data processing device. The computer storage medium may be a machine-readable storage device, a machine-readable memory board, a random-access or serial-access memory device, or one or more combinations thereof, or a part thereof. The computer storage medium is not a propagating signal.

[0081] References in this disclosure such as “one embodiment,” “an embodiment,” “an example embodiment,” “some embodiments,” and “some implementation” should be noted as indicating that while the described embodiments may include certain features, structures, or characteristics, not all embodiments necessarily include those features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, where certain features, structures, or characteristics are described in relation to an embodiment, it is within the knowledge of those skilled in the art that such features, structures, or characteristics will be affected in relation to other embodiments, whether explicitly stated or not.

[0082] In general, terms can be understood at least partially from their use in context. For example, the term “one or more” as used herein can be used, at least partially depending on the context, to describe any feature, structure, or characteristic in a singular sense, or to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” can be understood, at least partially depending on the context, to convey either a singular or plural usage. Furthermore, the term “based on” can be understood not necessarily intended to convey an exclusive set of factors, but rather, at least partially depending on the context, to allow for the presence of additional factors that are not necessarily explicitly described.

[0083] It should be readily understood that the meanings of “on,” “above,” and “over” in this disclosure should be interpreted most broadly, so that “on” not only means “directly on” something, but also includes the meaning of “on” something that has an intermediate feature or layer between them. Furthermore, “above” or “over” can mean not only “above” or “on” something, but also “above” or “on” something that has no intermediate feature or layer between them (i.e., directly on something).

[0084] Furthermore, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” can be used herein to facilitate descriptions of the relationship between one element or feature and another, as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in a usage or processing step, in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0085] As used herein, the term “substrate” refers to a material on which subsequent material layers are added. A substrate includes a “top” surface and a “bottom” surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the top surface of the substrate. The bottom surface is on the opposite side of the top surface, and therefore, the bottom surface of the substrate is on the opposite side of the top surface of the substrate. The substrate itself can be patterned. The material added on top of the substrate may or may not be patterned. Furthermore, the substrate can include a wide range of semiconductor materials such as silicon, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate can be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0086] As used herein, the term “layer” refers to a portion of a material that includes a region having thickness. A layer has a top and bottom surface, where the bottom surface of the layer is relatively close to the substrate and the top surface is relatively far from the substrate. A layer may extend over the entirety of a structure below or above it, or may have a smaller extent than the extent of a structure below or above it. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any set of horizontal surfaces between the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along tapered surfaces. A substrate may be a layer, which may contain one or more layers, and / or have one or more layers on top of, above, and / or below it. A layer may contain multiple layers. For example, an interconnection layer may include one or more conductive layers and contact layers (on which contacts, interconnection lines, and / or vertical interconnection accesses (VIA) are formed) and one or more dielectric layers.

[0087] As used herein, the term “nominal / nominally” refers to a desired or target value of a characteristic or parameter of a component or process step, set during the design phase of a product or process, along with a range of values ​​above and / or below the desired value. As used herein, the range of values ​​may be due to slight variations in the manufacturing process or tolerances. As used herein, the term “about” indicates a value of a given quantity that may vary based on a specific technology node related to the semiconductor device in question. Based on a specific technology node, the term “about” may indicate a value of a given quantity that varies within a range of, for example, 10 to 30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0088] In this disclosure, the terms “horizontal / horizontally / lateral / laterally” mean nominally parallel to the side of the substrate, and the terms “vertical” or “vertically” mean nominally perpendicular to the side of the substrate.

[0089] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred herein to as “memory strings,” such as NAND strings) on a laterally oriented substrate, such that the memory strings extend perpendicularly to the substrate.

[0090] This disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. For the sake of brevity of this disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature on or above a second feature in the following description may include embodiments in which the first and second features may be in direct contact, and embodiments in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplification and clarity and does not in itself presuppose any relationships between the various embodiments and / or configurations described.

[0091] The foregoing descriptions of specific implementations can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0092] While this disclosure includes details of many specific embodiments, these should not be interpreted as limitations on the scope of what is claimed as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular embodiment of a particular invention. Certain features described in this disclosure in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, features may be described above as acting in a particular combination and may be initially claimed as such, but one or more features from a claimed combination may, in some cases, be removed from the combination, and the claims may cover a sub-combination or a variation of a sub-combination.

[0093] Similarly, while the operations are shown in the drawings and described in the claims in a specific order, this should not be understood as requiring that such operations be performed in a specific order shown, or in a sequential order, or that all illustrated operations be performed, in order to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged in multiple software products.

[0094] Specific embodiments of the subject matter are described. Other embodiments are also within the scope of the claims below. For example, the operations described in the claims can be performed in a different order and still achieve the desired results. As an example, the processes shown in the accompanying drawings do not necessarily require the specific order or sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0095] The scope and width of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely in accordance with the following claims and their equivalents. [Explanation of Symbols]

[0096] 100 Semiconductor device, 101 Region, 102 Bonding layer, 103 Region, 104 Conductive bonding pad, 110 Peripheral die, CMOS die, 112 Substrate, 114 Peripheral circuit, 120 Array die, 122 Insulating material, 130 Array structure, 131 Bit line, 132 Conductive layer, 133 Gate line, 134 Insulating layer, 135 Conductive layer, 136 Vertical memory cell string, 136a OX / SIN / OX(ONO), 136b Polysilicon, 137 Protective layer, 140 Connection structure, 141 Boundary, 142 Channel structure, 144 Part, 150 Conductive connection structure, 152 Conductive connection part, 152a Conductive connection part, 152b Conductive connection part, 160 Pad layer, Conductive pad layer, 162 Insulating layer, 164 Conductive pad, 164a Conductive pad, 164b Conductive pad, 164c Conductive pad, 170 Dielectric layer, 172 Protective layer, 174 Pad opening, 200 Process, 202 Step, 204 Step, 206 Step, 208 Step, 300a Integrated structure, 300b Integrated structure, 300c Structure, 300d Structure, 300e Structure, 300f Structure, 300g Structure, 301 First region, 302 Bonding layer, 303 Second region, Etching region, 304 Conductive bonding pad, 310 Peripheral die, 312 Substrate, 314 Peripheral circuit, 320 Array die, 322 Insulating material, 324 Bottom polysilicon layer, 326 Insulating layer, 327 Insulating material, 328 Protective layer, 329 Trench, 329a Trench, 329b Trench, 329c Trench, 330 Array structure, 331 Bit line, 332 Conductive layer, 333 Gate line, 334 Insulating layer, 335 Conductive layer, 336 Vertical memory cell string, 336a ONO layer, 336b Polysilicon layer, Polysilicon, 337 Protective layer, 340 Connection structure, 341 Boundary, 342 Channel structure, Stop line, 350 Conductive connection structure, 352 Conductive connection part, 352a Conductive connection part, 352b Conductive connection part, 360 Conductive pad layer, 362 Insulating layer, 364 Conductive pad, 364a Conductive pad, 364b Conductive pad, 364c Conductive pad, 370 Dielectric layer, 372 Protective layer, 374 Pad opening, 400 System, 402 Memory system, Memory card, 404 3D memory device, 406Memory controller, 408 host devices

Claims

1. A step of providing an integrated structure comprising an array structure in a first region and a conductive connection structure in a second region adjacent to the first region, wherein at least a portion of at least one polysilicon layer lies on the conductive connection structure. The steps include etching at least a portion of the at least one polysilicon layer in order to expose one or more conductive connection portions within the conductive connection structure, The steps include depositing insulating material on the array structure and the conductive connection structure, The steps include forming a conductive vertical interconnect access (VIA) that penetrates the insulating material so as to contact one or more conductive connection portions and a conductive layer within the array structure, A method that includes this.

2. The step of forming the conductive via is, The steps include etching the insulating material to expose one or more conductive connection portions in the conductive connection structure, along with a portion of the conductive layer in the array structure, A step of depositing a conductive material on one or more conductive connection portions within the conductive connection structure and on a portion of the conductive layer within the array structure in order to form the conductive vias, wherein each of the conductive vias is bonded to a corresponding one of the one or more conductive connection portions and the portion of the conductive layer. The method according to claim 1, including the method described in claim 1.

3. The steps include depositing a conductive pad layer on the conductive via, The steps include depositing at least one cover layer on the conductive pad layer, The steps include forming one or more pad openings that penetrate the at least one cover layer in order to expose one or more corresponding portions of the conductive pad layer, The method according to claim 1 or 2, further comprising:

4. A step of depositing a dielectric layer on the conductive pad layer, wherein the dielectric layer is located between the conductive pad layer and the at least one cover layer, The step of forming the one or more pad openings is, To form the corresponding pad opening, the step of etching through the at least one cover layer and the dielectric layer, The method according to claim 3, including the method described in claim 3.

5. The method according to claim 3 or 4, wherein the conductive pad layer comprises a first conductive material and the conductive via comprises a second conductive material different from the first conductive material.

6. The at least one polysilicon layer comprises a plurality of portions, at least one portion of the at least one polysilicon layer is a first portion of the at least one polysilicon layer, and a second portion of the at least one polysilicon layer is located on the array structure. The step of providing the aforementioned integrated structure is: The steps include etching the second portion of the at least one polysilicon layer to expose multiple strings of memory cells and gate lines between adjacent groups of strings in the array structure, A step of forming the conductive layer over the first region, wherein the conductive layer is in contact with the end faces of a plurality of strings of the memory cell and the gate wires, The method according to any one of claims 1 to 5, including the method described in any one of claims 1 to 5.

7. The method according to claim 6, wherein the end faces and gate lines of the plurality of strings of the memory cell form a uniform surface.

8. The method according to claim 6, wherein the end faces and gate lines of the plurality of strings of the memory cell form a non-uniform surface.

9. The step of forming the conductive via is, The step of forming a conductive via that penetrates the insulating material so as to contact a portion of the conductive layer located above the gate wire. The method according to any one of claims 6 to 8, including the method described in any one of claims 6 to 8.

10. The step of etching at least a portion of the at least one polysilicon layer is: The step of etching the entirety of at least a portion of the at least one polysilicon layer within the etching region. Includes, The first region and the second region are arranged along a first direction, and the one or more conductive connectors extend along a second direction perpendicular to the first direction. The etching region has first and second opposite edges along the first direction, the first edge is extendable to the edge of the plane of the integrated structure, and the second edge is extendable to the edge of the second region. The etching region has an etching depth from the top surface to the bottom surface along the second direction, and the distance between the top surface of the etching region and the end face of each of the one or more conductive connection parts in the conductive connection structure is less than or equal to the etching depth. The method according to any one of claims 1 to 9.

11. The step of depositing the insulating material on the array structure and the conductive connection structure is: The step of depositing the insulating material between adjacent conductive connection portions within the conductive connection structure and on the conductive layer within the array structure. Includes, The aforementioned method, The step of depositing the insulating material on the array structure and the conductive connection structure, and then polishing the surface of the deposited insulating material. The method according to any one of claims 1 to 10, further comprising:

12. An array structure including conductive layers coupled to multiple strings of memory cells, A conductive connection structure located separately from the aforementioned array structure, comprising a plurality of conductive connection parts, A conductive pad layer disposed above the array structure and the conductive connection structure, comprising a plurality of conductive pads connected to a portion of the conductive layer and each of the plurality of conductive connection portions via corresponding conductive vias, The plurality of conductive connection parts are separated by an insulating material filled within the conductive connection structure. Semiconductor devices.

13. The semiconductor device according to claim 12, wherein the corresponding conductive vias are separated and insulated by the insulating material filled between the conductive pad layer, the array structure, and the conductive connection structure.

14. The semiconductor device according to claim 12 or 13, wherein no conductive material is present between the conductive connection structure and the array structure.

15. The semiconductor device according to any one of claims 12 to 14, wherein no conductive material exists between the plurality of conductive connection portions in the conductive connection structure.

16. The semiconductor device according to any one of claims 12 to 15, wherein the connection angle between the conductive pad layer and at least one of the respective conductive vias is about 90 degrees.

17. The array structure and the conductive connection structure are integrated within the first die. The semiconductor device further includes a second die integrated with the first die, and at least one of the plurality of conductive connection portions is coupled to a control circuit in the second die. A semiconductor device according to any one of claims 12 to 16.

18. A cover layer is further provided on the conductive pad layer, The cover layer includes a plurality of pad openings on the plurality of conductive pads in the conductive pad layer, and each of the plurality of conductive pads is coupled to at least one of the corresponding conductive vias. A semiconductor device according to any one of claims 12 to 17.

19. An array structure including conductive layers coupled to multiple strings of memory cells, A conductive connection structure located separately from the array structure, comprising a plurality of conductive connection parts, wherein the plurality of conductive connection parts are separated by an insulating material filled in the conductive connection structure, A conductive pad layer disposed above the array structure and the conductive connection structure, comprising a plurality of conductive pads bonded to a portion of the conductive layer and each of the plurality of conductive connection portions via corresponding conductive vias, A memory device having, A controller coupled to the memory device and configured to control the memory device, A system equipped with these features.

20. The memory device is A plurality of conductive interconnects that penetrate a cover layer above the conductive pad layer so as to contact the plurality of conductive pads in the conductive pad layer, wherein each of the plurality of conductive pads is coupled to at least one of the corresponding conductive vias. Furthermore, The controller is coupled to the memory device via at least one of the plurality of conductive interconnections. The system according to claim 19.

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