Devices and methods for testing semiconductor wafers
The temperature-controllable clamp device with zone-specific heating and insulating regions addresses the challenge of maintaining constant chip temperatures during wafer testing, enhancing thermal response and preventing overheating by direct chip temperature sensing and dynamic power adjustment.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- ERS ELECTRONICS
- Filing Date
- 2024-02-20
- Publication Date
- 2026-06-04
AI Technical Summary
Existing wafer testing technologies face challenges in independently and quickly controlling temperature within each zone to maintain constant chip temperatures under dynamic load, and in adjusting the temperature sensor (chuck) to eliminate thermal resistance between the upper chuck surface and the back wafer surface, leading to delayed heat dissipation and potential overheating.
A temperature-controllable clamp device with a chuck and heating device featuring a plurality of separate heating zones, surrounded by lateral insulating regions, allows for rapid heat dissipation and improved thermal response characteristics by using a temperature sensing device to directly detect chip temperature and adjust heating/cooling power accordingly.
Enables rapid test pulse sequences without distorted measurements by rapidly dissipating excess heat, maintaining stable chip temperatures, and preventing overheating through zone-specific thermal management.
Smart Images
Figure 2026518196000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a device and method for testing a semiconductor wafer using a temperature - controllable clamp device.
Background Art
[0002] The present invention and a series of problems underlying it will be described herein by way of an integrated circuit on a wafer surface, but are not limited thereto. In a manufacturing sequence for manufacturing an integrated circuit, wafer testing can be performed on an un - divided wafer to detect defective integrated circuits early and remove them. For this purpose, the wafer to be tested is inserted into a wafer prober and brought to a desired test temperature by a temperature - controllable chuck (a device for temperature - controlling the wafer substrate) located therein. When the wafer is at the desired test temperature, an electrical connection to the contact area of the integrated circuit to be tested is established using a contact needle configuration located on a needle head. The needle head having contact needles is attached to what is called a probe card, and the probe card forms an interface between the test system and the wafer via the contact needles of the needle head.
[0003] Wafer testing is typically performed within a temperature range of - 60°C to 400°C, but in exceptional cases, it is performed at even more extreme temperatures above and / or below zero. During high-chip performance testing, heat dissipation is delayed due to the finite heat transfer resistance between the semiconductor wafer and the clamping device. This leads to a problem where the semiconductor wafer is locally heated to a temperature higher on the front surface in the current region than on the back surface in contact with the clamping device. Typically, at power levels exceeding 100W, a localized temperature difference of approximately 40K occurs between the front surface of the semiconductor wafer and the support surface of the clamping device. This temperature difference hinders test measurements that are specifically intended to provide isothermal electrical characteristics of the circuits integrated on the semiconductor wafer. Simultaneously, at higher power levels, the chip can overheat beyond its maximum allowable temperature, potentially leading to an electrical failure risk.
[0004] Patent Document 1 discloses a device and method for testing a semiconductor wafer using a temperature-controllable clamp device, the method comprising the steps of: controlling the temperature of the clamp device to a predetermined measurement temperature using an electric heating device with a predetermined heating power and a cooling device with a predetermined cooling power through which a fluid is passed for cooling; placing the back surface of the semiconductor wafer against the support surface of the temperature-controllable clamp device; placing a probe card on the front surface of the semiconductor wafer; testing the temperature-controllable semiconductor wafer by applying the test power of the test device to the chip area on the front surface of the semiconductor wafer using the probes on the placed probe card; and detecting the temperature rise of the fluid reflecting the test power during the test.
[0005] In this context, the heating power is greater than a predetermined test power, and the heating power is reduced by drawing the test power with substantially constant cooling power during the test, taking into account the temperature rise of the fluid detected during the test. The temperature rise of the fluid is detected by considering the signal from an associated temperature sensing device, which detects the input and output temperatures of the fluid supplied from the cooling device to the clamping device for cooling during the test.
[0006] This essentially involves dissipating high power input at a single point through a clamping device (chuck). In this context, it is essential that the temperature control of the chuck behaves exactly the same at every position across the entire wafer (in this case, 300 mm in diameter). While this system functions well, it has relatively slow thermal response characteristics.
[0007] Patent Document 2 discloses a method for setting the temperature of a substrate carrier on which a substrate is placed, in a test device for testing a device under test formed on a substrate, wherein the substrate placement surface of the substrate carrier is subdivided into a plurality of regions, and a heater is placed in each of the plurality of regions. This method includes the steps of performing feedback control on a heater in a main region corresponding to the device under test among the plurality of regions so that the temperature of the main region becomes a target temperature, and controlling a heater in a sub-region adjacent to the main region among the plurality of regions. When the heater in the sub-region is controlled, if there is no temperature overshoot in the main region, the heater in the sub-region is controlled so that the temperature difference between the main region and the sub-region becomes a predetermined value, and if there is a temperature overshoot in the main region, the heater in the sub-region is controlled so that the temperature difference between the set target temperature and the temperature in the sub-region becomes a predetermined value.
[0008] Patent Document 3 discloses a test interface board comprising a plurality of socket interface boards, each socket interface board having a socket for receiving a DUT; a separate active thermal interposer having thermal properties and playing a role in establishing thermal contact with the DUT; a superstructure operable to include the separate active thermal interposer; and an operating mechanism operable to provide a contact force for bringing the separate active thermal interposer into contact with the DUT.
[0009] All known test devices fail to solve the following two problems related to wafer testing: 1) How can the temperature within each zone be controlled independently and quickly so that the chip temperature remains constant under dynamic load? It is always observed that the chuck itself is thermally inert and it is not possible to adjust the temperature on a zone-by-zone basis.
[0010] 2) How can the temperature of the temperature sensor (chuck) be adjusted according to the chip temperature, thereby eliminating thermal resistance between the upper chuck surface and the back wafer surface? [Prior art documents] [Patent Documents]
[0011] [Patent Document 1] European Patent No. 1844342 [Patent Document 2] European Patent Application Publication No. 3937216 [Patent Document 3] U.S. Patent Application Publication No. 2012 / 0396801 [Overview of the project] [Problems that the invention aims to solve]
[0012] Therefore, an object of the present invention is to provide a device and method for testing semiconductor wafers using a temperature-controllable clamp device having improved thermal response characteristics. [Means for solving the problem]
[0013] To achieve this objective, the present invention provides a device for testing a semiconductor wafer using the temperature-controllable clamp device described in claim 1, and a method for testing a semiconductor wafer using the temperature-controllable clamp device described in claim 17. A plate-shaped zone heating device described in claim 16 is also provided.
[0014] A preferred form of development constitutes the subject matter of the relevant dependent claims. The underlying concept of the present invention is to provide a temperature-controllable clamping device having a chuck device and a heating device, wherein the heating device is applicable to the chuck device and has a plurality of separate heating zones. The heating zones are arranged in the form of a planar matrix below the support surface of the zone heating device, each surrounded by a lateral insulating region. The lateral insulating region suppresses heat transfer laterally, but maintains heat transfer vertically. As a result, excess heat from the test can be dissipated more rapidly by cooling the chuck device, and the thermal response characteristics can be substantially improved. This further enables the execution of a test pulse sequence using a test power that can change rapidly over time without the measurement results being distorted by delayed heat dissipation.
[0015] In a preferred evolution, the temperature sensing device is configured to directly detect the rise in chip temperature during the test, which reflects the test power, and to pass the rise in chip temperature to the temperature control device, which is configured to reduce the heating power with a constant cooling power based on the rise in chip temperature directly detected during the test, in order to stabilize the measured temperature.
[0016] In a more preferred development, the lateral insulation region has its own annular cavity within a plate-shaped zone heating device. This provides effective lateral insulation. In a more preferred embodiment, the annular cavities are arranged in an overlapping manner in a plate-shaped zone heating device. This allows for considerable space savings.
[0017] In a further preferred embodiment, each annular cavity within the plate-shaped zone heating device has a corresponding first vacuum terminal on its back surface opposite to the support surface for vacuuming the cavity. Thus, the effectiveness of thermal shielding can be further increased.
[0018] In a further preferred embodiment, the annular cavity within the plate-shaped zone heating device is exposed to the support surface. This also similarly enhances the effectiveness of the thermal shield. In a further preferred embodiment, the heat-insulating region has a heat-insulating material embedded within the plate-shaped zone heating device. Thereby, the stability of the plate-shaped zone heating device is improved.
[0019] In a further preferred embodiment, the plate-shaped zone heating device is formed from a ceramic, glass-ceramic, glass, or plastic material. Thereby, manufacturing becomes simpler and more flexible.
[0020] In a further preferred embodiment, each heating zone has a heating resistor that can be electrically controlled via associated electrical terminals. In this way, accurately controllable zone heating can be formed.
[0021] In a further preferred embodiment, the temperature detection device has an associated temperature sensor device that is integrated into the chip under test and can be contacted via the temperature probe of the probe card. This enables the high-precision determination of the rise in chip temperature in real time.
[0022] In a further preferred embodiment, the temperature detection device comprises an infrared thermometer arranged on the probe card. By doing so, additional probes and additional temperature sensor devices within the chip under test can be omitted.
[0023] In a further preferred embodiment, the chuck device has a single cooling circuit for the cooling fluid. Thereby, manufacturing is simplified. In a further preferred embodiment, the chuck device has a plurality of cooling circuits, and by means of these cooling circuits, individual heating zones can be selectively cooled individually by the cooling fluid. Thereby, the response characteristics are further improved.
[0024] In a further preferred embodiment, a valve device controllable by a temperature control device is provided to selectively operate each individual cooling circuit. In a further preferred embodiment, the chuck device has a second vacuum suction groove, through which a plate-shaped heating device can be applied to the chuck device. Thus, the plate-shaped zone heating device can be quickly applied and removed when needed.
[0025] Embodiments of the present invention are shown in the drawings and will be described in more detail in the following description. [Brief explanation of the drawing]
[0026] [Figure 1] This is a schematic cross-sectional view of a device for testing semiconductor wafers according to a first embodiment of the present invention. [Figure 2] This is a partial schematic cross-sectional view of a zone heating device for testing semiconductor wafers according to a first embodiment of the present invention. [Figure 3] This is a partial schematic cross-sectional view of an improved zone heating device for a device for testing semiconductor wafers according to a second embodiment of the present invention. [Figure 4] This is a schematic cross-sectional view of a device for testing semiconductor wafers according to a third embodiment of the present invention. [Figure 5] This is a plan view of an improved zone heating device for a device for testing semiconductor wafers according to a fourth embodiment of the present invention. [Figure 6] This is a partial schematic cross-sectional view of an improved zone heating device for testing semiconductor wafers according to a fourth embodiment of the present invention. [Figure 7] This is a schematic cross-sectional view of a device for testing semiconductor wafers according to a fifth embodiment of the present invention. [Figure 8] This is a schematic cross-sectional view of a device for testing semiconductor wafers according to a sixth embodiment of the present invention. [Modes for carrying out the invention]
[0027] In drawings, similar reference numbers represent similar or functionally equivalent components. Figure 1 is a schematic cross-sectional view of a device for testing semiconductor wafers according to a first embodiment of the present invention.
[0028] In Figure 1, reference numerals 90 and 100 represent temperature-controllable clamp devices 90 and 100 for a semiconductor wafer 50, each comprising a metal (e.g., Cu) chuck device 100 and a plate-shaped zone heating device 90 applicable to or applicable to the chuck device 100, having a plurality of separate heating zones H1 to H8. By a drive mechanism (not shown), the temperature-controllable clamp devices 90 and 100 can be displaced vertically within the contact surface of the semiconductor wafer 50, which is defined by a support surface AF of the plate-shaped zone heating device 90. The support surface AF has a first vacuum suction groove 91 for clamping the semiconductor wafer 50.
[0029] The chuck device 100 has a second vacuum suction groove 81, by which the plate-shaped zone heating device 90 can be clamped to the chuck device 100. Thus, the plate-shaped zone heating device can be quickly applied and removed when needed. The chuck device 100 and the plate-shaped zone heating device 90 are typically configured in a circular shape and have the same diameter, for example, about 200 mm or 300 mm.
[0030] The heating zones H1 to H8 (shown in one dimension only in Figure 1, see Figure 5) are arranged in the form of a planar matrix inside the zone heating device 90, below the support surface AF of the zone heating device 90, and are embedded in the material of the zone heating device 90. In the embodiments described herein, the plate-shaped zone heating device 90 is formed from ceramic, glass ceramic, glass, or plastic material.
[0031] The heating zones H1 to H8 are each formed by heating resistors and can be individually electrically controlled via their respective electrical terminals (see Figures 2 and 3). Their size is typically a few millimeters. 2 Depending on the chip size, one or more chips CH on the semiconductor wafer 50 may be heated in each heating zone.
[0032] In this embodiment, the heating zones H1 to H8 are square, and each is surrounded by lateral insulating regions I1 to I7. The lateral insulating regions I1 to I7 are circumferential, and therefore form island-like insulating regions I1 to I7. The insulating regions I1 to I7 are formed overlapping the sides of the heating zones H1 to H8.
[0033] The programmable test control device 20 is used to test a temperature-controlled semiconductor wafer 50 clamped to the support surface AF of a zone heating device 90 by applying a predetermined electrical test power PT as an individual pulse or pulse sequence to each chip DUT under test on the front surface of the semiconductor wafer 50 via probes P1 and P2 located on the needle head NK of the probe card 10. The electrical connection between the test control device 20 and the probe card extends through line PL.
[0034] A temperature control device 30 is further provided and connected to the test device 20, the chuck device 100, and the zone heating device 90, and is designed to set a predetermined measurement temperature for the chip DUT under test.
[0035] For this purpose, the temperature control device 30 controls the chuck device 90 to a predetermined cooling power PK using a cooling fluid. The cooling fluid is supplied to the chuck device 100 via input line F1 and input terminal 11a and discharged via output line F2 and output terminal 11b. In this embodiment, the chuck device 100 has a single cooling circuit K for the cooling fluid (shown as a dashed line in Figure 1).
[0036] Optionally, the chuck device 100 may have a heating device H100 controllable by a temperature control device 30 via lines S1, S2 and corresponding terminals 10a, 10b to stabilize cooling. Similarly, one or more temperature sensors TS1 electrically connected to the temperature control device 30 via lines (not shown) may serve this purpose.
[0037] Via bus line H30, the temperature control device 30 can control the associated heating zone corresponding to the chip DUT under test to a predetermined heating power PH, where the predetermined heating power PH is greater than a predetermined test power PT. For this purpose, the temperature control device 30 receives a position signal POS from the test device 20 during the test, and the position signal POS provides the assignment of the associated heating zone to be controlled for the chip DUT under test.
[0038] The temperature sensing device (TSC) within the integrated circuit IC of the chip DUT under test is used to directly detect the rise in chip temperature during testing, reflecting the test power PT. The temperature sensing device (TSC) has an associated temperature sensor device (TSC), which is integrated into the chip CH, DUT under test and can be contacted via temperature probes T1, T2 of probe card 10. This enables high-precision real-time determination of the rise in chip temperature.
[0039] For this purpose, the chip temperature T DUT The data is transmitted in real time to the test device 20 via the first temperature monitoring line TL, and from there to the temperature control device 30 via the second temperature monitoring line TL'.
[0040] The temperature control device 30 is designed to stabilize the measured temperature by reducing the heating power PH in the relevant heating zone (H3 in this case) with a constant cooling power PK based on the rise in chip temperature directly detected during the test.
[0041] The lateral adiabatic regions (I2 and I3 in this case) suppress heat transfer laterally, while maintaining heat transfer perpendicular to the chuck device 100. As a result, excess heat from the test can be dissipated very rapidly by cooling the chuck device 100. This makes it possible to perform a test pulse sequence using a test power that can change rapidly over time without the measurement results being distorted by delayed heat dissipation.
[0042] Figure 2 is a partial schematic cross-sectional view of a zone heating device for testing semiconductor wafers according to a first embodiment of the present invention. As shown in Figure 2, the lateral adiabatic regions I1 to I7 (of which I2 and I3 are shown here) each have annular cavities H within the plate-shaped zone heating device 90, and the annular cavities H extend as close as possible to the support surface AF and the opposite back surface RF.
[0043] Heating zones H1 to H8 (of which H3 and H4 are shown here) each have associated heating resistors HR3 and HR4, which are wound around heating zones H1 to H8 to set the thermal power density as high as possible. Heating resistors HR3 and HR4 can be electrically controlled by a temperature control device 30 via bus line H30 through associated electrical terminals H31, H32 and H41, H42, respectively.
[0044] Figure 3 is a partial schematic cross-sectional view of an improved zone heating device relating to a device for testing semiconductor wafers according to a second embodiment of the present invention. In the second embodiment, each annular cavity H' (indicated here as adiabatic regions I2' and I3') within the plate-shaped heating device 90' has an associated first vacuum terminal VL' on the back surface RF opposite to the support surface AF for vacuuming the cavity H'.
[0045] In all other respects, the second embodiment is configured in the same manner as the first embodiment. Figure 4 is a schematic cross-sectional view of a device for testing semiconductor wafers according to a third embodiment of the present invention.
[0046] In the third embodiment, the temperature detection devices 120 and 121 are configured as infrared thermometers 120 and 121, placed on the probe card 10, and have an IR light guide 120 and an evaluation circuit 121, the evaluation circuit 121 is further connected to a first temperature monitor line TL. Therefore, probes T1 and T2 are not required.
[0047] In all other respects, the third embodiment is configured in the same manner as the first embodiment. Figure 5 is a plan view of an improved zone heating device for a device for testing semiconductor wafers according to a fourth embodiment of the present invention, and Figure 6 is a partial schematic cross-sectional view thereof.
[0048] In the fourth embodiment, 32 square heating zones H1'' to H32'' are provided embedded beneath the support surface AF. The terminals of the heating resistors are guided inside the plate-shaped zone heating device 90'' to the edge of the zone heating device 90'', where they are connected to the bus line H30.
[0049] Unlike the previously described embodiment, the annular cavities H'' (indicated here as thermal insulation regions I2'' and I3'') within the plate-shaped zone heating device 90'' surrounding the heating zones (in this case H3'' and H4'') are exposed on the support surface AF.
[0050] In all other respects, the fourth embodiment is configured in the same manner as the first embodiment. Figure 7 is a schematic cross-sectional view of a device for testing semiconductor wafers according to a fifth embodiment of the present invention.
[0051] In the fifth embodiment, the insulating regions I1''' to I7''' have insulating material, such as glass fiber, embedded within the plate-shaped zone heating device 90'''. In all other respects, the fifth embodiment is configured similarly to the first embodiment.
[0052] Figure 8 is a schematic cross-sectional view of a device for testing semiconductor wafers according to a sixth embodiment of the present invention. In the sixth embodiment, not all elements are shown in order to make the drawings easier to understand; only the substantial differences from the first embodiment are shown.
[0053] In the sixth embodiment, the chuck device 100' has a plurality of cooling circuits K1 to K8, which can be used to selectively and individually cool individual heating zones H1 to H8 with a cooling fluid. For this purpose, valve devices V1 to V8 are provided that can be controlled by a temperature control device 30 via a control line SEL to selectively operate each individual cooling circuit K1 to K8. The valve devices V1 to V8 have valves for each cooling circuit on line F1, and these valves open when the associated cooling circuit is activated.
[0054] In all other respects, the sixth embodiment is configured similarly to the first embodiment. Although the present invention has been described above using preferred embodiments, the present invention is not limited thereto and can be modified in many ways.
[0055] In particular, the shape, size, and number of the insulated and heated zones are merely illustrative examples and can be modified as desired.
Claims
1. A device for testing semiconductor wafers, A temperature-controllable clamping device having a chuck device (100;100') and a plate-shaped zone heating device (90;90';90'';90'''), wherein the zone heating device is applicable to the chuck device (100;100') and has a plurality of separate heating zones (H1 to H8; H1'' to H32''), and the temperature-controllable clamping device (90,100;90',100,90'',100;90''',100;90,100'), The heating zones (H1 to H8; H1'' to H32'') are arranged in the form of a planar matrix below the support surface (AF) of the zone heating device (90; 90'; 90''; 90''''), and each is surrounded by a lateral insulating region (I1 to I7; I2', I3'; I2'', I3''; I1''' to I7'''), A test control device (20) for testing a temperature-controlled semiconductor wafer (50) clamped to the support surface (AF) of the zone heating device (90;90';90'';90''') by applying a predetermined electrical test power (PT) to each chip (DUT) under test on the front surface of the semiconductor wafer (50) via probes (P1, P2) of a probe card (10), A temperature control device (30) is connected to the test device (20), the chuck device (100, 100'), and the zone heating device (90, 90'', 90'', 90''''), and is configured to use a cooling fluid to control the chuck device (90) to a predetermined cooling power (PK) and to control the associated heating zone corresponding to the chip (DUT) under test to a predetermined heating power (PH), wherein the predetermined heating power (PH) is greater than the predetermined test power (PT), and A temperature detection device (TSC; 120, 121) for detecting a temperature rise during testing and sending the temperature rise to the temperature control device (30) and Equipped with, The temperature control device (30) is a device for testing a semiconductor wafer, configured to reduce the heating power (PH) with a constant cooling power (PK) based on the temperature rise of the chip directly detected during the test, in order to stabilize the measured temperature.
2. A device for testing a semiconductor wafer as described in claim 1, The temperature detection devices (TSC; 120, 121) are configured to directly detect the temperature rise of the chip, which reflects the test power (PT), during the test, and to pass the temperature rise of the chip to the temperature control device (30). The temperature control device (30) is a device for testing a semiconductor wafer, configured to reduce the heating power (PH) with a constant cooling power (PK) based on the temperature rise of the chip directly detected during the test, in order to stabilize the measured temperature.
3. The device for testing a semiconductor wafer according to claim 1 or 2, wherein the lateral insulating regions (I1 to I7; I2', I3'; I2'', I3'') each have annular cavities (H; H'; H'') within the plate-shaped zone heating device (90; 90'; 90'').
4. The device for testing a semiconductor wafer according to claim 3, wherein the annular cavities (H; H'; H''') are arranged to overlap in the plate-shaped zone heating device (90; 90'; 90''').
5. A device for testing a semiconductor wafer according to claim 3 or 4, wherein each of the annular cavities (H') in the plate-shaped zone heating device (90') has a corresponding first vacuum terminal (VL') on the back surface (RF) opposite to the support surface (AF) for vacuuming the cavity (H').
6. The device for testing a semiconductor wafer according to claim 3 or 4, wherein the annular cavity (H''') within the plate-shaped zone heating device (90''') is exposed to the support surface (AF).
7. The device for testing a semiconductor wafer according to claim 3, 4, or 5, wherein the heat insulating region (I1'''' to I7'''') has a heat insulating material embedded in the plate-shaped zone heating device (90'''').
8. The plate-shaped zone heating device (90; 90'; 90'''; 90''') is formed from a ceramic, glass-ceramic, glass, or plastic material, and is a device for testing a semiconductor wafer according to any one of claims 1 to 7.
9. A device for testing a semiconductor wafer according to any one of claims 1 to 8, wherein each of the heating zones (H1 to H8; H1'' to H32'') has a heating resistor (HR3, HR4) that can be electrically controlled via associated electrical terminals (H31, H32; H41, H42).
10. The device for testing a semiconductor wafer according to any one of claims 1 to 9, wherein the temperature detection device (TSC) is integrated on the chip under test (DUT) and has an associated temperature sensor device (TSC) that can be contacted via the temperature probes (T1, T2) of the probe card (10).
11. The device for testing a semiconductor wafer according to any one of claims 1 to 9, wherein the temperature detection device (120, 121) comprises infrared thermometers (120, 121) arranged on the probe card (10).
12. The chuck device (100) has a single cooling circuit (K) for the cooling fluid, the device for testing a semiconductor wafer according to any one of claims 1 to 11.
13. The chuck device (100') has a plurality of cooling circuits (K1 to K8), and the individual heating zones (H1 to H8) can be selectively and individually cooled by the cooling fluid using the cooling circuits (K1 to K8), the device for testing a semiconductor wafer according to any one of claims 1 to 12.
14. The device for testing a semiconductor wafer according to claim 13, wherein a valve device controllable by the temperature control device (30) is provided to selectively operate each individual cooling circuit (K1 to K8).
15. A device for testing a semiconductor wafer according to any one of claims 1 to 14, wherein the chuck device (100) has a second vacuum suction groove (81), and the plate-shaped heating device (90; 90'; 90''; 90'''') is applicable to the chuck device (100) via the second vacuum suction groove (81).
16. A plate-shaped zone heating device (90) for heating a semiconductor wafer using a plurality of separate heating zones (H1 to H8), wherein the heating zones (H1 to H8) can be selectively heated and are arranged in the form of a planar matrix below the support surface (AF) of the zone heating device (90; 90'; 90'''; 90''''') for the semiconductor wafer (50), each surrounded by lateral insulating regions (I1 to I7), wherein the device is particularly applicable to a chuck device (100; 100') for use in a device for testing a semiconductor wafer as described in any one of claims 1 to 13.
17. A method for testing a semiconductor wafer using a temperature-controllable clamping device, A step of providing a temperature-controllable clamp device (90, 100; 90', 100, 90'', 100; 90''', 100; 90', 100; 90', 100; 90', 100; 90', 100; 90', 100; 90', 100; 90', 100; 90', 100; 90', 100', the step of providing a temperature-controllable clamp device (90, 100; 90', 100; 90', 100; 90', 100', the heating zones (H1, H8; H1'', H32'') are arranged in a planar matrix below the support surface (AF) of the zone heating device (90, 90'; 90''; 90''''), each surrounded by a lateral insulating region (I1, I7; I2', I3'; I2'', I3''; I1'''', I7''''), The step of testing a temperature-controlled semiconductor wafer (50) clamped on the support surface (AF) of the zone heating device (90;90';90''';90''') by applying a predetermined test power (PT) to each chip (DUT) under test on the front surface of the semiconductor wafer (50) via probes (P1, P2) of a probe card (10), A step of controlling the chuck device (90) to a predetermined cooling power (PK) using a cooling fluid to set a predetermined measurement temperature, and controlling the associated heating zone corresponding to the chip (DUT) under test to a predetermined heating power (PH), wherein the predetermined heating power (PH) is greater than the predetermined test power (PT), A step to detect a temperature rise during the test, A method for testing a semiconductor wafer, comprising the step of reducing the heating power (PH) with a constant cooling power (PK) based on the temperature rise detected during the test in order to stabilize the measured temperature.
18. A device for testing a semiconductor wafer according to claim 17, The rise in chip temperature, which reflects the test power (PT), was directly detected during the test. A device in which the heating power (PH) is reduced by a constant cooling power based on the rise in chip temperature directly detected during the test, in order to stabilize the measured temperature.