Segmented formation of gate interface

Abstract

A method for forming a semiconductor structure includes: performing a first deposition process to deposit a first high-dielectric-constant dielectric layer on the surface of a substrate; performing an interface formation process to form an interface layer on the surface of the substrate; performing a second deposition process to deposit a second high-dielectric-constant dielectric layer on the interface layer; performing a plasma nitriding process to insert nitrogen atoms into the first high-dielectric-constant dielectric layer and the second high-dielectric-constant dielectric layer; and performing an annealing process to passivate the chemical bonds in the first high-dielectric-constant dielectric layer and the second high-dielectric-constant dielectric layer.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 458,331, filed Apr. 10, 2023, which is hereby incorporated by reference in its entirety.

[0002]

[0002] The embodiments described herein generally relate to semiconductor device manufacturing, and more specifically, to systems and methods for forming a high - quality high - dielectric - constant dielectric material layer within a semiconductor structure.

Background Art

[0003]

[0003] As metal - oxide - semiconductor field - effect transistors (MOSFETs) are scaled down to achieve high device performance and low power consumption, in order to improve transistor speed, the thickness of the conventional silicon dioxide (SiO2) gate dielectric must be reduced. Unfortunately, this also results in an increase in leakage current. As a result, in order to achieve further scaling without inhibiting leakage performance, it has become inevitable to replace the silicon dioxide gate dielectric with a high - dielectric - constant dielectric material. Among various high - dielectric - constant dielectric materials, hafnium oxide (HfO2) has been used since the 45nm MOSFET technology node due to its high dielectric constant and excellent thermal stability on a silicon substrate. However, in order to further scale the equivalent oxide thickness (EOT) after the 32nm MOSFET technology node, simply reducing the thickness of the high - dielectric - constant dielectric material layer increases the overall leakage current through the two - layer of SiO2 and the high - dielectric double - layer, leaving problems.

[0004]

[0004] Therefore, in order to ensure the desired structural and electrical properties, there is a need for systems and methods that can be used to form a thin (e.g., with an EOT less than 1nm) high - dielectric - constant dielectric material layer having a controllable chemical structure.

Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure provide a method for forming a semiconductor structure. The method includes performing a first deposition process to deposit a first high dielectric layer on the surface of a substrate; performing an interface formation process to form an interface layer on the surface of the substrate; performing a second deposition process to deposit a second high dielectric layer on the interface layer; performing a plasma nitriding process to insert nitrogen atoms into the first high dielectric layer and the second high dielectric layer; and performing an annealing process to passivate the chemical bonds in the first high dielectric layer and the second high dielectric layer.

[0006]

[0006] Embodiments of the present disclosure provide a method for forming a semiconductor structure. The method includes performing a first deposition process to deposit a first high dielectric constant dielectric layer on the surface of a substrate, performing an interface formation process to form an interface layer on the surface of the substrate, and performing a second deposition process to deposit a second high dielectric constant dielectric layer on the interface layer.

[0007]

[0007] Embodiments of the present disclosure further include providing a processing system. The processing system comprises a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, a fifth processing chamber, a sixth processing chamber, and a system controller. The system controller is configured to perform a first deposition process in the first processing chamber to deposit a first high dielectric layer on the surface of the substrate, an interface formation process in the second processing chamber to form an interface layer on the surface of the substrate, a second deposition process in the third processing chamber to deposit a second high dielectric layer on the interface layer, a plasma nitriding process in the fourth processing chamber to insert nitrogen atoms into the first and second high dielectric layers, and an annealing process in the fifth processing chamber to passivate the chemical bonds in the first and second high dielectric layers. The substrate is transferred between the first, second, third, fourth, and fifth processing chambers without breaking the vacuum within the processing system.

[0008]

[0008] To enable a detailed understanding of the above-described features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and therefore should not be considered to limit its scope, as the Disclosure may allow for other equally valid embodiments. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic top view of an exemplary multi-chamber processing system according to one embodiment. [Figure 2] This is a processing flow diagram of a method for forming a semiconductor structure according to one embodiment. [Figure 3A-3C] This is a schematic diagram of a semiconductor structure according to one embodiment. [Modes for carrying out the invention]

[0010]

[0012] For ease of understanding, the same reference numerals have been used to indicate identical elements common to the figures where possible. It is intended that elements and features of one embodiment can be advantageously incorporated into other embodiments without further description.

[0011]

[0013] As gate structure dimensions decrease, new material structures are needed to bring about improvements. The use of high-dielectric-constant dielectric materials allows for higher dielectric constants in gate structures compared to conventional gate structures using materials such as silicon oxide. However, similar to silicon oxide, reducing the thickness of the gate structure increases leakage current. For example, gate leakage increases as the effective oxide thickness decreases. Therefore, the inverse correlation between gate leakage and effective oxide thickness can form a limit to the performance of transistors and the devices they are manufactured from.

[0012]

[0014] High-dielectric-constant dielectric materials can offer greater channel mobility than silicon oxide at similar thicknesses. As industry demands thinner effective oxide thicknesses without increasing gate leakage, efforts to maximize the dielectric constant (also known as the "κ value") of known high-dielectric-constant materials are reaching their limits due to morphological properties. Conventional techniques have struggled to overcome the inherent properties of high-dielectric-constant materials, which can impose an upper limit on the κ value, and incorporating new films has required continuous device modifications.

[0013]

[0015] Embodiments described herein provide systems and methods for improving the properties of high-dielectric-constant dielectric materials. By manufacturing the high-dielectric-constant dielectric material in two segments, the generation of particles within the high-dielectric-constant dielectric material during the thermal oxidation process can be suppressed, leading to improved device performance. Furthermore, the high-dielectric-constant dielectric material of the two segments may be different, resulting in a higher overall dielectric constant.

[0014]

[0016] Figure 1 is a schematic top view of an embodiment of a multi-chamber processing system 100 according to several embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with corresponding transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers can be processed and transferred within the various chambers of the processing system 100 without exposing them to the external ambient environment (e.g., atmospheric ambient environment that may be present in a fab). For example, wafers can be processed in various chambers and moved between various chambers in a low-pressure (e.g., about 300 Torr or less) or vacuum environment without disrupting the low-pressure or vacuum environment between the various processes performed on the wafers within the processing system 100. Thus, the processing system 100 can provide an integrated solution for processing a subset of wafers.

[0015]

[0017] Examples of processing systems that may be appropriately modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, or other suitable processing systems commercially available from Applied Materials, Inc., Santa Clara, California. It is assumed that other processing systems (including those from other manufacturers) may be adapted to benefit from the embodiments described herein.

[0016]

[0018] As illustrated in the embodiment of Figure 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate wafer transfer. The docking station 140 is configured to receive one or more forward-opening unified pods (FOUPs) 144. In some embodiments, each factory interface robot 142 generally includes a blade 148 located at one end of the factory interface robot 142, configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0017]

[0019] Load lock chambers 104 and 106 have corresponding ports 150 and 152 connected to the factory interface 102, and corresponding ports 154 and 156 connected to the transfer chamber 108. Transfer chamber 108 further has corresponding ports 158 and 160 connected to the holding chambers 116 and 118, and corresponding ports 162 and 164 connected to the processing chambers 120 and 122. Similarly, transfer chamber 110 has corresponding ports 166 and 168 connected to the holding chambers 116 and 118, and corresponding ports 170, 172, 174, and 176 connected to the processing chambers 124, 126, 128, and 130. Ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, and 176 may be slit valve openings equipped with slit valves. The slit valve openings, equipped with slit valves, allow wafers to pass through them, for example, by transfer robots 112, 114, and provide a seal between each chamber to prevent gas from passing between them. Generally, any port is open to transfer wafers through it; otherwise, the port is closed.

[0018]

[0020] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidically connected to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and conduits fluidly connected to the various chambers. During operation, the factory interface robot 142 transfers wafers from the FOUP 144 to the load lock chamber 104 or 106 via port 150 or 152. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 104 or 106 facilitates the passage of wafers between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0019]

[0021] For wafers in the pumped-down load lock chamber 104 or 106, the transfer robot 112 transfers the wafers from the load lock chamber 104 or 106 to the transfer chamber 108 via port 154 or 156. The transfer robot 112 can then transfer the wafers to and / or between processing chambers 120 or 122 via the corresponding ports 162 or 164 for processing, or to holding chambers 116 or 118 via the corresponding ports 158 or 160 for holding in awaiting further transfer. Similarly, the transfer robot 114 can access wafers in the holding chamber 116 or 118 via port 166 or 168, and can transfer wafers to and / or between any of the processing chambers 124, 126, 128, and 130 via the corresponding ports 170, 172, 174, and 176 for processing, and transfer them to the holding chambers 116 and 118 via the corresponding ports 166 and 168 for holding in awaiting further transfer. The transfer and holding of wafers within and between the various chambers can be performed in a low-pressure or vacuum environment provided by the gas and pressure control system.

[0020]

[0022] Processing chambers 120, 122, 124, 126, 128, and 130 may be any suitable chamber for processing wafers. In some embodiments, processing chamber 122 may be capable of performing a cleaning process, processing chamber 120 may be capable of performing an etching process, processing chamber 124 may be capable of performing the respective deposition processes, processing chamber 126 may be a rapid thermal oxidation (RTO) chamber, processing chamber 128 may be a debonding plasma nitriding (DPN) chamber, and processing chamber 130 may be a rapid heat treatment (RTP) chamber. Processing chamber 122 may be a SiCoNi® pre-cleaning chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 120 may be a Selectra® etching chamber available from Applied Materials, Inc., Santa Clara, California. Processing chamber 124 may be a Centura® Epi chamber, a Volta® CVD / ALD chamber, or an EnCoRe® PVD chamber, all available from Applied Materials, Inc. in Santa Clara, California. Processing chamber 128 may be a Centura® DPN chamber, all available from Applied Materials, Inc. in Santa Clara, California. Processing chamber 130 may be a RadOx® DPN chamber, all available from Applied Materials, Inc. in Santa Clara, California.

[0021]

[0023] The system controller 190 is connected to the processing system 100 to control the processing system 100 or its components. For example, the system controller 190 can control the operation of the processing system 100 by directly controlling the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, and 130 of the processing system 100, or by controlling controllers associated with the chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, and 130. During operation, the system controller 190 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0022]

[0024] The system controller 190 generally includes a central processing unit (CPU) 192, memory 194, and support circuits 196. The CPU 192 may be one of any form of general-purpose processor available for use in an industrial environment. The memory 194 or non-temporary computer-readable medium is accessible by the CPU 192 and may be one or more memories (e.g., random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage). The support circuits 196 are connected to the CPU 192 and may include a cache, clock circuit, input / output subsystem, and power supply, etc. Various methods disclosed herein can generally be implemented by the CPU 192 executing computer instruction code stored in memory 194 (or the memory of a particular processing chamber) as a software routine, under the control of the CPU 192. Once the computer instruction code is executed by the CPU 192, the CPU 192 controls the chamber to perform processing in various ways.

[0023]

[0025] Other processing systems may have other configurations. For example, more or fewer processing chambers may be connected to the transfer device. In an exemplary embodiment, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other embodiments, as the transfer device within the processing system, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., zero holding chambers) may be implemented.

[0024]

[0026] FIG. 2 is a process flow diagram of a method 200 for forming a semiconductor structure 300 according to one or more implementations of the present disclosure. FIGS. 3A, 3B, and 3C are cross-sectional views of a part of the semiconductor structure 300 corresponding to various states of the method 200. It should be understood that FIGS. 3A, 3B, and 3C show only partial schematic views of the semiconductor structure 300, and the semiconductor structure 300 may include any number of transistor portions and additional materials having the aspects as shown. Further, although the method steps shown in FIG. 2 are described sequentially, other processing sequences including one or more method steps that are omitted and / or added and / or rearranged in another desirable order are within the scope of the embodiments of the present disclosure provided herein.

[0025]

[0027] The method 200 starts with a pre-cleaning process in block 210 to pre-clean the surface 302 of the substrate. The pre-cleaning process may include etching the surface of the substrate 302 by a wet process using an etching solution such as Standard Clean 1 (SC1) containing NH4OH (ammonium hydroxide), H2O2 (hydrogen peroxide), and H2O (water), or by a dry etching process such as, for example, a SiConi (trademark) remote plasma-assisted dry etching process in which the surface of the substrate 302 is exposed to N2, NF3, and NH3 plasma by-products. The pre-cleaning process may be performed in a suitable pre-cleaning chamber.

[0026]

[0028] In block 220, following a pre-cleaning treatment, a first deposition treatment is performed to deposit a first high-dielectric-constant dielectric layer 304 onto the surface 302 of the pre-cleaned substrate, as shown in Figure 3A. The first high-dielectric-constant dielectric layer 304 may be formed from a first high-dielectric-constant dielectric material such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), ytterbium oxide (Y2O3), or aluminum oxide (Al2O3). The first high-dielectric-constant dielectric layer 304 has a minimum thickness of about 3 Å to about 10 Å (e.g., about 5 Å) as a continuous layer (e.g., a single layer of the first high-dielectric-constant dielectric material) on the pre-cleaned surface of the substrate 302. At this thickness, no grains are formed within the first high-dielectric-constant dielectric layer 304 during the subsequent thermal oxidation treatment of block 230. The deposition treatment may include an atomic layer deposition (ALD) blanket deposition treatment. In the atomic layer deposition (ALD) blanket deposition process, a metal-containing precursor and an oxygen-containing precursor are alternately supplied to the exposed surface of the semiconductor structure 300. In some embodiments, the metal-containing precursor is purged before the oxygen-containing precursor is supplied. The metal may be a transition metal such as hafnium (Hf), zirconium (Zr), or titanium (Ti); a rare earth metal such as lanthanum (La), ytterbium (Yb), or yttrium (Y); an alkaline earth metal such as strontium (Sr); or another metal such as aluminum (Al). As an oxidizing agent, any oxygen-containing precursor that can react with the metal may be used. For example, the oxygen-containing precursor may be water, ozone, hydrogen peroxide, diatomic oxygen, a hydroxyl-containing precursor or alcohol, a nitrogen and oxygen-containing precursor, plasma-enhanced oxygen including locally or remotely enhanced oxygen, or any other material containing oxygen that can be incorporated into the metal to form a layer of metal oxide on the substrate 302, or may include these. In one embodiment, the metal-containing precursor is hafnium tetrachloride (HfCl4), and the oxidizing agent is water (H2O), forming a hafnium dioxide (HfO2) layer. The ALD treatment may be carried out at a temperature of about 200°C to about 400°C (e.g., about 270°C). The deposited first high dielectric constant dielectric layer 304 may be amorphous. The first deposition treatment may be carried out in a processing chamber such as processing chamber 124 or 126 shown in Figure 1.In some embodiments, the first deposition process may include a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

[0027]

[0029] In block 230, following the first deposition process, an interface formation process is performed to form an interface layer 306 on the surface 302 of the substrate as shown in FIG. 3B. The interface formation process may include a suitable thermal oxidation process of the surface of the substrate through the first high-k dielectric layer 304, such as an enhanced in-situ steam generation (eISSG) process using nitrous oxide (N2O) gas. The interface layer 306 formed in block 230 is a thin amorphous silicon oxide (SiO2) layer having a thickness of about 3 Å to about 10 Å (e.g., about 5 Å) and corresponding to one or more single layers of silicon oxide. In some embodiments, the interface layer 306 may be formed by an in-situ steam generation (ISSG) process using H2 gas and O2 gas, or a rapid thermal oxidation (RTO) process using O2 gas. The interface layer 306 can improve the quality of the interface (e.g., interface state density, capacitance, frequency dispersion, and leakage current) between the substrate 302 and the high-k dielectric layer. The interface formation process may be performed in a processing chamber such as the processing chamber 128 shown in FIG. 1.

[0028]

[0030] In block 240, following the interface formation treatment, a second deposition treatment is performed to deposit a second high-dielectric-constant dielectric layer 308 on the first high-dielectric-constant dielectric layer 304, as shown in Figure 3C. The second high-dielectric-constant dielectric layer 308 can be formed from a second high-dielectric-constant dielectric material such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2), ytterbium oxide (Y2O3), or aluminum oxide (Al2O3). The second high-dielectric-constant dielectric material may be the same as or different from the first high-dielectric-constant dielectric material. For example, the second high-dielectric-constant dielectric material may be hafnium dioxide (HfO2) doped with a transition metal such as zirconium (Zr) or titanium (Ti), or a rare earth metal such as lanthanum (La), thereby increasing the κ value of the second high-dielectric-constant dielectric layer 308 by, for example, about 25%. The second high-dielectric-constant dielectric layer 308 has a thickness of approximately 10 Å to approximately 25 Å. The second deposition process for block 240 is generally the same as the first deposition process for block 220. The deposited second high-dielectric-constant dielectric layer 308 may be amorphous.

[0029]

[0031] In block 250, following a second deposition process, a plasma nitriding process is performed to insert nitrogen atoms into the vacancies and defects of the first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308. The plasma nitriding process may be a debonding plasma nitriding (DPN) process and is performed in a DPN chamber, such as the processing chamber 130 shown in Figure 1. The plasma nitriding process exposes the first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308 to a nitrogen plasma, which may allow nitrogen radicals or nitrogen atoms to be incorporated into the first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308 throughout their entire thickness. Gases that can be used for plasma processing include nitrogen-containing gases such as nitrogen (N2), ammonia (NH3), or mixtures thereof. In one embodiment, the nitrogen gas is a mixture of ammonia (NH3) with approximately 3% to 8% nitrogen (N2). As a result of the incorporation of nitrogen into the vacancies and defects of the first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308, the plasma nitriding treatment may not change the thickness of the first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308. The plasma nitriding treatment can increase the overall κ value of the first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308 by, for example, about 25%.

[0030]

[0032] Nitriding can be performed at temperatures ranging from approximately 0°C to 500°C for approximately 10 to 300 seconds.

[0031]

[0033] In block 260, following plasma nitriding, an annealing treatment is performed to passivate the chemical bonds remaining in the plasma-nitrided first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308. The annealing treatment may include spike heat annealing in a nitrogen (N2) and argon (Ar) atmosphere, performed in a rapid heat treatment (RTP) chamber such as the treatment chamber 130 shown in Figure 1. The annealing treatment can passivate the metastable nitrogen bonds formed by the plasma nitriding of block 240, which may result in crystallization of the amorphous first high-dielectric-constant dielectric layer 304 and the second high-dielectric-constant dielectric layer 308.

[0032]

[0034] Spike heat annealing can be performed at a temperature of approximately 700°C to 850°C for approximately 1 to 30 seconds, at a pressure of approximately 10 Torr to 740 Torr.

[0033]

[0035] In block 270, following the annealing process, an optional passivation process is performed to diffuse oxygen or an oxidizing agent from the ambient atmosphere into the substrate 302 through the second high-dielectric-constant dielectric layer 308, the first high-dielectric-constant dielectric layer 304, and the interface layer 306, forming a fresh silicon dioxide (SiO2) monolayer that is added to the interface layer 306 formed in block 230. The passivation process may include thermal annealing in an oxygen (O2) atmosphere, performed in a rapid heat treatment (RTP) chamber such as the processing chamber 130 shown in Figure 1. The passivation process can improve the reliability of the device formed on the substrate 302, for example, extending the device life of a p-type transistor.

[0034]

[0036] Passivation can be performed at a temperature of approximately 500°C to 800°C for approximately 1 second to 60 seconds, at a low pressure of approximately 1 Torr to 50 Torr.

[0035]

[0037] The first deposition process of block 220, the interface formation process of block 230, the second deposition process of block 240, the plasma nitriding process of block 250, the annealing process of block 260, and any passivation process of block 270 can be performed without breaking the vacuum environment within a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1.

[0036]

[0038] Embodiments described herein provide a system and method for forming a high-quality, thin, high-dielectric-constant dielectric material layer. The high-dielectric-constant dielectric material layer is produced in two segments: one segment in which a thin layer is deposited before thermal oxidation treatment, and the other segment in which a thicker layer is deposited. Thus, the generation of grains within the entire high-dielectric-constant dielectric material during the thermal oxidation process can be suppressed, leading to improved device performance.

[0037]

[0039] While the above description applies to embodiments of the present disclosure, other embodiments and additional embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure. The scope of the present disclosure is determined by the following claims.

Claims

1. A method for forming a semiconductor structure, The first deposition process is performed to deposit a first high-dielectric-constant dielectric layer on the surface of the substrate, Performing an interface formation process to form an interface layer on the surface of the substrate, A second deposition process is performed to deposit a second high-dielectric-constant dielectric layer on the interface layer, Plasma nitriding treatment is performed to insert nitrogen atoms into the first high-dielectric-constant dielectric layer and the second high-dielectric-constant dielectric layer, Performing an annealing treatment to passivate the chemical bonds in the first high-dielectric-constant dielectric layer and the second high-dielectric-constant dielectric layer. A method that includes this.

2. The method according to claim 1, wherein the first deposition process, the interface formation process, the second deposition process, the plasma nitriding process, and the annealing process are performed within the processing system without breaking the vacuum.

3. Before the first deposition process, the surface of the substrate is pre-cleaned, After the annealing treatment, a passivation treatment is performed to diffuse oxygen or an oxidizing agent from the surrounding atmosphere into the substrate through the second high dielectric constant dielectric layer, the first high dielectric constant dielectric layer, and the interface layer. The method according to claim 1, further comprising:

4. The first high dielectric constant dielectric layer is made of hafnium oxide (HfO ２ ) includes and has a thickness between 3 Å and 10 Å, The second high dielectric constant dielectric layer is made of hafnium oxide (HfO ２ The method according to claim 1, comprising ) and having a thickness between 10 Å and 25 Å.

5. Each of the first and second deposition treatments includes atomic layer deposition (ALD) treatment, wherein hafnium tetrachloride (HfCl) is used in the treatment. ４ The method according to claim 1, wherein ) and water are alternately supplied to the substrate.

6. The aforementioned interface layer is silicon dioxide (SiO ２ ) including, The interface formation treatment involves nitrous oxide (N) ２ O) The method according to claim 1, comprising using a gas to thermally oxidize the substrate through the first high dielectric layer.

7. The aforementioned plasma nitriding treatment involves nitrogen (N ２ ) and ammonia (NH ３ The method according to claim 1, comprising exposing the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer to a nitrogen plasma using a mixture of gases.

8. The annealing treatment is performed at a temperature between 700°C and 850°C, using nitrogen (N ２ The method according to claim 1, comprising spike annealing the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer in an atmosphere of ) and argon (Ar).

9. A method for forming a semiconductor structure, The first deposition process is performed to deposit a first high-dielectric-constant dielectric layer on the surface of the substrate, Performing an interface formation process to form an interface layer on the surface of the substrate, A second deposition process is performed to deposit a second high-dielectric constant dielectric layer on the interface layer. A method that includes this.

10. The method according to claim 9, wherein the first deposition process, the interface formation process, and the second deposition process are performed within the processing system without breaking the vacuum.

11. The first high dielectric constant dielectric layer contains hafnium oxide (HfO ２ ), has a thickness between 3 Å and 10 Å, and The second high dielectric constant dielectric layer is made of hafnium oxide (HfO ２ The method according to claim 9, comprising ) and having a thickness between 10 Å and 25 Å.

12. Each of the first and second deposition treatments includes atomic layer deposition (ALD) treatment, wherein hafnium tetrachloride (HfCl) is used in the treatment. ４ The method according to claim 9, wherein ) and water are alternately supplied to the substrate.

13. The aforementioned interface layer is silicon dioxide (SiO ２ ) including, The interface formation treatment involves nitrous oxide (N) ２ O) The method according to claim 9, comprising using a gas to thermally oxidize the substrate through the first high dielectric layer.

14. A processing system, First processing chamber, Second processing chamber, Third processing chamber, Fourth processing chamber, A fifth processing chamber, and System Controller The system controller is equipped with, The first deposition process is performed in the first processing chamber to deposit a first high dielectric constant dielectric layer on the surface of the substrate, Performing an interface formation process in the second processing chamber to form an interface layer on the surface of the substrate, The second deposition process is performed in the third processing chamber to deposit a second high-dielectric-constant dielectric layer on the interface layer, Plasma nitriding is performed in the fourth processing chamber to insert nitrogen atoms into the first high-dielectric-constant dielectric layer and the second high-dielectric-constant dielectric layer, The annealing process is performed in the fifth processing chamber to passivate the chemical bonds in the first high-dielectric-constant dielectric layer and the second high-dielectric-constant dielectric layer. It is configured to do the following: A processing system in which the substrate is transferred between the first processing chamber, the second processing chamber, the third processing chamber, the fourth processing chamber, and the fifth processing chamber without breaking the vacuum within the processing system.

15. The seventh processing chamber, and Eighth processing chamber The system controller is equipped with, Prior to the first deposition process, the surface of the substrate is pre-cleaned in the seventh processing chamber, After the annealing treatment, a passivation treatment is performed in the eighth processing chamber to diffuse oxygen or an oxidizing agent from the surrounding atmosphere into the substrate through the second high dielectric constant dielectric layer, the first high dielectric constant dielectric layer, and the interface layer. The processing system according to claim 14, further configured to perform the following:

16. The first high dielectric constant dielectric layer is made of hafnium oxide (HfO ２ ) includes and has a thickness between 3 Å and 10 Å, The second high dielectric constant dielectric layer is made of hafnium oxide (HfO ２ The processing system according to claim 14, comprising ) and having a thickness between 10 Å and 25 Å.

17. Each of the first and second deposition treatments includes atomic layer deposition (ALD) treatment, wherein hafnium tetrachloride (HfCl) is used in the treatment. ４ The processing system according to claim 14, wherein ) and water are alternately supplied to the substrate.

18. The aforementioned interface layer is silicon dioxide (SiO ２ ) including, The interface formation treatment involves nitrous oxide (N) ２ O) The processing system according to claim 14, comprising using a gas to thermally oxidize the substrate through the first high dielectric constant dielectric layer.

19. The aforementioned plasma nitriding treatment involves nitrogen (N ２ ) and ammonia (NH ３ The processing system according to claim 14, comprising exposing the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer to a nitrogen plasma using a mixture of gases.

20. The annealing treatment is performed at a temperature between 700°C and 850°C, using nitrogen (N ２ The processing system according to claim 14, comprising spike annealing the first high dielectric constant dielectric layer and the second high dielectric constant dielectric layer in an argon (Ar) atmosphere.

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