Proactively warning the host about background folding

Abstract

Aspects of this disclosure configure a memory subsystem controller such that a host can deallocate data before a folding operation. The controller generates instructions to fold data stored in individual parts of a set of memory components. Before executing the instructions to fold data stored in individual parts of the set of memory components, the controller sends a communication to the host indicating the instructions to fold data stored in individual parts. The controller conditions the execution of the instructions to fold data stored in individual parts of the set of memory components based on the transmission of the communication to the host.

Description

Technical Field

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[0001] Priority Application This application claims the benefit of priority of U.S. Provisional Application No. 63 / 527,717, filed Jul. 19, 2023, which is hereby incorporated by reference in its entirety.

[0002] Examples of the present disclosure generally relate to memory subsystems, and more particularly to providing adaptive media management for memory components such as memory dies.

Background Art

[0006] Aspects of this disclosure configure system components, such as a memory subsystem controller, to perform folding (garbage collection) operations in coordination and / or participation by a host. The memory subsystem controller can identify one or more components that store data that needs to be folded. The memory subsystem controller can delay folding of data stored in one or more memory components to allow a host to participate and selectively deallocate the data stored in one or more memory components. If the host deallocates (invalidates) the data, the memory subsystem controller prevents the data from folding. If the host cannot deallocate the data before the timer and / or event expires, the memory subsystem controller automatically folds the data stored in one or more memory components. In some cases, these memory components may be part of a RG and can be folded according to the folding operations of the RG and RU. This ensures that the performance of the memory system remains optimal by reducing the write amplitude when the host deallocates data before the memory subsystem controller performs the folding operation. This improves the overall efficiency of the memory subsystem's operation.

[0007] A memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in relation to Figure 1. Generally, a host system can utilize a memory subsystem that includes one or more memory components, such as a memory device for storing data (e.g., a memory die or a memory plane spanning multiple memories). The host system can send access requests (e.g., write commands, read commands) to the memory subsystem, such as to store data in the memory subsystem and to read data from the memory subsystem. Data (or sets of data) specified by the host are hereafter referred to herein as “host data,” “application data,” or “user data.” In some cases, the memory subsystem may include optional features such as Flexible Data Placement (FDP) functionality that defines RG and RU. This protocol allows a remote host to control data storage on the memory subsystem.

[0008] The memory subsystem can initiate media management operations, such as write operations, on host data stored in memory devices. For example, the firmware of the memory subsystem may rewrite previously written host data from one location to a new location on a memory device as part of garbage collection management operations. For example, data to be rewritten when initiated by firmware is hereafter referred to herein as “garbage collection data.” “User data” may include host data and garbage collection data. Hereafter herein, “system data” refers to data created and / or maintained by the memory subsystem in order to perform operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical-to-physical address mapping tables), data from logging, scratchpad data, etc.

[0009] Many different media management operations can be performed on a memory device. For example, media management operations may include different scan speeds, different scan frequencies, different wear leveling, different read disturb management, different near miss error correction (ECC), and / or different dynamic data refresh. Wear leveling ensures that all blocks in a memory component approach their defined erase cycle budget simultaneously, rather than some blocks approaching it earlier. Read disturb management counts all read operations to the memory component. If a certain threshold is reached, the surrounding area is refreshed. Near miss ECC refreshes all data read by the application that exceeds a set threshold for errors. Dynamic data refresh scans read all data and identify the error status of all blocks as a background operation. This scan-read triggers a refresh operation if a certain threshold for errors per block or per ECC unit is exceeded.

[0010] A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. In some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. In some memory devices, a block is the smallest area that can be erased. Such blocks may be called logical units (LUNs) or addressable. Each block consists of a set of pages. Each page consists of a set of memory cells that store bits of data. A memory device may be a raw memory device (e.g., NAND) that is managed externally, for example by an external controller. A memory device may be a managed memory device (e.g., managed NAND) that is a raw memory device combined with a local embedded controller for memory management within the same memory device package.

[0011] Certain memory systems group physical memory components into different RGs, each containing multiple RUs. RUs can be of any size, at least the same size as a LUN; that is, a RU can be the size of a single block or the size of a superblock spanning multiple memory dies. These memory systems allow the host to store data in a specific RG and / or a specific RU within those RGs using corresponding RU handles (write pointers). This gives the host greater control over where data is physically stored. Once data is stored in individual RGs, garbage collection operations can be performed, but are limited to folding the data using the RUs of the individual RGs. That is, the data cannot be folded into any RU or another RG, but remains stored within the same RG.

[0012] While allowing the host device to control where data is physically stored provides additional flexibility, such a process also leads to inefficiencies in data storage. For example, the need to perform garbage collection operations within the same RG can increase the write amplitude of the memory subsystem. Also, in some cases, old and unnecessary data may be folded into the RG, which unnecessarily increases the write amplitude and wastes resources. Because the memory subsystem controller does not know which data is important and which is not, it treats all data at the same level of importance and performs folding operations as needed without involving the host. This can degrade memory performance and efficiency by increasing the write amplitude.

[0013] Aspects of this disclosure address the aforementioned and other defects by providing a memory controller that can coordinate with the host regarding which data needs to be folded. Specifically, the memory controller can delay folding data until a timer and / or event expires and inform the host of the possibility that a folding operation may be performed on data stored in a particular memory component (e.g., logical block addresses (LBA), RG, and / or RU). The host can analyze the data and selectively deallocate or invalidate the data to prevent the memory controller from performing a garbage collection or folding operation on that data. This reduces write amplitude and improves the overall efficiency of the memory subsystem's operation.

[0014] In some examples, the memory controller generates instructions to fold the data stored in individual parts of a set of memory components. Before executing the instructions to fold the data stored in individual parts of the set of memory components, the memory controller sends a communication to the host indicating the instructions to fold the data stored in the individual parts. Based on the transmission of this communication to the host, the memory controller conditions the execution of the instructions to fold the data stored in individual parts of the set of memory components.

[0015] In some examples, the memory subsystem includes a FDP. In some cases, the memory controller groups a set of memory components into multiple RGs. Each RG can contain a subset of RUs. Individual parts can contain individual RUs of the subset of RUs of the individual RG. In some examples, the memory controller initializes a timer in response to sending a communication to the host. The memory controller determines that the timer has reached a threshold before receiving instructions from the host in relation to the individual parts. In response to determining that the timer has reached a threshold before receiving instructions from the host in relation to the individual parts, the memory controller automatically folds the data stored in the individual parts of the set of memory components.

[0016] In some examples, the memory controller prevents the data stored in individual parts from folding in response to receiving instructions from the host before a timer reaches a threshold. In some examples, the instructions include a request to deallocate or invalidate the data stored in individual parts. In some examples, the timer is configurable.

[0017] In some examples, the memory controller receives instructions from the host to deallocate or invalidate the data stored in individual parts. In response to receiving instructions from the host, the memory controller prevents the data stored in individual parts from folding. In some examples, the memory controller identifies one or more LBAs associated with the data stored in individual parts and provides the identified one or more LBAs to the host via communication.

[0018] In some examples, the host identifies multiple LBAs, including one or more LBAs and an additional set of adjacent LBAs. The host generates instructions to deallocate or invalidate the data stored in the multiple LBAs. In some examples, communication is sent to the host in response to generating instructions that are asynchronous and fold the data stored in the individual parts.

[0019] In some examples, communications are stored in a log file on the memory subsystem. The memory controller receives instructions from the host to read the log file and, in response to receiving a request from the host to read the log file, retrieves communications for transmission to the host. In some examples, the memory controller folds data stored in individual RUs into another RU of an individual RG. In some examples, communications identify individual RUs of a subset of RUs. In some cases, instructions to fold data are generated in response to determining that an individual part meets one or more folding criteria. In some cases, one or more folding criteria include at least one of a low free block count, static wear leveling, read disturb, or error handling.

[0020] While various examples are described herein as being implemented with respect to a memory subsystem (e.g., a controller of the memory subsystem), some or all parts of a particular embodiment may be implemented with respect to a host system, such as a software application or operating system of the host system.

[0021] FIG. 1 shows an exemplary computing environment 100 that includes a memory subsystem 110 according to some examples of the present disclosure. The memory subsystem 110 can include media such as memory components 112A-112N (hereinafter also referred to as “memory devices” herein). The memory components 112A-112N can be volatile memory devices, non-volatile memory devices, or a combination of such. The memory components 112A-112N can be implemented by individual dies such that the first memory component 112A can be implemented by a first memory die (or a first aggregate of memory dies) and the second memory component 112N can be implemented by a second memory die (or a second aggregate of memory dies). Each memory die can include a plurality of planes capable of storing or programming data.

[0022] In some examples, one of the memory components 112A-112N can be associated with a first RG and another component of the memory components 112A-112N can be associated with a second RG. In some cases, a first portion of the memory components 112A-112N can be associated with a first RU of a first RG and a second portion of the memory components 112A-112N can be associated with a second RG. The memory subsystem 110 can have any number of RGs and any number of RUs within each RG and, in some cases, can implement an FDP.

[0023] In some examples, a first memory component 112A, a block or page of the first memory component 112A, or a group of memory components including the first memory component 112A can be associated with a first reliability (function) grade, value, scale, or lifetime PEC. The terms “reliability grade,” “value,” or “scale” are used interchangeably throughout and may have the same meaning. A second memory component 112N, or a group of memory components including the second memory component 112N, can be associated with a second reliability (function) grade, value, scale, or lifetime PEC. In some examples, each memory component 112A-112N can store its own configuration data specifying its respective reliability grade and lifetime PEC, and current PEC. In some examples, a memory or register can be associated with all of the memory components 112A-112N and can store a table mapping different groups, bins, or sets of memory components 112A-112N to their respective reliability grades, lifetime PEC values, and / or current PEC values.

[0024] In some examples, a memory or register can be associated with all of the memory components 112A - 112N and can store a table that maps portions of the memory components 112A - 112N to different groups of RGs. The table can specify which sets of the memory components 112A - 112N map to or are associated with and grouped into a first RG and which portions of the memory components 112A - 112N within that set correspond to RUs within the first RG. The table can also store a display and track the number of PECs of the first RG. Similarly, the table can specify which other sets of the memory components 112A - 112N map to or are associated with and grouped into a second RG and which portions of the memory components 112A - 112N within that set correspond to RUs within the second RG. In some cases, the table stores a list of LBAs associated with each RU.

[0025] In some examples, the memory subsystem 110 is a storage system. The memory subsystem 110 can be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controllers (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO - DIMMs), and non - volatile dual inline memory modules (NVDIMMs).

[0026] The computing environment 100 may include a host system 120 coupled to a memory system. The memory system may include one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 shows an example of a host system 120 coupled to one memory subsystem 110. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to connections between components that can be indirect or direct (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, and magnetic.

[0027] The host system 120 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, or embedded computer (e.g., one contained in a vehicle, industrial equipment, or networked commercial device), or such a computing device including memory and processing devices. The host system 120 may include or be coupled to the memory subsystem 110 so that the host system 120 can read data from or write data to the memory subsystem 110. The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, the Serial Advanced Technology Attachment (SATA) interface, Peripheral Component Interconnection Express (PCIe) interface, Computer Express Link (CXL) interface, Universal Serial Bus (USB) interface, Fibre Channel interface, and Serial Attached SCSII (SAS) interface. The physical host interface can be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe or CXL interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for passing control signals, address signals, data signals, and other signals between the memory subsystem 110 and the host system 120.

[0028] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. An example of a non-volatile memory component is a negative AND (NAND) flash memory. Each of memory components 112A to 112N may include one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., TLC or QLC). In some examples, a particular memory component 112 may include both SLC and MLC portions of a memory cell. Each memory cell may store one or more bits of data (e.g., a block) used by the host system 120. Although non-volatile memory components such as NAND flash memory have been described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, the memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase-change memory (PCM), magnetoresistive random access memory (MRAM), negative OR (NOR) flash memory, electrically erasable and programmable read-only memory (EEPROM), and crosspoint arrays of non-volatile memory cells.

[0029] A crosspoint array of non-volatile memory cells, in combination with a stackable cross-grid data access array, can perform bit storage based on changes in bulk resistance. Furthermore, in contrast to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, allowing the non-volatile memory cells to be programmed without being pre-erased. In addition, the memory cells of memory components 112A-112N can be grouped as memory pages or blocks that can reference units of memory component 112 used to store data. For example, a single first row spanning a first set of pages or blocks of memory components 112A-112N may correspond to or be grouped as a first block stripe, and a single second row spanning a second set of pages or blocks of memory components 112A-112N may correspond to or be grouped as a second block stripe.

[0030] The memory subsystem controller 115 can communicate with the memory components 112A to 112N to perform memory operations such as reading data, writing data, or erasing data, and other such operations. The memory subsystem controller 115 can also communicate with the memory components 112A to 112N to perform various memory management operations, such as different scan speeds, different scan frequencies, different wear leveling, different read disturb management, garbage collection operations, different near-miss ECC operations, and / or different dynamic data refreshes.

[0031] The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or separate components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in the local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing routines that control the operation of the memory subsystem 110, including processing various processes, operations, logic flows, and communications between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers that store memory pointers, fetched data, etc. The local memory 119 may also include read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem 110 in Figure 1 is shown to include a memory subsystem controller 115, in other embodiments of the present disclosure the memory subsystem 110 may not include a memory subsystem controller 115 and instead may rely on external control (for example, provided by an external host or by a processor 117 or controller separate from the memory subsystem 110).

[0032] Generally, the memory subsystem controller 115 can receive commands or actions from the host system 120 and translate the commands or actions into instructions or appropriate commands to achieve desired access to memory components 112A-112N. In some examples, the commands or actions received from the host system 120 may specify configuration data for memory components 112N-112N. The configuration data may describe different groups of memory components 112N-112N and / or lifetime PEC values ​​and / or reliability grades associated with different blocks within each of the memory components 112N-112N. In some examples, the commands or actions received from the host system 120 may include write commands that specify or identify individual RGs and / or RUs within individual RGs to which data should be programmed. Based on the individual RGs specified by the write commands, the memory subsystem controller 115 can determine the memory components 112A-112N associated with the individual RGs and generate write pointers used to program data to the determined memory components 112A-112N. In some cases, the host system 120 can select individual RU handles and program data using the selected individual RU handles. Any data written by the host system 120 using individual RU handles can be stored in the designated RU associated with the RU handle. Different RUs are used by the host system 120 to physically store the data, based on which RU handles are used by the host system 120 to program the data. In some cases, the host system 120 can track which LBAs are associated with which RU handles and, based on the LBAs, can determine which RU the data is stored in.

[0033] The memory subsystem controller 115 can perform other memory management operations, such as wear leveling, garbage collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation. The memory subsystem controller 115 may further include a host interface circuit for communicating with the host system 120 via a physical host interface. The host interface circuit can convert commands received from the host system 120 into command instructions for accessing memory components 112A-112N, and convert responses associated with memory components 112A-112N into information for the host system 120.

[0034] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM or other temporary storage location or device) and addressing circuitry (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory components 112A-112N.

[0035] A memory device may be a raw memory device (e.g., NAND) managed externally by an external controller (e.g., a memory subsystem controller 115). A memory device may be a managed memory device (e.g., managed NAND) which is a raw memory device combined with a local embedded controller (e.g., a local media controller) for memory management within the same memory device package. Any one of the memory components 112A to 112N may include a media controller (e.g., media controllers 113A and 113N) to manage the memory cells of the memory component (e.g., to perform one or more memory management operations), to communicate with the memory subsystem controller 115, and to execute memory requests (e.g., read or write) received from the memory subsystem controller 115.

[0036] The memory subsystem controller 115 may include a media operation manager 122. The media operation manager 122 can be configured to coordinate with the host system 120 regarding which data needs to be folded. That is, the media operation manager 122 can delay folding data (or performing other media management operations) until a timer and / or event expires, and informs the host system 120 about the possibility of performing a folding operation on data stored in a particular memory component (e.g., logical block addresses (LBA), RG, and / or RU). The host system 120 can analyze the data and selectively deallocate or invalidate the data to prevent the media operation manager 122 from performing a media management operation such as a garbage collection operation or a folding operation on that data. This reduces write amplitude and improves the overall efficiency of the memory subsystem 110's operation.

[0037] Depending on the example, the media operation manager 122 may include logic (e.g., a set of transient or non-transient machine instructions, such as firmware) or one or more components that cause the media operation manager 122 to perform the operations described herein. The media operation manager 122 may include tangible or intangible units that can perform the operations described herein. Further details regarding the operation of the media operation manager 122 are described below.

[0038] Figure 2 is a block diagram of an exemplary media operation manager 200 (corresponding to media operation manager 122) according to some embodiments of the present disclosure. As shown, the media operation manager 200 includes configuration data 220 and a folding management component 230. In some examples, the media operation manager 200 may differ in components or arrangement from that shown in Figure 2 (for example, fewer or more components).

[0039] Configuration data 220 accesses and / or stores configuration data associated with memory components 112A-112N. In some examples, configuration data 220 is programmed within the media operation manager 200. For example, the media operation manager 200 can communicate with memory components 112A-112N to retrieve configuration data and store configuration data 220 locally in the media operation manager 122. In some examples, the media operation manager 122 communicates with the host system 120. The host system 120 receives input from an operator or user specifying parameters including a configurable timer value that controls how much delay the media operation manager 122 gives before folding the data, an event that triggers the execution of the folding operation, lifetime PEC values ​​for different bins, groups, blocks, block stripes, memory dies, and / or sets of memory components 112A-112N, and / or group assignments that define different RU and RG sizes. The media operation manager 122 receives configuration data from the host system 120 and stores the configuration data in configuration data 220.

[0040] The configuration data 220 can store a map that identifies which set of memory components 112A to 112N is used to implement different RGs. For example, the configuration data 220 can store a map that associates a first RG with a first part of memory components 112A to 112N (e.g., a first set of the first die or LBA) and a second RG with memory components 112A to 112N (e.g., a second set of the second die or LBA). That is, the map can store the physical address or LUN representation of the first part of memory components 112A to 112N associated with the first RG, and the physical address or LUN representation of the second part of memory components 112A to 112N associated with the second RG.

[0041] For example, Figure 3 is a block diagram of an exemplary embodiment of the RG system 300 of the memory subsystem 110. The RG system 300 includes a placement handle component 320 used to store different groups of maps (e.g., maps stored by configuration data 220). The RG system 300 can receive a write command 310 specifying at least an RG and / or a placement handle. The placement handle component 320 can use the placement handle 322 to look up a map to identify a RU 324 associated with the specified RG. The RG system 300 can then generate a write pointer 330 to write data to the identified RU 324.

[0042] As shown in Figure 3, multiple RGs are defined. For example, RG system 300 includes a first RG340 and a second RG342. The first RG340 includes a first group of RU350. The second RG342 includes a second group of RU352. In some cases, the first RG340 may represent a single memory die, and the second RG342 may represent another single memory die. Each RU in the first group of RU350 is implemented by a part of memory components 112A-112N, such as blocks, planes, superblocks, and pages. Similarly, each RU in the second group of RU350 is implemented by a different part of memory components 112A-112N, such as blocks, planes, superblocks, and pages. All garbage collection operations performed within the RU of an individual RG are constrained to that individual RG. For example, a garbage collection operation performed on individual RUs in the first group of RU350 will fold the data using only the RUs in the first group of RU350, and a garbage collection operation performed on individual RUs in the second group of RU352 will fold the data using only the RUs in the second group of RU352.

[0043] Referring again to Figure 2, the folding management component 230 can identify one or more memory components 112A-112N that need to be folded. For example, the folding management component 230 can look up the memory components 112A-112N to determine whether one or more memory components 112A-112N meet one or more folding criteria. One or more folding criteria may include at least one of low free block count, static wear leveling, read disturb, and / or error handling. The folding management component 230 may optionally select one or more RUs for folding or garbage collection. Accordingly, the folding management component 230 may store each memory component 410 selected for folding in table 400 (shown in Figure 4). In some cases, the folding management component 230 may store identifiers 446 of LBAs that are subject to folding or selected for folding. The folding management component 230 can store identifiers 412 of one or more RUs and / or RGs that are subject to folding or selected for folding.

[0044] The folding management component 230 can also store a corresponding timer 440 associated with each identifier of the memory component 410. The timer 440 may be configurable and can be used to control or delay the folding of data stored in the memory components 112A-112N identified by the identifiers of the memory component 410. The timer 440 can be a specified amount, such as an individual value 444 (e.g., a specified threshold). When the individual value 444 exceeds the limit (e.g., the timer has completely elapsed or reached the specified value), the corresponding data stored in the memory component identified by the memory component 410 can be folded (e.g., written to another RU or another part of the memory components 112A-112N). In some examples, when the timer 440 expires (reaches the specified value), the folding management component 230 determines whether the data stored in the corresponding memory components 112A-112N still needs to be folded. The folding management component 230 can therefore condition the folding of the data based on this determination. Different parts of memory component 410 can be associated with different timer values. For example, identifier 412 corresponding to a first set of RUs can be associated with timer value 449, while another set of RUs or another part of memory components 112-112N can be associated with individual values ​​444 having timer values ​​different from timer value 449.

[0045] In some examples, the timer 440 can be associated with a specific event 448, such as a power-based event. When a specific event 448 occurs, the corresponding data stored in the memory component identified by the memory component 410 can be folded (for example, written to another RU or another part of memory components 112A-112N).

[0046] For example, the host system 120 can generate an instruction to deallocate or invalidate data stored in memory components 112A-112N associated with a specific identifier among the identifiers stored in memory component 410. In such a case, the folding management component 230 can prevent or avoid folding the data stored in memory components 112A-112N associated with a specific identifier among the identifiers. If the host system 120 does not send an instruction to deallocate or invalidate the data before the timer expires or before the event stored in timer 440 is reached, the folding management component 230 can continue executing an instruction to fold the data.

[0047] In some examples, in response to adding entries such as identifier 446 and / or identifier 412 to table 400, the folding management component 230 can generate a communication for transmission to the host system 120 that contains or represents the added entries to table 400. In some examples, the folding management component 230 sends the communication in direct response to adding entries to table 400 so that the communication is sent asynchronously. In some cases, the host system 120 can query a log file stored by the folding management component 230 to retrieve communications periodically. In any case, the host system 120 can identify one or more LBAs to be folded based on the communications received from the folding management component 230. The host system 120 can then determine which RUs are being used to store the data and whether the data is still needed. If the data is no longer needed, the host system 120 can generate an instruction to deallocate the data from the RU identified in the communications received from the folding management component 230. The host system 120 can prevent data from folding by sending a command to deallocate the data before the timer associated with the RU expires. In some cases, the host system 120 can identify one or more LBAs in the communication received from the folding management component 230. The host system 120 can then pad one or more LBAs with multiple adjacent LBAs to create areas in memory components 112A-112N to be deallocated. The host system 120 can send a command to deallocate the data stored in the areas to prevent data stored in memory components 112A-112N from folding.

[0048] Figure 5 is a flowchart of exemplary method 500 for enabling a host to participate in a folding operation according to several embodiments of the present disclosure. Method 500 can be executed by processing logic that may include hardware (e.g., processing devices, circuits, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions executed by the processing devices), or a combination thereof. In some embodiments, method 500 is executed by the media operation manager 122 of Figure 1. The processes are shown in a specific sequence or order, but unless otherwise specified, the order of the processes can be modified. Thus, illustrated examples should be understood as examples only, the illustrated processes can be executed in a different order, and some processes can be executed in parallel. Furthermore, one or more processes can be omitted in various embodiments. Thus, not all processes are required in all embodiments. Other process flows are also possible.

[0049] Here, as shown in Figure 5, method (or process) 500 begins with operation 510, in which the media operation manager 122 of the memory subsystem (e.g., memory subsystem 110) identifies one or more RUs that need to be folded. Next, in operation 520, the media operation manager 122 notifies the host of one or more RUs that need to be folded, including one or more LBAs of the RUs that communicate asynchronously or synchronously (e.g., via log files). In operation 530, the media operation manager 122 configures a delay for performing the folding operation on the data stored in the one or more RUs, and in operation 540 determines whether the instruction is received from the host in relation to the data stored in the one or more RUs. Specifically, in operation 540, the media operation manager 122 determines whether the folding operation is still required for the data stored in the one or more RUs, for example, based on whether the host deallocates or invalidates the data stored in the one or more RUs. In operation 550, the media operation manager 122 executes an instruction to fold data stored in one or more RUs, such as when the timer associated with a configurable delay expires before it receives an instruction from the host to deallocate or invalidate the data. Then, in operation 560, the media operation manager 122 logs the folding event to the FDP log.

[0050] Figure 6 is a flowchart of exemplary method 600 for enabling a host to participate in a folding operation according to several embodiments of the present disclosure. Method 600 can be carried out by processing logic that may include hardware (e.g., processing devices, circuits, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions actuated or executed by the processing devices), or a combination thereof. In some examples, method 600 is performed by the media operation manager 122 in Figure 1. The processes are shown in a specific sequence or order, but unless otherwise specified, the order of the processes can be modified. Thus, illustrated examples should be understood as examples only, the illustrated processes can be executed in a different order, and some processes can be executed in parallel. Furthermore, one or more processes can be omitted in various embodiments. Thus, not all processes are required in all embodiments. Other process flows are also possible.

[0051] Referring here to Figure 6, method (or process) 600 begins in operation 605, when the media operation manager 122 of the memory subsystem (e.g., memory subsystem 110) generates an instruction to fold the data stored in the individual parts of the set of memory components. Next, in operation 610, the media operation manager 122 sends a communication to the host indicating the instruction to fold the data before executing the instruction to fold the data. In operation 615, the media operation manager 122 conditions the execution of the instruction to fold the data stored in the individual parts based on the transmission of the communication to the host (e.g., based on whether the host deallocated the data before the timer or event expired).

[0052] In consideration of the above disclosures, various examples are listed below. Note that one or more features of the examples should be considered individually or in combination within the disclosures of this application.

[0053] Example 1: A system comprising a set of memory components of a memory subsystem, and at least one processing device operably coupled to the set of memory components, the processing device being configured to perform an operation which includes generating instructions for folding data stored in individual parts of the set of memory components, sending a communication to a host indicating the instructions for folding data stored in the individual parts of the set of memory components before executing the instructions for folding data stored in the individual parts of the set of memory components, and conditional on the transmission of the communication to the host on executing the instructions for folding data stored in the individual parts of the set of memory components.

[0054] Example 2. The system described in Example 1, wherein the memory subsystem includes flexible data placement (FDP).

[0055] Example 3. The system according to Example 2, wherein the operation involves grouping the set of memory components into a plurality of recyclable groups (RGs), each of the plurality of RGs comprising a subset of recyclable units (RUs), and the individual parts comprising the individual RUs of the subset of RUs of the individual RG.

[0056] Example 4. The system according to any one of Examples 1 to 3, wherein the operation includes initializing a timer in response to transmitting the communication to the host, determining that the timer has reached a threshold before receiving an instruction from the host in relation to the individual parts, and automatically folding the data stored in the individual parts of the set of memory components in response to the determination that the timer has reached a threshold before receiving an instruction from the host in relation to the individual parts.

[0057] Example 5. The system according to Example 4, wherein the operation includes preventing the data stored in the individual parts from folding in response to the timer receiving the command from the host before the threshold is reached.

[0058] Example 6. The system according to Example 5, wherein the instruction includes a request to deallocate or invalidate the data stored in the individual parts.

[0059] Example 7. The timer is configurable, as described in any one of Examples 4-6.

[0060] Example 8. The system according to any one of Examples 1 to 7, wherein the operation includes receiving a command from the host to deallocate or invalidate the data stored in the individual parts, and preventing the data stored in the individual parts from folding in response to receiving the command from the host.

[0061] Example 9. The system according to any one of Examples 1 to 8, wherein the operation includes identifying one or more logical block addresses (LBAs) associated with the data stored in the individual parts, and providing the identified one or more LBAs to the host in the communication.

[0062] Example 10. The system according to Example 9, wherein the operation includes the host identifying a plurality of LBAs, including the one or more LBAs and an additional set of adjacent LBAs, and the host generating an instruction to deallocate or invalidate the data stored in the plurality of LBAs.

[0063] Example 11. The system according to any one of Examples 1 to 10, wherein the communication is asynchronous and sent to the host in response to generating the instruction to fold the data stored in individual parts.

[0064] Example 12. The system according to any one of Examples 1 to 11, wherein the communication is stored in a log file on the memory subsystem, and the operation includes receiving a request from the host to read the log file, and in response to receiving the request from the host to read the log file, retrieving the communication for transmission to the host.

[0065] Example 13. The system according to any one of Examples 1 to 12, wherein the operation involves grouping the set of memory components into a plurality of recyclable groups (RGs), each RG of which includes a subset of recyclable units (RUs), and the individual portion includes individual RUs of the subset of RUs of the individual RG, and folding the data stored in the individual RUs into another RU of the RG.

[0066] Example 14. The communication is the system described in Example 13, which identifies the individual RUs of a subset of the RUs.

[0067] Example 15. The system according to any one of Examples 1 to 14, wherein the instruction for folding the data is generated in response to determining that the individual parts satisfy one or more folding criteria.

[0068] Example 16. The system according to Example 15, wherein the one or more folding criteria include at least one of a low free block count, static wear leveling, read disturb, or error handling.

[0069] A method having instructions for performing any one of the above examples, and a computer-readable storage medium.

[0070] Figure 7 shows an exemplary machine of the form of computer system 700, in which a set of instructions can be executed to cause the machine to perform one or more of the methods described herein. In some embodiments, computer system 700 may correspond to a host system (e.g., host system 120 in Figure 1) which is coupled to or utilizes a memory subsystem (e.g., memory subsystem 110 in Figure 1), or can be used to perform controller operations (e.g., to run an operating system to perform operations corresponding to the media operation manager 122 in Figure 1). In alternative embodiments, the machine may be connected to other machines in a local area network (LAN), intranet, extranet, and / or the internet (e.g., network-connected). The machine may function as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0071] A machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, web appliance, server, network router, network switch, network bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by that machine. Furthermore, although a single machine is shown, the term “machine” shall also be interpreted as including any collection of machines that individually or collectively execute one or more sets of instructions in order to perform any one or more of the methods described herein.

[0072] An exemplary computer system 700 includes a processing device 702, main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static memory 706 (e.g., flash memory, static random access memory (SRAM)), and a data storage device 718, which communicate with each other via a bus 730.

[0073] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor or a central processing unit. More specifically, the processing device 702 may be a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. The processing device 702 may also be one or more dedicated processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or similar. The processing device 702 is configured to execute instructions 726 for performing the operations and steps described herein. The computer system 700 may further include a network interface device 708 for communication over the network 720.

[0074] The data storage device 718 may include a machine-readable storage medium 724 (also known as a computer-readable medium) in which one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein are stored. The instructions 726 may also reside entirely or at least partially in the main memory 704 or in the processing device 702 during their execution by the computer system 700, and the main memory 704 and / or the processing device 702 also constitute the machine-readable storage medium. The machine-readable storage medium 724, the data storage device 718, and / or the main memory 704 may correspond to the memory subsystem 110 in Figure 1.

[0075] In one embodiment, instruction 726 implements a function corresponding to the media operation manager 122 in Figure 1. Although the machine-readable storage medium 724 is shown as a single medium in the exemplary embodiment, the term “machine-readable storage medium” should be interpreted to include a single or more mediums that store one or more sets of instructions. The term “machine-readable storage medium” should also be interpreted to include any medium capable of storing or encoding a set of instructions for execution by a machine, causing the machine to execute one or more of the methods of this disclosure. Accordingly, the term “machine-readable storage medium” should be interpreted to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0076] Some of the preceding detailed explanations are presented in terms of algorithms and symbolic representations of operations on data bits in computer memory. Such descriptions and representations of algorithms are methods used by those skilled in the art in data processing techniques to most effectively convey the essence of their operation. Here, and generally, an algorithm is considered to be a self-consistent sequence of operations leading to a desired result. Operations require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Primarily for reasons of common use, it has sometimes been found convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0077] However, it should be recognized that all these and similar terms should be related to appropriate physical quantities and are merely convenient designations applicable to those quantities. This disclosure may refer to actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities in the registers and memory of a computer system and convert them into other data similarly represented as physical quantities in the memory or registers of a computer system or such information storage system.

[0078] This disclosure also relates to an apparatus for performing the operations described herein. This apparatus may include a general-purpose computer that can be built specifically for the intended purpose or that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in any type of disk, including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), erasable and programmable read-only memory (EPROM), EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each of which is coupled to a computer system bus.

[0079] The algorithms and representations described herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used programmatically in accordance with the teachings herein, or it may be advantageous to construct more specialized equipment to perform the methods. The structures of various such systems appear as described above. Furthermore, this disclosure does not describe any particular programming language. It should be understood that various programming languages ​​may be used to perform the teachings of this disclosure as described herein.

[0080] This disclosure may be presented as a computer program product or software that includes a machine-readable medium containing instructions that can be used to program a computer system (or other electronic device) to perform a process in accordance with this disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable (e.g., computer-readable) storage media such as read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, and flash memory components.

[0081] In the above-mentioned specification, embodiments of the disclosure have been described with reference to specific exemplary embodiments. It is evident that various modifications can be made without departing from the broader scope of the disclosure set forth in the following claims. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

Claims

1. It is a system, The set of memory components of the memory subsystem, At least one processing device operably coupled to the set of memory components, To generate instructions for folding the data stored in individual parts of the set of memory components, Before executing the instruction to fold the data stored in the individual parts of the set of memory components, a communication indicating the instruction to fold the data stored in the individual parts is sent to the host. The execution of the instruction to fold the data stored in the individual parts of the set of memory components is conditional on the transmission of the communication to the host, The at least one processing device configured to perform an operation including, The system comprising the above.

2. The system according to claim 1, wherein the memory subsystem includes flexible data placement (FDP).

3. The aforementioned operation is, The grouping of the set of memory components into a plurality of recyclable groups (RGs), wherein each RG of the plurality of RGs includes a subset of recyclable units (RUs), and each of the individual parts includes the individual RUs of the subset of RUs of the individual RG. The system according to claim 2, including the above.

4. The aforementioned operation is, Initializing the timer in response to sending the communication to the host, In relation to the individual parts, it is determined that the timer has reached a threshold before receiving a command from the host, In response to the timer determining that the threshold has been reached before receiving the instruction from the host in relation to the individual parts, the data stored in the individual parts of the set of memory components is automatically folded. The system according to claim 1, including the following:

5. The aforementioned operation is, In response to the timer receiving the command from the host before reaching the threshold, prevent the data stored in the individual parts from folding. The system according to claim 4, including the system described in claim 4.

6. The system according to claim 5, wherein the instruction includes a request to deallocate or invalidate the data stored in the individual parts.

7. The system according to claim 4, wherein the timer is configurable.

8. The aforementioned operation is, Receiving a command from the host to deallocate or invalidate the data stored in the individual parts, In response to receiving the command from the host, prevent the data stored in the individual parts from being folded, The system according to claim 1, including the following:

9. The aforementioned operation is, Identifying one or more logical block addresses (LBAs) associated with the data stored in each of the aforementioned parts, To provide the identified one or more LBAs to the host in the communication, The system according to claim 1, including the following:

10. The aforementioned operation is, The host identifies a plurality of LBAs, including the one or more LBAs and an additional set of adjacent LBAs. The host generates an instruction to deallocate or invalidate the data stored in the multiple LBAs, The system according to claim 9, including the system described in claim 9.

11. The system according to claim 1, wherein the communication is asynchronous and transmitted to the host in response to generating instructions for folding the data stored in the individual parts.

12. The aforementioned communication is stored in a log file on the memory subsystem, and the aforementioned operation is, Receiving a request from the host to read the log file, In response to receiving the request from the host to read the log file, the communication is retrieved for transmission to the host, The system according to claim 1, including the following:

13. The aforementioned operation is, The grouping of the set of memory components into a plurality of recyclable groups (RGs), wherein each RG of the plurality of RGs includes a subset of recyclable units (RUs), and each of the individual parts includes the individual RUs of the subset of RUs of the individual RG, The data stored in each of the aforementioned RUs is folded into another RU of each of the aforementioned RGs, The system according to claim 1, including the following:

14. The system according to claim 13, wherein the communication identifies the individual RUs of a subset of the RUs.

15. The system according to claim 1, wherein the instruction for folding the data is generated in response to determining that the individual parts satisfy one or more folding criteria.

16. The system according to claim 15, wherein the one or more folding criteria include at least one of a low free block count, static wear leveling, read disturb, or error handling.

17. It is a method, To generate instructions for folding data stored in individual parts of a set of memory components of a memory subsystem, Before executing the instruction to fold the data stored in the individual parts of the set of memory components, a communication indicating the instruction to fold the data stored in the individual parts is sent to the host. The execution of the instruction to fold the data stored in the individual parts of the set of memory components is conditional on the transmission of the communication to the host, The method, including the method described above.

18. The method according to claim 17, wherein the memory subsystem includes flexible data placement (FDP).

19. The method according to claim 18, comprising grouping the set of memory components into a plurality of recyclable groups (RGs), wherein each RG of the plurality of RGs includes a subset of recyclable units (RUs), and the individual parts include individual RUs of the subset of RUs of the individual RG.

20. A non-temporary computer-readable storage medium, which, when executed by at least one processing device, the at least one processing device, To generate instructions for folding data stored in individual parts of a set of memory components of a memory subsystem, Before executing the instruction to fold the data stored in the individual parts of the set of memory components, a communication indicating the instruction to fold the data stored in the individual parts is sent to the host. The execution of the instruction to fold the data stored in the individual parts of the set of memory components is conditional on the transmission of the communication to the host, The non-temporary computer-readable storage medium includes instructions for performing an operation that includes the following.

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