System and method for correct-by-construction timing convergence for face-to-face bonding

Abstract

A system and related method for achieving correct-by-construction timing convergence may comprise a first semiconductor device providing a thin interface module on a base die, the thin interface module including an address register mechanism for an address interconnect that follows an address clock from an address clock interconnect, a data register mechanism for a data interconnect that follows a data clock from a data clock interconnect, and a plurality of junction mechanisms that communicate with a second semiconductor device via the address interconnect and the data interconnect.

Description

Technical Field

[0004] ,

[0003]

[0001] Cross - reference to related applications This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 518,988, filed on August 11, 2023, entitled "INTEGRATED CIRCUIT HAVING MEMORIES AND A SHARED WRITE PORT", identified by filing number P23 - 133 - US - PSP, the entire content of which is incorporated herein by reference.

[0002] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,733, filed on November 27, 2023, entitled "METHOD AND SYSTEM FOR KNOWN - GOOD - DIE TESTABILITY OF FACE - TO - FACE BONDED CHIPLETS", the entire content of which is incorporated herein by reference.

[0003] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 602,737, filed on November 27, 2023, entitled "SYSTEM AND METHOD FOR HAVING CORRECT - BY - CONSTRUCTION TIMING CLOSURE", the entire content of which is incorporated herein by reference.

[0004] This application claims the benefit and priority of U.S. Provisional Patent Application No. 63 / 567,649, filed on March 20, 2024, entitled "ASSEMBLY HAVING A FACE - TO - FACE BONDED CHIPLET", identified by filing number P24 - 052 - US - PSP, the entire content of which is incorporated herein by reference.

[0005] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,742, filed on 23 April 2024, identified by reference number P24-081-US-PSP, entitled “INTEGRATED CIRCUIT HAVING MICROVAULT MEMORIES,” the entire contents of which are incorporated herein by reference.

[0006] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 637,764, filed on 23 April 2024, identified by reference number P24-082-US-PSP, entitled “FEFET STRUCTURES ON INTEGRATED CIRCUITS,” the entire contents of which are incorporated herein by reference.

[0007] This application claims the interests and priority of U.S. Provisional Patent Application No. 63 / 674,471, filed on 23 July 2024, identified by reference number P24-135-US-PSP, entitled “SYSTEM, METHOD, AND APPARATUS FOR WAFER-SCALE MEMORY,” the entire contents of which are incorporated herein by reference.

[0008] Technical field This disclosure relates to an integrated circuit. More specifically, this disclosure relates to a system and method involving correct-by-construction timing convergence. [Background technology]

[0009] Explanation of related technologies A chiplet refers to a small chip designed to function as a single entity while utilizing advanced packaging technology. This miniaturized chip is created by dividing a larger chip into several smaller chips, each possessing a unique function or capability. The concept, stemming from the semiconductor industry, requires overcoming the physical limitations of traditional monolithic chip designs and achieving higher levels of integration. The idea behind chiplets is to create a modular system of interconnected and interchangeable chips that can be combined in different configurations to create advanced computing systems with improved performance, power efficiency, and functionality. [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] Chiplets are derived from different architectures such as CPUs, GPUs, memory, or I / O, and can be assembled and stacked in various ways according to the requirements of a specific application. One of the advantages of the chiplet approach is that different chiplets from different manufacturers can be mixed and matched to create custom solutions that meet specific computing requirements. Because chiplets can be upgraded or replaced without requiring a complete system redesign, this approach also enables shorter time to market, reduced development costs, and increased flexibility.

[0011] The effects of chiplets can be utilized in a variety of industries, including consumer electronics, cloud computing, and data centers, where there is a high demand for high-performance computing and energy efficiency. Chiplets are expected to play a significant role in future computing and are thought to unlock new possibilities for creating more powerful and / or advanced electronic devices. [Means for solving the problem]

[0012] Summary of the Invention

[0013] A system for achieving correct-by-construction timing convergence is disclosed herein, comprising a first semiconductor device having a thin interface module, an address register for storing addresses for the address interconnect based on an address clock from an address clock interconnect, a data register for storing data for the data interconnect based on a data clock from a data clock interconnect, and a plurality of junctions on the surface of the first semiconductor device, designed to interface with a second semiconductor device connected to and bonded to the address interconnect and the data interconnect.

[0014] This system is designed, as an optional feature, to achieve correct-by-construction timing convergence between the first and second semiconductor devices. Optionally, the first and second semiconductor devices in this system may be face-to-face bonded together. Optionally, the first and second semiconductor devices in this system may be stacked together. Another optional feature of this system is that the address clock interconnect and data clock interconnect may be connected to merge the address clock and data clock.

[0015] In one embodiment, a data register in the system may be a read data register designed to receive read data through a data interconnect. Optionally, the system may also include a write data register, which is configured to store write data in the register and provide the write data to a plurality of write data interconnects, and the plurality of interconnects also include these write data interconnects. In another embodiment, a data register may be a write data register designed to provide write data to a data interconnect. Furthermore, the system may include at least two read data registers designed to receive read data from a plurality of read data interconnects, where the plurality of interconnects also include these read data interconnects.

[0016] In a further embodiment, the first semiconductor device in the system may have a read interface register, where an address register and a data register together form this read interface register. This read interface register is designed to store read addresses and read data from a read interconnect based on a read clock from a read clock interconnect. The read interconnect includes an address interconnect and a data interconnect, while the address clock and data clock form a read clock. The address clock interconnect and the data clock interconnect also form a read clock interconnect. Furthermore, the first semiconductor device may include a write interface register designed to store write addresses and write data from a write interconnect in accordance with a write clock from a write clock interconnect. Multiple read junctions operably connected to the read interconnect of the read interface register may be located on the surface of the first semiconductor device, and these junctions also comprise these read junctions. Furthermore, multiple write junctions operably connected to the write interconnect of the write interface register may be located on the surface of the first semiconductor device.

[0017] In one embodiment, the system includes a second semiconductor device having a read peripheral, the read peripheral having a read peripheral interconnect connected to the surface of the second semiconductor device and configured to connect to a plurality of read junctions, thereby connecting the read peripheral of the second semiconductor device to the read interface register of the first semiconductor device. In another embodiment, the system includes a second semiconductor device having a write peripheral, the write peripheral having a write peripheral interconnect connected to the surface of the second semiconductor device and configured to connect to a plurality of write junctions, thereby connecting the write peripheral of the second semiconductor device to the write interface register of the first semiconductor device. In yet another embodiment, the read interconnect consists of a read address interconnect and a read data interconnect. Furthermore, the system may have a plurality of read junctions, including read address junctions located on the surface of the first semiconductor device and operably connected to the read address interconnect of the read interface register, and read data junctions located on the surface of the first semiconductor device and operably connected to the read data interconnect of the read interface register. Furthermore, multiple junctions may include read clock junctions, and the read clock interconnect optionally connects the read clock junctions to read interface registers.

[0018] In one embodiment, the system features a write interconnect comprising a write address interconnect and a write data interconnect. Furthermore, the system may include a plurality of write junctions, each having a plurality of write address junctions and a plurality of write data junctions, which are located on the surface of the first semiconductor device and connected to the write address interconnect and the write data interconnect of the write interface register, respectively. Optionally, the junctions of the system may also include a write clock junction, the write clock interconnect connecting this junction to the write interface register.

[0019] A method for forming a semiconductor device with correct-by-construction timing convergence includes forming a thin interface module on a base die, creating address registers and data registers within the thin interface module, and forming a series of junctions on the surface of a first semiconductor device that connect to an address interconnect and a data interconnect. These junctions are then bonded to a second semiconductor device. A possible improvement to this method is that the thin interface module may be located close to the junctions, specifically at a distance less than a predetermined distance. This enables correct-by-construction timing convergence between the first and second semiconductor devices. In one embodiment, the method includes bonding a plurality of junctions to the second semiconductor device by face-to-face bonding of the first semiconductor device to the second semiconductor device. In another embodiment, the bonding process includes stacking the first and second semiconductor devices together. Furthermore, the thin interface module may be formed on the base die by creating the thin interface module beneath a plurality of junctions. Alternatively, the plurality of junctions may be formed on top of the thin interface module. Furthermore, the forming operations in the method may be implemented according to a netlist.

[0020] In the method, multiple junctions and address registers are formed in a separation relationship from one another such that communication between the junctions and address registers takes less than a predetermined amount of time. Furthermore, address interconnects and data interconnects are wired perpendicularly to the multiple junctions. Moreover, both the first and second semiconductor devices are joined together. Optionally, this joining can be achieved using face-to-face bonding techniques. The first and second semiconductor devices can then be stacked together in the method.

[0021] In one embodiment, the method includes merging an address clock interconnect and a data clock interconnect together, resulting in the merging of the address clock and the data clock. In another embodiment, the method includes receiving read data via a data interconnect, the data register used being a read data register. Furthermore, this embodiment may optionally include storing write data in a write data register and providing write data to a plurality of write data interconnects, where the plurality of interconnects also include write data interconnects. In yet another embodiment, the method includes providing write data to a data interconnect, where the data register functions as a write data register. Furthermore, this embodiment may optionally include receiving first read data from a first memory module in a second semiconductor device in a first read data register and receiving second read data from a second memory module in a second read data register in a second semiconductor device.

[0022] In one embodiment, the method includes a first semiconductor device having a read interface register formed by an address register and a data register, configured to store read addresses from a read address interconnect and read data from a read interconnect in accordance with a read clock from a read clock interconnect, and a write interface register configured to store write addresses and write data from a write interconnect in accordance with a write clock from a write clock interconnect. Furthermore, the first semiconductor device has a plurality of read junctions and write junctions disposed on the surface of the first semiconductor device, which are operably connected to the read interconnect and write interconnect of the read interface register and the write interface register, respectively.

[0023] In another embodiment, the method further includes a second semiconductor device having a read peripheral, the read peripheral having a read peripheral interconnect connected to the surface of the second semiconductor device and configured to connect to a plurality of read junctions in the first semiconductor device, thereby connecting the read peripheral of the second semiconductor device to the read interface register of the first semiconductor device. In yet another embodiment, the method also includes a second semiconductor device having a write peripheral, the write peripheral having a write peripheral interconnect connected to the surface of the second semiconductor device and configured to connect to a plurality of write junctions in the first semiconductor device, thereby connecting the write peripheral of the second semiconductor device to the write interface register of the first semiconductor device. Furthermore, in an alternative embodiment, the read interconnect of the method comprises a read address interconnect and a read data interconnect. And in another embodiment, the plurality of read junctions comprises read address junctions and read data junctions located on the surface of the first semiconductor device, which are operably connected to the read address interconnect and read data interconnect of the read interface register, respectively. In one embodiment of the method, the plurality of junctions may include read clock junctions that enable a read clock interconnect to connect the read clock junctions to read interface registers. In another embodiment, the write interconnect in the method may consist of a write address interconnect and a write data interconnect.

[0024] Further embodiments of the method may include a plurality of write address junctions disposed on a surface of a first semiconductor device and connected to a write address interconnect of a write interface register, and a plurality of write data junctions disposed on a surface of the first semiconductor device and connected to a write data interconnect of the write interface register. Further, in another embodiment, the plurality of junctions may include a write clock junction that enables a write clock interconnect to connect the write clock junction to the write interface register. A method of using the system according to any other embodiment includes providing an address to an address register and loading the address into the address register by clocking an address clock. In one embodiment, a method of using the system may include providing data to a data register and then loading the data into the data register by clocking a data clock.

[0025] A system for achieving timing convergence in a collect bi-construction may include a first semiconductor device that provides a thin interface module in a base die, the thin interface module including an address register mechanism for an address interconnect that follows an address clock from an address clock interconnect, a data register mechanism for a data interconnect that follows a data clock from a data clock interconnect, and a plurality of junction mechanisms for communicating with a second semiconductor device via the address interconnect and the data interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] BRIEF DESCRIPTION OF THE DRAWINGS

[0027] These and other aspects will become more apparent from the following detailed description of various embodiments of the present disclosure with reference to the drawings.

[0028] [Figure 1]Figure 1 is a block diagram of an integrated circuit, which may be part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure.

[0029] [Figure 2] Figure 2 shows a perspective view of an assembly having the integrated circuit of Figure 1 mounted on a semiconductor device that is electrically connected to another device to form an assembly, according to an embodiment of the present disclosure.

[0030] [Figure 3] Figure 3 shows a block diagram illustrating the memory address space of the integrated circuit of Figure 1, according to an embodiment of the present disclosure.

[0031] [Figure 4] Figure 4 shows a block diagram illustrating the memory address space having the signal interface of the integrated circuit of Figure 1, according to an embodiment of the present disclosure.

[0032] [Figure 5] Figure 5 shows a diagram of an integrated circuit that may be part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure.

[0033] [Figure 6] Figure 6 shows a perspective view of an assembly having the integrated circuit of Figure 1 mounted on a semiconductor device electrically connected to a system-on-chip, according to an embodiment of the present disclosure.

[0034] [Figure 7A] Figure 7A shows a block diagram of a system that employs collect-by-construction timing convergence for an application chiplet having a read register and a write register, and a memory chiplet, according to an embodiment of the present disclosure. [Figure 7B]Figure 7B shows a block diagram of a system that employs collect-by-construction convergence for an application chiplet having read registers and write registers, and a memory chiplet, according to an embodiment of the present disclosure.

[0035] [Figure 8] Figure 8 shows a block diagram of a system that employs collect-by-construction timing convergence for application chiplets and memory chiplets having common read / write address registers, according to an embodiment of the present disclosure.

[0036] [Figure 9] Figure 9 shows a flowchart illustrating a method for ensuring that correct-by-construction timing convergence is achieved according to embodiments of the present disclosure. [Modes for carrying out the invention]

[0037] Modes for carrying out the invention

[0038] Figure 1 shows a block diagram of an integrated circuit 100 that can be packaged as a bondable chiplet (e.g., a bondable face-to-face chiplet) according to embodiments of the present disclosure. The integrated circuit (IC) 100 includes a group of modules 106, comprising modules 108, 110, 112, and 114. The IC 100 also features a shared write port 102 configured to write to the group of modules 106 using a write peripheral 104. Furthermore, the IC 100 includes read peripherals 116, 118, 120, and 122, as well as read ports 124, 126, 128, and 130 configured to read from modules 108, 110, 112, and 114.

[0039] The write port 102 may be configured to provide a single write address space for all of the module group 106, where each of modules 108, 110, 112, and 114 has its own dedicated read ports 124, 126, 128, and 130, respectively. The integrated circuit 100 may be packaged as part of a chiplet configured to be electrically connected to another integrated circuit device (e.g., another chiplet or IC package, with or without electrical contacts, electrical bumps, etc.). The chiplet may be electrically connected to another device by means of bonding, soldering, wafer-wafer bonding, face-face chiplet bonding, chiplet-wafer bonding, chiplet-interposer bonding, and / or together by an interposer or other interface connection technology. An interposer may not be used, one or more interposers may be used, or other interface connection technologies common to heterogeneous 3D system-in-package solutions may be used to electrically connect the chiplet to another device.

[0040] Each read port (124, 126, 128, 130) in the chiplet may feature electrical contacts on one or more sides of the chiplet. Read ports 124, 126, 128, 130 may use a multicycle pipeline circuit. When bonded to another device (e.g., wafer, chiplet, chip, SOC, package, FPGA, etc.), the electrical contacts may be arranged in a manner that provides exclusive access to specific modules 108, 110, 112, 114. For example, a processing / computation element may have exclusive access to module 108 via read port 124, which may contain neural network weights in its register file. Similarly, different processing / computation elements may have exclusive read access to module 110 via read port 126, which may contain different register files. In this particular embodiment, this arrangement of electrical contacts ensures that each computing / processing element has the dedicated access it needs to efficiently perform its specific calculation, thereby providing a compact, modular, and expandable system that allows different processing elements to maintain dedicated access to specific modules 108, 110, 112, and 114. Without dedicated access, different processing elements might have to use the same resources in a row, which would slow down the overall processing speed. By providing dedicated access, the proposed chiplet ensures, in this particular embodiment, that each processing element can operate at its maximum capacity without interference from other computing elements.

[0041] The write peripheral 104 is a peripheral circuit responsible for processing and writing data to memory cells located within modules 108, 110, 112, and 114. The write peripheral 104 may include dedicated contacts such that the chip is electrically connected (e.g., junctioned) to a chiplet of the integrated circuit, and as a result, the write port 102 is accessible via a shared write logic system that includes utilizing a shift register-based different voltage design, preferably a high-voltage design, having a shared write address and data component. This shared write logic system is designed to be accessed via a junction chip, another junction chiplet, and / or other circuitry in the same package as the integrated circuit 100. The shift register may allow the system to move data through a series of steps, each of which receives data from the previous step. By utilizing the shift register, the system can increase data throughput while maintaining a low data transfer rate. The shared write address space refers to the location where data is written to the chiplet.

[0042] In another embodiment, the interlock 132 may disable the read ports 124, 126, 128, and 130 while data is being written to the module group 106 via the write port 102. Similarly, the interlock 132 may disable the write port 102 when read operations are being performed on the read ports 124, 126, 128, and 130. The written data can then be simultaneously accessed by all processing elements that need to read the data via the respective read ports 124, 126, 128, and 130. This ensures that all processing elements have the most frequently used data available to them, regardless of other reads being performed simultaneously by other processing elements.

[0043] The circuitry of the writing peripheral 104 includes a write driver. This unit receives the data to be written and converts the data into a suitable signal that can change the state of the memory cell. Depending on the type of memory technology used, the signal may include a voltage level, a current pulse, or other type of energy. The shared write logic system may be high voltage due to the specific voltage requirements of the chiplet. The write driver must provide sufficient power to reliably change the state of the memory cell, but it must also operate within parameters suitable to avoid causing damage or unnecessary wear.

[0044] Furthermore, the circuitry of the writing peripheral 104 may feature a data buffer or a write buffer. This component temporarily stores the data to be written, enabling the write operation to be performed at an optimal pace. By balancing the rate of incoming data with the rate at which the memory cell can be written, the write buffer helps prevent data loss and optimizes system performance.

[0045] Furthermore, in some embodiments, the writing peripheral device 104 may include a write control unit that coordinates a series of operations in the writing process. This write control unit generates control signals to activate the write driver at the appropriate time, controls the flow of data from the write buffer, and adjusts the timing of the write operation. By synchronizing these various operations, the write control unit ensures efficient and reliable writing operations.

[0046] Furthermore, the writing peripheral 104 may include a data encoding mechanism to improve reliability and data integrity. For example, before data is written to the memory cell, the mechanism encodes the data in a manner that allows potential errors to be detected and, in some cases, corrected when the data is read later. This may be useful in systems where data integrity is a higher priority, such as servers or scientific research devices.

[0047] Furthermore, the writing peripheral 104 may include a timing unit that functions as the heartbeat of the system, supplying a clock signal to synchronize the operation of various components of the system. In some systems, the timing unit may include components such as an oscillator, a clock generator, or a phase-locked loop. The timing unit may ensure that all operations occur at appropriate times relative to each other.

[0048] IC100 may be implemented as a face-to-face junction chiplet in which modules 108, 110, 112, and 114 are formed from non-volatile memory. In some specific embodiments, IC100 may also feature dynamic allocation circuits for allocating memory blocks to the module group 106 based on the use of the module group 106 (for example, each module 108 may include dynamic allocation circuits that dynamically allocate a range of read locations for its respective processing elements).

[0049] IC100 features multiple clocks, each of which supplies a clock to a module of the multiple modules, providing each module with isolated timing relative to the other modules of the multiple modules. The module group 106 may be arranged in any topology known to those skilled in the art. The bit cell density can be up to 10 times denser than the embedded SRAM cells in the module group 106.

[0050] IC100 may be formed in a chiplet including a first side and a second side, the second side being configured to be bonded to a second semiconductor device. IC100 may include high-voltage writing logic adjacent to the first side of the chiplet. Decoder circuits, driver circuits, and register circuits may be formed in the silicon substrate portion of the chiplet, while the module group 106 is formed in the second layer portion of the chiplet. The second semiconductor device may comprise a plurality of processing elements. Each processing element includes an interface for communicating with each of the multiple modules in the module group 106 when the second semiconductor device is bonded to the chiplet.

[0051] Silicon substrates traditionally serve as the initial stage in IC manufacturing, focusing on the creation of active components, particularly transistors. Techniques such as diffusion, ion implantation, oxidation, and material deposition are employed to create the complex structures of transistors. These processes operate on a small scale. By applying photolithography, etching, and implantation techniques, it becomes possible to precisely define the transistor structure. The importance of silicon substrates lies in their ability to establish the basic building blocks necessary for signal processing, amplification, and control within the IC. This layer is sometimes referred to as the line front-end ("FEOL").

[0052] In the manufacturing process, a second layer may be added, which traditionally plays the role of interconnect manufacturing, facilitating electrical connections between various IC components. This stage has traditionally focused on creating passive components, including interconnects, vias, and metal-insulator-metal (MIM) capacitors. The process for the second layer is typically different from the process used on the silicon substrate in terms of precision and scale. Interconnects are formed by depositing and patterning metal layers, usually aluminum or copper, to construct a wiring network. Dielectric layers, such as silicon dioxide or low-k dielectrics, are incorporated to insulate the interconnects and prevent signal interference between different wiring layers. The traditional function of the second layer is to establish the necessary interconnects that enable the routing and distribution of electrical signals throughout the IC. However, as described herein, circuits may also be utilized within this second layer (sometimes referred to as the back-end of the line ("BEOL")).

[0053] Alternative embodiments of IC100 may be implemented as a stacked die, monolithic design, TSV, or through-silicon electrode. In a stacked die design, several dies may be stacked on top of each other, with each die performing a different function such as memory and processing. The stacked dies may communicate through wire junctions, microbumps, or bumpless junctions. In a monolithic design, the various functions and modules of IC100 may be incorporated into a single die, forming a more compact and power-efficient design.

[0054] Furthermore, IC100 may include one or more interlocks 132 to prevent conflicts when reading or writing data. The module group 106 may be formed from various non-volatile or semi-volatile (e.g., very long refresh periods) memory technologies, such as static random access memory (SRAM), ferroelectric field-effect transistors (FeFETs), ferroelectric random access memory (FeRAM), resistive random access memory (ReRAM), spin-orbit torque (SOT) memory, spin-transfer torque (STT) memory, charge traps, floating-gate memory, and / or Schottky diodes.

[0055] The module group 106 may utilize a static random access memory (SRAM) topology. The SRAM topology may employ a cross-coupled flip-flop structure (e.g., a latch flip-flop) that ensures that stored data remains intact as long as power is supplied. Therefore, in some specific embodiments, the module group 106 may utilize heterogeneous types of memory, including volatile and non-volatile memory types.

[0056] Module group 106 may utilize a flash memory topology. Flash memory is a non-volatile memory technology used in applications requiring data persistence, such as solid-state drives (SSDs) and USB flash drives. The flash memory topology disclosed herein features a matrix of memory cells, each composed of a floating-gate transistor or a charge trap device. Module group 106 may also utilize wear-leveling techniques to extend the lifespan of the memory cells.

[0057] The module group 106 may utilize a ferroelectric random access memory (FeRAM) topology. The FeRAM topology utilizes a ferroelectric material capable of maintaining a polarization state. In a particular embodiment, one such memory topology may utilize an FeFET to program the ferroelectric material by holding state information. The ferroelectric material may be used to function as a memory bit cell by holding state information.

[0058] The module group 106 may utilize a phase-change memory (PCM) topology, which is a non-volatile memory technology that utilizes a reversible phase change of material to store data. The PCM topology may include any phase-change material, for example, a chalcogenide alloy or chalcogenide glass housed within the memory cell.

[0059] The module group 106 may utilize a resistive random access memory (ReRAM) topology, which is a non-volatile memory technology based on the resistive switching phenomenon. The ReRAM topology may utilize a thin film material that exhibits a reversible change in resistance when an electrical stimulus is applied.

[0060] Module group 106 may utilize a spin-orbit torque (SOT) magnetic random access memory topology. SOT-MRAM is a type of non-volatile memory that utilizes spin-orbit torque to switch the magnetic state of storage elements. The SOT-MRAM topology may incorporate a magnetic tunnel junction (MTJ) structure and leverage spin-orbit interaction effects to write and read data. The magnetic tunnel junction may have a dielectric layer between the magnetic fixed layer and the magnetic free layer. Writing may be performed by switching the magnetization of the free magnetic layer by applying an in-plane current in an adjacent SOT layer. Reading may be performed by applying current to the magnetic tunnel junction. In some specific embodiments, SOT-MRAM can optimize the spin-orbit material by using a current-driven switching scheme while minimizing write energy consumption.

[0061] Module group 106 may utilize a spin-transfer torque (STT) magnetic random-access memory topology. STT-MRAM is another type of non-volatile memory that relies on spin-transfer torque to manipulate the magnetic state of the storage elements. The STT-MRAM topology may use a magnetic tunnel junction (MTJ) structure in which the magnetization orientation determines the stored data. Furthermore, the orientation of the magnetic layers in the magnetic tunnel junction or spin valve can be modified, for example, using a spin-polarization current.

[0062] IC100 may include a single write peripheral 104 having its own dedicated clock, or each module 108, 110, 112, 114 may have its own dedicated write peripheral utilizing a shared clock (not shown in Figure 1). Furthermore, the module group 106 may be organized into separate compartments, each having its own dedicated read peripheral 116, 118, 120, 122 having an independent clock.

[0063] Another possible embodiment of IC100 includes an interface (e.g., the same, different, higher, or lower voltage) to enable data transfer outside the packaging of IC100. Furthermore, in additional specific embodiments, IC100 may also include an integrated microcontroller unit (MCU) or digital signal processor (DSP) that processes data within the IC.

[0064] Figure 2 shows a perspective view of assembly 200 of the integrated circuit 212 of Figure 1, mounted on a chiplet 230 bonded to a second device 226 according to an embodiment of the present disclosure. The integrated circuit 212 is the circuit within the chiplet 230. The second device 226 may be a chiplet, a semiconductor wafer, a semiconductor package, a encapsulation circuit, etc. For example, the second device 226 may be an AI accelerator such that each processing unit has read access to one module (or a predetermined set) of the module group 236. In yet another embodiment, the second device 226 may be a network controller, where offload circuitry exists to read data from each of the modules and process incoming / outgoing packets, etc. The assembly 200 includes a module group 236 having a plurality of modules, including a first module 232 and a second module 234. Figure 2 shows several modules, but for clarity only modules 232 and 234 have reference numbers. The integrated circuit 212 further includes a shared write port 222. The shared write port 222 is interfaced to the write peripheral device 202.

[0065] The second device 226 may write data to any module in the module group 236 using a shared write port 222 via an address and data bus along with a clock and enable signal, although other methods of writing data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc., may be used. Each module has a read port having a read address 218 (for sending an address to module 234) and a read port 220 (for reading data from module 232).

[0066] The module group 236 is formed in a chiplet 230 having two sides including a surface 228 that can be bonded to and complement the second device 226. The chiplet 230 may be formed by forming a circuit on a silicon substrate 204 and then adding a second layer 206. In other embodiments, these layers may be in reverse order, and / or other layers may be added, removed, etc. The read address 218 and read data 220 are used to read the module 232.

[0067] The second device 226 may read data from module 232 using an address and data bus along with clock and enable signals, but other methods for reading data may be considered. For example, series connections, parallel connections, various buses, or ports such as DDR (Double Data Rate) interface, SRAM (Static Random Access Memory) interface, NAND flash memory interface, NOR flash memory interface, HBM (High Bandwidth Memory) interface, GDDR (Graphics Double Data Rate) interface, NVMe (Non-Volatile Memory Express) interface, SPI, IC2, etc. may be used.

[0068] All read ports (e.g., 218 and 222) are configured to be deactivated when a write operation is applied to the shared write port 222. The read ports may also be configured to handle reads simultaneously with each other. The shared write port 222 is configured to write to the address space, where it is configured to write to the first module 232 via a first portion of the address space and to the second module 234 via a second portion of the address space. Each of the multiple modules 236 includes an independent read port that reads simultaneously through its own independent read port relating to any of the multiple modules.

[0069] Each read port for each module may include contacts for a circuit found in the second device 226 for interface connection via metal contacts. Thus, there may be metal contacts on the upper layer 208 configured to interface with metal contacts on the surface 228 of the chiplet 230, and as a result, the metal contacts enable a read space having the same extent as the module read space of module 236. All of the read spaces of the module group 236 may have the same extent as one another (as described with reference to Figures 3 and 4).

[0070] In one embodiment, the read peripherals for the first module 232 are mounted on the silicon substrate 204 (sometimes referred to as the front end of the line). In the manufacturing process, a second layer 206 (sometimes referred to as the back end of the line) may then be built on top of the silicon substrate 204 (and any circuitry) and may include each memory bit cell. In an alternative embodiment, the read peripherals for the first module 232 are mounted on the second layer 206 and are located between the module group 236 and the surface 228 of the chiplet 230.

[0071] The module group 236 may be configured to process only write commands during reset. The write command may be a "slow write" command; that is, the module group 236 may have a write speed that is very low compared to the read speed of the module group 236. The write logic may be frozen (or disabled) when the module group 236 is used to read data. In some specific embodiments, the integrated circuit 212 provides the ability to allocate memory blocks to the module group 236 based on its use. In other embodiments, the memory address is fixed with the allocation. The integrated circuit 212 may be implemented as a face-to-face bonded chiplet 230. The face-to-face bond may be a bump-less wafer bond.

[0072] The module group 236 may have a single write peripheral 202. In other embodiments, each module of the module group 236 may have a dedicated write peripheral that utilizes a shared clock. In yet another embodiment, the module group 236 may also be organized into separate partitions, each having a partition with a dedicated read peripheral, where each dedicated read peripheral has an independent clock. The partitions may consist of one, two, or more modules of the module group 236.

[0073] The overall circuit architecture of the write peripheral 202 may include a set of different components, including a write driver, address decoder, sense amplifier, data input latch, data bus, and / or any combination thereof. The write driver or write buffer may be responsible for the task of transferring data to the memory cell. The write driver or write buffer may amplify the input signal to the memory cell to achieve an appropriate level. The address decoder may be used to interpret the memory address supplied as input to which data should be written. The address decoder may be used to select a target memory cell by activating specific rows and columns of the memory array linked to the address. The sense amplifier may be used to identify and amplify the signal from the memory cell during a read operation and to participate in refreshing the memory cell after data has been written during a write operation. The write operation is initiated by a write enable signal. When a write command is initiated, this signal causes the write driver and decoder to proceed with the write process. The data input latch may be used as a temporary storage unit to hold data that has been set to be written to memory until the write operation is implemented. A data bus with a transmit route may be used to facilitate the movement of data from the data input latch to the memory cell.

[0074] The write operation to the module group may be performed through a priority arbitration circuit that facilitates the access of modules in a predetermined order, and the shared write port 222 may be configured to write to a virtual address space mapped to a physical memory space. The integrated circuit 212 may include high-voltage write logic used in the write peripheral 202, and the second semiconductor device 226 may have multiple processing elements, each of which includes an interface for communicating with each module of the module group 236. Furthermore, the chiplet 230 may include an interface to the shared write port 222 on the second side, thereby interface-connecting to a complementary interface in the second semiconductor device 226.

[0075] Furthermore, the integrated circuit 212 may include a power gating circuit that selectively cuts off the power to the module 236 when it is not in use. In addition, the integrated circuit 212 may have a programming peripheral 202 for the module group 236 connected to dedicated I / O pads to enable data transfer outside the integrated circuit package.

[0076] The integrated circuit 212 may utilize multiple modules of a group of modules 236 that are grouped together. These modules may be synchronized with one another in certain embodiments. In some cases, all modules are synchronized, while in other examples, only specific modules are synchronized. For example, the circuitry in the second device 226 may need to be synchronized with a specific module when reading data from one of the modules in the group of modules 236.

[0077] To synchronize the modules, the integrated circuit 212 may use various timing techniques. In some cases, multiple clocks may be supplied to each module of the module group 236, thereby allowing each module to have isolated timing relative to the other modules in the group. This isolation ensures that any delay in one module does not affect the functionality of other modules. It should be noted that the clocks used may or may not need to be synchronized. In some cases, a common clock may be used to synchronize the modules. In yet another embodiment, the clock signal or signal(s) may be provided by a second device 226.

[0078] In alternative embodiments, other synchronization techniques, such as phase comparison of clock signals or synchronization methods of a phase-locked loop (PLL), may be used. Another embodiment for synchronizing modules in an IC may use synchronization of a delay-locked loop (DLL). In this method, a delay element is added to the clock signal path, and its output is compared with the input clock signal. A feedback loop adjusts the delay element until the output of the DLL matches the input, resulting in synchronization of the clock signals.

[0079] In another embodiment, the integrated circuit 212 may achieve synchronization between modules using a combination of different synchronization techniques. For example, some modules may use PLL synchronization, while others may use clock delay line or DLL synchronization depending on their specific requirements. Furthermore, the integrated circuit 212 may also use redundant synchronization techniques to ensure reliability and redundancy in case one method fails. For example, the integrated circuit 212 may use both PLL synchronization and DLL synchronization simultaneously, so that if one method fails, the others can still maintain synchronization.

[0080] Figure 3 shows a block diagram 300 illustrating the memory address space of the integrated circuit of Figure 1, according to an embodiment of the present disclosure. The memory address space includes a write address space 316 and read data address spaces 310, 312, and 314.

[0081] The write address space 316 consists of various units in which data, such as weights and / or instructions, can be stored. These units are referred to as memory addresses. The module group 302 includes several memory modules 304, 306, and 308. The write address space 316 can be distributed among the memory modules 304, 306, and 308 such that the write address space 316 extends from 0 to N*M-1. As shown in Figure 3, the module group 302 has N memory modules 304, 306, and 308, where N is a positive integer and each module has a memory size of M. The total number of unique write memory addresses in the write address space is N*M, which can be referred to by integers from 0 to N*M-1.

[0082] Starting at 0, the memory addresses in the write address space 316 are arranged sequentially up to N*M-1. In other words, the first address is 0, the last address is N*M-1, and there are a total of N*M addresses. This ordering can be linear (each address increasing by 1) or some other incidental designation pattern.

[0083] Write memory addressing can be implemented in various ways depending on the system architecture. One method used in a particular embodiment is to use a base register and a limit register. The base register holds the smallest valid physical write memory address, and the limit register specifies the size of the range. Thus, the base is added to the relative address to generate a logical address. In other embodiments, a memory addressing scheme may be used, where the base used is set to 0. Further write addressing techniques will be understood by those skilled in the art.

[0084] For any device writing to module group 302, each memory module may have a unique set of write memory addresses, and as a result, all memory addresses within module group 302 are unique with respect to data writing, for example, starting with 0 for the first module and ending with N*M-1 for the last module. In some embodiments, this allocation may depend on the memory management system of the devices writing data to modules 304, 306, and 308, which can range from a simple fixed partitioning scheme to a more complex dynamic partitioning model.

[0085] For example, in a simple linear model where each module (304, 306, or 308) has an address of the same size M, the first module 304 has write addresses 0 to M-1, the second module has write addresses M to 2M-1, the third module has write addresses 2M to 3*M-1, and so on. Therefore, the Nth module 308 has write addresses (N-1)*M to N*M-1.

[0086] Those skilled in the art may use other implementations of write memory addresses from 0 to N*M-1, which depend on various factors, such as hardware architecture, operating system, memory management scheme, and the nature of programs executed in the system.

[0087] The module group 302 has different read data address spaces 310, 312, and 314. These read address spaces 310, 312, and 314 may have overlapping address spaces, contiguous address spaces, or address spaces with the same extent. The read address spaces 310, 312, and 314 may be independent of each other. The system includes three independent read address spaces labeled as read address spaces 310, 312, and 314. Each of these read address spaces is separate from the others, meaning that reads can be performed in each space without affecting the others.

[0088] The read address spaces 310, 312, and 314 may be defined as contiguous blocks of memory addresses, each having its own start and end addresses. In the module group 302, each read address space 310, 312, and 314 may have addresses in the range of 0 to M-1, where M is the maximum value determined by the size of the modules 304, 306, and 308 used.

[0089] In one embodiment, simultaneous reads may be implemented as described herein, by enabling one processing unit to interface with each of the read address spaces 310, 312, and 314. The independence of the read address spaces 310, 312, and 314 ensures that each processing unit can access its desired data without causing any interference or conflict with other processing units.

[0090] Figure 4 shows a block diagram illustrating the memory address space having the signal interface of the integrated circuit of Figure 1, according to embodiments of the present disclosure. The signals used in Figure 4 may be used in any embodiment described herein. However, those skilled in the art will understand that different signaling schemes may be used.

[0091] Module group 402 includes modules 404, 406, and 408 that share a common write peripheral 411. The write peripheral 411 includes a write address bus containing the address of the data to be written, a write data bus containing the data, and a write clock that causes the write (e.g., on the leading or trailing edge of a clock signal). The write occurs only if the write enable signal indicates that the write should occur. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In some embodiments, the write peripheral 411 may be on a chiplet 230, and in other embodiments, the write peripheral 411 is on a second device 226.

[0092] Module group 402 has modules 404, 406, and 408, each having its own read peripheral 410, 412, and 414. Each of the read peripherals 410, 412, and 414 has a read address bus for transmitting a read address, a read data bus for receiving data, a read clock which is a clock used to control the timing of the output of digital data, and an output enable which is a prerequisite for the output of data. Any logic may be used, for example, high voltage may correspond to 1, low voltage may correspond to 0, and vice versa. In further embodiments, multibit or analog data storage may be used. In some embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the chiplet 230, and in other embodiments, one or more of the read peripherals 410, 412, and 414 may be located on the second device 226.

[0093] Figure 5 shows a diagram of an integrated circuit 500, which may be part of a semiconductor device such as a chiplet, according to an embodiment of the present disclosure. The integrated circuit 500 may be arranged in a semiconductor device such as a chiplet, having a silicon substrate 506 and a second layer 508. Within the integrated circuit 500, there may be array sections forming a module 502, where the memory bit cells 522 of a three-dimensional column array have components necessary for memory storage in a non-volatile memory, semi-volatile memory, or memory format as described herein.

[0094] Even if only a single module 502 is shown, the integrated circuit 500 may include a group of modules having multiple modules, such as a first module and a second module. The memory bit cell 522 is written to by shared write ports 512, 516, which include both a write address bus line 512 and a write data bus 516. These buses extend through a second layer 508 and may be connected to a second semiconductor device via an interposer. The second device has electrical contacts that complement the electrical contacts on the surface 518, enabling the second device to be electrically connected to the write address and data buses. The memory bit cell 522 can be read out by read ports 524, 526, which include a read address bus line 524 and a read data bus 526. Both of these buses may also extend through the second layer 508 to a second semiconductor device connected to the surface 518, which also has complementary electrical contacts that enable the second semiconductor device to be electrically connected to the read address and data buses.

[0095] Various types of memory technologies, such as a vertically connected fabric structure formed from non-volatile memory unit cells arranged in a three-dimensional column array 522, may be used for the memory bit cell 522. The memory bit cell 522 may utilize one or more of the following: crosspoint, 3D-NAND, 3D-NOR, 3D AND, and / or stacked planar layers.

[0096] In some embodiments, the integrated circuit 500 is electrically connected to a second semiconductor device (not shown in Figure 5) comprising another integrated circuit, which may be a system-on-chip or a field-programmable gate array. In some embodiments, the memory bit cell 522 may be formed from various non-volatile memory types such as FeFET, FeRAM, ReRAM, SOT, or STT. Furthermore, alternatively or optionally, the memory bit cell may be formed from a non-volatile memory unit cell having a two-terminal, three-terminal, or four-terminal device.

[0097] For example, the memory unit bit cell 522 may be formed from a ferroelectric material such as a ferroelectric tunnel junction, diode, capacitor, single-gate transistor, or dual-gate transistor. Alternatively, the memory unit bit cell 522 may be formed from a memristor material, such as at least one ReRAM, or a magnetic material, such as at least one spin-orbit torque device or at least one spin-transition torque device. Furthermore, the non-volatile memory unit cell 522 may also be formed from a phase-change material or an antiferroelectric material.

[0098] In some alternative embodiments, the non-volatile memory unit cell 522 may be formed from other types of materials, such as phase-change materials, antiferroelectric materials, or multi-bit PCM materials. The non-volatile unit cell may be formed using different structures, such as resistive random-access memory (RRAM) technology, magnetic random-access memory (MRAM) technology, or ferroelectric random-access memory (FRAM) technology.

[0099] Furthermore, in some implementations, 3D NAND technology may be used to form the memory unit bit cell 522. For example, the memory unit bit cell 522 may be formed from stacked memory layers, where each layer contains multiple memory cells that can be accessed using a shared bit line. In such a case, read ports 524, 526 may be connected to bit lines, and write ports 512, 516 may be connected to word lines that control access to each layer.

[0100] In another embodiment, the 3D connected fabric structure may be constructed of stacked layers of NAND gates, NOR gates, or AND gates, and in some cases, different types of logic gates may be combined to optimize the functionality of the structure. In addition, the 3D connected fabric structure may be formed using through-silicon (TSV) technology, which enables vertical interconnection of different layers of the structure.

[0101] Furthermore, the non-volatile memory unit cell may include a two-terminal device, such as a capacitive or memristor device with or without an additional selector device such as a series diode; a three-terminal device, such as a floating-gate transistor or a transistor with an access gate; or a four-terminal device, such as a transistor with two access gates. The type and configuration of the non-volatile memory unit cell 522 may depend on the requirements of a particular application, including circuit speed, power consumption, and reliability. The memory unit cell may include, or may consist of, a single ferroelectric transistor or a 6T SRAM cell. The memory unit cell may also be a combination of many different devices, including, but not limited to, one or more of the following: transistors, memristors, capacitors, etc.

[0102] In some embodiments, ferroelectric materials may be used to form non-volatile memory unit cells 522. Ferroelectric materials may be implemented as thin-film devices, including, but not limited to, ferroelectric tunnel junctions, capacitors, single-gate transistors, or dual-gate transistors, or any other type of device.

[0103] In another embodiment, the non-volatile memory unit cell 522 may be formed from a memristor material, such as a metal oxide memristor (MOM), a conductive bridge RAM (CBRAM), or a valence-change memory (VCM), each offering different advantages in terms of power consumption, speed, durability, and so on.

[0104] Furthermore, in some embodiments, the non-volatile memory unit cell 522 may be formed from a magnetic material, such as a spin-orbit torque (SOT) device, a spin-transition torque (STT) device, or a perpendicular magnetic tunnel junction (p-MTJ).

[0105] In one embodiment, the module group may include a number of modules, each of which can be accessed through dedicated read ports 524, 526 having dedicated read peripherals 520, while sharing the same write ports 512, 516 and a shared write peripheral 510. The shared write ports 512, 516 may be configured to selectively write to one or more of the modules in the module group, including memory bit cells 522. Each module may have the same or different sizes, and different module sizes may be configured to optimize the use of the memory array in different operating scenarios, etc.

[0106] Furthermore, the integrated circuit 500 may be formed using different manufacturing processes and technologies, including but not limited to CMOS or bipolar CMOS-DMOS (BCD) processes, silicon on insulator (SOI) processes, FinFET processes, silicon germanium (SiGe) processes, and gallium arsenide (GaAs) processes.

[0107] Figure 6 shows a perspective view of assembly 600 having the integrated circuit of Figure 1 mounted on a semiconductor device such as a chiplet 230, which is electrically connected to a system-on-a-chip ("SOC") 610, according to an embodiment of the present disclosure. In this embodiment, the semiconductor device is a chiplet 230 that is electrically connected to a system-on-a-chip ("SOC") 610.

[0108] Referring to Figure 6, the SOC610 includes a silicon substrate 602 on which multiple processing elements are formed, including a processing element 606. The processing elements can communicate with each other through a network-on-chip ("NOC") 604, which is a communication fabric that directs data transfer between processing elements. The communication fabric can take various forms, including buses, switches, NOCs, etc. In the SOC610, the NOC 604 directs data traffic between various nodes (e.g., processing elements 606) and links that provide communication paths between nodes.

[0109] The processing elements, including processing element 606, may be any suitable type of processor capable of executing instructions, including a microprocessor, graphics processing unit (GPU), digital signal processor (DSP), or application-specific integrated circuit (ASIC).

[0110] Furthermore, the SOC610 may comprise various modules, such as module 232, which are grouped together to provide memory functionality to assembly 600 as described herein. Modules in module group 236 may be connected to their respective processing elements to provide readable memory to each processing element. In some embodiments, the connection between modules (e.g., module 232) and processing elements (e.g., 606) may be achieved through interconnects in the silicon substrate 602.

[0111] After the circuit is formed on the silicon substrate 602, a second layer 608 may be placed on the substrate. The second layer 608 may be any suitable material, such as an insulating material, a metal, a dielectric, or an interconnect layer, and the second layer 608 may be bonded to the chiplet 230. Bonding may be performed using any suitable technique, including but not limited to adhesives, soldering, or welding.

[0112] In general, assembly 600 provides a means for integrating a chiplet 230, which may include the integrated circuit shown in Figure 1, into the SOC 610. The integration of the chiplet 230 offers various advantages, such as improved functionality, higher performance, and lower power consumption. Furthermore, the integration of the chiplet 230 into the SOC 610 can be achieved in various ways depending on the specific application and design objectives of the system.

[0113] Assembly 600 can incorporate various modifications and alterations to meet the specific requirements of the system. For example, the processing elements formed on the silicon substrate 602 can vary in number, type, and arrangement. Similarly, the modules in the module group 236 can vary in number, type, and function.

[0114] Furthermore, the second layer 608 may be modified to include additional functions. For example, the second layer 608 may include passive components such as resistors, capacitors, and inductors, or active components such as transistors or diodes. By incorporating these components into the second layer 608, the functionality and performance of the system can be further improved.

[0115] In another variation, assembly 600 may incorporate a heterogeneous integration technique, where the chiplet 230 is manufactured using a different technique than that used in SOC610. This technique allows for the optimal use of different manufacturing techniques for different parts of the system, resulting in improved performance and reduced power consumption.

[0116] Figures 7A and 7B show block diagrams of a system 700 that employs collect-by-construction timing convergence for an application chiplet 702 having an interface circuit 701 having read registers 726a, 726b and write register 728, and a memory chiplet 704, according to embodiments of the present disclosure. Thus, the system 700 may include two separate semiconductor devices, e.g., an application chiplet 702 and a memory chiplet 704, which may be formed on two separate dies. The interface circuit 701 (which may be referred to as an interface module) may include registers 726a, 726b, and 728 to enable the application chiplet 702 to have collect-by-construction timing convergence for the memory group 706 in the memory chiplet 704.

[0117] The memory chiplet 704 may include a group of modules 706 having modules 708a, 708b, and 708c that are independently accessible via read peripherals 722a, 722b, and 722c, respectively. The memory chiplet 704 may also include a shared write peripheral 710, where data may be written to memory locations within the group of modules 706. Interconnects found within the memory chiplet 704 may, for example, in a particular embodiment, be connected to a surface via a junction to facilitate communication between semiconductor devices 702 and 704 when they are joined together in a stack configuration. The designer of the application chiplet 702 may place an interface module 701 using a netlist at a predetermined distance from the surface of the application chiplet 702. That is, the timing and characteristics of signals may be predetermined to operate the memory of the memory chiplet 704. For example, the signal travel time from the read register 726 may be less than a predetermined time.

[0118] The interface module 701 may include one or more read registers 726a, 726b, and write register 728 that can communicate with the memory chiplet 704 via several junctions as shown in Figure 7B.

[0119] The read register 726a may interface with and communicate with other circuits within the application chiplet 702 via the read application programming interface ("API") 714a. That is, the read API 714a may be a bus through which data can be requested by external circuits (e.g., via the CPU) to provide data from the memory chiplet 704 to other circuits (e.g., a preferred CPU).

[0120] The read register 726a may be controlled via a read clock received via the read clock interconnect 712a. The read clock interconnect 712a may also be connected to a read clock junction 738a, which can be connected to a read peripheral 722a in the memory chiplet 704 to provide clocking to the memory contained in the memory chiplet 704. The interconnect may be connected together by the read clock junction 738a on the application chiplet 702 and by their respective junctions (not explicitly shown in Figure 7B) in the memory chiplet 704.

[0121] The read register 726a may be connected to a read address interconnect 716a (which may have multiple parallel connections) that communicates the read address loaded into the read register 726a. The read address interconnect 716a is connected to multiple read address junctions 740a so that the read address can be received by the memory chiplet 704. The read address is a value that can be translated by the read peripheral 722a to query a location within module 708a.

[0122] Furthermore, the read register 726a includes a read data interconnect 718a that can receive data from module 708a via a plurality of read data junctions 742a. ​​The data may be held by register 726a for communication with other circuits via read API 714a.

[0123] Furthermore, the read register 726a may include a read data enable interconnect 720a to enable the output of data from module 708a. The read data enable interconnect 720a is connected to the read data enable junction 744a so that when stacked, the chiplets 702 and 704 communicate electrically with each other.

[0124] The read register 726b, which can communicate with other circuits via the read application programming interface (API) 714b, may be the same as or identical to the read register 726a in the application chiplet 702. The read API 714b functions as a bus from which external circuits, such as a CPU, can request data from the memory chiplet 704.

[0125] The read register 726b is controlled by a read clock received through the read clock interconnect 712b. The read clock interconnect 712b is connected to a read clock junction 738b that provides clocking to the memory chiplet 704. The read clock junction 738b connects the interconnects in the application chiplet 702 and the memory chiplet 704.

[0126] The read register 726b is connected to the read address interconnect 716b, which transmits the loaded read address. The read address interconnect 716b is connected to multiple read address junctions 740b, enabling the memory chiplet 704 to receive the read address. The read address is used by the read peripheral 722b to query its location within module 708b.

[0127] Furthermore, the read register 726b has a read data interconnect 718b that receives data from module 708. The data is stored in register 726b and can be communicated to other circuits via the read API 714b.

[0128] Furthermore, the read register 726b includes a read data enable interconnect 720b that enables the output of data from module 708b. The read data enable interconnect 720b is connected to the read data enable junction 744b to enable electrical communication between the stacked chiplets 702 and 704.

[0129] Furthermore, the interface module 701 includes a write interface register 728 that receives write data and write addresses via a write application programming interface 724 in order to write write data to the module group 706. The write interface register 728 receives a write clock via a write clock interconnect 730, which is also connected to the surface of the semiconductor device via a write clock junction 746. The write interface register 728 also has a write address interconnect 732 connected to it in order to provide write addresses from the write interface register 728 to a plurality of write address junctions 748 on the surface. The write interface register 728 is also connected to a write data interconnect 734 in order to transmit data via a plurality of write data junctions 750. The write interface register 728 is also connected to a write data enable interconnect 736 that transmits a write enable signal via a write enable junction 752.

[0130] Figure 8 shows a block diagram of a system 800 that employs collect-by-construction timing convergence for an application chiplet having a common read / write address register 812 and a memory chiplet 802, according to an embodiment of the present disclosure. The system 800 may include various interconnected components and may be part of a stack of chiplets joined together.

[0131] The interface module 806 contains circuitry that interfaces different system components. This logic incorporates an address register 810, a read data register 816, and a write data register 820 to facilitate memory transfers between chiplets. The memory chiplet 802 is responsible for data storage within system 800. The read / write select interconnect 826 functions as a mechanism or signal used to select between read and write operations, providing flexibility and control over the system's functionality. The read / write select interconnect 826 is connected to the read / write junction 836. The clock, via the clock interconnect 808, functions as a timing signal to facilitate synchronization across the system, including the address register 810, the read data register 816, the write data register 820, and the memory 802.

[0132] The address interconnect 804 facilitates the transmission of address signals to the memory chiplet 802 via multiple junctions 828. Addresses may be read or written depending on the value of the read / write selection signal in the read / write selection interconnect 826. The address register 810 acts as a storage mechanism for addresses received via API 812 by loading addresses into the address interconnect 804, communicating addresses to memory 802 via the address interconnect junction 830. The address register API 812 functions as an application programming interface related to the address register, which may be accessed by other circuits. To synchronize operation, a clock is transmitted using the clock interconnect 808 to enable the loading of addresses into the address register 810.

[0133] In the embodiment shown in Figure 8, two data registers are used: a read data register 816 and a write data register 820. The read data register 816 receives data in read mode when selected by the read / write selector 826, while the write data register 820 provides data to be written to the memory chiplet 802.

[0134] The read data register 816 functions as a dedicated register for storing read data, ensuring data integrity and accessibility. The read data register 816 is connected to memory 802 via the read data interconnect 814 and the read data junction 832. Furthermore, an application programming interface, namely the read data register API 818, is associated with the read data register 816. This API enables seamless integration and interaction with other circuits.

[0135] Similarly, there is a write data register 820 responsible for storing write data, and a write data register API 822 associated with the write data register 820. The write data register 820 functions as a dedicated register for storing write data to be written to the memory chiplet 802. The write data register API 822 functions as an application programming interface for receiving write data from other circuits. The write data signal is transmitted through the write data interconnect 824 via the write data junction 834, enabling smooth data transfer during write operations to the memory chiplet 802.

[0136] In the embodiment shown in Figure 8, the read data register 816 and the write data register 820 may be connected to the memory chiplet 802 through junctions, which are conductive connectors such as conductive pads. The memory chiplet 802 also includes complementary conductive connectors (e.g., conductive pads). These conductive pads may be metal pads commonly used in integrated circuit technology. The metal pads may function as contacts that interface the chiplets together.

[0137] A netlist may be used to provide a visual representation of the circuit layout, representing a comprehensive representation of the interconnections between various components present in a system. The system incorporates multiple junctions, indicating multiple physical connections that facilitate seamless communication between components or devices.

[0138] Figure 9 shows a flowchart of Method 900, which ensures that correct-by-construction timing convergence is achieved according to an embodiment of the present disclosure.

[0139] Method 900 may also include forming a thin interface module on the base die (block 902). For example, the device may have a thin interface module on the base die as described above. As also shown in Figure 9, Method 900 may also include forming an address register in the thin interface module, wherein the address register is configured to store addresses for the address interconnect in accordance with an address clock from the address clock interconnect (block 904). For example, as described above, the device may have an address register in the thin interface module, wherein the address register is configured to store addresses for the address interconnect in accordance with an address clock from the address clock interconnect. As further shown in Figure 9, Method 900 may also include forming a data register in the thin interface module, wherein the data register is configured to store data for the data interconnect in accordance with a data clock from the data clock interconnect (block 906). For example, as described above, the device may form data registers in a thin interface module, and the data registers are configured to store data for the data interconnect in the registers according to a data clock from the data clock interconnect.

[0140] Method 900 may include forming a plurality of junctions located on the surface of a first semiconductor device, wherein the junctions are operably connected to an address interconnect and a data interconnect (block 908). For example, as described above, the device may form a plurality of junctions located on the surface of a first semiconductor device, wherein the junctions are operably connected to an address interconnect and a data interconnect. The junctions may be routed perpendicular to the surface using EDA software (e.g., one using a netlist), where a thin interface module can be a predetermined maximum distance from the junctions. There may also be constraints that the wires must be routed directly perpendicular to the surface of the chiplet.

[0141] Method 900 may involve stacking the first and second semiconductor devices together (block 910), joining multiple junctions to the second semiconductor device via complementary junctions or the like (block 912), and joining the first and second semiconductor devices together (block 914).

[0142] Various alternatives and modifications can be conceived by those skilled in the art without departing from this disclosure. Therefore, this disclosure is intended to include all such alternatives, modifications, and variations. Furthermore, while some embodiments of this disclosure are shown in the drawings and / or described herein, this disclosure is not intended to be limited thereto, as this disclosure is broad in the scope of what the art makes possible, and the specification is intended to be read similarly. Therefore, the above description should not be construed as a limitation, but merely as an example of a particular embodiment. Those skilled in the art will conceive of other modifications within the scope and spirit of the claims appended herein. Other elements, steps, methods, and techniques that differ slightly from those described above and / or in the appended claims are also intended to be within the scope of this disclosure.

[0143] The embodiments shown in the drawings are presented solely to demonstrate specific examples of the present disclosure. The drawings described are illustrative and non-limiting. In the drawings, for illustrative purposes only, the sizes of some elements may be exaggerated and not depicted to a particular scale. Furthermore, elements shown in the drawings with the same number may be identical or similar elements, depending on the context.

[0144] When the term “equipped with” is used herein and in the claims, the term does not exclude other elements or steps. When an indefinite or definite article is used with a single noun, for example, “a,” “an,” or “the,” this includes multiple such nouns unless specifically stated otherwise. Therefore, the term “equipped with” should not be interpreted as being limited to the items enumerated therein, and since the term does not exclude other elements or steps, the scope of the expression “a device comprising items A and B” should not be limited to a device consisting only of components A and B. This expression means to the present disclosure that A and B are merely related components of a device.

[0145] Furthermore, the terms “First,” “Second,” “Third,” and similar terms, whether used in the specification or in the claims, are provided to distinguish similar elements and are not necessarily provided to describe a sequential or chronological order. Terms used in this manner are interchangeable under appropriate circumstances (unless otherwise expressly disclosed), and it should be understood that embodiments of the disclosure described herein may operate in sequences and / or arrangements other than those described or shown herein.

Claims

1. A system for achieving correct-by-construction timing convergence, wherein the system is The first semiconductor device comprises a thin interface module, the thin interface module is An address register configured to store the address for the address interconnect in the register according to the address clock from the address clock interconnect, A data register configured to store data for the data interconnect in the register according to the data clock from the data clock interconnect, A plurality of junctions arranged on the surface of the first semiconductor device, wherein the plurality of junctions are operably connected to the address interconnect and the data interconnect, and the plurality of junctions are configured to interface with the second semiconductor device to be joined, A system that includes these features.

2. The system according to claim 1, wherein the system is configured to achieve correct-by-construction timing convergence between the first and second semiconductor devices.

3. The system according to claim 1, wherein the first and second semiconductor devices are both face-to-face bonded.

4. The system according to claim 1, wherein the first and second semiconductor devices are stacked together.

5. The system according to claim 1, wherein the address clock interconnect and the data clock interconnect are connected together to merge the address clock and the data clock.

6. The system according to claim 1, wherein the data register is a read data register configured to receive read data via the data interconnect.

7. The system according to claim 6, further comprising a write data register configured to store write data in a register and provide the write data to a plurality of write data interconnects, wherein the plurality of connections include the write data interconnects.

8. The system according to claim 1, wherein the data register is a write data register configured to provide write data to the data interconnect.

9. The system according to claim 8, further comprising at least two read data registers configured to receive read data from a plurality of read data interconnects, wherein the plurality of junctions include the read data interconnects.

10. The first semiconductor device is A read interface register, wherein the address register and the data register form the read interface register, and the read interface register is configured to store read addresses from the read interconnect and read data from the read interconnect in the register according to the read clock from the read clock interconnect, the read interconnect includes the address interconnect and the data interconnect, the address clock and the data clock form the read clock, and the address clock interconnect and the data clock interconnect form the read clock interconnect, and A write interface register configured to store the write address and write data from the write interconnect in a register according to the write clock from the write clock interconnect, A plurality of read junctions arranged on the surface of the first semiconductor device, wherein the plurality of read junctions are operably connected to the read interconnect of the read interface register, and the plurality of junctions include the plurality of read junctions, A plurality of write junctions arranged on the surface of the first semiconductor device, wherein the plurality of write junctions are operably connected to the write interconnect of the write interface register, The system according to claim 1, further comprising the following:

11. The aforementioned system, The second semiconductor device further comprises the second semiconductor device, The system according to claim 10, comprising a read peripheral, wherein the read peripheral has a read peripheral interconnect connected to the surface of the second semiconductor device and is configured to connect to the plurality of read junctions, thereby connecting the read peripheral of the second semiconductor device to the read interface register of the first semiconductor device.

12. The aforementioned system, The second semiconductor device further comprises the second semiconductor device, The system according to claim 10, comprising a writing peripheral device, wherein the writing peripheral device has a writing peripheral device interconnect connected to the surface of the second semiconductor device and is configured to connect to the plurality of writing junctions, thereby connecting the writing peripheral device of the second semiconductor device to the writing interface register of the first semiconductor device.

13. The aforementioned read interconnect is, Read address interconnect and Read data interconnect and The system according to claim 10, comprising:

14. The plurality of read junctions are, A plurality of read address junctions arranged on the surface of the first semiconductor device, wherein the plurality of read address junctions are operably connected to the read address interconnect of the read interface register, A plurality of read data junctions arranged on the surface of the first semiconductor device, wherein the plurality of read data junctions are operably connected to the read data interconnect of the read interface register, The system according to claim 13, comprising:

15. The system according to claim 14, wherein the plurality of junctions include read clock junctions, and the read clock interconnect connects the read clock junctions to the read interface registers.

16. The aforementioned write interconnect is The write address interconnect, Write data interconnect and The system according to claim 10, comprising:

17. The plurality of writing junctions are, A plurality of write address junctions arranged on the surface of the first semiconductor device, wherein the plurality of write address junctions are connected to the write address interconnect of the write interface register, A plurality of write data junctions arranged on the surface of the first semiconductor device, wherein the plurality of write data junctions are connected to the write data interconnect of the write interface register, The system according to claim 16, comprising:

18. The system according to claim 17, wherein the plurality of junctions include a write clock junction, and the write clock interconnect connects the write clock junction to the write interface register.

19. A method for forming a first semiconductor device with correct-by-construction timing convergence, wherein the method is: Forming a thin interface module on the base die, The thin interface module is configured to form an address register, wherein the address register is configured to store the address for the address interconnect in accordance with the address clock from the address clock interconnect. The thin interface module is configured to form a data register, wherein the data register is configured to store data for the data interconnect in accordance with the data clock from the data clock interconnect. The process involves forming a plurality of junctions arranged on the surface of the first semiconductor device, wherein the plurality of junctions are operably connected to the address interconnect and the data interconnect. The plurality of joints are joined to a second semiconductor device, Methods that include...

20. The method according to claim 19, further comprising achieving correct-by-construction timing convergence between the first and second semiconductor devices by forming the thin interface module with respect to the plurality of joints at a separation relationship of less than a predetermined distance.

21. The method according to claim 19, wherein the operation of joining the plurality of joints with the second semiconductor device includes face-to-face bonding of the first semiconductor device to the second semiconductor device.

22. The method according to claim 19, wherein the operation of joining the plurality of joints with the second semiconductor device includes stacking the first semiconductor device and the second semiconductor device together.

23. The method according to claim 19, wherein the operation of forming the thin interface module on the base die includes forming the thin interface module beneath the plurality of joints.

24. The method according to claim 19, wherein the operation of forming the plurality of joints includes forming the plurality of joints on the thin interface module.

25. The method according to claim 19, wherein the forming operation is implemented according to a netlist.

26. The method according to claim 19, further comprising forming the plurality of junctions and the address registers in a separation relationship with respect to each other such that communication between the plurality of junctions and the address registers is less than a predetermined amount of time.

27. The method according to claim 19, further comprising wiring the address interconnect and the data interconnect vertically to the plurality of joints.

28. The method according to claim 19, further comprising joining the first and second semiconductor devices together.

29. The method according to claim 28, wherein the joining is a face-to-face joining.

30. The method according to claim 19, further comprising stacking the first and second semiconductor devices together.

31. The method according to claim 19, further comprising merging the address clock and the data clock by merging the address clock interconnect and the data clock interconnect together.

32. The method according to claim 19, further comprising receiving read data via the data interconnect, wherein the data register is a read data register.

33. The process involves storing the data to be written in the write data register, The means of providing the aforementioned write data to a plurality of write data interconnects, wherein the plurality of connections include the write data interconnects, The method according to claim 32, further comprising:

34. The method according to claim 19, further comprising providing write data to the data interconnect, wherein the data register is a write data register.

35. The first read data is received in the first read data register from the first memory module in the second semiconductor device, The second read data is received in the second read data register from the second memory module in the second semiconductor device, The method according to claim 34, further comprising:

36. The first semiconductor device is A read interface register, wherein the address register and the data register form the read interface register, and the read interface register is configured to store read addresses from a read address interconnect and read data from a read interconnect in the register according to a read clock from a read clock interconnect, the read interconnect includes the address interconnect and the data interconnect, the address clock and the data clock form the read clock, and the address clock interconnect and the data clock interconnect form the read clock interconnect, and A write interface register configured to store the write address and write data from the write interconnect in a register according to the write clock from the write clock interconnect, A plurality of read junctions arranged on the surface of the first semiconductor device, wherein the plurality of read junctions are operably connected to the read interconnect of the read interface register, and the plurality of junctions include the plurality of read junctions, A plurality of write junctions arranged on the surface of the first semiconductor device, wherein the plurality of write junctions are operably connected to the write interconnect of the write interface register, The method according to claim 19, further comprising:

37. The method according to claim 36, wherein the second semiconductor device comprises a read peripheral, the read peripheral has a read peripheral interconnect connected to the surface of the second semiconductor device, and is configured to connect to the plurality of read junctions, thereby connecting the read peripheral of the second semiconductor device to the read interface register of the first semiconductor device.

38. The method according to claim 36, wherein the second semiconductor device comprises a writing peripheral, the writing peripheral has a writing peripheral interconnect connected to the surface of the second semiconductor device, and is configured to connect to the plurality of writing junctions, thereby connecting the writing peripheral of the second semiconductor device to the writing interface register of the first semiconductor device.

39. The aforementioned read interconnect is, Read address interconnect and Read data interconnect and The method according to claim 36, comprising:

40. The plurality of read junctions are, A plurality of read address junctions arranged on the surface of the first semiconductor device, wherein the plurality of read address junctions are operably connected to the read address interconnect of the read interface register, A plurality of read data junctions arranged on the surface of the first semiconductor device, wherein the plurality of read data junctions are operably connected to the read data interconnect of the read interface register, The method according to claim 36, comprising:

41. The method according to claim 40, wherein the plurality of junctions include read clock junctions, and the read clock interconnect connects the read clock junctions to the read interface registers.

42. The aforementioned write interconnect is The write address interconnect, Write data interconnect and The method according to claim 36, comprising:

43. The plurality of writing junctions are, A plurality of write address junctions arranged on the surface of the first semiconductor device, wherein the plurality of write address junctions are connected to the write address interconnect of the write interface register, A plurality of write data junctions arranged on the surface of the first semiconductor device, wherein the plurality of write data junctions are connected to the write data interconnect of the write interface register, The method according to claim 42, comprising:

44. The method according to claim 43, wherein the plurality of junctions include a write clock junction, and the write clock interconnect connects the write clock junction to the write interface register.

45. A method of using the system described in one of claims 1 to 18, Providing the aforementioned address to the aforementioned address register, By clocking the address clock, the address is loaded into the address register, Methods that include...

46. A method of using the system described in one of claims 1 to 18, To provide the aforementioned data to the data register, By clocking the data clock, the data is loaded into the data register. Methods that include...

47. A system for achieving correct-by-construction timing convergence, wherein the system is The base die comprises a first semiconductor means that provides a thin interface module, and the thin interface module is An addressing means that stores the address for the address interconnect in a register according to the address clock from the address clock interconnect, A data means for storing data for the data interconnect in a register according to the data clock from the data clock interconnect, Multiple bonding means for communicating with a second semiconductor device via address interconnect means and data interconnect means, A system that includes these features.

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