Attenuator

Abstract

To provide an attenuator that reduces insertion loss, increases dynamic attenuation range, and maintains phase stability. [Solution] The attenuator includes a first transistor, a second transistor, a third transistor, and a compensation circuit. The first and second terminals of the first transistor are respectively connected to a signal input terminal and a signal output terminal. The second transistor is connected between the first terminal of the transistor and a ground terminal. The third transistor is connected between the second terminal of the first transistor and a ground terminal. The compensation circuit is connected in parallel to the first transistor. A plurality of control terminals of the first transistor, the second transistor, and the third transistor receive a first bias voltage, a second bias voltage, and a third bias voltage, respectively. The compensation circuit and the first transistor form a resonant circuit. The resonant circuit has a resonant frequency.

Description

[Technical Field]

[0001] The present invention relates to attenuators, and more particularly to voltage-controlled attenuators. [Background technology]

[0002] In circuit design, attenuators are used to precisely control the signal strength within a circuit and reduce the strength of electrical signals. They are currently widely used in many communication hardware devices, including phased-array transceivers, mobile communication systems, satellite communication systems, automotive radar systems, vehicle network systems, and front-end control circuits. Installing an attenuator in such communication hardware devices allows precise adjustment of the strength of electronic signals, ensuring compatibility between the electronic signals and the communication hardware devices.

[0003] Transistors are an essential component in many existing attenuators. Due to the parasitic capacitance present in transistors, existing attenuators suffer from excessively high insertion loss and an excessively narrow dynamic attenuation range (insertion loss corresponds to the overall loss of the attenuator). To address these drawbacks, existing attenuators have incorporated multiple switches and complex filtering networks to compensate for or cancel the parasitic effects of the parasitic capacitance, thereby reducing the negative impact of the parasitic capacitance on the attenuator. However, these existing parasitic capacitance compensation methods have reduced phase stability. Furthermore, PN diodes in communications hardware, CMOS varistors used in complementary metal-oxide semiconductor integrated circuits, and FET-based voltage-controlled attenuators have difficulty simultaneously meeting the requirements of high output, low loss, and high phase stability due to limitations in breakdown voltage and parasitic capacitance. Furthermore, existing attenuators have also struggled to meet millimeter-wave application requirements, such as phase shift issues.

[0004] Therefore, how to maintain high phase stability and high power handling capability of an attenuator while compensating for the negative effects of parasitic capacitance (corresponding to reducing insertion loss and increasing dynamic attenuation range) is an important issue in the field of communications technology. Summary of the Invention [Means for solving the problem]

[0005] The present invention provides an attenuator including a first transistor, a second transistor, a third transistor, and a compensation circuit. The first and second terminals of the first transistor are respectively connected to a signal input terminal and a signal output terminal. The second transistor is connected between the first terminal of the transistor and a ground terminal. The third transistor is connected between the second terminal of the first transistor and a ground terminal. The compensation circuit is connected in parallel with the first transistor. The control terminals of the first transistor, the second transistor, and the third transistor receive a first bias voltage, a second bias voltage, and a third bias voltage, respectively. The compensation circuit and the first transistor form a resonant circuit. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a circuit diagram of an attenuator according to some examples of the present invention; [Figure 2] 4 is a diagram showing the relationship between the phase change amount and input power of attenuators according to some examples of the present invention and prior art; DETAILED DESCRIPTION OF THE INVENTION

[0007] The spirit of the present invention will be clearly explained through the drawings and detailed description below. After understanding the examples of the present invention, those skilled in the art can change and modify the techniques taught in the present invention without departing from the spirit and scope of the present invention. As used herein, terms such as "comprise," "include," "have," and "contain" are all open-ended terms and have inclusive meanings, including, but not limited to, those terms. Terms such as "substantially" and "approximately" are used herein to describe or describe minor variations. When applied to an event or situation, the term may include the exact moment when the event or situation occurs, as well as the approximate time when the event or situation occurs. For example, when applied to a numerical value, the term may include a variation range of ±10% or less of the numerical value, e.g., ±5% or less, ±4% or less, ±3% or less, ±2% or less, ±1% or less, ±0.5% or less, ±0.1% or less, or ±0.05% or less. Unless otherwise specified, terms used herein generally have their ordinary meanings as used in the relevant field, the present invention, and the specific context. Certain terms for describing the present invention will be discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present invention.

[0008] 1 is a circuit diagram of an attenuator 100 according to some embodiments of the present invention. The attenuator 100 is a voltage-controlled attenuator, particularly applicable to the millimeter-wave frequency band. As shown in FIG. 1, a signal S_in is input to a signal input terminal n_IN and processed by the attenuator 100, after which a signal S_out is output from a signal output terminal n_OUT. That is, the attenuator 100 attenuates the signal S_in to a signal S_out. Here, the signals S_in and S_out can be voltage signals or current signals.

[0009] Specifically, the attenuator 100 includes transistors M1 to M3 and a compensation circuit C_comp. A first terminal of the transistor M1 is connected to a signal input terminal n_IN; a second terminal of the transistor M1 is connected to a signal output terminal n_OUT. The transistor M2 is connected between the first terminal of the transistor M1 and the ground terminal GND. Specifically, a first terminal of the transistor M2 is connected to the first terminal of the transistor M1; a second terminal of the transistor M2 is connected to the ground terminal GND. The transistor M3 is connected between the second terminal of the transistor M1 and the ground terminal GND. Specifically, a first terminal of the transistor M3 is connected to the second terminal of the transistor M1; a second terminal of the transistor M3 is connected to the ground terminal GND. Thus, the transistors M1 to M3 form a π-type attenuation circuit, where the transistor M1 serves as a series transistor of the π-type attenuation circuit; and the transistors M2 and M3 serve as parallel transistors of the π-type attenuation circuit.

[0010] In some examples, the transistors M1 to M3 are all N-type metal-oxide-semiconductor field-effect transistors (MOSFETs) or all P-type MOSs. In other examples, the transistors M2 and M3 are all N-type and the transistor M1 does not need to be in the same conductivity state as the transistors M2 and M3. In some examples, the transistors M1 to M3 are gallium nitride high electron mobility transistors (GaN HEMTs). GaN HEMTs have a high breakdown voltage.

[0011] The control terminal of transistor M1 receives bias voltage Vg1; the control terminal of transistor M2 receives bias voltage Vg2; and the control terminal of transistor M3 receives bias voltage Vg3. The π-type attenuation circuit formed by transistors M1 to M3 adjusts the attenuation of signal S_out relative to signal S_in using bias voltages Vg1 to Vg3, i.e., a voltage-controlled attenuator. Here, bias voltage Vg1 is used as the series bias voltage; bias voltages Vg2 and Vg3 are used as shunt bias voltages. In some examples, bias voltages Vg2 and Vg3 are the same. Therefore, attenuator 100 is a dual-bias voltage-controlled attenuator in which the attenuation is controlled by the series bias voltage and the shunt bias voltage. In some examples, the attenuation is the difference between the signal strength of signal S_out and the signal strength of signal S_in. In some examples, the series bias voltage and the shunt bias voltage vary from 0V to -2V in increments of 0.4V each.

[0012] The compensation circuit C_comp is connected in parallel to the transistor M1. Specifically, the compensation circuit C_comp is connected between the first end of the transistor M1 and the second end of the transistor M1. Therefore, the compensation circuit C_comp and the transistor M1 form a resonant circuit (i.e., an RLC circuit or an LC circuit). The resonant circuit has a resonant frequency. The electric and magnetic fields stored in the inductance and capacitance of the resonant circuit can be converted and compensated for by each other. When the resonant circuit resonates, the resonant circuit is purely resistive, so the parasitic capacitance or parasitic inductance of the transistor M1 does not act, and the negative impact of the parasitic effect of the transistor M1 is eliminated. Therefore, by introducing the compensation circuit C_comp, the attenuator 100 of the present invention can reduce insertion loss and increase the dynamic attenuation range.

[0013] Although the attenuator 100 of the present invention is proposed to solve the negative problem of parasitic capacitance (which may include gate-source parasitic capacitance Cgs and drain-source parasitic capacitance Cds), it should be understood that this should not be construed as limiting the scope of the present invention. The attenuator 100 of the present invention can solve not only the negative problem of parasitic capacitance but also the negative problem of parasitic inductance. Specifically, if the transistor M1 has a non-negligible parasitic capacitance, the compensation circuit C_comp can compensate for the parasitic effect of the parasitic capacitance using a circuit with a sufficiently high inductance value. Conversely, if the transistor M1 has a non-negligible parasitic inductance, the compensation circuit C_comp can compensate for the parasitic effect of the parasitic inductance using a circuit with a sufficiently high capacitance value. Therefore, in some examples, the compensation circuit C_comp can include a spiral inductor and / or an active inductor. In other examples, the compensation circuit C_comp includes a parallel-plate capacitor. In some examples, the compensation circuit C_comp is a spiral inductor or an active inductor. In some other examples, the compensation circuit C_comp is a parallel plate capacitor. Those skilled in the art can select a compensation circuit C_comp that meets actual needs, and the present invention is not limited thereto.

[0014] Continuing with reference to FIG. 1, in some examples, the attenuator 100 further includes a bias voltage control circuit 110, a bias voltage control circuit 120, and a bias voltage control circuit 130. The bias voltage control circuit 110 generates a bias voltage Vg1 for the transistor M1 and is coupled to the control end of the transistor M1. The bias voltage control circuit 120 generates a bias voltage Vg2 for the transistor M2 and is coupled to the control end of the transistor M2. The bias voltage control circuit 130 generates a bias voltage Vg3 for the transistor M3 and is coupled to the control end of the transistor M3.

[0015] In particular, in some examples, bias voltage control circuit 110 includes a voltage source 111 and a radio frequency choke 112. The voltage source 111 and the radio frequency choke 112 are connected in series to each other. Bias voltage control circuit 120 includes a voltage source 121 and a radio frequency choke 122. The voltage source 121 and the radio frequency choke 122 are connected in series to each other. Bias voltage control circuit 130 includes a voltage source 131 and a radio frequency choke 132. The voltage source 131 and the radio frequency choke 132 are connected in series to each other. In this example, voltage sources 111 and 121 are all DC.

[0016] Also, in some examples, bias voltage control circuit 110, bias voltage control circuit 120, and bias voltage control circuit 130 may be circuits with different configurations. In some examples, at least two of bias voltage control circuit 110, bias voltage control circuit 120, and bias voltage control circuit 130 are identical. In some examples, bias voltage control circuit 110 and bias voltage control circuit 120 are identical; bias voltage control circuit 120 and bias voltage control circuit 130 are identical.

[0017] Specifically, in some examples, the matching circuit 140 includes an inductor 141 and a capacitor 142. The inductor 141 is coupled between a first terminal of the transistor M1 and the signal input terminal n_IN. The capacitor 142 is coupled between the signal input terminal n_IN and the ground terminal GND. The matching circuit 150 includes an inductor 151 and a capacitor 152. The inductor 151 is coupled between a second terminal of the transistor M1 and the signal output terminal n_OUT. The capacitor 152 is coupled between the signal input terminal n_IN and the ground terminal GND. More specifically, in some examples, the capacitors 142 and 152 are non-polarized capacitors. In other examples, the capacitors 142 and 152 are polarized capacitors.

[0018] In one example, the attenuator 100 is a voltage-controlled attenuator suitable for use in the Ka-band (27 GHz to 29 GHz). The resonant circuit of the compensation circuit C_comp and the transistor M1 has a resonant frequency of approximately 28 GHz. The reflection coefficients S11 and S22 of the signal input terminal n_IN and the signal output terminal n_OUT can be reduced to less than -10 dB. In one example, the improvement in the reflection coefficients S11 and S22 results in impedance matching closer to 50 Ω. Furthermore, compared to the attenuator 100 without the compensation circuit C_comp, the dynamic attenuation range of the attenuator 100 with the compensation circuit C_comp increases from 15 dB to 36.86 dB, and the insertion loss decreases from 3.2 dB to 2.6 dB. Furthermore, the matching circuits 140 and 150 first perform an impedance matching analysis on the dual bias voltage control network of the attenuator 100 to determine whether to select a series bias voltage or a shunt bias voltage. In some examples, first, for example, through impedance matching analysis, the series bias voltage and shunt bias voltage values ​​of groups 19 to 22 are selected as reference options, and then the series bias voltage and shunt bias voltage actually applied to the attenuator 100 are set according to usage requirements, thereby effectively reducing the return loss of the attenuator 100. In one example, using GaN HEMTs as transistors M1 to M3 can increase the 1 dB compressed output power (P1dB) of the attenuator 100 to more than 22.7 dBm.

[0019] FIG. 2 shows the relationship between the phase variation and input power for some examples of attenuators according to the present invention and the prior art. Line L1 corresponds to the attenuator 100 of the present invention, which incorporates a compensation circuit C_comp; line L2 corresponds to the prior art attenuator without a compensation circuit C_comp. As shown in FIG. 2, as the input power increases, the phase variation of the attenuator 100 of the present invention remains approximately zero. Conversely, after the input power reaches approximately 18 dBm, the phase variation of the prior art attenuator begins to deviate from zero. That is, after the input power reaches approximately 18 dBm, the phase of the prior art attenuator becomes unstable. Therefore, the attenuator 100 has better phase stability than the prior art attenuator. Furthermore, in the 27 GHz to 29 GHz band, the phase variation (P1dB) at an input power of P1dB decreases from 9.8 degrees to 0.9 degrees. This shows that the compensation effect of the compensation circuit C_comp can simultaneously reduce the insertion loss, increase the dynamic attenuation range, and maintain phase stability.

[0020] The attenuator of the present invention forms a resonant circuit using a compensation circuit and a series transistor of a π-type attenuation circuit, which cancels the parasitic effect of the parasitic capacitance of the series transistor during resonance, thereby achieving the effects of reducing insertion loss, increasing the dynamic attenuation range, and maintaining phase stability at the same time. In addition, by configuring the π-type attenuation circuit using a GaN HEMT, the power handling capability of the attenuator can be improved. Therefore, the attenuator of the present invention effectively solves the shortcomings of existing attenuators.

[0021] Although the present invention has been disclosed above through detailed examples, the present invention does not exclude other possible embodiments. Therefore, the scope of protection of the present invention should be considered to be defined by the scope of the attached utility model claims, and is not limited to the above examples. Those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Based on the above examples, all changes and modifications to the present invention are also included in the scope of protection of the present invention. [Explanation of symbols]

[0022] 100: Attenuator 110: Bias voltage control circuit 111: Voltage source 112: Radio frequency choke 120: Bias voltage control circuit 121: Voltage source 122: Radio frequency choke 130: Bias voltage control circuit 131: Voltage source 132: Radio frequency choke 140: Matching circuit 141: Inductor 142: Capacitor 150: Matching circuit 151: Inductor 152: Capacitor M1 to M3: Transistors Vg1~Vg3: Bias voltage L1, L2: Line C_comp: Compensation circuit GND: Ground end n_IN: signal input terminal n_OUT: Signal output terminal S_in, S_out: Signal

Claims

1. An attenuator comprising: a first transistor having a first end coupled to a signal input end and a second end coupled to a signal output end; a second transistor connected between the first terminal of the first transistor and a ground terminal; a third transistor coupled between the second terminal of the first transistor and the ground terminal; and a compensation circuit coupled in parallel with the first transistor; a plurality of control ends of the first transistor, the second transistor and the third transistor respectively receive a first bias voltage, a second bias voltage and a third bias voltage; The compensation circuit and the first transistor form a resonant circuit, the resonant circuit having a resonant frequency.

2. a first bias voltage control circuit for generating the first bias voltage for the first transistor; a second bias voltage control circuit for generating the second bias voltage for the second transistor; and a third bias voltage control circuit for generating the third bias voltage for the third transistor; 2. The attenuator of claim 1, wherein the first bias voltage control circuit, the second bias voltage control circuit, and the third bias voltage control circuit each include a voltage source and a radio frequency choke, and the voltage source and the radio frequency choke are connected in series with each other.

3. a first matching circuit including a first inductor and a first capacitor, the first inductor being coupled between the first transistor and the signal input terminal, and the first capacitor being coupled between the signal input terminal and the ground terminal; and 2. The attenuator according to claim 1, further comprising: a second matching circuit including a second inductor and a second capacitor, the second inductor being coupled between the first transistor and the signal output terminal, and the second capacitor being coupled between the signal output terminal and the ground terminal.

4. 2. The attenuator of claim 1, wherein the compensation circuit is a spiral inductor.

5. 2. The attenuator of claim 1, wherein the second bias voltage is the same as the third bias voltage.

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