Transfer Processing Unit

Abstract

A transfer processing device (10) comprises a computation command number acquisition circuit (20), a buffer circuit (30), a transfer information acquisition circuit (40), and a software processing unit (50). The computation command number acquisition circuit (20) acquires a transfer command number corresponding to transfer information, which is information relating to a next transfer destination for a computation command. The buffer circuit (30) is disposed between the computation command number acquisition circuit (20) and the transfer information acquisition circuit (40), and temporarily stores and relays a computation command and a computation command number that are supplied from the computation command number acquisition circuit (20) to the transfer information acquisition circuit (40). The transfer information acquisition circuit (40) acquires the transfer information on the basis of the computation command number, and attaches the acquired transfer information to the computation command. The buffer circuit (30) holds the computation command number and the computation command until there is an output request from the transfer information acquisition circuit (40). Due to the foregoing, this invention can prevent a mistaken transfer caused by a timing deviation between software processing by the software processing unit (50) and transfer processing of the computation command.

Description

[Technical field]

[0001] The present invention relates to a transfer processing device that performs processing for transferring an arithmetic instruction. [Background technology]

[0002] In recent years, advanced services using virtual reality or artificial intelligence on the Internet have been developed. In this situation, in order to flexibly respond to advanced services, a technology (see Patent Document 1) has been developed that configures a virtual computer on software using multiple high-performance computer resources. In such a virtual computer, multiple arithmetic instructions are distributed and executed by multiple physical machines (distributed computers). At this time, the arithmetic instructions are transferred from one physical machine to another physical machine. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2018-36947 A Summary of the Invention [Problem to be solved by the invention]

[0004] Here, the arithmetic instructions are transferred by the transfer processing circuit so as to be transferred at high speed, but there are various arithmetic instructions transferred in the virtual computer, and software processing may be required for the transfer processing circuit. Examples of such software processing include recovery from a soft error in a table held by the transfer processing circuit, and updating of a table held by the transfer processing circuit. Here, since the processing speed of software processing is generally slower than the processing speed of the transfer processing circuit, the software processing may not be able to keep up with the transfer processing of the arithmetic instructions. In this case, the transfer processing of the arithmetic instructions is not performed normally, and erroneous transfer of the arithmetic instructions occurs.

[0005] An object of the present invention is to prevent erroneous transfer caused by a timing mismatch between software processing and transfer processing of an arithmetic instruction. [Means for solving the problem]

[0006] In order to solve the above-mentioned problems, a transfer processing device according to the present invention includes an operation instruction number acquisition circuit configured to acquire an operation instruction identifier that identifies an operation instruction to be transferred, acquire the operation instruction number corresponding to the acquired operation instruction identifier from an operation instruction identifier table having a plurality of combinations of operation instruction identifiers and operation instruction numbers, and output the acquired operation instruction number together with the operation instruction, a transfer information acquisition circuit configured to acquire the operation instruction number and the operation instruction output from the operation instruction number acquisition circuit, acquire the transfer information corresponding to the input operation instruction number from a transfer information table having a plurality of combinations of operation instruction numbers and transfer information, and output the acquired transfer information together with the operation instruction, a software processing unit that executes software processing on the transfer information acquisition circuit, and a buffer circuit that is arranged between the operation instruction number acquisition circuit and the transfer information acquisition circuit and relays the operation instruction number and the operation instruction, and is configured to hold the operation instruction number and the operation instruction while the software processing is being executed, and output the operation instruction number to the transfer information acquisition circuit after the software processing is completed. Effect of the Invention

[0007] According to the present invention, it is possible to prevent erroneous transfer due to a timing mismatch between software processing and transfer processing of an arithmetic instruction. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a configuration diagram of a transfer processing device according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a flowchart of an operation instruction obtaining process executed by the operation instruction number obtaining circuit of FIG. [Diagram 3]FIG. 3 is a flowchart of a buffer memory process executed by the memory buffer circuit of FIG. [Figure 4] FIG. 4 is a flowchart of a transfer information acquisition process executed by the transfer information acquisition circuit of FIG. [Diagram 5] FIG. 5 is a flowchart of the table recovery process executed by the software processing unit in FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An arithmetic instruction transfer processing device 10 according to an embodiment of the present invention will be described with reference to the drawings.

[0010] <Overall configuration of the operation instruction transfer processing device> As shown in Fig. 1, a transfer processing device 10 according to this embodiment is connected to a network N. The transfer processing device 10 is configured as one of a plurality of distributed computers constituting a node of a virtual computer. The transfer processing device 10 is configured to be able to communicate with a server computer 110 that controls the predetermined calculation and a plurality of other distributed computers 120 via the network N. The transfer processing device 10, the server computer 110, and the plurality of other distributed computers 120 transmit and receive arithmetic instructions that constitute software components to be processed in a distributed manner, and execute the received arithmetic instructions.

[0011] As shown in FIG. 1, the transfer processing device 10 includes an operation instruction number acquisition circuit 20, a buffer circuit 30, a transfer information acquisition circuit 40, a software processing unit 50, and a storage unit 60. The above circuits 20 to 40 included in the transfer processing device 10 constitute a transfer processing circuit 10A that performs processing for transferring an operation instruction. The transfer processing circuit 10A is configured with an FPGA (Field Programmable Gate Array), and each of the above circuits 20 to 40 is configured with a part of the FPGA. The transfer processing circuit 10A may be configured with a logic circuit other than the FPGA. The software processing unit 50 is configured with a CPU that executes a program stored in the storage unit 60, and a RAM that is the main memory of the CPU.

[0012] The operation command received by the transfer processing device 10 from the server computer 110 or another distributed computer 120 is input to the operation command number acquisition circuit 20. The operation command number acquisition circuit 20 acquires a transfer command number corresponding to transfer information (e.g., a port number to send the operation command and / or a destination address of the operation command) which is information on the next transfer destination of the operation command. The buffer circuit 30 is disposed between the operation command number acquisition circuit 20 and the transfer information acquisition circuit 40, and temporarily stores and relays the operation command and the operation command number supplied from the operation command number acquisition circuit 20 to the transfer information acquisition circuit 40. The transfer information acquisition circuit 40 acquires transfer information based on the operation command number and assigns the acquired transfer information to the operation command. The operation command to which the transfer information is assigned is transmitted to the transfer destination indicated by the transfer information by a communication device such as a network card (not shown) based on the transfer information. If the transfer destination is the distributed computer 120, the operation command is stored in the memory 120A of the distributed computer 120 and executed by the operation device 120B. The arithmetic device 120 may be included in a processor such as a CPU, and the memory 120A may be a cache memory, etc. A large number of arithmetic instructions are input to the transfer processing device 10, and the circuits 20 to 40 process the arithmetic instructions in sequence.

[0013] Although details will be described later, when acquiring a transfer instruction number, the operation instruction number acquisition circuit 20 refers to an operation instruction identifier table 29 which has a plurality of combinations of operation instruction identifiers based on operation instructions and operation instruction numbers. The operation instruction identifier table 29 is stored in the memory 21 of the operation instruction number acquisition circuit 20. When acquiring transfer information, the transfer information acquisition circuit 40 refers to a transfer information table 49 which has a plurality of combinations of operation instruction numbers and transfer information. The transfer information table 49 is stored in the memory 41 of the transfer information acquisition circuit 40. The software processing unit 50 manages the updates of the tables 29, 49.

[0014] Each of the circuits 20 to 40 performs processing by logic circuits, rather than by executing a program. This type of processing can be called hardware processing. On the other hand, the software processing unit 50 performs processing by executing a program (software). This type of processing is software processing. The processing speed of the hardware processing is faster than the processing speed of the software processing. The buffer circuit 30 holds operation commands and the like for a predetermined period of time to absorb the difference in processing speed between the hardware processing and the software processing. For example, the buffer circuit 30 is configured not to output operation commands and the like to the transfer information acquisition circuit 40 until the software processing unit 50 finishes updating the transfer information table 49.

[0015] <Calculation command> The configuration of the calculation instruction is arbitrary. Here, the calculation instruction includes an 8-byte internal processor consisting of a header at the beginning, etc., and a calculation instruction body indicating the content (data) of the calculation instruction. The internal processor includes information such as the address of the computer that sent the calculation instruction and the length of the entire calculation instruction. The calculation instruction body is a RISC calculation instruction of 32 bits = 4 bytes, etc.

[0016] <Operation instruction number acquisition circuit 20> As shown in FIG. 1, the operation instruction number obtaining circuit 20 includes a memory 21, an operation instruction processing unit 22, a table processing unit 23, and an error detection and correction unit 24.

[0017] The memory 21 stores the above-mentioned operation instruction identifier table 29. The operation instruction identifier table 29 is divided into two tables, a master first table 29A and a slave second table 29B, which have the same contents, for the purpose of soft error countermeasures. In each of the first table 29A and the second table 29B, an operation instruction number is associated with a plurality of operation instruction identifiers. Here, the order of the rows of the operation instruction identifiers in the tables 29A and 29B is the operation instruction number. For example, the operation instruction number corresponding to the operation instruction identifier in the 51st row is 51. The operation instruction number also corresponds to the rows of the transfer information table 49. Therefore, the operation instruction number is associated with the transfer information. The operation instruction identifier is obtained based on the operation instruction and identifies the operation instruction. The operation instruction number is set for each operation instruction identifier and corresponds to one transfer information.

[0018] The memory 21 may include a Content Addressable Memory (CAM), and the CAM may store the operation instruction identifier table 29. In this case, the operation instruction number is set as an address of the memory 41 of the transfer information corresponding to the operation instruction number in the transfer information table 49 of the transfer information acquisition circuit 40. With this configuration, the transfer information can be acquired at high speed.

[0019] The operation instruction processing unit 22, the table processing unit 23, and the error detection and correction unit 24 cooperate to execute an operation instruction number acquisition process for acquiring an operation instruction number shown in Fig. 2. This process is started when an operation instruction is input to the operation instruction number acquisition circuit 20.

[0020] In the calculation instruction number acquisition process of Fig. 2, the calculation instruction processing unit 22 holds the input calculation instruction in its own RAM, and reads only a predetermined length of the calculation instruction from the beginning (step S101). Here, the calculation instruction is assumed to consist of an 8-byte internal processor and a 32-bit RISC calculation instruction. The calculation instruction processing unit 22 reads information from the beginning to the 12th byte of the calculation instruction, that is, the entire calculation instruction. Only a portion of the information may be read.

[0021] Thereafter, the arithmetic instruction processing unit 22 determines whether the software processing unit 50 can execute the arithmetic instruction (step S102). The arithmetic instruction processing unit 22 periodically communicates with the software processing unit 50 and monitors whether the software processing unit 50 has a surplus of resources. If the software processing unit 50 has a surplus of resources, the arithmetic instruction processing unit 22 determines that the software processing unit 50 can execute the arithmetic instruction (step S102; Yes). In this case, the arithmetic instruction processing unit 22 outputs the arithmetic instruction to the software processing unit 50 to cause the software processing unit 50 to execute the arithmetic instruction (step S103). If the types of arithmetic instructions that the software processing unit 50 can execute are limited, the arithmetic instruction processing unit 22 may determine whether the software processing unit 50 can execute the arithmetic instruction based on the "opcode" (to be described later) of the RISC arithmetic instruction or the like.

[0022] If the software processing unit 50 cannot execute the arithmetic instruction (step S103; No), the arithmetic instruction processing unit 22 acquires an arithmetic instruction identifier for identifying the arithmetic instruction based on the information read in step S101 (step S104). The arithmetic instruction identifier includes information on the type of operation of the arithmetic instruction and the address of the sender of the arithmetic instruction. In this embodiment, the transfer destination of the arithmetic instruction, that is, another distributed computer that executes the arithmetic instruction, is assigned according to the type of operation and the address of the sender. The information on the type of operation of the arithmetic instruction is acquired based on the arithmetic instruction body. If the arithmetic instruction body (RISC arithmetic instruction) is "funct7 rs2 rs1 funct3 rd opcode", the information on the type of operation of the arithmetic instruction is a total of 17 bits that combines funct7, funct3, and opcode. Alternatively, the information on the type of operation of the arithmetic instruction may be information that combines funct7, funct3, and the lower 2 bits, lower 2 bits, and lower 5 bits of opcode that can identify the type of operation. For example, if funct7 is 00, funct3 is 00, and opcode is 10011, the operation type information is 000010011. The source address is extracted from the internal identifier of the operation instruction.

[0023] Step S105 after step S104 is executed by the table processing unit 23 and the error detection and correction unit 24. Specifically, the table processing unit 23 reads the entries (operation instruction identifiers) of the first table 29A, which is the main table of the operation instruction identifier table 29, one by one, and searches for an entry that matches the operation instruction identifier acquired by the operation instruction processing unit 22. Each entry of the operation instruction identifier table 29 is managed in word units, and an error detection and correction code is added to each entry. Every time an entry is read by the table processing unit 23, the error detection and correction unit 24 performs error detection and correction processing on the entry. The error detection and correction code is a measure against soft errors caused by bit inversion due to cosmic rays, etc.

[0024] Possible cases of error detection results include (1) no error detection, (2) an error detection and correction possible, and (3) an error detection and correction impossible. For example, when the detection result of the first table 29A is the above (1), the table processing unit 23 checks the entry read above against the operation instruction identifier acquired by the operation instruction processing unit 22. If the two do not match, the table processing unit 23 reads the entry of the next row. In the above (2), the error detection and correction unit 24 corrects the error in the entry by the error detection and correction code, and the table processing unit 23 checks the corrected entry against the operation instruction identifier. If the two do not match, the table processing unit 23 reads the entry of the next row. In the above (3), the table processing unit 23 reads the entry of the second table 29B, and the error detection and correction unit 24 detects an error in the entry. The cases of the detection results are the same as the above (1) to (3). In the above (1) and (2), the entry or the corrected entry is matched with the operation instruction identifier. In the above (3), the table processing unit 23 stops matching the currently read entry with the operation instruction identifier and reads the next entry.

[0025] Although not shown, the error detection and correction unit 24 stores the results of the error detection performed above for each entry in the first table 29A and the second table 29B separately in a RAM or the like included in the error detection and correction unit 24. The results include the above (1) to (3).

[0026] After step S105, if the operation instruction identifier acquired by the operation instruction processing unit 22 matches an entry, the table processing unit 23 acquires an operation instruction number corresponding to the entry (step S106). For example, if the operation instruction identifier 000010011 matches the 512th row of the first table, the number 512 is acquired as the operation instruction number. Thereafter, the operation instruction processing unit 22 outputs the operation instruction and the operation instruction number acquired in step S106 to the buffer circuit 30 (step S107). The operation instruction number may be output in a state where it is placed in a predetermined area of ​​the internal processor.

[0027] Thereafter, the error detection and correction unit 24 notifies the software processing unit 50 of the result of the error detection stored in the RAM or the like (step S108). Upon receiving the notification, the software processing unit 50 updates the operation instruction identifier table or the like (details will be described later).

[0028] As described above, in this embodiment, by adding an error detection and correction code to each entry of the operation instruction identifier table and duplicating the operation instruction identifier table, measures are taken against soft errors of bit inversion caused by cosmic rays. There are several error detection and correction codes, but in this embodiment, since the error to be detected is a bit inversion caused by cosmic rays, which is an error that occurs less frequently, SECDED (single error correction double error detection), which performs single error correction and double error detection, is used for error detection and correction. This allows efficient error correction without increasing the circuit impact.

[0029] <Buffer circuit 30> 1, the buffer circuit 30 includes a buffer memory control unit 31 and a buffer memory 32. The buffer memory control unit 31 executes the buffer memory process of FIG. 3 to control the buffer memory 32 to hold the calculation instruction number and the calculation instruction output by the calculation instruction processing unit 22 until an output request is received from the transfer information acquisition circuit 40.

[0030] In the buffer memory process, the buffer memory control unit 31 first acquires attribute information of the calculation instruction based on the calculation instruction number and the calculation instruction output by the calculation instruction number acquisition circuit 20 (step S201). The attribute information here consists of the calculation instruction number and the length of the calculation instruction included in the first internal processor of the calculation instruction. Hereinafter, the calculation instruction number is G1, the length of the calculation instruction is G2, and the calculation instruction is F.

[0031] Thereafter, the buffer memory control unit 31 calculates an error detection code for the entire calculation instruction F so that an error can be detected if an error is superimposed on the calculation instruction F, and appends the calculated error detection code to the end of the calculation instruction F (step S202). In this example, CRC8 (Cyclic Redundancy Check 8) is appended as the error detection code. The error detection code is not limited to CRC8, and various similar error detection code formats are applicable. The error detection code may be an error detection and correction code that is also capable of correction. In the following, the error detection code is referred to as the calculation instruction F. The length G2 of the calculation instruction in the internal processor is corrected to the length G2 including the error detection code at the end.

[0032] After that, the buffer memory control unit 31 generates an identifier that links the attribute information (G1, G2) of the calculation instruction F obtained in step S201 with the calculation instruction F (step S203). This identifier is placed before the calculation instruction F and is information that identifies the calculation instruction F. The buffer memory control unit 31 prepares a fixed-length identifier and embeds the attribute information (G1, G2) in this identifier. At this time, it is preferable to determine in advance an area in the identifier to which the attribute information (G1, G2) is assigned. By embedding the attribute information (G1, G2) of the input calculation instruction in the identifier, the input calculation instruction F is linked with the attribute information (G1, G2) of the input calculation instruction. Hereinafter, the identifier generated in step S203 is referred to as S.

[0033] Thereafter, the buffer memory control unit 31 calculates an error detection and correction code for the entire identifier S so that the generated identifier S can be detected and corrected for errors, and embeds the calculated error detection and correction code in a specific area in the identifier S, for example, [23:16] that does not affect the length of the operation instruction and the operation instruction number (step S204). For example, if a SECDED code is applied as the error detection and correction code, it is possible to cover the error pattern of the soft error that actually occurs. The error detection and correction code may be intended only for the length of the operation instruction and the operation instruction number of the identifier S. In this case, the error detection and correction of the identifier S described below is intended only for the length of the operation instruction and the operation instruction number of the identifier S.

[0034] Thereafter, the buffer memory control unit 31 starts buffering the calculation instruction F in the buffer memory 32 (step S205). In the previous step S204, the identifier S is generated based on the length G2 of the calculation instruction F and the calculation instruction number G1 obtained from the calculation instruction F, so that the buffering of the identifier S in the buffer memory 32 may be delayed compared to the calculation instruction F. In step S205, before buffering the calculation instruction F, an area for buffering the identifier S is secured in the buffer memory 32. Then, the calculation instruction F is stored in the buffer memory 32, avoiding this secured area. The area for the identifier S is an area that has a higher read order than the calculation instruction F.

[0035] After that, the buffer memory control unit 31 starts buffering the identifier S in the area secured in the buffer memory 32 (step S206).

[0036] Thereafter, the buffer memory control unit 31 monitors and controls the buffering state of the arithmetic instruction F and the identifier S (step S207). More specifically, the buffer memory control unit 31 monitors whether the identifier S and the arithmetic instruction F have all been stored in the buffer memory 32. After storing the identifier S and the arithmetic instruction F in the buffer memory, the buffer memory control unit 31 holds the accumulated identifier S and arithmetic instruction F in the buffer memory 32 until an output instruction for the identifier S and the arithmetic instruction F in the subsequent process is received.

[0037] The transfer information acquisition circuit 40 issues an output command for a set of one identifier S and an arithmetic instruction F to the buffer circuit 30 at an appropriate timing. The buffer memory control unit 31 waits until it receives this output command, and when it receives the output command, it reads out a part of the set of the identifier S and the arithmetic instruction F, including at least the entire identifier S, from the buffer memory 32 (step S208). The buffer memory 32 is of a FIFO (first in first out) type here, and when there is an output command, the identifier S stored first in the buffer memory 32 is output. In other words, when the arithmetic instruction F is output, the identifier S held in the previous area is output. At this time, if the bit width of the buffer memory 32 is larger than the number of bits of the identifier S and the identifier S is stored from the beginning of the first layer of the buffer memory 32, the read information will include all the identifiers S if only the first layer of the buffer memory 32 is taken out.

[0038] After reading the identifier S, the buffer memory control unit 31 reads the error detection and correction code (SECDED code) embedded in the identifier S, and uses the read error detection and correction code to determine whether the identifier S contains an error (step S209). If there is no error (step S209; No), it is guaranteed that the identifier S is correct information. In this case, the buffer memory control unit 31 reads the remainder of the calculation instruction F from the buffer memory 32, and outputs the identifier S and the entire calculation instruction F to the transfer information acquisition circuit 40 (step S210). The remainder of the calculation instruction F is specified by the information on the length of the calculation instruction F included in the identifier S.

[0039] When an error is detected in the identifier S (step S209; Yes), the buffer memory control unit 31 determines whether the detected error is correctable (step S211). In this case, if there is one bit error in the identifier S due to a soft error or the like, the error is correctable. If there are two or more bit errors in the identifier S due to a soft error or the like, the error cannot be corrected.

[0040] If the error in the identifier S can be corrected (step S211; Yes), the buffer memory control unit 31 performs error detection and correction on the identifier S (step S212). This error detection and correction ensures that the identifier S read from the buffer memory 32 is correct information without errors. Thereafter, the buffer memory control unit 31 reads the remainder of the calculation instruction F from the buffer memory 32, and outputs the corrected identifier S and calculation instruction F to the transfer information acquisition circuit 40 (step S213).

[0041] If the error in the identifier S is uncorrectable (step S211; No), the information on the length G2 of the calculation instruction in the identifier S and the calculation instruction number G1 is unreliable. In particular, if the length G2 of the calculation instruction is incorrect, and other calculation instructions are stored in the buffer memory 32, the boundary between the end of the calculation instruction F and the beginning of the identifier S of the other calculation instruction becomes unclear, and all calculation instructions F that are processed sequentially are processed incorrectly. For this reason, if the error in the identifier S is uncorrectable, the buffer memory control unit 31 clears (discards) all calculation instructions and identifiers currently stored in the buffer memory 32 (step S214). At this time, the buffer memory control unit 31 may clear (discard) the calculation instruction that is being read from the buffer memory 32 and the calculation instruction that is being stored in the buffer memory 32. If the calculation instruction and the identifier are of fixed length, only the calculation instruction corresponding to the identifier to be processed may be discarded.

[0042] According to the above series of processes, the buffer memory control unit 31 can obtain the correct identifier S and calculation instruction F through a simple process of reading only the first layer of the buffer memory 32, rather than reading and processing up to the end of the calculation instruction F from the buffer memory 32.

[0043] Furthermore, even if a bit error that can be detected and corrected occurs due to a soft error, processing can be continued without stopping the processing of the operation instruction by performing a simple process of correcting the error in the length G2 of the operation instruction and the operation instruction number G1.

[0044] In addition, when an error occurs that cannot be corrected by the implemented error detection and correction, by discarding the calculation instructions, etc. in the buffer memory 32, it is possible to suppress the impact on subsequent calculation instruction processing simply by sacrificing the calculation instructions stored in the buffer memory 32.

[0045] <Transfer information acquisition circuit 40> As shown in FIG. 1, the transfer information acquisition circuit 40 includes a memory 41, an arithmetic instruction processing unit 42, a table processing unit 43, and an error detection and correction unit 44.

[0046] The memory 41 stores the above-mentioned transfer information table 49. The transfer information table 49 is divided into two tables, a master first table 49A and a slave second table 49B, which have the same contents, for soft error countermeasures. Each entry in the transfer information table 49 is managed in units of words, and an error detection and correction code is added to each entry. In the transfer information table 49, that is, the master first and slave second tables 49A and 49B, a plurality of transfer information items are associated with a plurality of operation instruction numbers, respectively. Here, the order of the rows of the transfer information in the master first and slave second tables 49A and 49B is the operation instruction number. For example, the operation instruction number corresponding to the transfer information in the 51st row is 51.

[0047] The calculation command processing unit 42, the table processing unit 43, and the error detection and correction unit 44 cooperate to execute the transfer information acquisition process shown in Fig. 4. The transfer information acquisition circuit 40 supplies an output command of a calculation command to the buffer circuit 30 at any timing when the software processing unit 50 is not executing software processing described below. The transfer information acquisition process is started when an identifier S and a calculation command F are input from the buffer circuit 30 to the transfer information acquisition circuit 40 in response to the output command.

[0048] In the transfer information acquisition process, first, the calculation command processing unit 42 holds the identifier S and the calculation command F in its own RAM, and extracts the calculation command number included in the identifier S (step S301). The calculation command processing unit 42 may first perform error detection and correction processing using the error detection and correction code included in the identifier S. The calculation command processing unit 42 may also perform error detection using the error detection code at the end of the calculation command F.

[0049] Thereafter, the table processing unit 43 acquires the transfer information stored in the row indicated by the operation instruction number from the first table 49A of the transfer information table 49 (step S302). For example, when the operation instruction number indicates the 512th row, the 512th transfer information is acquired. Thereafter, the error detection and correction unit 44 performs an error detection and correction process on the transfer information based on the error detection and correction code added to the acquired transfer information (step S303). The error detection result may be (1) no error detection, (2) an error detection and correction possible, or (3) an error detection and correction impossible. In the case of (1) above, the transfer information is used as it is in step S304 and thereafter. In the case of (2) above, the error detection and correction unit 44 corrects the error. In this case, the corrected transfer information is used in step S304 and thereafter. In the case of (3) above, the table processing unit 43 acquires the transfer information by referring to the second table 49B, and performs error detection and correction in the same manner as described above. If the error detection and correction unit 44 detects an uncorrectable error in the transfer information read from the second table 49B, the transfer information acquisition process is stopped.

[0050] Although not shown, the error detection and correction unit 44 stores the results of the error detection performed above for each entry in the first table 49A and the second table 29B separately in a RAM or the like included in the error detection and correction unit 44. The results include the above (1) to (3).

[0051] The calculation instruction processing unit 42 assigns the transfer information acquired by the table processing unit 43 or corrected by the error detection and correction unit 44 to the calculation instruction F as information indicating the transfer destination of the calculation instruction F, and outputs the transfer information and the calculation instruction F (step S304). The calculation instruction processing unit 42 may also output the identifier S in addition to the transfer information and the calculation instruction F.

[0052] Thereafter, the error detection and correction unit 44 notifies the software processing unit 50 of the result of the error detection stored in the RAM or the like (step S305). Upon receiving the notification, the software processing unit 50 updates the operation instruction identifier table or the like (details will be described later).

[0053] As described above, in this embodiment, by adding an error detection and correction code to each entry of the transfer information table and duplicating the table, measures are taken against soft errors of bit inversion caused by cosmic rays. As above, SECDED, which performs single error correction and double error detection, is used for error detection and correction. This allows efficient error correction without increasing the circuit impact.

[0054] <Software Processing Unit 50> 1, the software processing unit 50 includes a table recovery determination unit 51, a table update unit 52, and a table processing stop / restart unit 53. When an error is detected in an entry of the above-mentioned arithmetic instruction identifier table 29 and the transfer information table 49, since entries are recorded in advance in each table, this error may be a bit inversion caused by a soft error. Therefore, the software processing unit 50 performs processing for recovering the tables using the above-mentioned units 51 to 53.

[0055] The table recovery determination unit 51 counts the number of times an error has been detected (whether or not it can be corrected) for each entry in the operation instruction identifier table 29, based on the error detection result (step S108) notified by the error detection and correction unit 24 of the operation instruction number acquisition circuit 20 each time an operation instruction is processed. The count value is tabulated and stored for each entry. Through this process, the accuracy, or quality, of the entries in the operation instruction identifier table 29 is monitored.

[0056] The table recovery determination unit 51 counts the number of times an error has been detected (whether or not it can be corrected) for each entry in the transfer information table 49, based on the transfer information notified from the error detection and correction unit 44 of the transfer information acquisition circuit 40 each time an arithmetic instruction is processed (step S305). The count value is tabulated and stored for each entry. Through this process, the accuracy, or quality, of the entries in the transfer information table 49 is monitored.

[0057] The table recovery determination unit 51 determines whether the count value of a certain entry has exceeded a predetermined threshold value each time the above notification (step S108 or S305) is received. When the table recovery determination unit 51 determines that the count value has exceeded the threshold value, it determines that the table recovery process shown in FIG. 5 should be performed on the table to which the entry belongs.

[0058] If an error is detected, it is possible that a bit inversion has occurred due to a soft error, since an entry had been written in the table beforehand.

[0059] The following describes the table recovery process when the count value for an entry in the transfer information table 49 exceeds the predetermined threshold value.

[0060] In the table recovery process of Fig. 5, first, the table processing stop / restart unit 53 instructs the transfer information acquisition circuit 40, which handles the transfer information table 49 that is the target of the current table recovery process, to stop table processing (step S401). The table processing here is processing that refers to the transfer information table 49, and corresponds to step S302 in Fig. 4. When the transfer information acquisition circuit 40 receives the instruction, if it is performing the processing of step S302, it stops the processing. If the target of the table recovery process is the operation instruction identifier table 29, the table processing corresponds to steps S105 and S106 in Fig. 2.

[0061] After step S401, table update unit 52 updates the table of first table 49A or second table 49B of transfer information table 49 to which the entry whose count value exceeds the predetermined threshold belongs (step S402). When updating, table update unit 52 may rewrite only the entry whose count value exceeds the threshold to correct data, or may rewrite the entire first table 49A or second table 49B. Table update unit 52 may update both first table 49A and second table 49B. Data required for updating may be acquired from storage unit 60 or server computer 110, for example.

[0062] When the above update is completed, the table processing stop / restart unit 53 instructs the transfer information acquisition circuit 40 to start table processing (step S403). When the transfer information acquisition circuit 40 receives the instruction and the processing of step S302 is stopped, the transfer information acquisition circuit 40 resumes the processing.

[0063] The software processing unit 50 communicates with the operation instruction number acquisition circuit 20 or the transfer information acquisition circuit 40, and can rewrite the entry in which the error, i.e., the bit inversion, occurred to a normal entry every time an error is detected as described above. However, in order to search the above-mentioned tables 29 or 49 at high speed, it is desirable to reduce the rewriting process as much as possible. For this reason, in the operation instruction number acquisition circuit 20 or the transfer information acquisition circuit 40, once an error is detected in an entry, the table processing unit 23 or 43 may store this information in a table such as a RAM, and in subsequent searches, the entry in which the error was detected may be avoided. This can improve the efficiency of the search, i.e., reduce the processing delay for the search.

[0064] When search results are accumulated for a large number of operation instructions, and it becomes impossible to search for entries due to the accumulation of soft errors, it is possible that the processing in the operation instruction number acquisition circuit 20 or the transfer information acquisition circuit 40 may be stopped. As described above, the table recovery determination unit 51 monitors the error detection status of the entire entry, and makes a table recovery determination at the above threshold value, thereby preventing the occurrence of adverse effects such as the above processing stop.

[0065] The table recovery determination unit 51 may count only the cases where an error has been detected and the error is uncorrectable, rather than the cases where an error has been detected. This can reduce processing delays.

[0066] The software processing unit 50 may appropriately change the transfer destination (transfer information) defined in the arithmetic instruction identifier table 29 and the transfer information table 49. For example, the server computer 110 monitors the transfer processing device 10 and the distributed computer 120 and manages which arithmetic instruction is to be transferred to which computer. In this case, the server computer 110 instructs the software processing unit 50 to update the contents of the above tables 29 and 49 that define the transfer destination of the arithmetic instruction according to the situation. Based on the instruction, the software processing unit 50 updates the contents of the above tables 29 and 49 by performing software processing on the arithmetic instruction number acquisition circuit 20 or the transfer information acquisition circuit 40 by the table update unit 52 or the like. In this case, the table processing in the arithmetic instruction number acquisition circuit 20 or the transfer information acquisition circuit 40 is also appropriately stopped. By updating the contents of the tables 29 and 49, for example, when the server computer 110 detects that a certain distributed computer 120 is no longer able to execute distributed processing, the distributed computer 120 can be excluded from candidates for the transfer destination.

[0067] (Effects of the embodiment) As described above, the software processing unit 50 performs software processing on the operation instruction number acquisition circuit 20 or the transfer information acquisition circuit 40 to recover or update the table. At this time, particularly in the transfer information acquisition circuit 40, the transfer processing (such as step S302 in FIG. 4 that refers to the transfer information table 49) which is a hardware processing for transferring the operation instruction is stopped while the software processing is being executed, and the transfer processing is delayed by the software processing. If the buffer circuit 30 is not provided, an operation instruction is input from the operation instruction number acquisition circuit 20 to the transfer information acquisition circuit 40 even while the transfer processing in the transfer information acquisition circuit 40 is stopped and software processing is being executed. In such a case, the operation instruction currently being processed by the transfer information acquisition circuit 40 is mixed with the operation instruction input later, and the transfer processing of the operation instruction is not performed normally, and the operation instruction is transferred to the desired destination together with other operation instructions that are not intended, which may cause inconvenience such as erroneous transfer of the operation instruction. In this embodiment, the buffer circuit 30 is provided between the operation instruction number acquisition circuit 20 and the transfer information acquisition circuit 40. The buffer circuit 30 does not output the operation instruction held at that time until it receives an output instruction from the transfer information acquisition circuit 40. In this way, the buffer circuit 30 is configured to output the operation instruction number and operation instruction output by the operation instruction number acquisition circuit 20 after the software processing for the transfer information acquisition circuit 40 is completed. This prevents the software processing from catching up with the transfer processing of the operation instruction, which causes the transfer processing of the operation instruction to be performed incorrectly and results in an erroneous transfer of the operation instruction. In other words, according to this embodiment, erroneous transfer due to a timing mismatch between the software processing and the transfer processing of the operation instruction is prevented. This realizes a highly reliable transfer.

[0068] Even if an error due to a soft error occurs in an entry of the table 29 or 49 referenced when transferring an arithmetic instruction, the table is duplicated and an error detection and correction code is added to each entry (for example, word unit), so the transfer processing device 10 is resistant to soft errors. In addition, the software processing unit 50 can determine whether or not the entire table needs to be restored, and rewrite the entire table after soft errors have accumulated, which makes it possible to avoid updating the table during a search, thereby increasing the table processing speed and reducing processing delays.

[0069] Furthermore, the buffer circuit 30 adds information (identifier S) including an operation instruction number and an error detection and correction code before the operation instruction F, and when storing the operation instruction F, it reserves a storage area for the information before storing the operation instruction. Therefore, when reading the operation instruction F, the identifier S, which is the information, is read first, so that error detection using the error detection and correction code can be performed without reading the entire operation instruction F. This reduces the processing delay in the buffer circuit 30, and also eliminates the need for an extra buffer for writing the operation instruction F, thereby reducing the circuit size.

[0070] The software processing unit 50 of this embodiment can also operate as an arithmetic instruction execution unit that acquires an arithmetic instruction input to the transfer processing circuit 10A, i.e., the arithmetic instruction number acquisition circuit 20, when the arithmetic instruction is executable, and executes the arithmetic instruction. This allows the transfer processing device 10 to perform distributed processing. When the software processing unit 50 as an arithmetic instruction execution unit cannot execute an arithmetic instruction, the arithmetic instruction number acquisition circuit 20 acquires an arithmetic instruction number and outputs the acquired arithmetic instruction number together with the arithmetic instruction. This allows the transfer processing device 10 to transfer an arithmetic instruction to another distributed computer 120 or the like when the arithmetic instruction cannot be executed. The arithmetic instruction execution unit may be configured by a device other than the software processing unit 50. The arithmetic instruction execution unit may be configured by a processor that executes a program, or the like.

[0071] (Variations, etc.) Although the present invention has been described with reference to the above embodiment, the present invention is not limited to the above embodiment. Various modifications may be made to the above embodiment. Modifications are listed below, and at least some of the following modifications may be combined with each other to the extent that they are not inconsistent.

[0072] The internal processor of the calculation instruction may include a destination address of the distributed computer 120 that executes the calculation instruction. In this case, the destination address may be included in the calculation instruction identifier. In this case, the transfer information may be information indicating the transfer destination by specifying a port connected to a network to which the distributed computer 120 having the destination address is connected. In this case, the calculation instruction output from the transfer information acquisition circuit 40 is transmitted from the transfer processing device 10 with the destination address included in the internal processor of the calculation instruction as the final destination. The destination address may be acquired by the buffer circuit 30 and included in the identifier S instead of or in addition to the calculation instruction number. The calculation instruction number may be transmitted separately together with the calculation instruction F. The destination address may be assigned to the source of the calculation instruction and the type of calculation of the calculation instruction. In this case, the buffer circuit 30 refers to a table, for example, and acquires and uses the destination address assigned to the combination of the source address included in the internal processor of the calculation instruction and the opcode of the calculation instruction. In this case, the transfer information acquisition circuit 40 also outputs an identifier S, and the operation command output from the transfer information acquisition circuit 40 is transmitted from the transfer processing device 10 with the destination address included in the identifier S as the final destination. Note that the internal processor of the operation command may be appropriately deleted during the process by the transfer processing device 10.

[0073] The destination address included in the internal processor of the arithmetic instruction, the destination address included in the identifier S, or the destination address indicated by the transfer information may be a memory address that is an address of various memories 120A such as a cache memory, an on-chip memory, or a DRAM memory accessed by the arithmetic device 120B in the distributed computer 120 that executes the arithmetic instruction. The arithmetic device 120B is included in a processor such as a CPU of the distributed computer 120. The various memories may be provided inside or outside the processor. As described above, the transfer information or the arithmetic instruction may include the memory address of the memory 120B accessed by the arithmetic device that executes the arithmetic instruction as a destination address, or the transfer information acquisition circuit 40 may be configured to output the address as a destination address by the identifier S or the like separately from the transfer information or the arithmetic instruction. According to such a configuration, since the arithmetic instruction is placed once in the memory 120A, flexible and high-speed arithmetic processing is possible even when a large amount of arithmetic instructions need to be executed. Furthermore, the address of a shared memory shared by multiple distributed computers 120 can be specified as the memory address, and an arithmetic instruction (including data used in the arithmetic) can be stored once in the shared memory and used, so that a large amount of information processing, i.e., the execution of arithmetic instructions, can be performed accurately.

[0074] The error detection and correction includes a mode in which only error detection is performed. That is, an error detection code may be used as the error detection and correction code. Any code type may be used for error detection and correction. For error detection, a parity code or a cyclic redundancy check code such as CRC may be used. For error detection and correction, a Reed-Solomon code may be used in addition to a single error correction or SECDED that detects two errors.

[0075] The information included in the computation instruction identifier may be a combination of header information such as the destination or source address and priority. The computation instruction may have a configuration other than an 8-byte internal processor at the beginning and a 32-bit RISC computation instruction. One computation instruction may be an 8-byte internal processor followed by a series of multiple instructions. The length of the internal processor and computation instruction is not limited to the above embodiment and is arbitrary. The internal processor may include not only information on the length of the instruction but also the number of consecutive instructions, user ID information, etc. The internal processor may directly include the computation instruction identifier. The above various computations or calculations may use the value (priority) and length of a VLAN (Virtual LAN) tag, and any numerical value may be used.

[0076] The arithmetic instruction may not be a RISC arithmetic instruction, but may be an instruction with a large function such as an arithmetic instruction for converting an image size. The arithmetic instruction may be a unique arithmetic instruction that is not standardized. The arithmetic instruction may be stored in a communication protocol, for example, an http request, from the distributed computer 120. The arithmetic instruction may be input to the transfer processing device 10 using various protocols such as MQTT, CoAP, QUIC, WebSocket, NATS, Kafka, REST, and a unique protocol. The arithmetic instruction transmitted from the transfer processing device 10 may also be transferred using various protocols similar to the above. The transfer direction of the arithmetic instruction is not limited to one-way, but may be bidirectional. A plurality of distributed computers may be connected to the transfer processing device 10. The transfer processing device 10 may be various switches, network cards, etc. that relay arithmetic instructions.

[0077] The software processing unit 50 may restore the first table 29A or 49A at the same time as accessing the second table 29B or 49B. This makes it possible to restore the table to a healthy state without affecting searches.

[0078] Errors in entries may be detected not only by soft errors but also by various factors such as noise. Errors may occur simultaneously in multiple entries. For example, error areas may spread to physically close locations in the memory. When errors are detected in multiple entries, the table update unit 52 may update the entire table. In addition, the table recovery determination unit 51 may recover the table immediately when an error is detected in one entry. The table may be rewritten multiple times. As a result, if the time required for storing calculation commands in the buffer is within 1 ms, for example, if there is a buffer of about 1 KB in the case of video distribution at about 10 Mbps, the calculation delay can be minimized even when real-time processing is required. [Explanation of symbols]

[0079] 10...transfer processing device, 10A...transfer processing circuit, 20...operation instruction number acquisition circuit, 21...memory, 22...operation instruction processing unit, 23...table processing unit, 24...error detection and correction unit, 29...operation instruction identifier table, 29A...first table, 29B...second table, 30...buffer circuit, 31...buffer memory control unit, 32...buffer memory, 40...transfer information acquisition circuit, 41...memory, 42...operation instruction processing unit, 43...table processing unit, 44...error detection and correction unit, 49...transfer information table, 49A...first table, 49B...second table, 50...software processing unit, 51...table recovery determination unit, 52...table update unit, 53...table processing stop / restart unit, 60...memory unit, 110...server computer, 120...distributed computer, 120A...memory, 120B...operation device, N...network.

Claims

1. an operation instruction number acquisition circuit configured to acquire an operation instruction identifier for identifying an operation instruction to be transferred, acquire the operation instruction number corresponding to the acquired operation instruction identifier from an operation instruction identifier table having a plurality of combinations of the operation instruction identifier and the operation instruction number, and output the acquired operation instruction number together with the operation instruction; a transfer information acquisition circuit configured to receive the operation instruction number and the operation instruction output from the operation instruction number acquisition circuit, acquire the transfer information corresponding to the input operation instruction number from a transfer information table having a plurality of combinations of operation instruction numbers and transfer information, and output the acquired transfer information together with the operation instruction; a software processing unit that executes software processing on the transfer information acquisition circuit; a buffer circuit disposed between the operation instruction number acquisition circuit and the transfer information acquisition circuit for relaying the operation instruction number and the operation instruction, the buffer circuit being configured to hold the operation instruction number and the operation instruction while the software processing is being executed, and output the operation instruction number and the operation instruction to the transfer information acquisition circuit after the software processing is completed; A transfer processing device comprising:

2. the operation instruction identifier table is made redundant into a first table and a second table, an error detection and correction code is added to the operation instruction identifier of the operation instruction identifier table; the operation instruction number acquisition circuit is configured to detect whether there is an error in the operation instruction identifier of the first table by the error detection and correction code, and, when an error is detected, to acquire the operation instruction number by referring to the second table. The transfer processing device according to claim 1 .

3. The forwarding information table is redundantly configured into a first table and a second table, an error detection and correction code is added to the transfer information in the transfer information table; the forwarding information acquisition circuit is configured to detect whether there is an error in the forwarding information of the first table by the error detection and correction code, and, when an error is detected, to acquire the forwarding information by referring to the second table.

3. A transfer processing device according to claim 1 or 2.

4. The buffer circuit includes: When storing the operation command, information including the operation command number and an error detection and correction code is added in front of the operation command, When storing the arithmetic instruction, a storage area for the information is secured before storing the arithmetic instruction.

4. The transfer processing device according to claim 1, wherein the transfer processing device is a data transfer device.

5. an operation instruction execution unit that acquires the operation instruction when the operation instruction is executable and executes the operation instruction, A transfer processing device according to any one of claims 1 to 4.

6. the operation instruction number acquisition circuit is configured to acquire the operation instruction number when the operation instruction execution unit cannot execute the operation instruction, and to output the acquired operation instruction number together with the operation instruction. The transfer processing device according to claim 5 .

7. The transfer information or the operation instruction includes a destination address, or the transfer information acquisition circuit is configured to output the destination address separately from the transfer information or the operation instruction; The destination address is an address of a memory to be accessed by a computing device that executes the computing instruction. A transfer processing device according to any one of claims 1 to 6.

Images