Low-Frequency Non-Separable Transform Signaling in Video Coding

Abstract

To provide a video processing method and a device for processing a video, used by a video encoder and decoder for processing an expression to be video coded by using control information which is useful for a decoding of an expression to be coated.SOLUTION: A method contains a step of executing a conversion between a video block of a video and a bit stream of the video. The video block uses a low-frequency non-separable conversion in a conversion. The bit stream is accordance with a format rule for regulating that a syntax element is contained in a syntax level in regard to a bit stream. The syntax element indicates whether or not a use of a scaling matrix introduced by a reference scaling list is in an enable in regard to the video block. The syntax level is a sequence level, a picture level, or a slice level.SELECTED DRAWING: Figure 12

Description

[Technical field]

[0001]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS Under applicable patent laws and / or regulations under the Paris Convention, this case is timely brought to claim priority to and the benefit of U.S. Provisional Patent Application No. 62 / 984,658, filed March 3, 2020. For all purposes under the law, the entire disclosure of the aforementioned application is incorporated by reference as part of the disclosure of this case.

[0002]

[0002] TECHNICAL FIELD This patent application relates to image and video coding and decoding. [Background technology]

[0003]

[0003] Digital video accounts for the largest bandwidth utilization in the Internet and other digital communications networks. It is expected that the bandwidth demands for digital video utilization will continue to increase as the number of connected user devices capable of receiving and displaying video increases. Summary of the Invention

[0004]

[0004] This specification discloses techniques that can be used by video encoders and decoders to process coded representations of video using control information useful for decoding the coded representations.

[0005] In one example aspect, a video processing method is disclosed that includes performing a conversion between a video block of a video and a bitstream of the video, where the bitstream complies with a format rule, the format rule specifying that a first syntax element is included in the bitstream at a video domain level indicating whether a scaling process is applied to transform coefficients or non-transform coefficients of the video block, where the video domain is smaller than a video picture of the video.

[0006]

[0006] In another exemplary aspect, a video processing method is disclosed, the method including performing a conversion between a video unit of a video domain of a video and a bitstream of the video, the bitstream conforming to a format rule, the format rule specifying that a first control information at a first level of the video domain in the bitstream indicates whether a second control information is included at a second level of the video unit in the bitstream, the first control information and / or the second control information including information regarding whether a scaling list is used for transform coefficients or for non-transform coefficients related to the transform.

[0007]

[0007] In another exemplary aspect, a video processing method is disclosed that includes performing a conversion between a video block of a video and a bitstream of the video, the video block using a low frequency non-separable transform for the conversion, the bitstream conforming to a format rule that specifies that a syntax element is included at a syntax level of the bitstream, the syntax element indicating whether use of a scaling matrix derived from a reference scaling list is enabled for the video block, the syntax level being a sequence level, a picture level, or a slice level.

[0008]

[0008] In another exemplary aspect, a video processing method is disclosed, the method comprising: determining to perform deblocking filtering on samples of the video unit along a boundary of the video unit using padded samples outside the boundary for conversion between a video unit of a video and a bitstream of the video; and performing the conversion according to the determination.

[0009]

[0009] In another exemplary aspect, a video processing method is disclosed, the method including performing a conversion between a video including one or more video pictures, each video picture including one or more tiles, and a coded representation of the video, the coded representation conforming to a format rule; the format rule specifying first information signaled in the coded representation and second information derived from the coded representation, at least the first information or the second information being related to a row index or a column index of the one or more tiles.

[0010]

[0010] In another exemplary aspect, a video processing method is disclosed. The method includes performing a conversion between a video unit of a video domain of a video and a coded representation of the video, the coded representation conforming to a format rule; the format rule specifies that a first control information in the video domain controls whether a second control information is included at a video unit level; the first control information and / or the second control information includes information on a luma mapping and chroma scaling (LMCS) or a chroma residual scaling (CRS) or a reshaping process (RP) used in the conversion.

[0011]

[0011] In yet another example, another video processing method is disclosed, the method including performing a conversion between a video including one or more video regions including one or more video units and a coded representation of the video; the coded representation conforms to a format rule; the format rule specifies that the coded representation includes two-level signaling of a scaling list usable for conversion of at least some of the video units, where a higher level of the two-level signaling at the video region level controls whether and where a lower level of the two-level signaling at the video unit level is included in the coded representation; and the scaling list includes information regarding a scaling used for conversion of at least some of the video units.

[0012] In yet another example, another video processing method is disclosed that includes determining a scaling list for a low frequency non-separable transform used to convert between a video unit of the video and a coded representation of the video; and performing the conversion based on the determination, where a syntax structure in the coded representation indicates whether the scaling list is enabled for the video unit.

[0013] In yet another example, a video encoder apparatus is disclosed, the video encoder comprising a processor configured to perform the method described above.

[0014]

[0014] In yet another exemplary aspect, a video decoder apparatus is disclosed, the video decoder comprising a processor configured to perform the method described above.

[0015] In yet another exemplary aspect, a computer readable medium having stored thereon code, the code embodying one of the methods described herein in the form of processor executable code, is disclosed.

[0016]

[0016] These and other features are described throughout this specification. [Brief description of the drawings]

[0017] [Figure 1]

[0017] Figure 1 shows an example of raster scan slice partitioning of a picture, where the picture is divided into 12 tiles and 3 raster scan slices. [Diagram 2]

[0018] Figure 2 shows an example of rectangular slice partitioning of a picture, where the picture is divided into 24 tiles (6 tile columns and 4 tile rows) and 9 rectangular slices. [Diagram 3]

[0019] FIG. 3 shows an example of a picture divided into tiles and rectangular slices, where the picture is divided into four tiles (two tile columns and two tile rows) and four rectangular slices. [Figure 4]

[0020] FIG. 4 shows a picture partitioned into 15 tiles, 24 slices, and 24 sub-pictures. [Diagram 5]

[0021] FIG. 5 is a block diagram of an exemplary video processing system. [Figure 6]

[0022] FIG. 6 is a block diagram of a video processing device. [Figure 7]

[0023] FIG. 7 is a flow chart of an exemplary method of video processing. [Figure 8]

[0024] FIG. 8 is a block diagram illustrating a video coding system according to some embodiments of the present disclosure. [Figure 9]

[0025] FIG. 9 is a block diagram illustrating an encoder according to some embodiments of the present disclosure. [Figure 10]

[0026] FIG. 10 is a block diagram illustrating a decoder according to some embodiments of the disclosure. [Figure 11]

[0027] Figure 11 shows an example of the padding process for deblocking filtering. [Figure 12]

[0028] FIG. 12 is a flow chart of an example method for video processing. [Figure 13] FIG. 13 is a flow chart of an example method of video processing. [Figure 14] FIG. 14 is a flow chart of an example method of video processing. [Figure 15] FIG. 15 is a flow chart of an example method of video processing. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018]

[0029] Section headings are used herein for ease of understanding, and do not limit the applicability of the techniques and embodiments disclosed in each section to that section alone. Furthermore, H.266 terminology is used in some descriptions only for ease of understanding, and not to limit the scope of the disclosed techniques. Thus, the techniques described herein are applicable to other video codec protocols and designs. In this specification, editorial changes relative to the current draft of the VVC specification are indicated as italicized text indicating canceled text (for convenience, indicated as text in <<< >>>) and bold italicized text indicating added text (for convenience, indicated as text in <<< >>>). Underline text (denoted as ).

[0019]

[0030] 1. Overview This invention relates to video coding technology. In particular, it relates to support for subpictures, LMCS, AMVR, and scaling lists. The subpicture aspects include deriving the number of rows and columns of tiles contained in a subpicture, and deriving a list of raster scan CTU addresses for CTUs contained in slices when each subpicture contains only one slice. The LMCS aspects relate to signaling the availability of LMCS at different levels. The AMVR aspects relate to the semantics of sps_affine_amvr_enabled_flag. The scaling list aspects relate to enabling the use of explicit scaling lists at various levels. The ideas may be applied individually or in various combinations to any video coding standard or non-standard video codec that supports single-layer and / or multi-layer video coding, such as the Versatile Video Coding (VVC) under development.

[0020] 2. Abbreviations ALF Adaptive Loop Filter AMVR Adaptive Motion Vector Difference Resolution APS Adaptive Parameter Set AU Access Unit AUD Access Unit Delimiter AVC Advanced Video Coding CLVS coded layered video sequence CPB Coded Picture Buffer CRA Clean Random Access CTU Coding Tree Unit CVS coded video sequences DPB Decoded Picture Buffer DPS Decoding Parameter Set EOB End of Bitstream EOS End of Sequence GDR Gradual Decoding Refresh HEVC High Efficiency Video Coding HRD Hypothesis Reference Decoder IDR Instant Decoding Refresh JEM Joint Exploration Model LFNST Low Frequency Non-separable Transformation LMCS Luma Mapping with Chroma Scaling MCTS Motion Constraint Tile Set NAL Network Abstraction Layer OLS Output Layer Set PH Picture Header PPS Picture Parameter Set PTL Profile, Tier & Level PU Picture Unit RBSP Raw Byte Sequence Payload SEI Supplemental Information SPS Sequence Parameter Set SVC Scalable Video Coding VCL Video Coding Layer VPS Video Parameter Set VTM VVC Test Model VUI Video Usage Information VVC Versatile Video Coding

[0031] 3. Introduction Video coding standards have evolved primarily through the development of well-known ITU-T and ISO / IEC standards. ITU-T created H.261 and H.263, ISO / IEC created MPEG-1 and MPEG-4 Visual, and the two organizations jointly created H.262 / MPEG-2 Video, H.264 / MPEG-4 Advanced Video Coding (AVC), and H.265 / HEVC standards. Since H.262, video coding standards have been based on a hybrid video coding structure, in which temporal prediction and transform coding are used. In 2015, the Joint Video Exploration Team (JVET) was jointly established by VCEG and MPEG to explore future video coding technologies beyond HEVC. Since then, many new methods have been adopted by JVET and put into reference software named the Joint Exploration Model (JEM). JVET meetings are held simultaneously once a quarter, and the new coding standard aims for a 50% bitrate reduction compared to HEVC. The new video coding standard was officially named Versatile Video Coding (VVC) at the April 2018 JVET meeting, and the first version of the VVC test model (VTM) was released at that time. As ongoing efforts are made to contribute to VVC standardization, new coding techniques are adopted into the VVC standard at each JVET meeting. The VVC working draft and test model VTM are updated after each meeting. The VVC project is currently aiming for technical completion (FDIS) at the July 2020 meeting.

[0021]

[0032] 3.1. Picture Partitioning Scheme in HEVC HEVC includes four different picture partitioning schemes, namely regular slice, dependent slice, tile, and Wavefront Parallel Processing (WPP), which can be applied for maximum transmission unit (MTU) size matching, parallel processing, and end-to-end delay reduction.

[0022]

[0033] Regular slices are similar to those in H.264 / AVC: each regular slice is encapsulated in its own NAL unit, and intra-picture prediction (intra-sample prediction, motion information prediction, coding mode prediction) and entropy coding dependencies across slice boundaries are disabled. Thus, regular slices can be reconstructed independently from other regular slices in the same picture (although interdependencies due to the loop filtering process may still exist).

[0023]

[0034] Regular slices are the only tool for parallelization available in H.264 / AVC in a virtually identical format. Parallelization based on regular slices does not require much inter-processor or inter-core communication (except for inter-processor or inter-core data sharing for motion compensation when decoding predictively coded pictures, which is typically much heavier than inter-processor or inter-core data sharing due to intra-picture prediction). However, for the same reasons, the use of regular slices can incur significant coding overhead due to the bit cost of slice headers and due to the lack of prediction across slice boundaries. Furthermore, regular slices (in contrast to the other tools mentioned below) also serve as the primary mechanism for bitstream partitioning to meet MTU size requirements due to the in-picture independence of regular slices and the fact that each regular slice is encapsulated in its own NAL unit. In many cases, the goals of parallelization and MTU size matching place conflicting demands on the slice layout in a picture. Recognition of this situation has led to the development of the parallelization tools described below.

[0024]

[0035] Dependent slices have short slice headers and allow for partitioning of the bitstream at treeblock boundaries without compromising any in-picture prediction. Essentially, dependent slices result in fragmentation of regular slices into multiple NAL units, resulting in reduced end-to-end delay, by allowing parts of a regular slice to be transmitted before the encoding of the entire regular slice is finished.

[0025]

[0036] In WPP, a picture is partitioned into single rows of coding tree blocks (CTBs). Entropy decoding and prediction are allowed to use data from CTBs of other partitions. Parallelism is made possible by parallel decoding of multiple CTB rows, where the start of decoding of one CTB row is delayed by two CTBs to ensure that the data related to the top and right of the target CTB is available before the target CTB is decoded. Using this staggered start (which looks like a wavefront when represented diagrammatically), parallelism is possible with as many processors / cores as the picture contains CTB rows. In-picture prediction between adjacent treeblock rows within a picture is allowed, so the inter-processor / inter-core communication required to enable in-picture prediction can be substantial. WPP partitioning does not result in the generation of additional NAL units compared to when it is not applied, so WPP is not a tool for MTU size matching. However, if MTU size matching is required, regular slices can be used with WPP, with some coding overhead.

[0026]

[0037] Tiles define horizontal and vertical boundaries that partition the picture into tile columns and rows. Tile columns go from the top of the picture to the bottom of the picture. Similarly, tile rows go from the left of the picture to the right of the picture. The number of tiles in a picture can be derived simply by multiplying the number of tile columns by the number of rows.

[0027]

[0038] The scan order of the CTBs is changed to be local within a tile (in the CTB raster scan order of the tile) before decoding the top-left CTB of the next tile in the picture tile raster scan order. As with regular slices, tiles break not only the entropy decoding dependency, but also the in-picture prediction dependency. However, they are not required to be contained in individual NAL units (similar to WPP in this respect); therefore tiles cannot be used for MTU size matching. Each tile can be processed by one processor / core, and the inter-processor / inter-core communication required for in-picture prediction between processing units decoding adjacent tiles is limited to conveying shared slice headers if the slice spans more than one tile and loop filtering related sharing of reconstructed samples and metadata. If more than one tile or WPP segment is included in a slice, the entry point byte offset for each tile or WPP segment in the slice, except for the first one, is signaled in the slice header.

[0028]

[0039] For simplicity, HEVC specifies restrictions on the application of four different picture partitioning schemes. A given coded video sequence cannot contain both tiles and wavefronts for most profiles specified in HEVC. For each slice and tile, one or both of the following conditions must be satisfied: 1) all coded treeblocks in a slice belong to the same tile; 2) all coded treeblocks in a tile belong to the same slice. Finally, a wavefront segment contains exactly one CTB row, and if WPP is used, if a slice starts in a CTB row, it must end in the same CTB row.

[0029]

[0040] The latest revisions to HEVC are specified in the following JCT-VC output document: JCTVC-AC1005, J. Boyce, A. Ramasubramonian, R. Skupin, GJ Sullivan, A. Tourapis, Y.-K. Wang (editors), "HEVC Additional Supplemental Enhancement Information (Draft 4)," Oct. 24, 2017, which is publicly available at: http: / / phenix.int-evry.fr / jct / doc_end_user / documents / 29_Macau / wg11 / JCTVC-AC1005-v2.zip Including this amendment, HEVC defines three MCTS-related SEI messages: a temporal MCTSs SEI message, an MCTSs extraction information sets SEI message, and an MCTSs extraction information nesting SEI message.

[0030]

[0041] The temporal MCTSs SEI message indicates the presence of MCTSs in the bitstream and signals the MCTSs. For each MCTS, motion vectors are restricted to point to full-sample locations within the MCTS and to fractional-sample locations that require only full-sample locations within the MCTS for interpolation, and the use of motion vector candidates for temporal motion vector prediction derived from blocks outside the MCTS is not allowed. In this way, each MCTS can be decoded independently, regardless of the presence of tiles not included in the MCTS.

[0031]

[0042] The MCTS Extraction Information Set SEI message provides supplemental information that can be used during MCTS sub-bitstream extraction (specified as part of the semantics of the SEI message) to generate a conforming bitstream for an MCTS set. The information consists of multiple extraction information sets, each of which defines multiple MCTS sets and includes the RBSP bytes of the alternative VPS, SPS and PPS used during the MCTS sub-bitstream extraction process. When extracting a sub-bitstream according to the MCTS sub-bitstream extraction process, the parameter sets (VPSs, SPSs and PPSs) need to be rewritten or replaced and the slice header needs to be slightly updated, because all or any of the slice address related syntax elements (including irst_slice_segment_in_pic_flag and slice_segment_address) typically need to have different values.

[0032]

[0043] 3.2. Picture Partitioning in VVC In VVC, a picture is divided into one or more tile rows and one or more tile columns. A tile is a set of CTUs that cover a rectangular area of ​​the picture. The CTUs within a tile are scanned in raster-scan order within that tile.

[0033]

[0041] A slice consists of an integer number of complete tiles, or an integer number of consecutive complete CTU rows within a tile of a picture.

[0034]

[0045] Two slice modes are supported: raster scan slice mode and rectangular slice mode. In raster scan slice mode, a slice contains a set of complete tiles in the tiled raster scan of the picture. In rectangular slice mode, a slice contains either a number of complete tiles that collectively form a rectangular area of ​​the picture, or a number of contiguous complete CTU rows of one tile that collectively form a rectangular area of ​​the picture. The tiles in a rectangular slice are scanned in tiled raster scan order within the rectangular area corresponding to the slice.

[0035]

[0046] A subpicture contains one or more slices that together cover a rectangular area of ​​the picture.

[0036]

[0047] Figure 1 shows an example of raster scan slice partitioning of a picture, where the picture is divided into 12 tiles and 3 raster scan slices.

[0037]

[0048] Figure 2 shows an example of rectangular slice partitioning of a picture, where the picture is divided into 24 tiles (6 tile columns and 4 tile rows) and 9 rectangular slices.

[0038]

[0049] FIG. 3 shows an example of a picture partitioned into multiple tiles and rectangular slices, where the picture is divided into four tiles (two tile rows and two tile columns) and four rectangular slices.

[0039]

[0050] Figure 4 shows an example of subpicture partitioning of a picture, where the picture is partitioned into 18 tiles, 12 on the left covering one slice of 4x4 CTU each, and 6 on the right covering two vertically stacked slices of 2x2 CTU each, resulting in a total of 24 slices of varying dimensions and 24 subpictures (each slice is a subpicture). 3.3 Signaling of SPS / PPS / Picture Header / Slice Header in VVC (as JVET-Q2001-vC) 7.3.2.3 Sequence Parameter Set RBSP Syntax

[0040]

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[0041]

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[0042]

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[0043]

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[0044]

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[0045]

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[0046]

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[0047]

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[0048]

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[0049]

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[0050]

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[0051]

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[0052]

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[0053]

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[0054]

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[0000] is inferred to be equal to PicWidthInCtbsY - 1. tile_row_height_minus1[ i ] plus 1 indicates the height of the i-th tile row in CTB units, for i in the range 0 to num_exp_tile_rows_minus1 - 1, inclusive. tile_row_height_minus1[ num_exp_tile_rows_minus1 ] is used to derive the height of tile rows with index greater than or equal to num_exp_tile_rows_minus1 as specified in Clause 6.5.1. The value of tile_row_height_minus1[ i ] shall be in the range 0 to PicHeightInCtbsY - 1, inclusive. If not present, the value of tile_row_height_minus1

[0000] is inferred to be equal to PicHeightInCtbsY - 1. rect_slice_flag equal to 0 specifies that the tiles within each slice are in raster scan order and slice information is not signaled in the PPS. rect_slice_flag equal to 1 specifies that the tiles within each slice cover a rectangular region of the picture and slice information is signaled in the PPS. If not present, rect_slice_flag is inferred to be equal to 1. If subpic_info_present_flag is equal to 1, the value of rect_slice_flag shall be equal to 1. single_slice_per_subpic_flag equal to 1 indicates that each subpicture consists of one and only one rectangular slice. single_slice_per_subpic_flag equal to 0 indicates that each subpicture may consist of one or more rectangular slices. If single_slice_per_subpic_flag is equal to 1, num_slices_in_pic_minus1 is inferred to be equal to sps_num_subpics_minus1. If not present, the value of single_slice_per_subpic_flag is inferred to be equal to 0. [ED.(GJS): Consider renaming or otherwise clarifying this flag if more than one subpicture exists in each picture to avoid interpretation that only this flag is relevant.] num_slices_in_pic_minus1 plus 1 indicates the number of rectangular slices in each picture that references the PPS. The value of num_slices_in_pic_minus1 shall be in the range of 0 to MaxSlicesPerPicture - 1, inclusive, where MaxSlicesPerPicture is specified in Annex A. If no_pic_partition_flag is equal to 1, the value of num_slices_in_pic_minus1 is inferred to be equal to 0. A tile_idx_delta_present_flag equal to 0 indicates that no value of tile_idx_delta is present in the PPS, and all rectangular slices in the picture that reference the PPS are specified in raster order according to the process specified in clause 6.5.1. [Ed.(RS):Mathematical Reference Added] A tile_idx_delta_present_flag equal to 1 indicates that a value of tile_idx_delta may be present in the PPS, and all rectangular slices in the picture that reference the PPS are specified in the order indicated by the value of tile_idx_delta. If not present, the value of tile_idx_delta_present_flag is inferred to be 0. slice_width_in_tiles_minus1[ i ] plus 1 specifies the width of the i-th rectangular slice in units of tile columns. The value of slice_width_in_tiles_minus1[ i ] shall be in the range 0 to NumTileColumns-1, inclusive. If slice_width_in_tiles_minus1[ i ] is not present, the following applies: - If NumTileColumns is equal to 1, the value of slice_width_in_tiles_minus1[ i ] is inferred to be equal to 0. - Otherwise, the value of slice_width_in_tiles_minus1[ i ] is inferred as specified in Clause 6.5.1. [Ed.(RS):Mathematical reference added] slice_height_in_tiles_minus1[ i ] plus 1 specifies the height of the i-th rectangular slice, in rows. The value of slice_height_in_tiles_minus1[ i ] shall be in the range 0 to NumTileRows-1, inclusive. If slice_height_in_tiles_minus1[ i ] is not present, the following applies: - If NumTileRows is equal to 1 or tile_idx_delta_present_flag is equal to 0 and tileIdx % NumTileColumns is greater than 0, the value of slice_height_in_tiles_minus1[ i ] is inferred to be equal to 0. - Otherwise (if NumTileRows is not equal to 1 and tile_idx_delta_present_flag is equal to 1 or tileIdx % NumTileColumns is equal to 0), if tile_idx_delta_present_flag is equal to 1 or tileIdx % NumTileColumns is equal to 0, the value of slice_height_in_tiles_minus1[ i ] is inferred to be equal to slice_height_in_tiles_minus1[ i - 1 ]. num_exp_slices_in_tile[ i ] specifies the number of explicit slices for a given slice height in the current tile that contains more than one rectangular slice. num_exp_slices_in_tile[ i ] shall be in the range from 0 to RowHeight[ tileY ] - 1, inclusive, where tileY is the tile row index containing the i-th slice. If not present, the value of num_exp_slices_in_tile[ i ] is inferred to be equal to 0. If num_exp_slices_in_tile[ i ] is equal to 0, the value of the variable NumSlicesInTile[ i ] is derived to be equal to 1. exp_slice_height_in_ctus_minus1[ j ] plus 1 specifies the height of the jth rectangular slice in the current tile in units of CTU rows. The value of exp_slice_height_in_ctus_minus1[ j ] shall be in the range 0 to RowHeight[ tileY ] - 1, inclusive, where tileY is the row index of the current tile. If num_exp_slices_in_tile[ i ] is greater than 0, then the variables NumSlicesInTile[ i ] and SliceHeightInCtusMinus1[ i + k ], for k in the range from 0 to NumSlicesInTile[ i ] - 1, are derived as follows:

[0055]

number

[0056] - subpicIdxA is equal to subpicIdxB, and sliceAddrA is less than sliceAddrB. 7.4.8.1 General slice header semantics The variable CuQpDeltaVal indicates the difference between the luma quantization parameter of the coding unit containing cu_qp_delta_abs and its prediction, and is set equal to 0. Cb , CuQpOffset Cr , and CuQpOffset CbCr Qp' for a coding unit that includes cu_chroma_qp_offset_flag Cb , Qp' Cr , and Qp' CbCr These are used in determining the individual values ​​of the quantization parameters, which are all set equal to zero. picture_header_in_slice_header_flag equal to 1 indicates that the PH syntax structure is present in the slice header. picture_header_in_slice_header_flag equal to 0 indicates that the PH syntax structure is not present in the slice header. It is a bitstream conformance requirement that the value of picture_header_in_slice_header_flag shall be the same among all coded slices in the CLVS. It is a bitstream conformance requirement that if picture_header_in_slice_header_flag is equal to 1 for a coded slice, no VCL NAL units with nal_unit_type equal to PH_NUT shall be present in the CLVS. If picture_header_in_slice_header_flag is equal to 0, all coded slices in the current picture shall have picture_header_in_slice_header_flag equal to 0 and the current PU shall have a PH NAL unit. slice_subpic_id indicates the subpicture ID of the subpicture that contains the slice. If slice_subpic_id is present, the value of the variable CurrSubpicIdx is derived such that SubpicIdVal[ CurrSubpicIdx ] is equal to slice_subpic_id. Otherwise (if slice_subpic_id is not present), CurrSubpicIdx is derived equal to 0. The length of slice_subpic_id is sps_subpic_id_len_minus1 + 1 bits. slice_address indicates the slice address of the slice. If not present, the value of slice_address is inferred to be equal to 0. If rect_slice_flag is equal to 1 and NumSlicesInSubpic[CurrSubpicIdx] is equal to 1, the value of slice_address is inferred to be equal to 0. If rect_slice_flag is equal to 0, the following applies: - A slice address is a raster scan tile index. - The length of slice_address is Ceil( Log2 ( NumTilesInPic ) ) bits. - The value of slice_address shall be in the range from 0 to NumTilesInPic - 1, inclusive. Otherwise (rect_slice_flag is equal to 1), the following applies: - The slice address is the subpicture level slice index of the slice. - The length of slice_address is Ceil( Log2( NumSlicesInSubpic[ CurrSubpicIdx ] ) ) bits. - The value of slice_address shall be in the range from 0 to NumSlicesInSubpic[CurrSubpicIdx] - 1, inclusive. It is a requirement of bitstream conformance that the following constraints apply: - If rect_slice_flag is equal to 0 or subpic_info_present_flag is equal to 0, the value of slice_address shall not be equal to the value of slice_address of any other coded slice NAL unit of the same coded picture. - Otherwise, the value pair of slice_subpic_id and slice_address shall not be equal to the value pair of slice_subpic_id and slice_address of any other coded slice NAL unit of the same coded picture. - The shape of the slices of the picture is such that each CTU, when decoded, has an entire left-boundary and an entire top-boundary that consist of either the picture boundary or the boundary of a previously decoded CTU. sh_extra_bit[ i ] may be equal to 1 or 0. Decoders conforming to this version of this specification MUST ignore the value of sh_extra_bit[ i ] as it does not affect the decoder's conformance to the profile specified in this version of the specification. num_tiles_in_slice_minus1 plus 1, if present, indicates the number of tiles in the slice. The value of num_tiles_in_slice_minus1 shall be in the range 0 to NumTilesInPic - 1, inclusive. The variable NumCtusInCurrSlice, which specifies the number of CTUs in the current slice, and the list CtbAddrInCurrSlice[ i ], for i ranging from 0 to NumCtusInCurrSlice - 1, inclusive, which specifies the picture raster scan address of the ith CTB in the slice, are derived as follows:

[0057]

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[0058]

number

[0051] LMCS includes two aspects: luma mapping (reshaping process, denoted as RP) and luma-dependent chroma residual scaling (CRS). For the luma signal, the LMCS mode operates based on two domains involved, including a first domain, which is the original domain, and a second domain, which is the reshaped domain, which maps the luma samples to specific values ​​according to a reshaping model. Furthermore, for the chroma signal, residual scaling may be applied, where the scaling coefficients are derived from the luma samples.

[0059]

[0052] The relevant syntax elements and semantics in the SPS, picture header (PH), and slice header (SH) are described as follows: Syntax Table 7.3.2.3 Sequence Parameter Set RBSP Syntax

[0060]

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[0061]

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[0062] 3.6. Adaptive Motion Vector Difference Resolution (AMVR) for Afine-Coded Blocks Affine AMVR is a coding tool that allows affine inter-coded blocks to transmit MV differentials at various resolutions, e.g., with a precision of 1 / 4 luma sample (by default, amvr_flag is set to 0), 1 / 61 luma sample, 1 luma sample.

[0063]

[0054] The relevant syntax elements and semantics of the SPS are described as follows: Syntax Table 7.3.2.3 Sequence Parameter Set RBSP Syntax

[0064]

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[0065]

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[0066]

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[0067]

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[0068]

number

[0000] - AuNominalRemovalTime

[0000] ) * RefLevelFraction[ i ][ j ] ) ÷ ( 256 * MinCr ), with respect to the value of SubpicSizeInSamplesY of AU 0, where MaxLumaSr and FormatCapabilityFactor are the same as the size of the AU at level ref_level_idc[ i ], 0, and MinCr is derived as shown in A.4.2 [Ed.(RS):fR is a profile-specific variable specified in A.4.2]. - the sum of NumBytesInNalUnit variables for AU n (greater than 0) corresponding to the jth subpicture shall be less than or equal to FormatCapabilityFactor * MaxLumaSr * ( AuCpbRemovalTime[ n ] - AuCpbRemovalTime[ n - 1 ] ) * RefLevelFraction[ i ][ j ] ÷ ( 256 * MinCr ), where MaxLumaSr and FormatCapabilityFactor are the values ​​specified in Tables A.2 and A.3, respectively, for AU n at level ref_level_idc[ i ], and MinCr is derived as specified in A.4.2. For any subpicture set that includes one or more subpictures and is composed of the list of subpicture indices SubpicSetIndices, and a number of subpictures in the subpicture set NumSubpicsInSet, the subpicture set level information is derived. The variable SubpicSetAccLevelFraction[ i ] for the total level fraction with respect to the reference level ref_level_idc[ i ] and the subpicture set variables SubpicSetCpbSizeVcl[ i ], SubpicSetCpbSizeNal[ i ], SubpicSetBitRateVcl[ i ], and SubpicSetBitRateNal[ i ] are derived as follows:

[0069]

number

[0070]

number

[0071]

number

[0072]

number

[0073]

number

[0074] - ph_scaling_list_present_flag is equal to 0.

[0075] - transform_skip_flag[xTbY][yTbY][cIdx] equal to 1.

[0076] -scaling_matrix_for_lfnst_disabled_flag is equal to 1 and ApplyLfnstFlag is equal to 1.

[0077] - ... 7.3.2.5 Adaptation Parameter Set RBSP Syntax

[0078]

number

[0079]

number

[0055] The existing design of sub-picture and LMCS in VVC has the following problems: 1) The derivation of the list SubpicNumTileRows[] (which specifies the number of tile rows contained in a subpicture), as in formula D.5, is incorrect because the index value idx of CtbToTileRowBd[idx] in the formula can be greater than the maximum allowed value. Furthermore, the derivation of both SubpicNumTileRows[] and SubpicNumTileCols[] (which specifies the number of tile columns contained in a subpicture) uses CTU-based arithmetic, which is unnecessarily complex.

[0080] 2) Deriving the array CtbAddrInSlice in Equation 29 is not correct when single_slice_per_subpic_flag is equal to 1 because the values ​​of the raster scan CTB addresses in the array for each slice need to be in the decoding order of the CTU, not the raster scan order of the CTU.

[0081] 3) LMCS signaling is inefficient. In most cases, LMCS is enabled for all slices of a picture when ph_lmcs_enabled_flag is equal to 1. However, in the current VVC design, in the case where LMCS is enabled for all slices of a picture, not only does ph_lmcs_enabled_flag equal to 1, but slice_lmcs_enabled_flag with value 1 also needs to be signaled for each slice.

[0082] a. The semantics of ph_lmcs_enabled_flag conflict with the trend to signal a slice level LMCS flag when ph_lmcs_enabled_flag is true. In the current VVC, when ph_lmcs_enabled_flag is true, it means that all slices shall have LMCS enabled. Therefore, there is no need to further signal the LMCS enabling flag in the slice header.

[0083] b. Additionally, if the picture header signals that LMCS is enabled, then typically LMCS is enabled for all slices. The control of LMCS in the slice header is primarily to handle corner cases. Thus, if the PH LMCS flag was true and the SH LMCS flag was always signaled, it could result in unnecessary bits being signaled for the general use case.

[0084] 4) The semantics of the SPS affine AMVR flag is not correct because for each affine inter-coded CU, affine AMVR may be enabled or disabled.

[0085] 5) The scaling list flag in the slice header, i.e., slice_scaling_list_present_flag, is not used to control the scaling process of the transform coefficients and is practically useless.

[0086] 6) Scaling list signaling is inefficient even when slice_scaling_list_present_flag is used to control the scaling process of transform coefficients. When ph_scaling_list_present_flag is equal to 1, in most cases, explicit scaling lists are used for all slices of a picture. However, the current VVC design not only requires that ph_scaling_list_present_flag be equal to 1, but also requires that a slice flag slice_scaling_list_present_flag with value 1 be signaled for each slice if explicit scaling lists are enabled for all slices of a picture.

[0087] 7) For LFNST coded blocks, the residual distribution may differ from the case where only the primary transform is applied. There is a higher probability that the explicitly signaled scaling list is not applied to those LFNST coded blocks. However, whether it is acceptable to apply the explicitly signaled scaling list is signaled in the APS, and this may waste unnecessary bits. 1. Illustrative Examples and Embodiments In order to solve the above problems and some other problems not mentioned, the methods summarized below are disclosed. The items should be considered as examples to explain the general concept and should not be interpreted in a narrow sense. Moreover, these items can be applied individually or in any combination.

[0088] Related to subpictures to solve the first and second problems 1. One or more of the following approaches are disclosed: a. The tile column index for each CTU column of the picture is derived.

[0089] b. The derivation of the number of tile columns contained in a sub-picture is based on the tile column indexes of the leftmost and / or rightmost CTUs contained in the sub-picture.

[0090] c. The tile row index for each CTU row of the picture is derived.

[0091] d. The derivation of the number of tile rows contained in the sub-picture is based on the tile row indexes of the top and / or bottom CTUs contained in the sub-picture.

[0092] e. The term picture-level slice index is defined as follows: The index is for a slice defined when rect_slice_flag is equal to 1 and refers to the list of slices of a picture in the order in which the slices are signaled in the PPS when single_slice_per_subpic_flag is equal to 0, or in the order of increasing subpicture index of the subpicture corresponding to the slice when single_slice_per_subpic_flag is equal to 1.

[0093] f. In one example, if a subpicture contains slices partitioned from tiles, the height of the subpicture cannot be counted in terms of tiles.

[0094] g. In one example, the height of a subpicture can be counted in terms of CTUs rather than tiles.

[0095] h. It is derived if the subpicture height is less than one tile row.

[0096] i. In one example, whether the height of a subpicture is less than one tile row is derived to be true if the subpicture only contains CTUs from one tile row, and the top CTU of the subpicture is not the top CTU of the tile row, or the bottom CTU of the subpicture is not the bottom CTU of the tile row.

[0097] ii. If each subpicture contains only one slice and the subpicture height is indicated to be less than one tile row, then for each slice with picture-level slice index i of the picture, for j in the range from 0 to the number of CTUs in the slice minus 1, inclusive, the value of CtbAddrInSlice[ i ][ j ] is derived to be the picture raster scan CTU address of the jth CTU in the subpicture's CTU raster scan.

[0098] iii. In one example, whether the height of the subpicture is less than one tile row is derived to be true if the distance between the subpicture top CTU and the subpicture bottom CTU is less than the height of the tile for the CTU.

[0099] iv. If each subpicture contains only one slice and the height of the subpicture is indicated to be at least one tile row, then for each slice with picture-level slice index i of the picture, for j in the range from 0 to the number of CTUs in the slice minus 1, inclusive, the value of CtbAddrInSlice[ i ][ j ] is derived to be the picture raster scan CTU address of the jth CTU in the following CTU ordering: 1) The CTUs of the various tiles in a subpicture are ordered such that the first CTU in the first tile with a lower tile index value precedes the second CTU in the second tile with a higher tile index value.

[0100] 2) The CTUs within a tile of a subpicture are ordered by a raster scan of the CTUs of the tile. Related to LMCS to solve the third problem (including sub-problems) 2. A two-level control of LMCS is introduced (including two aspects: luma mapping (a reshaping process denoted by RP) and luma-dependent chroma residual scaling (CRS)), where high-level (e.g., picture-level) and low-level (e.g., slice-level) control are used, and the presence of low-level control information depends on the high-level control information. In addition, the following applies: a. In the first example, one or more of the following subsections apply: i. The first indicator (e.g., ph_lmcs_enabled_type) is signaled at a higher level (e.g., in the picture header (PH)) and may specify how LMCS is enabled at a lower level, which is a non-binary value.

[0101] 1) In one example, when the first indicator is equal to X (e.g., X = 2), it specifies that LMCS is enabled for all slices associated with the PH; when the first indicator is equal to Y (Y! = X) (e.g., Y = 1), it specifies that LMCS is enabled for one or more slices, but not all, associated with the PH; when the first indicator is equal to Z (Z! = X and Z! = Y) (e.g., Z = 0), it specifies that LMCS is disabled for all slices associated with the PH.

[0102] a) Alternatively, further, if the first indicator is not present, the value of the indicator is presumed to be equal to a default value, such as Z.

[0103] 2) In one example, when the first indicator is equal to X (e.g., X = 2), it specifies that LMCS is disabled for all slices associated with the PH; when the first indicator is equal to Y (Y! = X) (e.g., Y = 1), it specifies that LMCS is disabled for one or more slices, but not all, associated with the PH; when the first indicator is equal to Z (Z! = X and Z! = Y) (e.g., Z = 0), it specifies that LMCS is enabled for all slices associated with the PH.

[0104] a) Alternatively, further, if the first indicator is not present, the value of the indicator is presumed to be equal to a default value, such as X.

[0105] 3) Alternatively, in addition, the first indicator may be conditionally signaled according to the value of an LMCS enabling flag at the sequence level (eg, sps_lmcs_enabled_flag).

[0106] 4) Alternatively, the first indicator may also be coded with u(v) or u(2) or ue(v).

[0107] 5) Alternatively, further, the first indicator may be coded with a truncated unary code.

[0108] 6) Alternatively, further LMCS APS information (eg, ph_lmcs_aps_id) used by the slice and / or CS enabling flags (eg, ph_chroma_residual_scale_flag) may be signaled under conditional checking of the value of the first indicator.

[0109] ii. A second indicator (e.g., slice_lmcs_enabled_flag) to enable / disable LMCS at a lower level can be signaled at a lower level (e.g., in the slice header), and it can be signaled conditionally by checking the value of the first indicator.

[0110] 1) In one example, the second indicator may be signaled under the condition check that "the first indicator is equal to Y."

[0111] a) Alternatively, the second indicator may be signaled under the condition check of "value of first indicator >> 1" or "value of first indicator / 2" or "value of first indicator & 0x01".

[0112] b) Alternatively, further, if the first indicator is equal to X, it may be presumed to be enabled; or if the first indicator is equal to Z, it may be presumed to be disabled.

[0113] b. In the second example, one or more of the following subsections apply: i. More than one indicator may be signaled and may be signaled at a higher level (e.g., in the Picture Header (PH)) to specify how LMCS is enabled at a lower level.

[0114] 1) In one example, two indicators (eg, two 1-bit flags) may be signaled in the PH.

[0115] a) In one example, the first indicator specifies whether at least one slice associated with the PH enables LMCS, and the second indicator specifies whether all slices associated with the PH enable LMCS.

[0116] i. Alternatively, further, the second indicator may be signaled conditionally according to the value of the first indicator, for example, if the first indicator specifies the presence of at least one slice that enables LMCS.

[0117] i. Alternatively, further, if the second indicator is not present, it is presumed that all slices have LMCS enabled.

[0118] ii. Alternatively, the third indicator may also be conditionally signaled in the SH according to the value of the second indicator, for example if the second indicator specifies that not all of the slices have LMCS enabled.

[0119] i. Alternatively, further, if the third indicator is not present, it may be estimated according to the value of the first and / or second indicator (e.g., estimated to be equal to the value of the first indicator).

[0120] b) Alternatively, the first indicator specifies whether at least one slice associated with the PH has LMCS disabled, and the second indicator specifies whether all slices associated with the PH have LMCS disabled.

[0121] i. Alternatively, further, the second indicator may be signaled conditionally according to the value of the first indicator, for example, if the first indicator specifies the presence of at least one slice for which LMCS is disabled.

[0122] i. Alternatively, further, if the second indicator is not present, it is presumed that all slices associated with the PH have LMCS enabled.

[0123] ii. Alternatively, the third indicator may also be conditionally signaled in the SH according to the value of the second indicator, for example if the second indicator specifies that not all of the slices have LMCS enabled.

[0124] i. Alternatively, further, if the third indicator is not present, it may be estimated according to the value of the first and / or second indicator (e.g., estimated to be equal to the value of the first indicator).

[0125] 2) Alternatively, in addition, the first indicator may be conditionally signaled according to the value of an LMCS enabling flag at the sequence level (eg, sps_lmcs_enabled_flag).

[0126] ii. A third indicator (e.g., slice_lmcs_enabled_flag) to enable / disable LMCS at a lower level can be signaled at a lower level (e.g., in the slice header), and it can be signaled conditionally by checking the value of the first indicator and / or the second indicator.

[0127] 1) In one example, the third indicator may be signaled under the condition check of "not all slices enable LMCS" or "not all slices disable LMCS".

[0128] c. In yet another example, the first and / or second and / or third indicators mentioned in the first / second examples may be used to control the use of the RP or CRS instead of the LMCS.

[0129] 3. The semantics of the three LMCS flags SPS / PH / SH are updated as follows: sps_lmcs_enabled_flag equal to 1 indicates that luma mapping with chroma scaling is <<<used>>> in CLVS. May be used sps_lmcs_enabled_flag equal to 0 specifies that luma mapping with chroma scaling is not used in CLVS.

[0130] ph_lmcs_enabled_flag equal to 1 means that luma mapping with chroma scaling is <<<enabled>>> for all slices associated with PH. May be enabled ph_lmcs_enabled_flag equal to 0 indicates that luma mapping with chroma scaling may be disabled for one, multiple, or all slices associated with the PH. Disabled for all slices If not present, the value of ph_lmcs_enabled_flag is inferred to be equal to 0.

[0131] slice_lmcs_enabled_flag equal to 1 means that luma mapping with chroma scaling is <<<enabled>>> for the current slice. useslice_lmcs_enabled_flag equal to 0 indicates that luma mapping with chroma scaling is <<<enabled>>> for the current slice. use If slice_lmcs_enabled_flag is not present, it is inferred to be equal to 0.

[0132] a. The PH and / or SH LMCS signaling is modified such that if LMCS is used for all slices of a picture, then no LMCS signaling is present in the SH.

[0133] i. Alternatively, further, how the LMCS is estimated depends on the PH LMCS signaling.

[0134] 1) In one example, if LMCS is used for all slices of a picture, it is presumed to be enabled; if LMCS is not used for all slices of a picture, it is presumed to be disabled. Related to Affine AMVR 4. The semantics of the affine AMVR flag in SPS is updated as follows: sps_affine_amvr_enabled_flag equal to 1 indicates that adaptive motion vector difference resolution is used in affine inter mode motion vector coding. Good sps_affine_amvr_enabled_flag equal to 0 indicates that adaptive motion vector difference resolution is not used in affine inter mode motion vector coding. If not present, the value of sps_affine_amvr_enabled_flag is inferred to be equal to 0. Related to the scaling list for solving the fifth and sixth problems 5. For blocks, the scaling process of the transform coefficients and / or non-transform coefficients is controlled according to syntax elements related to regions of video smaller than a picture, such as slices.

[0135] a. In one example, instead of using the SPS flag sps_scaling_list_enabled_flag and the PH flag ph_scaling_list_present_flag to control the scaling process of the transform coefficients, a scaling list flag in the slice header, e.g., slice_scaling_list_present_flag, is used, e.g., as in embodiment 3.

[0136] 6. A two-level control of explicit scaling lists is introduced, where high-level (e.g. picture-level) control and low-level (e.g. slice-level) control are used, and the presence of low-level control information depends on the high-level control information. Explicit scaling lists can be used in the scaling process of transform coefficients and / or non-transform coefficients. In addition, the following applies: a. In the first example, one or more of the following subsections apply: i. A first non-binary indicator (e.g., ph_explicit_scaling_list_enabled_type) may be signaled at a higher level (e.g., in the picture header (PH)) to specify how explicit scaling lists are enabled at the lower level.

[0137] 1) In one example, when the first indicator is equal to X (e.g., X = 2), it specifies that the explicit scaling list is enabled for all slices associated with the PH; when the first indicator is equal to Y (Y! = X) (e.g., Y = 1), it specifies that the explicit scaling list is enabled for one or more, but not all, slices associated with the PH; when the first indicator is equal to Z (Z! = X and Z! = Y) (e.g., Z = 0), it specifies that the explicit scaling list is disabled for all slices associated with the PH.

[0138] a) Alternatively, further, if the first indicator is not present, the value of the indicator is presumed to be equal to a default value, such as Z.

[0139] b) Alternatively, if the first indicator is further equal to Y (Y!=X) (e.g., Y=1), it specifies that the use of an explicit scaling list in the scaling process of transform coefficients and / or non-transform coefficients when decoding a slice is enabled for the picture.

[0140] c) Alternatively, if the first indicator is equal to Y (Y!=X) (e.g., Y=1), it specifies that the use of explicit scaling lists in the scaling process of transform coefficients and / or non-transform coefficients when decoding a slice may be enabled for the picture.

[0141] 2) In one example, when the first indicator is equal to X (e.g., X = 2), it specifies that the explicit scaling list is disabled for all slices associated with the PH; when the first indicator is equal to Y (Y! = X) (e.g., Y = 1), it specifies that the explicit scaling list is enabled for one or more, but not all, slices associated with the PH; when the first indicator is equal to Z (Z! = X and Z! = Y) (e.g., Z = 0), it specifies that the explicit scaling list is enabled for all slices associated with the PH.

[0142] a) Alternatively, further, if the first indicator is not present, the value of the indicator is presumed to be equal to a default value, such as X.

[0143] b) Alternatively, if the first indicator is equal to Y (Y != X) (e.g., Y=1), it specifies that the use of explicit scaling lists in the scaling process of transform coefficients and / or non-transform coefficients when decoding a slice may be disabled for the picture.

[0144] c) Alternatively, if the first indicator is equal to Y (Y!=X) (e.g., Y=1), it specifies that the use of explicit scaling lists in the scaling process of transform coefficients and / or non-transform coefficients when decoding a slice is disabled for the picture.

[0145] 3) Alternatively, in addition, the first indicator may be conditionally signaled according to the value of an explicit scaling list enabling flag at the sequence level (eg, sps_explicit_scaling_list_enabled_flag).

[0146] 4) Alternatively, the first indicator may also be coded with u(v) or u(2) or ue(v).

[0147] 5) Alternatively, the first indicator may also be coded with a truncated unary code.

[0148] 6) Alternatively, further scaling list APS (eg, ph_explicit_scaling_list_aps_id) used by the slice may be signaled under conditional checking of the value of the first indicator.

[0149] ii. A second indicator (e.g., slice_scaling_list_present_flag) to enable / disable the lower level explicit scaling list can be signaled at a lower level (e.g., in the slice header), and it can be signaled conditionally by checking the value of the first indicator.

[0150] 1) In one example, the second indicator may be signaled under the condition check that "the first indicator is equal to Y."

[0151] a) Alternatively, the second indicator may be signaled under the condition check of "value of first indicator >> 1" or "value of first indicator / 2" or "value of first indicator & 0x01".

[0152] b) Alternatively, further, the second indicator may be absent and it may be presumed to be enabled if the first indicator is equal to X; or it may be presumed to be disabled if the first indicator is equal to Z.

[0153] b. In the second example, one or more of the following subsections apply: i. More than one indicator may be signaled at a higher level (e.g., in the Picture Header (PH)) to specify how explicit scaling lists are enabled at lower levels.

[0154] 1) In one example, two indicators (eg, two 1-bit flags) may be signaled in the PH.

[0155] a) In one example, a first indicator specifies whether at least one slice associated with the PH has an explicit scaling list enabled, and a second indicator specifies whether all slices associated with the PH have the scaling list enabled.

[0156] i. Alternatively, further, the second indicator may be signaled conditionally according to the value of the first indicator, for example, if the first indicator specifies the presence of at least one slice that enables an explicit scaling list.

[0157] i. Alternatively, further, if the second indicator is not present, it is presumed that all slices have the explicit signaling list enabled.

[0158] ii. Alternatively, it may be required that if the first indicator is false in a conformance bitstream, then the second indicator must be false.

[0159] ii. Alternatively, the third indicator may also be signaled conditionally according to at least one of the value of the first indicator and the value of the second indicator, e.g., when the first indicator specifies that at least one slice has explicit scaling list enabled and the second indicator specifies that not all slices have explicit scaling list enabled.

[0160] i. Alternatively, further, if the third indicator is not present, it may be estimated according to the value of the first and / or second indicator (e.g., estimated to be equal to the value of the first indicator).

[0161] b) Alternatively, the first indicator specifies whether at least one slice associated with the PH has the explicit scaling list disabled, and the second indicator specifies whether all slices associated with the PH have the explicit scaling list disabled.

[0162] i. Alternatively, further, the second indicator may be signaled conditionally according to the value of the first indicator, for example, if the first indicator specifies the presence of at least one slice that disables the explicit scaling list.

[0163] i. Alternatively, further, if the second indicator is not present, all slices associated with the PH are presumed to have the explicit scaling list disabled.

[0164] ii. Alternatively, further, the third indicator may be conditionally signaled in the SH according to at least one of the value of the first indicator and the value of the second indicator, e.g., when the first indicator specifies that at least one slice has explicit scaling list enabled and the second indicator specifies that not all slices have explicit scaling list disabled.

[0165] i. Alternatively, further, if the third indicator is not present, it may be estimated according to the value of the first and / or second indicator (e.g., estimated to be equal to the value of the first indicator).

[0166] 2) Alternatively, in addition, the first indicator may be conditionally signaled according to the value of an explicit scaling list enabling flag at the sequence level (eg, sps_explicit_scaling_list_enabled_flag).

[0167] iv. A third indicator (e.g., slice_explicit_scaling_list_enabled_flag) to enable / disable the lower level explicit scaling list can be signaled at a lower level (e.g., in the slice header), and it can be signaled conditionally by checking the value of the first indicator and / or the second indicator.

[0168] 1) In one example, the third indicator may be signaled under the condition check that "not all slices enable the explicit scaling list" or "not all slices disable the explicit signaling list".

[0169] c. In a third example, two 1-bit flags are signaled at a higher level (e.g., in the picture header (PH)) to specify how explicit scaling lists are enabled at a lower level (e.g., in the slice header (SH)).

[0170] i. The first PH flag (e.g., named ph_all_slices_use_explicit_scaling_list_flag) equal to 1 specifies that all slices of the picture use an explicit scaling list, while the first PH flag equal to 0 specifies that each slice of the picture may or may not use an explicit scaling list.

[0171] ii. A second PH flag equal to 1 (e.g., named ph_no_slice_uses_explicit_scaling_list_flag) specifies that no slice of the picture uses an explicit scaling list. A second PH flag equal to 0 specifies that every slice of the picture may or may not use an explicit scaling list.

[0172] iii. The second PH flag is signaled only if the first PH flag is equal to 0.

[0173] iv. If the first PH flag is equal to 1 (or if the first PH flag is equal to 0 and the second PH flag is equal to 0), the scaling list APS ID is signaled in the PH.

[0174] v. If the first PH flag is equal to 0 and the second flag is equal to 0, then an SH flag (eg, named slice_use_explicit_scaling_list_flag) is signaled in the SH flag.

[0175] vi. If the first PH flag is equal to 1, then the value of the SH flag is inferred to be equal to 0.

[0176] vii. If the first PH flag is equal to 0 and the second PH flag is equal to 0, then the value of the SH flag is inferred to be equal to 0.

[0177] viii. If the value of the SH flag is equal to 1, the explicit scaling list is used to decode the slice. Otherwise, the explicit scaling list is used to decode the slice.

[0178] d. In a fourth example, one or more indicators of whether one or more of the scaling list related aspects (e.g., enable / disable, APS ID) are present in the PH or SH may be signaled.

[0179] Alternatively, a single indicator may be used, and further, the indicator may be a one-bit flag.

[0180] 1) In one example, if the indicator specifies that relevant aspects are present in the PH, then all slices assume the values ​​present in the PH and signaling of those relevant aspects is skipped in the SH.

[0181] 2) In one example, if the indicator specifies that related aspects are present in the SH, then the signaling of those related aspects is skipped in the PH.

[0182] ii. In one example, the one or more indicators are signaled in the PH.

[0183] iii. In another example, the one or more indicators are signaled in the PPS.

[0184] iv. In another example, one or more indicators are signaled in the SPS. 7. Whether to enable explicit scaling lists for LFNST coded blocks can be specified at sequence / picture / slice level instead of specifying it at APS.

[0185] In one example, syntax elements (eg, flags) may be signaled in SPS / PPS / PH / SH.

[0186] i. Alternatively, the syntax element may also be signaled under a condition check of whether LFNST is enabled (eg, sps_lfnst_enabled_flag is equal to 1).

[0187] ii. Alternatively, and further, for a video block, whether to apply an explicit or default scaling list may depend on the value of the syntax element and whether LFNST is enabled for this video block. 8. The deblocking filtering process for video unit samples along a video unit boundary may be performed based on padded samples. Figure 11 shows an example where samples p0, p1, and p2 are video unit samples along a video unit boundary and samples q0, q1, and q2 are padded samples to be used in the filtering process.

[0188] In one example, the video unit may be a picture.

[0189] b. In one example, the video unit may be a sub-picture.

[0190] c. In one example, the video unit may be a slice.

[0191] d. In one example, the video unit may be a tile.

[0192] e. In one example, the video unit may be a refresh region in gradual decoding refresh (GDR) and the boundary may be a boundary between refreshed and unrefreshed regions in a picture, and further, such a boundary may be signaled as a virtual boundary.

[0193] f. In one example, padding may be performed in a replicated manner. For example, the values ​​of q0, q1, and q2 may all be set equal to the value of p0. In one example, padding may be performed in a symmetric manner. For example, the values ​​of q0, q1, and q2 may all be set equal to the values ​​of p0, p1, and p2, respectively. 6. Embodiments In embodiments, certain text is shown in bold italics (for ease of translation, Underline text as <<< >>>) to highlight changes to the current version of the specification. Italicized text is removed from the current VVC specification description of the corresponding embodiment (for ease of translation, it is shown as text in <<< >>>). 6.1 Example 1: Subpicture Support This embodiment relates to item 1 and its sub-items. 3. Definition picture-level slice index: the index of the slice, defined if rect_slice_flag is equal to 1, relative to the list of slices in the picture, in the order in which the slices are signaled in the PPS if single_slice_per_subpic_flag is equal to 1, or in the order of increasing subpicture indices of the subpictures corresponding to the slices if single_slice_per_subpic_flag is equal to 1. <<< picture-level slice index: index of the slice into the list of slices in the picture in the order signaled in the PPS when rect_slice_flag is equal to 1 >>> 6.5.1 CTB Raster Scan, Tile Scan, and Subpicture Scan Processes ... For ctbAddrX ranging from 0 to PicWidthInCtbsY inclusive list CtbToTileColBd[ ctbAddrX ] and ctbToTileColIdx[ ctbAddrX ]specifies the horizontal CTB address in units of CTB to the left tile column boundary. for each tile column index It is a transformation and is derived as follows:

[0194]

number

[0195]

number

[0196]

number

[0197]

number

[0198]

number

[0199]

number

[0200]

number

[0201]

number

[0202]

number

[0203]

number

[0204]

number

[0205] - ph_scaling_list_present_flag is equal to 0. >>> - slice_explicit_scaling_list_enabled_flag equals 0.

[0206] - transform_skip_flag[xTbY][yTbY][cIdx] equal to 1.

[0207] -scaling_matrix_for_lfnst_disabled_flag is equal to 1 and ApplyLfnstFlag is equal to 1.

[0208] - ... 6.4. Embodiment 4: Approach #2 for Scaling List Support In this embodiment, the text associated with the scaling list is modified so that the following applies: 1) Instead of using the SPS flag for the scaling list and the PH flag for the scaling list, the scaling list flag in the slice header is used to control the scaling process of the transform coefficients. 2) If an explicit scaling list is used for all slices of a picture, no scaling list signaling is present in the SH. In the following, the values ​​of M and N may be set to 1 and 2, respectively. Alternatively, the values ​​of M and N may be set to 2 and 1, respectively. Alternatively, the following applies: 1) The syntax element ph_explicit_scaling_list_enabled_type is renamed to ph_explicit_scaling_list_mode. 2) Values ​​of ph_explicit_scaling_list_enabled_type equal to M, N, 0 are replaced by ph_explicit_scaling_list_mode equal to A, B, C (eg, 0, 1, 2), respectively. 3) The syntax condition "if( ph_explicit_scaling_list_enabled_type > 0 )" on ph_explicit_scaling_list_aps_id is replaced with "if( ph_explicit_scaling_list_mode != C )". Sequence Parameter Set RBSP Syntax and Syntax

[0209]

number

[0210]

number

[0211]

number

[0212] - ph_scaling_list_present_flag is equal to 0. >>> - slice_explicit_scaling_list_enabled_flag equals 0.

[0213] - transform_skip_flag[xTbY][yTbY][cIdx] equal to 1.

[0214] -scaling_matrix_for_lfnst_disabled_flag is equal to 1 and ApplyLfnstFlag is equal to 1.

[0215] - ...

[0057] Figure 5 is a block diagram illustrating an example video processing system 1900 in which various techniques disclosed herein may be implemented. Various implementations may include some or all of the components of the system 1900. The system 1900 may include an input 1902 for receiving video content. The video content may be received in a raw or uncompressed format, for example, 8 or 10 bit multi-component pixel values, or in a compressed or encoded format. The input 1902 may represent a network interface, a peripheral bus interface, or a storage interface. Examples of network interfaces include wired interfaces such as Ethernet, passive optical network (PON), etc., and wireless interfaces such as Wi-Fi or cellular interfaces.

[0216]

[0058] The system 1900 may include a coding component 1904 capable of implementing various coding or encoding methods described herein. The coding component 1904 may reduce the average bit rate of the video from the input 1902 to the output of the coding component 1904 to generate a coded representation of the video. Thus, coding techniques are sometimes referred to as video compression or video transcoding techniques. The output of the coding component 1904 may be stored or transmitted over a connected communication, as represented by component 1906. The stored or communicated bitstream (or coded) representation of the video received at the input 1902 may be used by component 1908 to generate pixel values ​​or displayable video that are sent to the display interface 1910. The process of generating a user-viewable video from the bitstream representation is often referred to as video decompression. Furthermore, although certain video processing operations may be referred to as "coding" operations or tools, it will be understood that the coding tools or operations may be used at an encoder, and that corresponding decoding tools or operations that reverse process the results of the coding may be performed at a decoder.

[0217]

[0059] Examples of peripheral bus interfaces or display interfaces may include Universal Serial Bus (USB) or High Definition Multimedia Interface (HDMI), Displayport, etc. Examples of storage interfaces include Serial Advanced Technology Attachment (SATA), PCI, IDE interfaces, etc. The technology described herein may be embodied in a variety of electronic devices, such as mobile phones, laptops, smart phones, or other devices capable of performing digital data processing and / or video display.

[0218]

[0060] Figure 6 is a block diagram of a video processing device 3600. The device 3600 may be used to implement one or more of the methods described herein. The device 3600 may be embodied in a smartphone, a tablet, a computer, an Internet of Things (IoT) receiver, etc. The device 3600 may include one or more processors 3602, one or more memories 3604, and video processing hardware 3606. The processor 3602 may be configured to implement one or more of the methods described herein. The memories 3604 may be used to store data and codes used to implement the methods and techniques described herein. The video processing hardware 3606 may be used to implement some of the techniques described herein in a hardware circuit.

[0219]

[0061] FIG. 8 is a block diagram illustrating an example video coding system 100 that can employ the techniques of this disclosure.

[0220] 8, video coding system 100 may include an originating (or source) device 110 and a destination (or destination) device 120. The originating device 110 generates encoded video data and may be referred to as a video encoding device. The destination device 120 is capable of decoding the encoded video data generated by the originating device 110 and may be referred to as a video decoding device.

[0221]

[0063] The source device 110 may include a video source 112, a video encoder 114, and an input / output (I / O) interface 116.

[0222]

[0064] The video source 112 may include a source such as a video capture device, an interface for receiving video data from a video content provider, and / or a computer graphics system for generating video data, or a combination of such sources. The video data may include one or more pictures. The video encoder 114 encodes the video data from the video source 112 to generate a bitstream. The bitstream may include a sequence of bits that form a coded representation of the video data. The bitstream may include a coded picture and associated data. A coded picture is a coded representation of a picture. The associated data may include a sequence parameter set, a picture parameter set, and other syntax structures. The I / O interface 116 may include a modulator / demodulator (modem) and / or a transmitter. The coded video data may be transmitted directly to the destination device 120 via the I / O interface 116 over the network 130a. The encoded video data may also be stored on a storage medium / server 130b for access by the destination device 120.

[0223]

[0065] The destination device 120 may include an I / O interface 126, a video decoder 124, and a display device 122.

[0224]

[0066] The I / O interface 126 may include a receiver and / or a modem. The I / O interface 126 may obtain encoded video data from the source device 110 or the storage medium / server 130b. The video decoder 124 may decode the encoded video data. The display device 122 may display the decoded video data to a user. The display device 122 may be integrated with the destination device 120 or may be external to the destination device 120, in which case the destination device is configured to interface with the external display device.

[0225]

[0067] The video encoder 114 and the video decoder 124 may operate in accordance with video compression standards such as the High Efficiency Video Coding (HEVC) standard, the Versatile Video Coding (VVC) standard, and other current and / or future standards.

[0226] FIG. 9 is a block diagram illustrating an example of a video encoder 200, which may be the video encoder 114 in the system 100 shown in FIG.

[0227]

[0069] Video encoder 200 may be configured to perform any or all of the techniques of this disclosure. In the example of FIG. 9, video encoder 200 includes multiple functional components. The techniques described in this disclosure may be shared among various components of video encoder 200. In some examples, a processor may be configured to perform any or all of the techniques described in this disclosure.

[0228]

[0070] Functional components of the video encoder 200 may include a partition unit 201, a prediction unit 202, which may include a mode selection unit 203, a motion estimation unit 204, a motion compensation unit 205, and an intra prediction unit 206, a residual generation unit 207, a transform unit 208, a quantization unit 209, an inverse quantization unit 210, an inverse transform unit 211, a reconstruction unit 212, a buffer 213, and an entropy coding unit 214.

[0229] In other examples, the video encoder 200 may include more, fewer, or different functional components. In one example, the prediction unit 202 may include an intra block copy (IBC) unit. The IBC unit may perform prediction in an IBC mode, in which at least one reference picture is the picture in which the current video block is located.

[0230]

[0072] Furthermore, some components, such as the motion estimation unit 204 and the motion compensation unit 205, may be highly integrated, but are depicted separately in the example of FIG. 9 for illustrative purposes.

[0231]

[0073] The partition unit 201 can partition a picture into one or more video blocks. The video encoder 200 and the video decoder 300 can support a variety of video block sizes.

[0232]

[0074] The mode selection unit 203 selects one of the coding modes, inter or intra, based on, for example, an error result, and provides the resulting intra-coded or inter-coded block to the residual generation unit 207 for residual block data generation and to the reconstruction unit 212 for reconstruction of the coded block to be used as a reference picture. In some examples, the mode selection unit 203 can select a combined intra & inter prediction (CIIP) mode, in which prediction is based on an inter prediction signal and an intra prediction signal. The mode selection unit 203 can also select the resolution of the motion vector for the block (e.g., sub-pixel or integer pixel accuracy) in the case of inter prediction.

[0233]

[0075] To perform inter prediction with respect to the current video block, motion estimation unit 204 may generate motion information for the current video block by comparing one or more reference frames from buffer 213 with the current video block. Motion compensation unit 205 may determine a predicted video block for the current video block based on the motion information and decoded samples of pictures from buffer 213 other than the picture associated with the current video block.

[0234]

[0076] The motion estimation unit 204 and the motion compensation unit 205 may perform various operations on the current video block depending on, for example, whether the current video block is an I slice, a P slice, or a B slice.

[0235]

[0077] In some examples, the motion estimation unit 204 may perform unidirectional prediction on the current video block, and the motion estimation unit 204 may search the reference pictures in list 0 or list 1 for a reference picture block for the current video block. The motion estimation unit 204 may then generate a reference index indicating a reference picture in list 0 or list 1 that contains the reference video block, and a motion vector indicating a spatial displacement between the current video block and the reference video block. The motion estimation unit 204 may output the reference index, the prediction direction indicator, and the motion vector as motion information of the current video block. The motion compensation unit 205 may generate a predicted video block of the current block based on the reference video block indicated by the motion information of the current video block.

[0236]

[0078] In another example, the motion estimation unit 204 may perform bi-directional prediction on the current video block, and the motion estimation unit 204 may search a reference picture in list 0 for a reference video block for the current video block, and may also search a reference picture in list 1 for another reference video block for the current video block. The motion estimation unit 204 may then generate a reference index indicating the reference picture in list 0 and list 1 that includes the reference video block, and a motion vector indicating a spatial displacement between the reference video block and the current video block. The motion estimation unit 204 may output the reference index and the motion vector of the current video block as the motion information of the current video block. The motion compensation unit 205 may generate a predicted video block of the current video block based on the reference video block indicated by the motion information of the current video block.

[0237]

[0079] In some examples, the motion estimation unit 204 may output a complete set of motion information for the decoding process of the decoder.

[0238]

[0080] In some examples, motion estimation unit 204 may not output a complete set of motion information for the current video. Rather, motion estimation unit 204 may signal motion information for the current video block with reference to motion information of other video blocks. For example, motion estimation unit 204 may determine that the motion information of the current video block is sufficiently similar to the motion information of a neighboring video block.

[0239]

[0081] In one example, the motion estimation unit 204 may specify a value in a syntax structure associated with a current video block that indicates to the video decoder 300 that the current video block has the same motion information as another video block.

[0240]

[0082] In another example, motion estimation unit 204 may identify another video block and a motion vector differential (MVD) in a syntax structure associated with the current video block. The motion vector differential indicates a difference between the motion vector of the current video block and the motion vector of the designated video block. Video decoder 300 may determine the motion vector of the current video block using the motion vector of the designated video block and the motion vector differential.

[0241]

[0083] As mentioned above, video encoder 200 can predictively signal motion vectors. Two examples of predictive signaling techniques that can be implemented by video encoder 200 include advanced motion vector predication (AMVP) and merge mode signaling.

[0242]

[0084] Intra prediction unit 206 may perform intra prediction on the current video block. When intra prediction unit 206 performs intra prediction on the current video block, intra prediction unit 206 may generate predictive data for the current video block based on decoded samples of other video blocks in the same picture. The predictive data for the current video block may include the video block to be predicted and various syntax elements.

[0243]

[0085] Residual generation unit 207 may generate residual data for the current video block by subtracting (e.g., as indicated by a minus sign) a predicted video block of the current video block from the current video block. The residual data for the current video block may include residual video blocks that correspond to different sample components of the samples in the current video block.

[0244]

[0086] In other examples, for a current video block, such as in skip mode, residual data for the current video block may not exist and residual generation unit 207 may not perform a subtraction operation.

[0245]

[0087] Transform processing unit 208 may generate one or more transform coefficient video blocks for the current video block by applying one or more transforms to a residual video block associated with the current video block.

[0246]

[0088] After the transform processing unit 208 generates a transform coefficient video block associated with the current video block, the quantization unit 209 may quantize the transform coefficient video block associated with the current video block based on one or more quantization parameter (QP) values ​​associated with the current video block.

[0247]

[0089] The inverse quantization unit 210 and the inverse transform unit 211 may apply inverse quantization and inverse transform, respectively, to the transform coefficient video block to reconstruct a residual video block from the transform coefficient video block. The reconstruction unit 212 may add the reconstructed residual video block to corresponding samples from one or more predicted video blocks generated by the prediction unit 202 to generate a reconstructed video block related to the current block, which may be stored in the buffer 213.

[0248]

[0090] After reconstruction unit 212 reconstructs the video blocks, a loop filtering operation may be performed to reduce video blocking artifacts in the video blocks.

[0249]

[0091] The entropy encoding unit 214 may receive data from other functional components of the video encoder 200. Once the entropy encoding unit 214 receives the data, the entropy encoding unit 214 may perform one or more entropy encoding operations to generate entropy encoded data and output a bitstream including the entropy encoded data.

[0250]

[0092] Some embodiments of the disclosed techniques include making a decision or determination to enable a video processing tool or mode. In one example, if a video processing tool or mode is enabled, the encoder will use or implement the tool or mode in processing blocks of video, but may not necessarily modify the resulting bitstream based on the use of the tool or mode. That is, the conversion of blocks of video to a bitstream (or bitstream representation) of video will use the video processing tool or mode if enabled based on the decision or determination. In another example, if a video processing tool or mode is enabled, the decoder will process the bitstream with the knowledge that the bitstream has been modified based on the video processing tool or mode. That is, the conversion of a bitstream of video to blocks of video will be performed using the video processing tool or mode enabled based on the decision or determination.

[0251] FIG. 10 is a block diagram illustrating an example of a video decoder 300, which may be the video decoder 114 in the system 100 shown in FIG.

[0252]

[0094] The video decoder 300 may be configured to perform any or all of the techniques described in this disclosure. In the example of FIG. 10, the video decoder 300 includes multiple functional components. The techniques described in this disclosure may be shared among various components of the video decoder 300. In some examples, a processor may be configured to perform any or all of the techniques described in this disclosure.

[0253]

[0095] In the example of Figure 10, the video decoder 300 includes an entropy decoding unit 301, a motion compensation unit 302, an intra prediction unit 303, an inverse quantization unit 304, an inverse transform unit 305, a reconstruction unit 306, and a buffer 307. The video decoder 300 may, in some examples, perform a decoding path that is generally the inverse of the encoding path described with respect to the video encoder 200 (Figure 9).

[0254]

[0096] The entropy decoding unit 301 may retrieve an encoded bitstream. The encoded bitstream may include entropy coded video data (e.g., coded blocks of video data). The entropy decoding unit 301 may decode the entropy coded video data, and from the entropy decoded video data, the motion compensation unit 302 may determine motion information including motion vectors, motion vector precision, reference picture list index, and other motion information. The motion compensation unit 302 may determine such information, for example, by implementing AMVP and merge mode.

[0255]

[0097] The motion compensation unit 302 may generate a motion compensated block by performing interpolation, possibly based on an interpolation filter. An identifier for an interpolation filter used with sub-pixel precision may be included in the syntax element.

[0256]

[0098] The motion compensation unit 302 may calculate interpolated values ​​for the fractional pixels of the reference block using an interpolation filter as used by the video encoder 200 during encoding of the video block. The motion compensation unit 302 may determine the interpolation filter used by the video encoder 200 according to received syntax information and generate the prediction block using the interpolation filter.

[0257]

[0099] The motion compensation unit 302 may use some of the syntax information to determine the size of the blocks used to code the frames and / or slices of the coded video sequence, partition information describing how each macroblock of a picture of the coded video sequence is partitioned, a mode indicating how each partition is coded, one or more reference frames (and reference frame lists) for each inter-coded block, and other information for decoding the coded video sequence.

[0258]

[0100] The intra prediction unit 303 may form a prediction block from spatially neighboring blocks, for example, using an intra prediction mode received in the bitstream. The inverse quantization unit 303 inverse quantizes, i.e., dequantizes, the quantized video block coefficients provided in the bitstream and decoded by the entropy decoding unit 301. The inverse transform unit 303 applies an inverse transform.

[0259]

[0101] The reconstruction unit 306 may sum the residual blocks with corresponding prediction blocks generated by the motion compensation unit 202 or the intra prediction unit 303 to form decoded blocks. If desired, a deblocking filter may be applied to filter the decoded blocks to remove blockiness artifacts. The decoded video blocks are then stored in a buffer 307, which provides reference blocks for subsequent motion compensation / intra prediction and also generates the decoded video for presentation on a display device.

[0260]

[0102] The following is a list of preferred solutions in some embodiments:

[0261]

[0103] The following solutions represent exemplary embodiments of the techniques discussed in the preceding sections (eg, item 1).

[0262] 1. A video processing method (e.g., method 900 shown in FIG. 7). The method includes: performing a conversion between a video including one or more video pictures (each video picture including one or more tiles) and a coded representation of the video, the coded representation conforming to a format rule; the format rule specifying first information to be signaled in the coded representation and second information derived from the coded representation, the first information or the second information being associated with row or column indices of one or more j tiles.

[0263]

[0105] 2. In the method of Solution 1, the format rules specify that a tile column index for each coding tree unit of each video picture is to be derived.

[0264]

[0106] 3. In the method of Solution 1, the format rules specify that a tile row index for each coding tree unit of each video picture is to be derived.

[0265]

[0107] The following solutions illustrate example embodiments of the techniques discussed in the previous sections (e.g., item 2). In these solutions, the video region may be a video picture, and the video unit may be a video block or a coding tree unit or a video slice.

[0266]

[0108] 4. A video processing method, the method comprising the steps of: performing a conversion between video units in a video domain of a video and a coded representation of the video, the coded representation complying with a format rule; the format rule specifying that first control information in the video domain controls whether second control information is included at video unit level or not; the first control information and / or the second control information includes information regarding a luma mapping and chroma scaling (LMCS) or a chroma residual scaling (CRS) or a reshaping process (RP) used in the conversion.

[0267]

[0109] 5. In the method of solution 4, the first control information includes an indicator of whether the second control information is included in the coded representation.

[0268]

[0110] 6. In the methods of solutions 4-5, a specific value of the first control information indicates that the LMCS is disabled for all video units in the video area.

[0269]

[0111] 7. In any of solutions 4-6, the second control information controls enabling of the LMCS in the video unit.

[0270]

[0112] 8. In the method of solution 4, the first control information includes a plurality of indicators.

[0271]

[0113] The following solutions represent exemplary embodiments of the techniques discussed in the preceding sections (eg, items 5-8).

[0272]

[0114] 9. A video processing method, comprising: performing a conversion between a video comprising one or more video regions each comprising one or more video units and a coded representation of the video, the coded representation conforming to a format rule; the format rule specifying that the coded representation includes two-level signaling of a scaling list usable for conversion of at least some of the video units, a higher level of the two-level signaling at a video region level controlling whether and where a lower level of the two-level signaling at a video unit level is included in the coded representation; and the scaling list includes information regarding a scaling used for conversion of at least some of the video units.

[0273]

[0115] 10. In the method of solution 9, a binary-valued field in the high-level signaling controls the occurrence of the low-level signaling.

[0274]

[0116] 11. In any of the methods of solutions 9-10, a binary valued field in the low level signaling controls disabling of the scaling list included in the low level signaling.

[0275]

[0117] 12. In any of the methods of solutions 9-11, the one or more video regions correspond to a video picture.

[0276]

[0118] 13. In any of Solutions 9-12, the one or more video units include a video slice or a video coding unit.

[0277]

[0119] The following solutions represent exemplary embodiments of the techniques discussed in the preceding sections (eg, items 5-8).

[0278]

[0120] 14. A video processing method, the method including: determining a scaling list for a low frequency non-separable transform used to convert between a video unit of the video and a coded representation of the video; and performing the conversion based on the determination, wherein a syntax structure in the coded representation indicates whether the scaling list is enabled for the video unit.

[0279]

[0121] 15. In the method of solution 14, the syntax structure is included in a sequence header, a picture header, or a slice header.

[0280]

[0122] 16. In any of solutions 14-15, the video unit includes a video block.

[0281]

[0123] 17. In any of Solutions 1-16, the converting includes encoding the video into a coded representation.

[0282]

[0124] 18. In any of Solutions 1-16, the converting includes decoding the coded representation to generate pixel values ​​for the video.

[0283]

[0125] 19. A video decoding device comprising a processor configured to perform the methods described in one or more of Solutions 1-18.

[0284]

[0126] 20. A video encoding device comprising a processor configured to perform the methods described in one or more of Solutions 1-18.

[0285]

[0127] 21. A computer program product having computer code stored therein which, when executed by a processor, causes the processor to perform a method as set forth in any of Solutions 1-18.

[0286]

[0128] 22. Any method, apparatus, or system described in this specification.

[0287]

[0129] In the solutions described herein, an encoder can conform to the format rules by generating a coded representation according to the format rules. In the solutions described herein, a decoder can use the format rules to parse syntax elements in the coded representation according to the format rules, along with knowledge of the presence and absence of the syntax elements, to generate decoded video.

[0288] 12 is a flow chart of an example video processing method 1200. An operation 1202 includes performing a conversion between a video block of a video and a bitstream of the video, where the bitstream complies with a format rule, where the format rule specifies that a first syntax element is included in the bitstream at a video domain level indicating whether a scaling process is applied to transform coefficients or non-transform coefficients of the video block, where the video domain is smaller than a video picture of the video.

[0289]

[0131] In some embodiments of the method 1200, the format rule specifies that the first syntax element is in a slice header of the slice, and the format rule specifies that the scaling process is not controlled by a second syntax element indicating whether a scaling list is enabled in a sequence parameter set of the bitstream. In some embodiments of the method 1200, the second syntax element specifies whether a scaling list is enabled, and the scaling list is included in a scaling list adaptation parameter set in a scaling process for transform coefficients during transformation of the slice. In some embodiments of the method 1200, the format rule specifies that the first syntax element is in a slice header of the slice, and the format rule specifies that the scaling process is not controlled by a third syntax element indicating whether a scaling list is present in a picture header in the bitstream. In some embodiments of method 1200, the first syntax element specifies whether a scaling list is enabled, and the scaling list is included in a scaling list adaptation parameter set for a scaling process for transform coefficients during transformation of a slice.

[0290]

[0132] Figure 13 is a flow chart of an example video processing method 1300. Operation 1302 includes performing a conversion between a video unit of a video domain of a video and a bitstream of the video, the bitstream conforming to a format rule, the format rule specifying that first control information at a first level of the video domain in the bitstream indicates whether second control information is included at a second level of the video unit in the bitstream, the first control information and / or the second control information including information regarding whether a scaling list is used for transform coefficients or for non-transform coefficients related to the transform.

[0291]

[0133] In some embodiments of the method 1300, the first control information selectively includes a first indicator, the first indicator indicating whether the scaling list is enabled for one or more slices at a first level of the video region and the scaling list is enabled at a second level of the video unit, the first indicator being a non-binary value. In some embodiments of the method 1300, the first level of the video region includes a picture header. In some embodiments of the method 1300, the first level of the video region includes a picture header, the first control information includes a first indicator, the scaling list is enabled for all slices of the picture header when the first indicator is equal to a first value, the scaling list is disabled for less than all slices of the picture header when the first indicator is equal to a second value, and the scaling list is disabled for all slices of the picture header when the first indicator is equal to a third value, the first value, the second value, and the third value being different from each other. In some embodiments of the method 1300, if the first control information excludes the first indicator, the value of the first indicator is presumed to be a default value.

[0292]

[0134] In some embodiments of the method 1300, the first level of the video region includes a picture header, the first control information includes a first indicator, the scaling list is enabled for all slices of the picture header when the first indicator is equal to a first value, the scaling list is enabled when decoding a slice of the video region that includes a video picture when the first indicator is equal to a second value, and the scaling list is disabled for all slices of the picture header when the first indicator is equal to a third value, and the first value, the second value, and the third value are different from each other. In some embodiments of the method 1300, the first level of the video region includes a picture header, the first control information includes a first indicator, the scaling list is enabled for all slices of the picture header when the first indicator is equal to the first value, and the scaling list is selectively enabled when decoding a slice of the video region that includes a video picture when the first indicator is equal to the second value. The scaling list is disabled for all slices in the picture header if the first indicator is equal to the third value, and the first value, the second value, and the third value are different from one another.

[0293]

[0135] In some embodiments of the method 1300, the first level of the video region includes a picture header, the first control information includes a first indicator, the scaling list is disabled for all slices of the picture header when the first indicator is equal to a first value, the scaling list is disabled for less than all slices of the picture header when the first indicator is equal to a second value, and the scaling list is enabled for all slices of the picture header when the first indicator is equal to a third value, and the first value, the second value, and the third value are different from each other. In some embodiments of the method 1300, the first level of the video region includes a picture header, the first control information includes a first indicator, the scaling list is enabled for all slices of the picture header when the first indicator is equal to the first value, and the scaling list is selectively disabled when decoding a slice of the video region including a video picture when the first indicator is equal to the second value. In some embodiments of the method 1300, the first level of the video region includes a picture header, the first control information includes a first indicator, the scaling list is enabled for all slices of the picture header when the first indicator is equal to the first value, the scaling list is disabled when decoding a slice of the video region including a video picture when the first indicator is equal to the second value, and the scaling list is disabled for all slices of the picture header when the first indicator is equal to a third value, and the first value, the second value, and the third value are different from each other.

[0294]

[0136] In some embodiments of the method 1300, the first indicator is selectively included in the first control information based on a value of a syntax element in the bitstream indicating whether the scaling list is enabled at a sequence level. In some embodiments of the method 1300, the first indicator is coded with u(v) or u(2) or ue(v). In some embodiments of the method 1300, the first indicator is coded with a truncated unary code. In some embodiments of the method 1300, adaptive parameter set (APS) information of the scaling list used by one or more slices is included in the bitstream based on a value of the first indicator indicating whether the scaling list is enabled for one or more slices at a first level of the video domain. In some embodiments of the method 1300, the second control information selectively includes a second indicator, the second indicator indicating whether a scaling list is enabled or disabled for one or more slices at a second level of the video unit, the second indicator being included in the bitstream based on a value of the first indicator included in the first control information, the first indicator indicating whether a scaling list is enabled or disabled for one or more slices at a second level of the video unit. In some embodiments of the method 1300, the second control information includes a slice header. In some embodiments of the method 1300, in response to the first indicator being equal to the first value, the second indicator is included in the second control information. In some embodiments of the method 1300, in response to performing a state check of the first indicator >>1, or the first indicator / 2, or the first indicator &0x01, the second indicator is included in the second control information, where >> indicates a right shift operation and & indicates bitwise logic and operation.

[0295]

[0137] In some embodiments of the method 1300, in response to the second indicator not being present in the second control information: a value of the second indicator is presumed to be enabled in response to the first indicator being equal to the first value, or a value of the second indicator is presumed to be disabled in response to the first indicator being equal to a third value, the first value, the second value of the first indicator, and the third value being different from each other. In some embodiments of the method 1300, the first control information includes a plurality of indicators, the plurality of indicators indicating whether a scaling list is enabled for one or more slices at a first level of the video region to specify whether a scaling list is enabled at a second level of the video unit, the plurality of indicators having a non-binary value. In some embodiments of the method 1300, the plurality of indicators includes at least two indicators included in a picture header. In some embodiments of method 1300, the at least two indicators include a first indicator, the first indicator indicating whether a scaling list is enabled for at least one slice associated with the picture header, and the at least two indicators optionally include a second indicator, the second indicator indicating whether a scaling list is enabled for all slices associated with the picture header. In some embodiments of method 1300, the second indicator is selectively signaled in the plurality of indicators based on a value of the first indicator.

[0296]

[0138] In some embodiments of the method 1300, a value of the first indicator indicates that the scaling list is enabled for at least one slice. In some embodiments of the method 1300, the scaling list is presumed to be enabled for all slices associated with the picture header in response to the second indicator not being present in the bitstream. In some embodiments of the method 1300, in response to the first indicator being false in the conformance bitstream, the second indicator is false. In some embodiments of the method 1300, the at least two indicators include a third indicator, the third indicator being selectively signaled in the slice header based on a first value of the first indicator or a second value of the second indicator. In some embodiments of the method 1300, a first value of the first indicator specifies that the scaling list is enabled for at least one slice, and a second value of the second indicator specifies that the scaling list is disabled for all slices. In some embodiments of method 1300, a value of the third indicator is estimated based on a first value of the first indicator and / or a second value of the second indicator in response to the third indicator being absent from the bitstream. In some embodiments of method 1300, the at least two indicators include a first indicator indicating whether a scaling list is disabled for at least one slice associated with the picture header, and the at least two indicators optionally include a second indicator specifying whether a scaling list is disabled for all slices associated with the picture header.

[0297]

[0139] In some embodiments of the method 1300, the second indicator is signaled with a plurality of indicators based on a first value of the first indicator. In some embodiments of the method 1300, the first value of the first indicator indicates that the scaling list is disabled for at least one slice. In some embodiments of the method 1300, the scaling list is presumed to be disabled for all slices associated with the picture header in response to the absence of the second indicator in the bitstream. In some embodiments of the method 1300, the at least two indicators selectively include a third indicator in the slice header based on a second value of the second indicator. In some embodiments of the method 1300, the first value of the first indicator indicates that the scaling list is enabled for at least one slice, and the second value of the second indicator indicates that the scaling list is enabled for all slices. In some embodiments of method 1300, a value of the third indicator is estimated based on a first value of the first indicator and / or a second value of the second indicator in response to the third indicator being absent from the bitstream. In some embodiments of method 1300, the plurality of indicators selectively include the first indicator based on a value of a syntax element indicating whether scaling lists are enabled at a sequence level.

[0298]

[0140] In some embodiments of the method 1300, the plurality of indicators selectively include a third indicator indicating whether the scaling list is enabled or disabled at the second level of the video unit, the third indicator being selectively signaled based on a first value of the first indicator and / or a second value of the second indicator. In some embodiments of the method 1300, the third indicator is selectively signaled based on a second indicator indicating that the scaling list is not enabled for all slices or that the scaling list is not disabled for all slices. In some embodiments of the method 1300, two 1-bit syntax elements are selectively signaled in the first control information at the first level of the video domain, specifying whether the scaling list is enabled at the second level of the video unit, the video domain including a video picture, and the video unit including one or more slices. In some embodiments of the method 1300, the first control information includes a picture header of the video picture and the second control information includes a slice header of a slice from the one or more slices.

[0299]

[0141] In some embodiments of the method 1300, the two 1-bit syntax elements include a first picture header syntax element, where all slices of the video picture use the scaling list in response to the first picture header syntax element being equal to 1, and each slice of the video picture selectively uses the scaling list in response to the first picture header syntax element being equal to 0. In some embodiments of the method 1300, the two 1-bit syntax elements include a second picture header syntax element, where no slices of the video picture use the scaling list in response to the second picture header syntax element being equal to 1, and each slice of the video picture selectively uses the scaling list in response to the second picture header syntax element being equal to 0. In some embodiments of method 1300, the second picture header syntax element is signaled in the bitstream when the first picture header syntax element is equal to 0. In some embodiments of method 1300, an adaptation parameter set (APS) identifier for the scaling list is signaled in the picture header in response to: the first picture header syntax element being equal to 1, or the first picture header syntax element being equal to 0 and the second picture header syntax element being equal to 0. In some embodiments of method 1300, a slice header syntax element is signaled in the slice header in response to the first picture header syntax element being equal to 0 and the second picture header syntax element being equal to 0.

[0300]

[0142] In some embodiments of the method 1300, a value of the slice header syntax element in the slice header is estimated to be 0 in response to the first picture header syntax element being equal to 1. In some embodiments of the method 1300, a value of the slice header syntax element in the slice header is estimated to be 0 in response to the first picture header syntax element being equal to 0 and the second picture header syntax element being equal to 0. In some embodiments of the method 1300, in response to the value of the slice header syntax element in the slice header being equal to 1, the scaling list is used to decode the slice. In some embodiments of the method 1300, the bitstream selectively includes one or more indicators indicating whether information related to the scaling list is indicated in the picture header or the slice header. In some embodiments of the method 1300, the one or more indicators include a one-bit indicator.

[0301]

[0143] In some embodiments of the method 1300, all slices of the video unit estimate values ​​from the picture header in response to the one-bit indicator indicating that the picture header in the first control information includes information related to the scaling list, and signaling of the information related to the scaling list is excluded from the slice header. In some embodiments of the method 1300, in response to the one-bit indicator indicating that the information related to the scaling list is indicated in the slice header, the information related to the scaling list is excluded from the picture header. In some embodiments of the method 1300, the one or more indicators are signaled in the picture header. In some embodiments of the method 1300, the one or more indicators are signaled in a picture parameter set (PPS). In some embodiments of the method 1300, the one or more indicators are signaled in a sequence parameter set (SPS).

[0302] 14 is a flow chart of an example video processing method 1400. Operation 1402 includes performing a conversion between a video block of a video and a bitstream of the video, where the video block uses a low frequency non-separable transform for the conversion, and the bitstream complies with a format rule that specifies that a syntax element is included at a syntax level of the bitstream, where the syntax element indicates whether use of a scaling matrix derived from a reference scaling list is enabled for the video block, where the syntax level is a sequence level, a picture level, or a slice level.

[0303]

[0145] In some embodiments of the method 1400, the syntax element is included in a sequence parameter set (SPS), a picture parameter set (PPS), a picture header, or a slice header. In some embodiments of the method 1400, the syntax element is included in an SPS, a PPS, a picture header, or a slice header based on whether a low-frequency non-separable transform is enabled for the video block. In some embodiments of the method 1400, the syntax element is included in an SPS based on whether a value of sps_lfnst_enabled_flag is equal to 1. In some embodiments of the method 1400, the method further includes determining whether to apply a scaling matrix derived from an explicit scaling list or a default scaling list to the video block based on the syntax element and whether a low-frequency non-separable transform is enabled for the video block.

[0304]

[0146] Figure 15 is a flow chart of an example video processing method 1500. Operation 1502 includes determining, for conversion between a video unit of a video and a video bitstream, to perform deblocking filtering on samples of the video unit along a boundary of the video unit using samples padded outside the boundary. Operation 1504 includes performing the conversion according to the determination.

[0305]

[0147] In some embodiments of the method 1500, the video unit comprises a video picture. In some embodiments of the method 1500, the video unit comprises a sub-picture of the video picture. In some embodiments of the method 1500, the video unit comprises a slice. In some embodiments of the method 1500, the video unit comprises a tile. In some embodiments of the method 1500, the video unit is a refreshed region resulting from a gradual decoding refresh (GDR), and the boundary is located between the refreshed region and the unrefreshed region of the video picture. In some embodiments of the method 1500, the boundary is indicated as a virtual boundary in the bitstream. In some embodiments of the method 1500, the padding process is performed in a replicating manner such that values ​​of two or more padded samples are equal to values ​​of samples from samples along the boundary of the video unit. In some embodiments of method 1500, the padding process is performed in a symmetric manner such that values ​​of at least a first padded sample and a second padded sample from the padded samples are equal to values ​​of a first sample and a second sample, respectively, from the samples along the boundary of the video unit.

[0306]

[0148] In some embodiments, performing the conversion includes encoding the video into a bitstream. In some embodiments, performing the conversion includes generating a bitstream from the video, the method including storing the bitstream in a non-transitory computer readable storage medium. In some embodiments, performing the conversion includes decoding the video from the bitstream. In some embodiments, the video decoding device comprises a processor configured to perform one or more operations described in this patent specification. In some embodiments, the video encoding device comprises a processor configured to perform one or more operations described in this patent specification. In some embodiments, the computer program product has computer instructions stored thereon that, when executed by the processor, cause the processor to perform one or more operations described in this patent specification. In some embodiments, the non-transitory computer readable storage medium stores a bitstream generated according to one or more operations described in this patent specification. In some embodiments, the non-transitory computer readable storage medium stores instructions that cause the processor to perform one or more operations described in this patent specification. In some embodiments, a bitstream generation method includes: generating a bitstream of a video according to one or more of the operations described herein and storing the bitstream on a computer-readable program medium. Some embodiments relate to methods, apparatus, bitstreams generated according to the disclosed methods, or systems described herein.

[0307]

[0149] In this specification, the term "video processing" may refer to video encoding, video decoding, video compression or video decompression. For example, a video compression algorithm may be applied during the conversion from a pixel representation of a video to a corresponding bitstream representation or vice versa. The bitstream representation of a current video block may correspond to bits distributed or co-located at different locations in the bitstream, for example as defined by a syntax. For example, a macroblock may be coded in terms of transformed and coded error residual values, and using bits in a header and other fields in the bitstream. Furthermore, during conversion, a decoder may parse the bitstream with the knowledge that some fields may be present or absent, based on a decision as described in the above solution. Similarly, an encoder may determine whether a particular syntax field is to be included or not, and accordingly generate a coded representation by including or excluding the syntax field from the coded representation.

[0308]

[0150] The disclosed and other solutions, examples, embodiments, modules, and functional operations described herein can be realized in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed herein and their structural equivalents, or in one or more combinations thereof. The disclosed and other embodiments can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a computer-readable medium for execution by or for controlling the operation of a data processing apparatus. The computer-readable medium can be a machine-readable storage device, a machine-readable storage substrate, a memory device, a machine-readable composition of matter affecting a transmitted signal, or one or more combinations thereof. The term "data processing apparatus" encompasses all apparatus, devices, and machines for processing data, including, for example, a programmable processor, a computer, or multiple processors or computers. An apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, such as code constituting a processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof. The transmitted signal may be an artificially generated signal, e.g., a machine-generated electrical, optical, or electromagnetic signal, generated to encode information for transmission to an appropriate receiving device.

[0309]

[0151] A computer program (also known as a program, software, software application, script, code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., a file that stores one or more modules, subprograms, or code portions). A computer program can be deployed to run on one computer or on multiple computers, which can be located at one site or distributed across multiple sites and interconnected by a communication network.

[0310]

[0152] The processes and logic flows described herein may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data to generate output. The processes and logic flows may also be performed by, and apparatus may be implemented as, special purpose logic circuitry, such as an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

[0311]

[0153] Processors suitable for executing computer programs include, for example, both general purpose and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The essential elements of a computer are a processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also includes one or more mass storage devices for storing data, such as magnetic, magnetic optical, or optical disks, or is operatively coupled to receive data from them, transfer data to them, or both. However, it is not required that a computer have such devices. Computer-readable media suitable for storing computer program instructions and data include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices such as EPROM, EEPROM, and flash memory devices; magnetic disks, such as internal hard disks or removable disks; magneto-optical disks; and CD ROM and DVD-ROM disks. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0312]

[0154] Although the present specification contains many details, these should not be construed as limitations on any subject matter or the scope of what may be claimed, but rather as descriptions of features that may be specific to certain embodiments of a particular technology. Certain features described herein in the context of separate embodiments may also be combined and implemented in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, although features may be described above as acting in a particular combination, or even initially claimed as such, one or more features of a claimed combination may, in some cases, be carved out of the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0313]

[0155] Similarly, although acts are depicted in a particular order in the figures, this should not be understood as requiring that such acts be performed in the particular order or sequence shown, or that all of the acts illustrated be performed, to achieve desired results. Moreover, the division of various system components in the embodiments described in this patent specification should not be understood as requiring such division in all embodiments.

[0314]

[0156] Only a few implementations and examples have been described, and other implementations, extensions and modifications are possible based on what is described and illustrated in this patent specification.

[0315] (Appendix 1) 1. A method of video processing comprising the step of performing a conversion between video blocks of a video and a bitstream of said video, the method comprising: the video block uses a low-frequency non-separable transform for the transform; the bitstream complies with format rules specifying that syntax elements are included at a syntax level with respect to the bitstream; The syntax element indicates whether utilization of a scaling matrix derived from a reference scaling list is enabled for the video block; and The syntax level is a sequence level, a picture level, or a slice level. (Appendix 2) 2. The method of claim 1, wherein the syntax element is included in a sequence parameter set (SPS), a picture parameter set (PPS), a picture header, or a slice header. (Appendix 3) 3. The method of claim 2, wherein the syntax element is included in the SPS, the PPS, the picture header, or the slice header based on whether the low frequency non-separable transform is enabled for the video block. (Appendix 4) 4. The method of claim 3, wherein the syntax element is included in the SPS based on whether the value of sps_lfnst_enabled_flag is equal to 1. (Appendix 5) 3. The method of claim 2, further comprising determining, based on the syntax element, whether to apply the scaling matrix derived from an explicit scaling list or a default scaling list to the block and whether the low frequency non-separable transform is enabled for the video block. (Appendix 6) 1. A video processing method comprising the steps of: determining, for converting between a video unit of a video and a bitstream of the video, for samples of the video unit along a boundary of the video unit, to perform deblocking filtering using samples padded outside the boundary; and performing said conversion in accordance with said determination; The method includes: (Appendix 7) 7. The method of claim 6, wherein the video unit comprises a video picture. (Appendix 8) 7. The method of claim 6, wherein the video unit includes a sub-picture of a video picture. (Appendix 9) 7. The method of claim 6, wherein the video units include slices. (Appendix 10) 7. The method of claim 6, wherein the video units include tiles. (Appendix 11) 7. The method of claim 6, wherein the video unit is a refreshed region resulting from a gradual decoding refresh (GDR), and the boundary is located between an unrefreshed region of a video picture and the refreshed region. (Appendix 12) 12. The method of claim 11, wherein the boundary is indicated in the bitstream as a virtual boundary. (Appendix 13) 7. The method of claim 6, wherein the padding process is performed in a replicative manner such that values ​​of two or more padded samples are equal to values ​​of samples from samples along the boundary of the video unit. (Appendix 14) 7. The method of claim 6, wherein the padding process is performed in a symmetric manner such that values ​​of at least a first padded sample and a second padded sample from the padded samples are equal to values ​​of a first sample and a second sample, respectively, from the samples along the boundary of the video unit. (Appendix 15) 15. The method of any one of claims 1 to 14, wherein the step of performing the conversion comprises encoding the video into the bitstream. (Appendix 16) 15. The method of any one of claims 1 to 14, wherein the step of performing the conversion includes a step of generating the bitstream from the video, the method further including a step of storing the bitstream in a non-transitory computer-readable storage medium. (Appendix 17) 15. The method of any one of claims 1 to 14, wherein the step of performing the conversion comprises decoding the video from the bitstream. (Appendix 18) 18. A video decoding apparatus comprising a processor configured to carry out the method described in one or more of claims 1 to 17. (Appendix 19) 18. A video encoding apparatus comprising a processor configured to perform the method described in one or more of claims 1 to 17. (Appendix 20) 18. A computer program product storing computer instructions which, when executed by a processor, cause the processor to perform a method according to any one of claims 1 to 17. (Appendix 21) A non-transitory computer-readable storage medium storing a bitstream generated by the method of any one of claims 1 to 17. (Appendix 22) A non-transitory computer-readable storage medium having stored thereon instructions for causing a processor to perform the method of any one of claims 1 to 17. (Appendix 23) generating a video bitstream according to the method of any one of claims 1 to 17; and storing the bitstream on a computer readable program medium; A bitstream generation method comprising: (Appendix 24) A bitstream generated by the method, apparatus, or disclosed method or system described herein.< / flag> < / flag> < / flag>

Claims

1. 1. A method of video processing comprising the step of performing a conversion between video blocks of a video and a bitstream of said video, the method comprising the steps of: the video block uses a low frequency non-separable transform for the transform; the bitstream conforms to a format rule specifying that a first syntax element is included at a syntax level for the bitstream; the first syntax element indicating whether an explicit scaling matrix is ​​enabled for the low-frequency non-separable transform coded block; The format rules further specify that a third syntax element is included in a slice header of the bitstream to control a scaling process applied to transform coefficients or non-transform coefficients; A method in which whether the first syntax element is included in a sequence parameter set (SPS) depends on the value of a second syntax element included in the SPS, the first syntax element being sps_scaling_matrix_for_lfnst_disabled_flag and the second syntax element being sps_lfnst_enabled_flag.

2. 2. The method of claim 1, wherein the first syntax element is included in the SPS based on whether the low-frequency non-separable transform is enabled.

3. 3. The method of claim 1 or 2, wherein the first syntax element is included in the SPS if a value of the second syntax element included in the SPS is equal to 1, and the value of the second syntax element equal to 1 indicates that the low-frequency non-separable transform is enabled.

4. The method according to any one of claims 1 to 3, further comprising: The method further includes determining whether to apply a default scaling matrix or an explicit scaling matrix of the explicit scaling matrices to the video block based on whether the low-frequency non-separable transform is enabled for the video block and the value of the first syntax element.

5. 5. The method of claim 4, wherein if a value of the first syntax element is equal to 1, indicating that use of the explicit scaling matrix for blocks coded with the low-frequency non-separable transform is disabled and that the low-frequency non-separable transform is enabled for the video block, then the default scaling matrix is ​​applied to the video block.

6. 6. The method of claim 5, wherein the scaling factor of the default scaling matrix is ​​equal to 16.

7. 7. The method of claim 1, wherein the step of performing a conversion comprises the step of encoding the video into the bitstream.

8. 7. The method of claim 1, wherein the step of performing the conversion comprises the step of decoding the video from the bitstream.

9. 1. An apparatus for processing video data comprising a processor and a non-transitory memory with instructions that, when executed by the processor, cause the processor to: performing a conversion between video blocks of a video and a bitstream of said video; the video block uses a low frequency non-separable transform for the transform; the bitstream conforms to a format rule specifying that a first syntax element is included at a syntax level for the bitstream; the first syntax element indicating whether an explicit scaling matrix is ​​enabled for the low-frequency non-separable transform coded block; The format rules further specify that a third syntax element is included in a slice header of the bitstream to control a scaling process applied to transform coefficients or non-transform coefficients; An apparatus, wherein whether the first syntax element is included in a sequence parameter set (SPS) depends on the value of a second syntax element included in the SPS, the first syntax element being sps_scaling_matrix_for_lfnst_disabled_flag and the second syntax element being sps_lfnst_enabled_flag.

10. A non-transitory computer-readable storage medium storing instructions that cause a processor to: performing a conversion between video blocks of a video and a bitstream of said video; the video block uses a low frequency non-separable transform for the transform; the bitstream conforms to a format rule specifying that a first syntax element is included at a syntax level for the bitstream; the first syntax element indicating whether an explicit scaling matrix is ​​enabled for the low-frequency non-separable transform coded block; The format rules further specify that a third syntax element is included in a slice header of the bitstream to control a scaling process applied to transform coefficients or non-transform coefficients; A storage medium, wherein whether the first syntax element is included in a sequence parameter set (SPS) depends on the value of a second syntax element included in the SPS, the first syntax element being sps_scaling_matrix_for_lfnst_disabled_flag and the second syntax element being sps_lfnst_enabled_flag.

11. A method for storing a bitstream of video, comprising: generating a bitstream of the video from video blocks of the video; and storing the bitstream in a non-transitory computer readable storage medium; wherein the video block uses a low frequency non-separable transform to generate the bitstream; the bitstream conforms to a format rule specifying that a first syntax element is included at a syntax level for the bitstream; the first syntax element indicating whether an explicit scaling matrix is ​​enabled for the low-frequency non-separable transform coded block; The format rules further specify that a third syntax element is included in a slice header of the bitstream to control a scaling process applied to transform coefficients or non-transform coefficients; A method in which whether the first syntax element is included in a sequence parameter set (SPS) depends on the value of a second syntax element included in the SPS, the first syntax element being sps_scaling_matrix_for_lfnst_disabled_flag and the second syntax element being sps_lfnst_enabled_flag.

Images