Signaling Global Motion Vectors in the Picture Header - Patent application

Abstract

To provide preferred signaling of a global motion vector in a picture header.SOLUTION: The present invention relates generally to the field of video compression. In particular, the present invention is directed to the signaling of global motion vectors in picture headers. A decoder includes a circuit network configured to receive a bitstream, extract a header, determine, using the header, a global motion model, and decode a current block of a current frame using the global motion model. Related apparatus, systems, techniques and articles are also described. Some implementations of the present subject matter may provide an efficient approach for communicating global motion to a decoder and the use of global motion vectors in improving compression efficiency.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] (CROSS REFERENCE TO RELATED APPLICATIONS) This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 838,509, filed April 25, 2019, and entitled “SIGNALING OF GLOBAL MOTION VECTOR IN PICTURE HEADER,” which is incorporated by reference in its entirety.

[0002] The present invention relates generally to the field of video compression. In particular, the present invention is directed to signaling global motion vectors in picture headers. [Background technology]

[0003] A video codec may include electronic circuitry or software that compresses or decompresses digital video. It can convert uncompressed video into a compressed format, or vice versa. In the context of video compression, a device that compresses video (and / or performs some function thereof) may typically be called an encoder, and a device that decompresses video (and / or performs some function thereof) may be called a decoder. Summary of the Invention [Means for solving the problem]

[0004] In one aspect, the decoder includes circuitry configured to receive the bitstream, extract the header, use the header to determine a global motion model, and decode the current block of the current frame using the global motion model.

[0005] In another aspect, a method includes receiving, by a decoder, a bitstream. The method includes extracting a header from the bitstream. The method includes determining a global motion model using the header. The method includes decoding a current block of a current frame using the global motion model.

[0006] The details of one or more variations of the subject matter described herein are set forth in the accompanying drawings and the description below. Other features and advantages of the subject matter described herein will be apparent from the description and drawings, and from the claims. The present specification also provides, for example, the following items: (Item 1) 1. A decoder, comprising: A circuitry comprising: receiving a bitstream; Extracting the header; determining a global motion model using said header; decoding a current block of a current frame using the global motion model; A circuit network configured to: A decoder comprising: (Item 2) 2. The decoder of claim 1, wherein the header includes a picture parameter set or a sequence parameter set. (Item 3) 2. The decoder of claim 1, wherein the header includes a flag that characterizes whether global motion is present for the current block. (Item 4) 2. The decoder of claim 1, wherein the header includes at least one parameter of the global motion model. (Item 5) 5. The decoder of claim 4, wherein the at least one parameter includes a control point motion vector. (Item 6) 6. The decoder of claim 5, wherein the control point motion vectors include translational motion vectors. (Item 7) 2. The decoder of claim 1, wherein the global motion model includes a translational motion model. (Item 8) 2. The decoder of claim 1, wherein the global motion model comprises a four-parameter affine motion model. (Item 9) Item 2. The decoder of item 1, wherein the global motion model includes a six-parameter affine motion model. (Item 10) an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transform processor, the inverse quantization and inverse transform processor configured to process the quantized coefficients including performing an inverse discrete cosine; A deblocking filter; A frame buffer; Intra prediction processor Item 1. The decoder of item 1, further comprising: (Item 11) 2. The decoder of claim 1, wherein the current block forms part of a quadtree+binary decision tree. (Item 12) 2. The decoder of claim 1, wherein the current block is a coding tree unit, a coding unit, or a prediction unit. (Item 13) 1. A method, comprising: receiving, by a decoder, a bitstream; extracting a header from the bitstream; determining a global motion model using said header; decoding a current block of a current frame using the global motion model; A method comprising: (Item 14) Item 14. The method according to item 13, wherein the header includes a picture parameter set or a sequence parameter set. (Item 15) Item 14. The method of item 13, wherein the header includes a flag that characterizes whether global motion is present for the current block. (Item 16) Item 14. The method according to item 13, wherein the header includes at least one parameter of the global motion model. (Item 17) Item 17. The decoder of item 16, wherein the at least one parameter includes a control point motion vector. (Item 18) 20. The method of claim 17, wherein the control point motion vector comprises a translational motion vector. (Item 19) 14. The method of claim 13, wherein the global motion model includes a translational motion model. (Item 20) 14. The method of claim 13, wherein the global motion model includes a four-parameter affine motion model. (Item 21) 14. The method of claim 13, wherein the global motion model includes a six-parameter affine motion model. (Item 22) The decoder further comprises: an entropy decoder processor configured to receive the bitstream and decode the bitstream into quantized coefficients; an inverse quantization and inverse transform processor, the inverse quantization and inverse transform processor configured to process the quantized coefficients including performing an inverse discrete cosine; A deblocking filter; A frame buffer; Intra prediction processor Item 14. The method of item 13, comprising: (Item 23) 12. The method of claim 11, wherein the current block forms part of a quadtree+binary decision tree. (Item 24) Item 12. The decoder of item 11, wherein the current block is a coding tree unit, a coding unit, or a prediction unit. [Brief description of the drawings]

[0007] For the purpose of illustrating the invention, the drawings show aspects of one or more embodiments of the invention, it being understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown in the drawings.

[0008] [Figure 1] FIG. 1 is a diagram illustrating motion vectors of an example frame with global and local motion.

[0009] [Diagram 2] FIG. 2 illustrates three example motion models that may be utilized for global motion, including their index values ​​(0, 1, or 2).

[0010] [Diagram 3] FIG. 3 is a process flow diagram according to some example implementations of the present subject matter.

[0011] [Figure 4] FIG. 4 is a system block diagram of an example decoder in accordance with some example implementations of the present subject matter.

[0012] [Diagram 5] FIG. 5 is a process flow diagram according to some example implementations of the present subject matter.

[0013] [Figure 6] FIG. 6 is a system block diagram of an example encoder in accordance with some example implementations of the present subject matter.

[0014] [Figure 7]FIG. 7 is a block diagram of a computing system that may be used to implement any one or more of the methodologies disclosed herein and any one or more portions thereof.

[0015] The drawings are not necessarily to scale and may be illustrated by phantom lines, schematic representations, and partial views. In some instances, details that are not necessary for an understanding of the embodiments or that make other details difficult to perceive may be omitted. Like reference symbols in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Global motion in video refers to motion that occurs in the entire frame. Global motion may be caused by camera motion, such as, but not limited to, camera panning and zooming, generating motion within a frame that may typically affect the entire frame. Motion that is present within a portion of a video may be referred to as local motion. Local motion may be caused by moving objects in a scene, for example, but not limited to, local motion may be caused by an object moving from left to right in a scene. Video may contain a combination of local and global motion. Some implementations of the present subject matter may provide an efficient approach for communicating global motion to a decoder and the use of global motion vectors in improving compression efficiency.

[0017] FIG. 1 is a diagram illustrating an example embodiment of motion vectors of an example frame 100 with global and local motion. Frame 100 may include several blocks of pixels, illustrated as squares, and their associated motion vectors, illustrated as arrows. Squares (e.g., blocks of pixels) with arrows pointing to the upper left indicate blocks with motion that may be considered to be global motion, and squares with arrows pointing in the other direction (indicated by 104) indicate blocks with local motion. In the illustrated example of FIG. 1, many of the blocks have the same global motion. Signaling global motion in a header, such as a picture parameter set (PPS) or sequence parameter set (SPS), and using the signal global motion may reduce the motion vector information required by blocks, resulting in improved prediction. For illustrative purposes, the embodiments described below refer to determining and / or applying global or local motion vectors at the block level, although global motion vectors may be determined and / or applied with respect to any region of a frame and / or picture (including, but not limited to, a region comprised of multiple blocks, a region bounded by any geometric form, such as, but not limited to, a region defined by geometric and / or exponential coding, in which one or more lines and / or curves bounding a shape may be angled and / or curved, and / or the entire frame and / or picture). Although signaling is described herein as being performed at the frame level and / or within the header and / or frame parameter set, signaling may alternatively or additionally be performed at a sub-picture level, where a sub-picture may include any region of a frame and / or picture as described above.

[0018] As an example, and with continued reference to FIG. 1, a simple translational motion is expressed as a two-component MV that describes the amount of block and / or pixel displacement within the current frame. x , M.V. yMore complex motions such as rotation, magnification, and warping may be described using affine motion vectors, where an "affine motion vector" as used in this disclosure is a vector that describes the uniform displacement of a set of pixels or points, such as a video picture and / or a set of pixels that illustrate an object represented within a picture that moves across a field of view in a video without changing its apparent shape during the motion. Some approaches to video encoding and / or decoding may use a four-parameter or six-parameter affine model for motion compensation in inter-picture coding. For example, still referring to FIG. 1, a six-parameter affine motion model may describe affine motion as follows: x'=ax+by+c y'=dx+ey+f The four-parameter affine motion can be described as follows. x'=ax+by+c y'=-bx+ay+f

[0019] where (x,y) and (x',y') are pixel locations in the current and reference pictures, respectively, and a, b, c, d, e, and f may represent parameters of an affine motion model.

[0020] Continuing with reference to FIG. 1, parameters used to describe affine motion are signaled to a decoder to apply affine motion compensation at the decoder. In some approaches, the motion parameters may be signaled explicitly or by signaling translational control point motion vectors (CPMVs) and then deriving affine motion parameters from the translational motion vectors. Two control point motion vectors (CPMVs) may be utilized to derive affine motion parameters for a four-parameter affine motion model, and three control point translational motion vectors (CPMVs) may be utilized to obtain parameters for a six-parameter motion model. Signaling affine motion parameters using control point motion vectors may enable the use of efficient motion vector coding methods to signal affine motion parameters.

[0021] In some implementations, and still referring to FIG. 1, signaling of global motion may be included in a header such as a PPS or SPS. Global motion may vary between pictures. Motion vectors signaled in the picture header may describe motion relative to previously decoded frames. In some implementations, global motion may be translational or affine. The motion model used (e.g., number of parameters, whether the model is affine, translational, or other) may also be signaled in the picture header.

[0022] Referring now to FIG. 2, three non-limiting exemplary embodiments of a motion model 200 that may be utilized for global motion, including their index values ​​(0, 1, or 2), are illustrated.

[0023] Still referring to Figure 2, the PPS may be used to signal parameters that change between pictures of a sequence. Parameters that remain the same for a sequence of pictures may be signaled in a sequence parameter set to reduce the size of the PPS and reduce the video bit rate. An exemplary picture parameter set (PPS) is shown in Table 1. [Table 1-1] [Table 1-2] [Table 1-3] [Table 1-4] [Table 1-5]

[0024] Continuing with reference to FIG. 2, additional fields may be added to the PPS to signal global motion. In case of global motion, the presence of global motion parameters in a sequence of pictures may be signaled in the SPS, and the PPS may reference the SPS by an SPS ID. The SPS may be modified to add a field to signal the presence of global motion parameters in the SPS in some approaches to decoding. For example, a 1-bit field may be added to the SPS. If the global_motion_present bit is 1, global motion related parameters may be expected to be in the PPS. If the global_motion_present bit is 0, global motion parameter related fields may not be present in the PPS. For example, a PPS as illustrated in Table 1 may be extended to include a global_motion_present field as shown in Table 2, for example. [Table 2]

[0025] Similarly, still referring to FIG. 2, the PPS may include a pps_global_motion_parameters field for the frame, eg, as shown in Table 3. [Table 3]

[0026] More specifically, with continued reference to FIG. 2, the PPS may include fields for characterizing global motion parameters, for example using control point motion vectors as shown in Table 4. [Table 4]

[0027] As a further non-limiting example, Table 5 below may represent an exemplary SPS. [Table 5-1] [Table 5-2] [Table 5-3] [Table 5-4] [Table 5-5] [Table 5-6] [Table 5-7] [Table 5-8]

[0028] An SPS table such as the one above may be extended as described above to incorporate a global motion presence indicator such as that shown in Table 6. [Table 6-1] [Table 6-2]

[0029] Additional fields may be incorporated within the SPS to reflect further indicators as described within this disclosure.

[0030] In an embodiment, still referring to FIG. 2, sps_affine_enabled_flag may specify whether affine model-based motion compensation may be used for inter prediction. If sps_affine_enabled_flag is equal to 0, the syntax may be constrained such that affine model-based motion compensation is not used in a coded video sequence (CLVS), and inter_affine_flag and cu_affine_type_flag may not be present in the coding unit syntax of the CLVS. Otherwise (sps_affine_enabled_flag is equal to 1), affine model-based motion compensation may be used in the CLVS.

[0031] Continuing with reference to FIG. 2, sps_affine_type_flag may specify whether 6-parameter affine model-based motion compensation may be used for inter prediction. If ps_affine_type_flag is equal to 0, the syntax may be constrained such that 6-parameter affine model-based motion compensation is not used in CLVS, and cu_affine_type_flag may not be present in the coding unit syntax of CLVS. Otherwise (sps_affine_type_flag is equal to 1), 6-parameter affine model-based motion compensation may be used in CLVS. When not present, the value of sps_affine_type_flag may be inferred to be equal to 0.

[0032] Still referring to FIG. 2, translational CPMV may be signaled within the PPS. Control points may be predefined. For example, control point MV 0 may be relative to the top left corner of the picture, MV 1 may be relative to the top right corner, and MV 3 may be relative to the bottom left corner of the picture. Table 4 illustrates an example approach for signaling CPMV data depending on the motion model used.

[0033] In an example embodiment, still referring to FIG. 2, an array amvr_precision_idx, which may be signaled within a coding unit, coding tree, or equivalent, may specify a resolution of motion vector differences AmvrShift, which may be defined as a non-limiting example as shown in Table 7 as shown below. The array indexes x0, y0 may specify the location (x0, y0) of the top-left luma sample of the considered coding block relative to the top-left luma sample of the picture, and when amvr_precision_idx[x0][y0] is absent, it may be inferred to be equal to 0. When inter_affine_flag[x0][y0] is equal to 0, the variables MvdL0[x0][y0][0], MvdL0[x0][y0][1], MvdL1[x0][y0][0], MvdL1[x0][y0][1], which represent the motion vector difference values ​​corresponding to the considered block, may be, for example, [ka] If inter_affine_flag[x0][y0] is equal to 1, then the variables MvdCpL0[x0][y0][0][0], MvdCpL0[x0][y0][0][1], MvdCpL0[x0][y0][1][0], MvdCpL0[x0][y0][1][1], MvdCpL0[x0][y0][2][0], and MvdCpL0[x0][y0][2][1] may be modified, for example, to the following, i.e. [ka] [ka] The shifting step may be modified as follows: [Table 7]

[0034] Continuing with reference to Figure 2, the global motion may be relative to a previously coded frame. When only one set of global motion parameters is present, the motion may be relative to a frame presented immediately before the current frame.

[0035] FIG. 3 is a process flow diagram illustrating an example process 300 for signaling a global motion model for decoding that may improve compression efficiency.

[0036] At step 305, still referring to FIG. 3, a bitstream is received by the decoder. A current block may be contained within the bitstream received by the decoder. The bitstream may include data found in a stream of bits that is, for example, an input to the decoder when using data compression. The bitstream may include information necessary to decode the video. The receiving step may include extracting and / or parsing the block and associated signaling information from the bitstream. In some implementations, the current block may include a coding tree unit (CTU), a coding unit (CU), or a prediction unit (PU). At step 310, a header may be extracted from the bitstream. At step 315, a global motion model may be determined using the header, and the determination of the global motion model may be performed as described above, including by determination as signaled within the PPS and / or SPS. At step 320, the current block of the current frame may be decoded using the determined global motion model.

[0037] 4 is a system block diagram illustrating an example decoder 400 capable of decoding a bitstream 428 using global motion model signaling, which may improve compression efficiency. The decoder 400 may include an entropy decoder processor 404, an inverse quantization and inverse transform processor 408, a deblocking filter 412, a frame buffer 416, a motion compensation processor 420, and an intra prediction processor 424.

[0038] In operation, still referring to FIG. 4, a bitstream 428 may be received by the decoder 400 and input to the entropy decoder processor 404, which entropy decodes a portion of the bitstream into quantized coefficients. The quantized coefficients may be provided to the inverse quantization and inverse transform processor 408, which may perform inverse quantization and inverse transform and generate a residual signal, which may be added to the output of the motion compensation processor 420 or the intra prediction processor 424, depending on the processing mode. The output of the motion compensation processor 420 and the intra prediction processor 424 may include block predictions based on previously decoded blocks. The sum of the predictions and residuals may be processed by the deblocking filter 630 and stored in the frame buffer 640.

[0039] FIG. 5 is a process flow diagram illustrating an example process 500 for encoding video using global motion signaling, which may improve compression efficiency according to some aspects of the present subject matter. In step 505, a video frame may undergo initial block segmentation, for example, using a tree-structured macroblock partitioning scheme, which may include partitioning the picture frame into CTUs and CUs. In step 510, a global motion for a current block may be determined. Determining the global motion may include determining a global motion model and associated parameters. In step 515, the global motion model, associated parameters, and block may be encoded and included in a bitstream. The encoding may include, for example, utilizing inter-prediction and intra-prediction modes.

[0040] FIG. 6 is a system block diagram illustrating an example video encoder 600 capable of signaling global motion, which may improve compression efficiency. The example video encoder 600 may receive an input video 604, which may first be segmented or divided according to a processing scheme such as a tree-structured macroblock partitioning scheme (e.g., quadtree+binarytree). An example of a tree-structured macroblock partitioning scheme may include partitioning a picture frame into large block elements called coding tree units (CTUs). In some implementations, each CTU may be further partitioned one or more times into several sub-blocks, called coding units (CUs). The end result of this partitioning may include a group of sub-blocks, which may be called prediction units (PUs). Transform units (TUs) may also be utilized.

[0041] 6, the exemplary video encoder 600 may include an intra-prediction processor 608, a motion estimation / compensation processor 612 (also referred to as an inter-prediction processor), which may assist in signaling and processing global motion, a transform / quantization processor 616, an inverse quantization / inverse transform processor 620, an in-loop filter 624, a decoded picture buffer 628, and / or an entropy coding processor 632. Bitstream parameters may be input to the entropy coding processor 632 for inclusion in an output bitstream 636.

[0042] In operation, and with further reference to Figure 6, for each block of a frame of the input video 604, it may be determined whether to process the block via intra-picture prediction or using motion estimation / compensation. The block may be provided to an intra-prediction processor 608 or a motion estimation / compensation processor 612. If the block is to be processed via intra-prediction, the intra-prediction processor 608 may perform processing and output a predictor. If the block is to be processed via motion estimation / compensation, the motion estimation / compensation processor 612 may perform processing, including signaling of global motion, if applicable.

[0043] Still referring to FIG. 6, a residual may be formed by subtracting the predictor from the input video. The residual may be received by a transform / quantization processor 616, which may perform a transform process (e.g., a discrete cosine transform (DCT)) to produce coefficients, which may be quantized. The quantized coefficients and any associated signaling information may be provided to an entropy coding processor 632 for entropy encoding and inclusion in an output bitstream 636. The entropy encoding processor 632 may assist in encoding signaling information related to encoding the current block. In addition, the quantized coefficients may be combined with the predictor and provided to an inverse quantization / inverse transform processor 620, which may reconstruct pixels that may be processed by an in-loop filter 624, the output of which may be stored in a decoded picture buffer 628 for use by a motion estimation / compensation processor 612, which is capable of signaling and processing global motion.

[0044] Although some variations have been described in detail above, other modifications or additions are possible. For example, in some implementations, the current block may include any symmetric block (8×8, 16×16, 32×32, 64×64, 128×128, and the like) and any asymmetric block (8×4, 16×8, and the like).

[0045] In some implementations, a quad-tree plus binary decision tree (QTBT) may be implemented, where at the coding tree unit level, the partition parameters of the QTBT are dynamically derived to fit local characteristics without transmitting any overhead. Then, at the coding unit level, a joint classifier decision tree structure may eliminate unnecessary iterations and control the risk of erroneous prediction. In some implementations, an LTR frame block update mode may be available as an additional option available per leaf node of the QTBT.

[0046] In some implementations, additional syntax elements may be signaled at different hierarchical levels of the bitstream. For example, a flag may be enabled throughout a sequence by including an enabled flag coded in a sequence parameter set (SPS). Additionally, a CTU flag may be coded at the coding tree unit (CTU) level.

[0047] It should be noted that any one or more of the aspects and embodiments described herein may be conveniently implemented using digital electronic circuitry, integrated circuitry, specially designed application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), computer hardware, firmware, software, and / or combinations thereof, as realized and / or implemented in one or more machines (e.g., one or more computing devices utilized as user computing devices for electronic documents, one or more server devices, such as document servers, etc.) programmed according to the teachings herein, as would be apparent to one skilled in the computer arts. These various aspects or features may include implementation in one or more computer programs and / or software executable and / or interpretable on a programmable system including at least one programmable processor, which may be special purpose or general purpose, coupled to receive data and instructions from and transmit data and instructions to a storage system, at least one input device, and at least one output device. Appropriate software coding may be readily prepared by skilled programmers based on the teachings of the present disclosure, as would be apparent to one skilled in the software arts. The aspects and implementations discussed above that employ software and / or software modules may also include suitable hardware to assist in implementing the machine-executable instructions of the software and / or software modules.

[0048] Such software may be a computer program product employing a machine-readable storage medium. A machine-readable storage medium may be any medium capable of storing and / or encoding a sequence of instructions for execution by a machine (e.g., a computing device) and causing the machine to perform any one of the methodologies and / or embodiments described herein. Examples of machine-readable storage media include, but are not limited to, magnetic disks, optical disks (e.g., CDs, CD-Rs, DVDs, DVD-Rs, etc.), magneto-optical disks, read-only memory "ROM" devices, random access memory "RAM" devices, magnetic cards, optical cards, solid-state memory devices, EPROMs, EEPROMs, programmable logic devices (PLDs), and / or any combination thereof. Machine-readable media, as used herein, is intended to include a single medium as well as a collection of physically separate media, such as, for example, a collection of compact discs or one or more hard disk drives in combination with a computer memory. As used herein, machine-readable storage media does not include a transitory form of signal transmission.

[0049] Such software may also include information (e.g., data) carried as a data signal on a data carrier, such as a carrier wave. For example, machine-executable information may be included as a data carrying signal embodied in a data carrier, which signal encodes a sequence of instructions, or a portion thereof, for execution by a machine (e.g., a computing device), and any associated information (e.g., data structures and data) that causes the machine to perform any one of the methodologies and / or embodiments described herein.

[0050] Examples of computing devices include, but are not limited to, e-book reading devices, computer workstations, terminal computers, server computers, handheld devices (e.g., tablet computers, smart phones, etc.), web appliances, network routers, network switches, network bridges, any machine capable of executing a sequence of instructions that define actions to be taken by the machine, and any combination thereof. In one embodiment, the computing device may include and / or be included within a kiosk.

[0051] 7 shows a diagrammatic representation of one embodiment of a computing device in the exemplary form of a computer system 700 on which a set of instructions for causing a control system to perform any one or more of the aspects and / or methodologies of the present disclosure may be executed. It is also envisioned that multiple computing devices may be utilized to implement a specially configured set of instructions for causing one or more of the devices to perform any one or more of the aspects and / or methodologies of the present disclosure. The computer system 700 includes a processor 704 and a memory 708 that communicate with each other and with other components via a bus 712. The bus 712 may include any of several types of bus structures, including, but not limited to, a memory bus, a memory controller, a peripheral bus, a local bus, and any combination thereof, using any of a variety of bus architectures.

[0052] Memory 708 may include a variety of components (e.g., machine-readable media), including, but not limited to, random access memory components, read-only components, and any combination thereof. In one embodiment, a basic input / output system 716 (BIOS), including the basic routines that help to transfer information between elements within computer system 700, such as during start-up, may be stored in memory 708. Memory 708 may also include (e.g., stored on one or more machine-readable media) instructions (e.g., software) 720 that embody any one or more of the aspects and / or methodologies of the present disclosure. In another embodiment, memory 708 may further include any number of program modules, including, but not limited to, an operating system, one or more application programs, other program modules, program data, and any combination thereof.

[0053] Computer system 700 may also include a storage device 724. Examples of storage devices (e.g., storage device 724) include, but are not limited to, hard disk drives, magnetic disk drives, optical disk drives in combination with optical media, solid-state memory devices, and any combination thereof. Storage device 724 may be connected to bus 712 by an appropriate interface (not shown). Exemplary interfaces include, but are not limited to, SCSI, Advanced Technology Attachment (ATA), Serial ATA, Universal Serial Bus (USB), IEEE 1394 (FIREWIRE®), and any combination thereof. In one embodiment, storage device 724 (or one or more components thereof) may be removably interfaced with computer system 700 (e.g., via an external port connector (not shown)). In particular, storage device 724 and associated machine-readable media 728 may provide non-volatile and / or volatile storage of machine-readable instructions, data structures, program modules, and / or other data for computer system 700. In one embodiment, the software 720 may reside, completely or partially, within the machine-readable medium 728. In another embodiment, the software 720 may reside, completely or partially, within the processor 704.

[0054] Computer system 700 may also include input devices 732. In one embodiment, a user of computer system 700 may type commands and / or other information into computer system 700 via input devices 732. Examples of input devices 732 include, but are not limited to, alphanumeric input devices (e.g., keyboards), pointing devices, joysticks, gamepads, audio input devices (e.g., microphones, voice response systems, etc.), cursor control devices (e.g., mice), touchpads, optical scanners, video capture devices (e.g., still cameras, video cameras), touch screens, and any combination thereof. Input devices 732 may be interfaced to bus 712 via any of a variety of interfaces (not shown), including, but not limited to, a serial interface, a parallel interface, a game port, a USB interface, a FIREWIRE® interface, an interface directly to bus 712, and any combination thereof. Input devices 732 may include a touch screen interface, which may be part of or separate from display 736, discussed further below. The input device 732 may be utilized as a user selection device for selecting one or more graphical representations within a graphical interface such as those described above.

[0055] A user may also input commands and / or other information to computer system 700 via storage device 724 (e.g., a removable disk drive, flash drive, etc.) and / or network interface device 740. A network interface device, such as network interface device 740, may be utilized to connect computer system 700 to one or more of a variety of networks, such as network 744, and one or more remote devices 748 connected thereto. Examples of network interface devices include, but are not limited to, a network interface card (e.g., a mobile network interface card, a LAN card), a modem, and any combination thereof. Examples of networks include, but are not limited to, a wide area network (e.g., the Internet, a corporate network), a local area network (e.g., a network associated with an office, a building, a campus, or other relatively small geographic space), a telephone network, a data network associated with a telephone / voice provider (e.g., a data and / or voice network of a mobile communications provider), a direct connection between two computing devices, and any combination thereof. A network, such as network 744, may employ wired and / or wireless modes of communication. In general, any network topology may be used. Information (eg, data, software 720 , etc.) may be communicated to and / or from computer system 700 via network interface device 740 .

[0056] Computer system 700 may further include a video display adapter 752 for communicating images displayable on a display device, such as display device 736. Examples of display devices include, but are not limited to, a liquid crystal display (LCD), a cathode ray tube (CRT), a plasma display, a light emitting diode (LED) display, and any combination thereof. Display adapter 752 and display device 736 may be utilized in combination with processor 704 to provide graphical representations of aspects of the disclosure. In addition to a display device, computer system 700 may include one or more other peripheral output devices, including, but not limited to, audio speakers, a printer, and any combination thereof. Such peripheral output devices may be connected to bus 712 via a peripheral interface 756. Examples of peripheral interfaces include, but are not limited to, a serial port, a USB connection, a FIREWIRE® connection, a parallel connection, and any combination thereof.

[0057] The foregoing is a detailed description of exemplary embodiments of the present invention. Various modifications and additions may be made without departing from the spirit and scope of the present invention. Each feature of the various embodiments described above may be combined with features of other described embodiments as appropriate to provide a combination of features in a related new embodiment. Furthermore, while the foregoing describes several separate embodiments, what is described herein is merely illustrative of the application of the principles of the present invention. In addition, although certain methods herein may be illustrated and / or described as being performed in a specific order, the order may be highly variable among those skilled in the art to achieve the embodiments as disclosed herein. Thus, the present description is intended to be taken as an example only, and is not intended to otherwise limit the scope of the present invention.

[0058] In the above description and in the claims, phrases such as "at least one of" or "one or more of" may occur and be followed by a conjunctive enumeration of elements or features. The term "and / or" may also occur within a list of two or more elements or features. Unless otherwise implied or expressly contradicted by the context in which such a phrase is used, this is intended to mean any of the elements or features listed individually or any of the recited elements or features in combination with any of the other recited elements or features. For example, the phrases "at least one of A and B," "one or more of A and B," and "A and / or B" are intended to mean "A alone, B alone, or A and B together," respectively. A similar interpretation is also intended with respect to lists containing more than two items. For example, the phrases "at least one of A, B, and C," "one or more of A, B, and C," and "A, B, and / or C" are intended to mean "A alone, B alone, C alone, A and B together, A and C together, B and C together, or A and B and C together." Additionally, use of the term "based on" above and in the claims is intended to mean "based at least on," such that unrecited features or elements are also permissible.

[0059] The subject matter described herein may be embodied in a system, an apparatus, a method, and / or an article, depending on the desired configuration. The implementations described in the foregoing description do not represent all implementations consistent with the subject matter described herein. Instead, they are merely some examples consistent with aspects related to the subject matter described. Although some variations have been described in detail above, other modifications or additions are possible. In particular, further features and / or variations may be provided in addition to those described herein. For example, the implementations described above may be directed to various combinations and subcombinations of the disclosed features and / or combinations and subcombinations of some further features disclosed above. In addition, the logic flow depicted in the accompanying figures and / or described herein does not necessarily require the particular order shown or sequential order to achieve the desired results. Other implementations may be within the scope of the following claims.

Claims

1. A video encoder for encoding a bitstream for decoding by a video decoder, the bitstream including a coded picture, the coded picture including a first region having a first plurality of contiguous coding blocks having global motion and a second region having a second plurality of contiguous coding blocks having local motion, the video decoder comprising: A circuitry comprising: receiving the bitstream; and For each current block in the first region: Extracting the headers, determining a motion model using the header, the motion model being common to all of the blocks in the first region, the motion model being one of translational motion, four-parameter affine motion, or six-parameter affine motion, and parameters for the motion model for each current block in the first region being determined from control point motion vectors signaled in the bitstream; and reconstructing the global motion within the first region by decoding each current block within the first region of the current frame using the parameters of the motion model. and For each block in the second region, reconstructing the local motion within the second region by decoding each block using motion information determined individually for each block; A circuit network configured to: A video encoder comprising:

2. The encoder of claim 1 , wherein the bitstream further comprises a header, the header comprising a picture parameter set or a sequence parameter set.

3. The encoder of claim 2 , wherein the header includes a flag that characterizes whether global motion is present for the current block.

4. The encoder of claim 1 , wherein the current block forms part of a quad-tree plus binary decision tree.

5. The encoder of claim 1 , wherein the current block is a coding tree unit, a coding unit, or a prediction unit.

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