Automatic breaker synchronizer

Abstract

A breaker is provided between two electrical circuits that closes if the electrical characteristics of the two electrical circuits match. Two check circuits are provided for comparing the electrical characteristics of the two electrical circuits. Each of the check circuits sets a corresponding permission for closing the breaker. The breaker closes only if both check circuits set permission for closing the circuit.

Description

[Technical field]

[0001] The present invention relates generally to breakers, and more particularly to synchronizing a breaker between a generator and a power grid.

[0002] A power plant is connected to the power grid at a main breaker. Many power plants employ large steam turbines to generate electricity. If the breaker is closed when the voltage and frequency of the power plant and the grid are not compatible, serious damage to equipment and potential physical injury to nearby personnel may occur. For example, if the voltage and frequency of the power plant and the grid are not compatible when the breaker is closed, the breaker is typically reopened immediately to isolate the power plant from the grid. However, such reopening of the circuit breaker may cause a catastrophic reaction or an explosion-like event. If the circuit breaker is not reopened in such an event, the voltage and / or frequency mismatch may result in rapid acceleration of the generator to match the grid, and such rapid acceleration of the generator and connected hardware (e.g., turbine) may cause equipment damage or sudden failure.

[0003] Summary of the Invention A system is described for connecting two electric circuits together while ensuring that the electrical characteristics of each of the circuits are compatible. The system includes two check circuits that must both set permission to close a breaker. The first electric circuit may be an electric power grid and the second electric circuit may be a generator. The electrical characteristics may be the voltage and frequency of each of the electric circuits.

[0004] The invention can be more fully understood from the following description taken in conjunction with the drawings, in which: [Brief description of the drawings]

[0005] [Figure 1]FIG. 1 is a block diagram of two separate circuits 10, 14, 18 and 12, 16, 20 for controlling the closure of a breaker 102 between two electrical circuits 98, 100. [Diagram 2] FIG. 1 is a schematic diagram of two derivation circuits 30, 32 for converting an electrical waveform 34 of a first electrical circuit 98 into an average voltage 38 and a frequency phase signal 40, and for converting an electrical waveform 36 of a second electrical circuit 100 into an average voltage 42 and a frequency phase signal 44. [Diagram 3] FIG. 1 is a schematic diagram of two derivation circuits 46, 48 for converting an electrical waveform 34 of a first electrical circuit 98 into an average voltage 50 and a frequency phase signal 52, and for converting an electrical waveform 36 of a second electrical circuit 100 into an average voltage 54 and a frequency phase signal 56. [Figure 4] FIG. 2 is a schematic diagram of two voltage circuits 58, 60 for forming reference voltages 62, 64 for use in A / D circuits 66, 68. [Diagram 5] 1 is a diagram of A / D circuits 66, 68 that convert the average voltages 38, 42, 50, 54 into digital voltage signals 70, 72 that are used by a first processor 74 and a second processor 76, respectively. [Figure 6] 1 is a schematic diagram of a first processor 74 and a second processor 76 each having an input and an output. [Figure 7] Schematic diagram of a drive circuit 86 that uses output 80 from a first processor 74 to send a signal 88 to a second electrical circuit 100, causing electrical characteristics (e.g., voltage or frequency, such as for speed adjustment) to change to suit the first electrical circuit 98. [Figure 8] FIG. 1 is a schematic diagram of two driver circuits 90, 92 that use outputs 82, 84 from a first processor 74 and a second processor 76 to send signals 94, 96 to relays 104, 106 for opening and closing the relays. [Figure 9] 1 is a schematic diagram of a breaker 102 disposed between two electrical circuits 98, 100, and two relays 104, 106 wired in series to close the breaker 102 when the relays 104, 106 are closed.

[0006] Detailed Description The purpose of the automatic synchronizer is to close the breaker between the generator and the power grid, taking into account the voltage and frequency of the two systems. When the generator voltage and frequency are approximately matched to the grid and the phase between the two grids is aligned, the module initiates a breaker close command. If a breaker close command occurs when these parameters are not matched, it can cause serious damage to the equipment and create a potentially dangerous situation for people in the vicinity of the equipment. To prevent this from happening, an external "sync check" relay is often installed. In the preferred embodiment, a built-in redundant electrical circuit is provided to reduce the risk in the event of a component failure. The redundant circuit provides the same functionality as the primary synchronizing circuit, but is designed differently by being implemented in an FPGA and uses different firmware written in a different programming language. The versatility behind the design of the built-in sync check function eliminates the possibility of a common design flaw. The sync check circuit acts as an enabler that prevents the breaker from closing if the two circuits do not agree that the correct conditions for breaker closing exist.

[0007] In the preferred embodiment, two separate logic paths, separate measurement and output, separate check measurement and output, communication and processing, and separate check processing are provided. For safety, each bus input is connected to two identical and separate analog circuits, each terminating with a separate ADC. The ADCs are connected to separate processors and run separate algorithms to detect frequency, phase, and voltage compatibility between the buses. For safety, DO1 is driven from a physical and logical source separate from DO2. AS01 is equipped with an additional processor responsible for independently monitoring the bus inputs and indicating whether it is safe to close the breaker (based on the configuration). The processor receives inputs from the separate analog circuits and the ADC and issues an independent digital output signal. The main breaker control function of AS01 monitors the state of the digital output controlled by the independent synchronous check function, and will not initiate breaker closure if the independent check digital output is not active, even if it determines that the breaker closure condition is met.

[0008] In the preferred embodiment, two separate (independent) input circuits are used. There are two separate and different processors. In the preferred embodiment, the microprocessor (MCF54415) and the FPGA are the two processors. This eliminates common processor glitches. Two separate and different firmware codes are used to eliminate common software bugs. The preferred embodiment uses two, C code and VHDL code. Each firmware cooperates with the other to ensure that the current state matches the course of action. If the two executions do not match, each processor disables the breaker closure until the condition is corrected. Two separate (independent) output circuits are used, whereby the two output circuits must match before the breaker closure is initiated. Some type of external enabling action is required, either by a human or by controller logic.

[0009] FIG. 1 shows a diagram of two separate logical paths communicating for diagnostic purposes.

[0010] In a preferred embodiment, two separate circuits are provided that are independent of each other with separate input and output sources, and additionally each circuit verifies the other circuit.

[0011] 2-9 show two separate circuits. Preferably, one circuit uses a microprocessor for control operations and the other circuit preferably uses an FPGA for control operations. Thus, the two circuits are not susceptible to design flaws that may affect all circuits in a compatible design.

[0012] The improvement of the preferred embodiment is full and multi-faceted redundancy and intercommunication between the two implementations. In some conventional systems, there is either a single circuit or a duplicate circuit with similar logic to initiate the closure of a breaker. In the preferred embodiment, different circuit designs, different processors (e.g., microprocessors vs. FPGAs), different programming codes and languages ​​are provided to provide full and multi-faceted redundancy. Other conventional approaches may have redundancy but include similar circuits that may have common defects or fail under similar conditions.

[0013] The primary application of the preferred embodiment is in power generation plants with a main breaker between the generator and the power grid. Such an application is referred to as the line generator mode. However, there are other applications for switch yard use, peer-to-peer bus connections, and dead bus applications. The preferred embodiment also covers the same or similar redundancy and protection methods for these other applications.

[0014] The improvements of the preferred embodiment prevent inadvertent generator breaker closure from a single component failure (or failure of multiple components in a similar redundant circuit) when the voltage, frequency, and phase of the two buses are mismatched, which can cause serious equipment damage and result in a dangerous situation. Additionally, the logic notifies an operator that a mismatch or failure exists so that the problem can be resolved in a timely manner.

[0015] An advantage of the preferred embodiment is that it reduces the risk of untimely breaker closure. Another advantage is that it notifies the user that a component failure may exist. Another advantage is that it reduces the risk of damage to equipment. Another advantage is that it reduces the risk of injury to personnel.

[0016] An improvement of the preferred embodiment is to provide separate and distinct electrical circuits, processors, and firmware, eliminating the risk of common design flaws. In the preferred embodiment, AND logic is used so that the two must match before allowing the breaker to close. Additionally, the two designs monitor each other so that if the two do not match, the module will prevent the breaker from closing and notify the user of a potential component failure.

[0017] In the preferred embodiment, diverse design components such as different processors, firmware and code are used, however, all product components, including critical and non-critical components, may be diverse to eliminate hardware anomalies. Additionally, separate circuits can be designed to provide different design implementations. In the preferred embodiment, a microprocessor and an FPGA are used, however, other types of processors or logic devices can be used as well. Additionally, different communication methods can be used between the two circuits.

[0018] The invention described herein may have any of the features described above, as well as one or more of the following features: The following features are illustrated with reference to the drawings.

[0019] The system for connecting a first electric circuit to a second electric circuit includes a breaker disposed between the first electric circuit and the second electric circuit, the breaker being closed for connection of the first electric circuit and the second electric circuit, a first check circuit for receiving a first electric characteristic measured from the first electric circuit and a second electric characteristic measured from the second electric circuit, and a second check circuit for receiving a third electric characteristic measured from the first electric circuit and a fourth electric characteristic measured from the second electric circuit. 8,30,32,66,74,90 sets a first permission 82,94 to close the breaker 102 if the measured first electrical characteristic 40,70 and the measured second electrical characteristic 44,70 match, and the second check circuit 12,16,20,46,48,68,76,92 sets a second permission 84,96 to close the breaker 102 if the third electrical characteristic 52,72 and the fourth electrical characteristic 56,72 match, and if the first permission 82,94 or the second permission 84,96 are not set to close the breaker 102, the breaker 102 remains open, and if both the first permission 82,94 and the second permission 84,96 are set to close the breaker 102, the breaker 102 is closed.

[0020] The system, wherein the first electrical circuit 98 includes a power supply network.

[0021] The system, wherein the second electrical circuit 100 includes a generator.

[0022] The system, wherein the second electrical circuit 100 further includes a turbine connected to a generator.

[0023] A system in which a first check circuit (10,14,18,30,32,66,74,90) includes a first processor (74) for setting a first permission (82,94), and a second check circuit (12,16,20,46,48,68,76,92) includes a second processor (76) for setting a second permission (84,96), and the first processor (74) and the second processor (76) are different types of processors.

[0024] The system wherein the first processor 74 is a microprocessor 74 and the second processor 76 is a field programmable gate array (FPGA) 76.

[0025] A system in which the first processor 74 is a larger capacity processor than the second processor 76.

[0026] The first processor 74 also determines modifications 80, 86, 88 to be made to the second electrical circuit 100 to match the first electrical characteristics 40, 70 and the second electrical characteristics 44, 70, while the second processor 76 does not determine any modifications to be made to the second electrical circuit 100, in the system.

[0027] A system, wherein a first processor 74 is programmed in a first programming language and a second processor 76 is programmed in a second programming language, the first programming language and the second programming language being different types of programming languages.

[0028] A system, wherein the first programming language is C code and the second programming language is VHDL code.

[0029] The system includes a first derivation circuit 30 that receives the electrical waveform 34 from the first electrical circuit 98 and forms a first measured electrical characteristic 38, 40, 70 that is provided to a first check circuit 66, 74, 90; a second derivation circuit 32 that receives the electrical waveform 36 from the second electrical circuit 100 and forms a second measured electrical characteristic 42, 44, 70 that is provided to the first check circuit 66, 74, 90; and a third derivation circuit 33 that receives the electrical waveform 34 from the first electrical circuit 98 and forms a third measured electrical characteristic 50, 52, 72 that is provided to the second check circuit 68, 76, 92. the first derivation circuit 30, the second derivation circuit 32, the third derivation circuit 46, and the fourth derivation circuit 48 receiving the electrical waveform 36 from the second electrical circuit 100 and forming a measured fourth electrical characteristic 54, 56, 72 which is supplied to the second check circuits 68, 76, 92, the first derivation circuit 30, the second derivation circuit 32, the third derivation circuit 46, and the fourth derivation circuit 48 being redundant matching circuits such that the measured first electrical characteristic 38, 40, 70 and the measured third electrical characteristic 50, 52, 72 are pairs and the measured second electrical characteristic 42, 44, 70 and the measured fourth electrical characteristic 54, 56, 72 are pairs.

[0030] The system further includes a first A / D (analog-to-digital) circuit 66 and a second A / D (analog-to-digital) circuit 68, where the first A / D circuit 66 receives the measured first electrical characteristic 38 and the measured second electrical characteristic 42 and provides corresponding first and second digital signals 70 to a first processor 74, and the second A / D circuit 68 receives the measured third electrical characteristic 50 and the measured fourth electrical characteristic 54 and provides corresponding third and fourth digital signals 72 to a second processor 76, where the first A / D circuit 66 and the second A / D circuit 68 are redundant matching circuits such that the first digital signal 70 and the third digital signal 72 are paired and the second digital signal 70 and the fourth digital signal 72 are paired.

[0031] The first check circuit 10, 14, 18, 30, 32, 66, 74, 90 outputs a close / open signal 94 to the first relay 104 based on the first permission 82, and the second check circuit 12, 16, 20, 46, 48, 68, 76, 92 outputs a close / open signal 96 to the second relay 106 based on the second permission 84, the first relay 104 and the second relay 106 being connected in series such that the breaker 102 can be closed only if both the first relay 104 and the second relay 106 are closed, in the system.

[0032] The system further includes a man-machine interface (HMI) that receives a third permission 78 to close the breaker 102 from a human operator, where if the third permission 78 is not set to close the breaker 102, the breaker 102 remains open, and if the first permission 82, the second permission 84, and the third permission 78 are all set to close the breaker 102, the breaker 102 is closed.

[0033] The first electrical characteristic 40,70 and the third electrical characteristic 52,72 include the voltage 70,72 and frequency 40,52, respectively, of the first electrical circuit 98, and the second electrical characteristic 44,70 and the fourth electrical characteristic 56,72 include the voltage 70,72 and frequency 44,56, respectively, of the second electrical circuit 100 of the system.

[0034] A system in which the first electrical characteristic 40,70 and the third electrical characteristic 52,72 are the same as each other, and the second electrical characteristic 44,70 and the fourth electrical characteristic 56,72 are the same as each other.

[0035] 1, the first circuits 10, 14, 18 may also include other digital inputs 22. For example, the frequency and voltage digital outputs 24, 26 of the two electrical circuits 98, 100 may be used for additional functions by the first processor 14, 74. A communication bus 28 may also be provided for communication with other hardware.

[0036] It will be appreciated that the preferred embodiments described herein can, if desired, be implemented as computerized methods on a non-transitory computer readable medium.

[0037] Although preferred embodiments of the present invention have been described, it should be understood that the present invention is not limited thereto and can be modified without departing from the invention herein. Although each embodiment described herein may be described with reference to certain features only and may not specifically refer to all features described with respect to other embodiments, it should be recognized that each feature described herein is interchangeable unless otherwise stated, even if no reference is made to a certain feature. It should also be understood that the advantages described above are not necessarily the only advantages of the present invention, and that it is not necessarily expected that all of the advantages described will be achieved by each embodiment of the present invention. The scope of the present invention is defined by the appended claims, and all apparatus and methods within the meaning of the claims are intended to be encompassed therein, either by word or by equivalence.

Claims

1. 1. A system for connecting a first electrical circuit to a second electrical circuit, comprising: a breaker disposed between the first electric circuit and the second electric circuit, the breaker being closed to connect the first electric circuit and the second electric circuit; a first check circuit that receives a first electrical characteristic measured from the first electrical circuit and a second electrical characteristic measured from the second electrical circuit; a second check circuit that receives a third electrical characteristic measured from the first electrical circuit and a fourth electrical characteristic measured from the second electrical circuit; Including, the first check circuit sets a first permission for closing the breaker if the measured first electrical characteristic and the measured second electrical characteristic match; the second check circuit sets a second permission for closing the breaker if the third electrical characteristic and the fourth electrical characteristic are compatible; if the first permission or the second permission is not set to close the breaker, the breaker remains open, and if both the first permission and the second permission are set to close the breaker, the breaker is closed; the first electrical circuit includes a power supply network; the second electric circuit includes a generator; The generator is connected to a turbine; the first check circuitry includes a first processor for setting the first permission, and the second check circuitry includes a second processor for setting the second permission, the first processor and the second processor being different types of processors; The system comprises: a first derivation circuit that receives an electrical waveform from the first electrical circuit and forms the measured first electrical characteristic that is provided to the first check circuit; a second derivation circuit that receives an electrical waveform from the second electrical circuit and forms the measured second electrical characteristic that is provided to the first check circuit; a third derivation circuit that receives an electrical waveform from the first electrical circuit and forms the third measured electrical characteristic that is provided to the second check circuit; a fourth derivation circuit that receives an electrical waveform from the second electrical circuit and forms the fourth measured electrical characteristic that is provided to the second check circuit; Further comprising: the first derivation circuit, the second derivation circuit, the third derivation circuit, and the fourth derivation circuit are redundant matching circuits such that the first measured electrical characteristic and the third measured electrical characteristic are paired, and the second measured electrical characteristic and the fourth measured electrical characteristic are paired. system.

2. the first processor is a microprocessor and the second processor is a field programmable gate array (FPGA); The system of claim 1 .

3. The first processor is a processor having a larger capacity than the second processor. The system of claim 1 .

4. the first processor also determines changes to be made to the second electrical circuit to match the first electrical characteristic with the second electrical characteristic, and the second processor does not determine any changes to be made to the second electrical circuit. The system of claim 2.

5. the first processor is programmed in a first programming language and the second processor is programmed in a second programming language, the first programming language and the second programming language being different programming languages; The system of claim 1 .

6. the first programming language is C code and the second programming language is VHDL code; The system of claim 5.

7. the system further includes a first A / D (analog-to-digital) circuit and a second A / D (analog-to-digital) circuit, the first A / D circuit receiving the first measured electrical characteristic and the second measured electrical characteristic and providing corresponding first and second digital signals to the first processor, the second A / D circuit receiving the third measured electrical characteristic and the fourth measured electrical characteristic and providing corresponding third and fourth digital signals to the second processor, the first A / D circuit and the second A / D circuit being redundant matching circuits such that the first digital signal and the third digital signal are paired and the second digital signal and the fourth digital signal are paired. The system of claim 1 .

8. the first check circuit outputs a close / open signal to a first relay based on the first permission, and the second check circuit outputs a close / open signal to a second relay based on the second permission, the first relay and the second relay being connected in series such that a breaker can be closed only when both the first relay and the second relay are closed. The system of claim 1 .

9. The system further includes a man-machine interface (HMI) for receiving a third authorization from a human operator to close the breaker, where if the third authorization is not set to close the breaker, the breaker remains open, and if the first authorization, the second authorization, and the third authorization are all set to close the breaker, the breaker is closed. The system of claim 1 .

10. the first electrical characteristic and the third electrical characteristic respectively include a voltage and a frequency of the first electrical circuit, and the second electrical characteristic and the fourth electrical characteristic respectively include a voltage and a frequency of the second electrical circuit; The system of claim 1 .

11. the first electrical characteristic and the third electrical characteristic are the same as each other, and the second electrical characteristic and the fourth electrical characteristic are the same as each other; The system of claim 1 .

12. the first electrical characteristic and the third electrical characteristic respectively include a voltage and a frequency of the first electrical circuit, the second electrical characteristic and the fourth electrical characteristic respectively include a voltage and a frequency of the second electrical circuit, the first electrical characteristic and the third electrical characteristic are mutually identical, the second electrical characteristic and the fourth electrical characteristic are mutually identical, the first electrical circuit includes a power supply network, and the second electrical circuit includes a generator; The system of claim 1 .

13. the first checking circuitry includes a first processor for setting the first permission, and the second checking circuitry includes a second processor for setting the second permission, the first processor and the second processor being different types of processors, the first processor being a larger capacity processor than the second processor, the first processor being programmed in a first programming language, and the second processor being programmed in a second programming language, the first programming language and the second programming language being different types of programming languages.

13. The system of claim 12.

14. The system further includes a first A / D (analog-to-digital) circuit and a second A / D (analog-to-digital) circuit, the first A / D circuit receiving the first measured electrical characteristic and the second measured electrical characteristic and providing corresponding first and second digital signals to the first processor, the second A / D circuit receiving the third measured electrical characteristic and the fourth measured electrical characteristic and providing corresponding third and fourth digital signals to the second processor, the first A / D circuit and the second A / D circuit being redundant matching circuits such that the first digital signal and the third digital signal are paired and the second digital signal and the fourth digital signal are paired. The system of claim 13.

15. The system further includes a man-machine interface (HMI) for receiving a third authorization from a human operator to close the breaker, the breaker remaining open if the third authorization is not set to close the breaker, and the breaker is closed if the first authorization, the second authorization, and the third authorization are all set to close the breaker, the first processor being a microprocessor and the second processor being a field programmable gate array (FPGA), and the first processor also controls the first electrical characteristic and the second electrical characteristic to be matched. determining a change to be made to the second electric circuit, the second processor does not determine any change to be made to the second electric circuit, the first programming language is C code, the second programming language is VHDL code, the first check circuit outputs a close / open signal to a first relay based on the first permission, the second check circuit outputs a close / open signal to a second relay based on the second permission, the first relay and the second relay are connected in series such that the breaker can be closed only if both the first relay and the second relay are closed.

15. The system of claim 14.

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