Electronic components and their manufacturing method

Abstract

To provide an electronic component in which a plurality of capacitors different in withstand voltage are incorporated.SOLUTION: An electronic component 1 includes: a first capacitor formed by conductor patterns 25, 31 and a dielectric film 4 located between these patterns; and a second capacitor formed by conductor patterns 26, 32 and a dielectric film 5 located between these patterns. The dielectric film 4 and the dielectric film 5 have different thicknesses from each other. Since the thicknesses of the dielectric film 4 and the dielectric film 5 are different from each other, it is possible to obtain breakdown voltages different from each other.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to an electronic component and a manufacturing method thereof, and more particularly to an electronic component having a plurality of built-in capacitors and a manufacturing method thereof. [Background technology]

[0002] A known chip-type electronic component with a built-in capacitor is the electronic component described in Patent Document 1. The electronic component described in Patent Document 1 configures a series circuit of a capacitor and an inductor using two conductor layers. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2008-34626 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, when a plurality of capacitors are built into one electronic component, there may be cases in which the capacitors are required to have different withstand voltages.

[0005] SUMMARY OF THE PRESENT EMBODIMENTS It is therefore an object of the present invention to provide an electronic component incorporating a plurality of capacitors with different withstand voltages, and a method for manufacturing the same. [Means for solving the problem]

[0006] The electronic component according to the present invention is an electronic component comprising a plurality of conductor layers stacked on a substrate, and includes a first capacitor formed by two of the plurality of conductor layers adjacent in the stacking direction and a dielectric film located between them, and a second capacitor formed by two of the plurality of conductor layers adjacent in the stacking direction and a dielectric film located between them, and is characterized in that the dielectric film constituting the first capacitor and the dielectric film constituting the second capacitor have different thicknesses.

[0007] According to the present invention, the dielectric film constituting the first capacitor and the dielectric film constituting the second capacitor have different thicknesses, so that different breakdown voltages can be obtained.

[0008] In the present invention, the first and second capacitors may each have a first conductor layer of the plurality of conductor layers as a lower electrode, and a second conductor layer of the plurality of conductor layers as an upper electrode. This makes it possible to form a plurality of capacitors having different breakdown voltages without increasing the number of stacked conductor layers. In this case, the thickness of the dielectric film constituting the first capacitor may be thinner than the thickness of the dielectric film constituting the second capacitor, and the thickness of the upper electrode constituting the first capacitor may be thicker than the thickness of the upper electrode constituting the second capacitor. This makes it possible to reduce the step caused by the difference in thickness of the dielectric films.

[0009] In the present invention, the dielectric film constituting the first capacitor may be made of a first dielectric film, and the dielectric film constituting the second capacitor may be made of a second dielectric film different from the first dielectric film. This allows the thickness and material of the first and second dielectric films to be selected arbitrarily. Alternatively, the dielectric film constituting the first capacitor may be made of a first dielectric film, and the dielectric film constituting the second capacitor may be made of a laminated film of the first dielectric film and the second dielectric film. This allows the thickness of the dielectric film constituting the second capacitor to be easily made thicker than the dielectric film constituting the first capacitor.

[0010] The electronic component according to the present invention may further include a plurality of terminal electrodes, the thickness of the dielectric film constituting the first capacitor being thinner than the thickness of the dielectric film constituting the second capacitor, the plurality of conductor layers including an inductor pattern, the first capacitor being connected between any two of the plurality of terminal electrodes via the inductor pattern, and the second capacitor being connected between any two of the plurality of terminal electrodes without the inductor pattern. This makes it possible to increase the withstand voltage of the second capacitor to which a high voltage may be applied.

[0011] A method for manufacturing an electronic component according to one aspect of the present invention includes the steps of forming a first conductor layer having first and second regions on a substrate, covering the first and second regions of the first conductor layer with a first dielectric film, forming a second conductor layer on the first region of the first conductor layer via the first dielectric film, covering the first dielectric film formed on the second region of the first conductor layer with the second dielectric film, and forming a third conductor layer on the second region of the first conductor layer via the first and second dielectric films. According to the present invention, it is possible to easily fabricate two capacitors having dielectric films with different thicknesses.

[0012] A method for manufacturing an electronic component according to another aspect of the present invention includes the steps of forming a first conductor layer having first and second regions on a substrate, covering the first and second regions of the first conductor layer with a first dielectric film, forming a second conductor layer on the first region of the first conductor layer via the first dielectric film, removing the first dielectric film formed on the second region of the first conductor layer, covering the second region of the first conductor layer with the second dielectric film, and forming the second conductor layer on the second region of the first conductor layer via the second dielectric film. According to the present invention, it is possible to easily fabricate two capacitors having dielectric films with different thicknesses or materials.

[0013] A method for manufacturing an electronic component according to yet another aspect of the present invention includes the steps of forming a first conductor layer having first and second regions on a substrate, covering the first and second regions of the first conductor layer with a first dielectric film, selectively reducing the thickness of the first dielectric film formed on the second region of the first conductor layer, and forming a second conductor layer on the first and second regions of the first conductor layer via the first dielectric film. According to the present invention, it is possible to easily fabricate two capacitors having dielectric films with different thicknesses. Effect of the Invention

[0014] In this way, according to the present invention, it is possible to provide an electronic component incorporating a plurality of capacitors with different withstand voltages, and a method for manufacturing the same. [Brief description of the drawings]

[0015] [Figure 1] FIG. 1 is a schematic plan view illustrating the structure of an electronic component 1 according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a schematic cross-sectional view taken along the line AA in FIG. [Diagram 3] FIG. 3 is a schematic plan view showing the pattern shape of the conductor layers M1 and MM. [Figure 4] FIG. 4 is a schematic plan view showing the positions of vias provided in the insulating layer 11. As shown in FIG. [Diagram 5] FIG. 5 is a schematic plan view showing the pattern shape of the conductor layer M2. [Figure 6] FIG. 6 is an equivalent circuit diagram of the electronic component 1. [Figure 7] FIG. 7 is a process diagram illustrating the method for manufacturing the electronic component 1 according to the first embodiment. [Figure 8] FIG. 8 is a process diagram illustrating a method for manufacturing the electronic component 1 according to the first embodiment. [Figure 9] FIG. 9 is a process diagram illustrating the method for manufacturing the electronic component 1 according to the first embodiment. [Figure 10]FIG. 10 is a process diagram illustrating the method for manufacturing the electronic component 1 according to the first embodiment. [Figure 11] FIG. 11 is a process diagram illustrating the method for manufacturing the electronic component 1 according to the first embodiment. [Figure 12] FIG. 12 is a process diagram illustrating the method for manufacturing the electronic component 1 according to the first embodiment. [Figure 13] FIG. 13 is a process diagram illustrating the method for manufacturing the electronic component 1 according to the first embodiment. [Figure 14] FIG. 14 is a process diagram illustrating a method for manufacturing the electronic component 1 according to the first embodiment. [Figure 15] FIG. 15 is a process diagram illustrating a method for manufacturing the electronic component 1 according to the first embodiment. [Figure 16] FIG. 16 is a schematic cross-sectional view for illustrating the structure of an electronic component 1a according to the second embodiment. [Figure 17] FIG. 17 is a process chart for explaining a method for manufacturing the electronic component 1a according to the second embodiment. [Figure 18] FIG. 18 is a process chart for explaining a method for manufacturing the electronic component 1a according to the second embodiment. [Figure 19] FIG. 19 is a process chart for explaining a method for manufacturing the electronic component 1a according to the second embodiment. [Figure 20] FIG. 20 is a process chart for explaining a method for manufacturing the electronic component 1a according to the second embodiment. [Figure 21] FIG. 21 is a schematic cross-sectional view illustrating the structure of an electronic component 1b according to a first modified example. [Figure 22] FIG. 22 is a schematic cross-sectional view illustrating the structure of an electronic component 1c according to a second modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0017] Fig. 1 is a schematic plan view illustrating the structure of an electronic component 1 according to a first embodiment of the present invention, and Fig. 2 is a schematic cross-sectional view taken along line AA in Fig. 1.

[0018] The electronic component 1 according to the first embodiment is an LC filter, and includes a substrate 2, conductor layers M1, MM, M2, and insulating layers 11, 12 formed on the main surface of the substrate 2, as shown in Figs. 1 and 2. The pattern shapes of the conductor layers M1, MM are shown in Fig. 3, the positions of the vias provided in the insulating layer 11 are shown in Fig. 4, and the pattern shape of the conductor layer M2 is shown in Fig. 5. The material of the substrate 2 may be any material that is chemically and thermally stable, generates little stress, and can maintain the smoothness of the surface. There is no particular limitation on the material, and examples of the material that can be used include silicon single crystal, alumina, sapphire, aluminum nitride, MgO single crystal, SrTiO3 single crystal, surface silicon oxide, glass, quartz, ferrite, and organic films. The surface of the substrate 2 is covered with a planarization layer 3. The planarization layer 3 can be made of alumina, silicon oxide, or the like.

[0019] The conductor layer M1 is the conductor layer located at the bottom, and includes conductor patterns 21 to 26 as shown in FIG. 3. Of these, the conductor patterns 21 to 24 are terminal electrode patterns, the loop-shaped conductor pattern 25 is an inductor pattern and a lower electrode of a capacitor, and the conductor pattern 26 is a lower electrode of the capacitor. One end of the conductor pattern 25 is connected to the conductor pattern 21. The conductor pattern 26 is connected to the conductor patterns 23 and 24. Each of these conductor patterns 21 to 26 is composed of a thin seed layer S in contact with the flattening layer 3, and a plating layer P made of copper (Cu) or the like that is provided on the seed layer S and has a thickness larger than that of the seed layer S. The same is true for the conductor patterns located on the other conductor layers MM and M2, and is composed of a laminate of the seed layer S and the plating layer P. However, some of the conductor layers located at the lower layers, such as the conductor layer M1 and the conductor layer MM, may be a single layer film formed by a sputtering method or the like.

[0020] Of the conductor patterns 21 to 26, the upper surface of the conductor pattern 25 constituting the lower electrode of the capacitor is covered with a first dielectric film (capacitive insulating film) 4, and the upper surfaces of the conductor pattern 26 constituting the lower electrode of the capacitor and a part of the first dielectric film 4 are covered with a second dielectric film (capacitive insulating film) 5. The first and second dielectric films 4 and 5 are made of an inorganic insulating material such as silicon nitride, and may be made of the same material or different materials. In addition, the film thicknesses may be the same or different. As an example, in the first embodiment, both the first and second dielectric films 4 and 5 are made of silicon nitride, and the first dielectric film 4 is thinner than the second dielectric film 5.

[0021] The conductor pattern 25 has a first region 25A and a second region 25B. A conductor pattern 31 is formed on the upper surface of the first region 25A via a first dielectric film 4. A conductor pattern 33 is formed on the upper surface of the second region 25B via a laminated film of the first dielectric film 4 and the second dielectric film 5. A conductor pattern 32 is formed on the upper surface of the conductor pattern 26 via a second dielectric film 5. The conductor patterns 31 to 33 belong to the conductor layer MM located between the conductor layer M1 and the conductor layer M2, and constitute the upper electrodes of the capacitors. This forms a first capacitor having the first region 25A of the conductor pattern 25 as a lower electrode and the conductor pattern 31 as an upper electrode, a second capacitor having the conductor pattern 26 as a lower electrode and the conductor pattern 32 as an upper electrode, and a third capacitor having the second region 25B of the conductor pattern 25 as a lower electrode and the conductor pattern 33 as an upper electrode. The thickness of the conductor layer MM is thinner than the conductor layers M1 and M2, which improves the pattern accuracy of the conductor layer MM. The conductor layers M1 and MM are covered with an insulating layer 11 made of a resin material such as polyimide.

[0022] 4, vias 41-48 that expose the conductor layers M1, MM are provided in the insulating layer 11. Of these, the vias 41-44 are provided at positions that expose the conductor patterns 21-24, respectively, the via 45 is provided at a position that exposes the end of the conductor pattern 25, and the vias 46-48 are provided at positions that expose the conductor patterns 31-33, respectively.

[0023] The conductor layer M2 is a second conductor layer provided on the surface of the insulating layer 11, and includes conductor patterns 51-59 as shown in FIG. 5. Of these, the conductor patterns 51-54 are terminal electrode patterns, the loop-shaped conductor pattern 55 is an inductor pattern, the conductor patterns 57 and 59 are lead-out patterns of the upper electrode, and the meandering conductor pattern 58 is an inductor pattern. The conductor patterns 51-54 are connected to the conductor patterns 21-24 through the vias 41-44, respectively. One end of the conductor pattern 55 is connected to the other end of the conductor pattern 25 through the via 45, and the other end of the conductor pattern 55 is connected to the conductor pattern 57 and is connected to the conductor patterns 31 and 33 through the vias 46 and 48, respectively. The conductor pattern 57 is connected to the conductor pattern 32 through the via 47.

[0024] FIG. 6 is an equivalent circuit diagram of the electronic component 1 according to the first embodiment.

[0025] 6, the electronic component 1 according to the first embodiment has a circuit configuration in which a capacitor C1 and an inductor L1 are connected in parallel between a terminal electrode E1 and an internal node N, an inductor L2 is connected between a terminal electrode E2 and the internal node N, a capacitor C2 is connected between terminal electrodes E3, E4 and the internal node N, and a capacitor C3 is connected between the terminal electrodes E1 and E2. The terminal electrode E1 corresponds to the conductor patterns 21, 51, the terminal electrode E2 corresponds to the conductor patterns 22, 52, the terminal electrode E3 corresponds to the conductor patterns 23, 53, and the terminal electrode E4 corresponds to the conductor patterns 24, 54. The internal node N corresponds to the conductor pattern 57. The capacitor C1 has the first region 25A of the conductor pattern 25 as a lower electrode and the conductor pattern 31 as an upper electrode. The capacitor C2 has the conductor pattern 26 as a lower electrode and the conductor pattern 32 as an upper electrode. Capacitor C3 has second region 25B of conductor pattern 25 as a lower electrode and conductor pattern 33 as an upper electrode. Inductor L1 is formed by conductor patterns 25 and 55, and inductor L2 is formed by conductor pattern 58.

[0026] Thus, the electronic component 1 according to the first embodiment has three capacitors C1 to C3 built in the same chip. Here, the capacitor C1 uses the first dielectric film 4 as a capacitive insulating film, the capacitor C2 uses the second dielectric film 5 as a capacitive insulating film, and the capacitor C3 uses a laminated film of the first dielectric film 4 and the second dielectric film 5 as a capacitive insulating film. In the first embodiment, the first dielectric film 4 is thinner than the second dielectric film 5, so that the capacitance per unit area of ​​the capacitor C1 is the largest and the capacitance per unit area of ​​the capacitor C3 is the smallest, while the dielectric strength voltage of the capacitor C3 is the highest and the capacitor C1 is the lowest.

[0027] Here, the reason why the capacitive insulating film of the capacitor C1 is designed to be the thinnest is that the capacitance required for the capacitor C1 is large, and the voltage applied to the capacitor C1 is relatively suppressed because the capacitor C1 is not directly connected between the two terminal electrodes but is connected between the two terminal electrodes via an inductor or another capacitor. In contrast, the capacitor C3 is directly connected between the terminal electrodes E1 and E3 without an inductor or another capacitor, so a relatively high voltage can be applied from the outside. For this reason, the capacitor C3 requires a higher withstand voltage, and in order to achieve this, the capacitive insulating film of the capacitor C3 is designed to be the thickest. As for the capacitor C2, like the capacitor C1, it is not directly connected between the two terminal electrodes but is connected between the two terminal electrodes via an inductor or another capacitor, but the required capacitance is smaller than that of the capacitor C1, so the withstand voltage is improved by using a thicker second dielectric film 5.

[0028] In this way, in the first embodiment, the thicknesses of the capacitive insulating films of the capacitors C1 to C3 are individually set according to the required capacitance and withstand voltage, so that it is possible to achieve both electrical characteristics and withstand voltage.

[0029] Next, a method for manufacturing the electronic component 1 according to the first embodiment will be described.

[0030] 7 to 15 are process diagrams illustrating a manufacturing method of the electronic component 1 according to the first embodiment. In the manufacturing process of the electronic component 1, a large number of electronic components 1 are obtained using an aggregate substrate, but the manufacturing process shown in Figs. 7 to 15 focuses on one electronic component 1.

[0031] First, as shown in FIG. 7, a planarization layer 3 is formed on a substrate (at this point, an aggregate substrate) 2 by using a sputtering method or the like, and the surface is smoothed by grinding or performing a mirror finish treatment such as CMP. After that, a seed layer S is formed on the surface of the planarization layer 3 by using a sputtering method or the like. Next, a resist layer (not shown) is spin-coated on the seed layer S, and then the resist layer is patterned so that the seed layer S in the region where the conductor layer M1 is to be formed is exposed. In this state, electrolytic plating is performed using the seed layer S as a power supply, thereby forming a plating layer P on the seed layer S. The laminate of the seed layer S and the plating layer P constitutes the conductor layer M1. In the cross section shown in FIG. 7, the conductor layer M1 includes conductor patterns 25, 26. After that, the resist layer is removed, and the seed layer S exposed on the surface is removed, thereby completing the conductor layer M1. The seed layer S can be removed by etching or ion milling.

[0032] Next, as shown in Fig. 8, a first dielectric film 4 is formed on the entire surface including the upper surface and side surfaces of the conductor layer M1. For the first dielectric film 4, for example, a paraelectric material such as silicon nitride (SiNx) or silicon oxide (SiOx) or a known ferroelectric material can be used. The first dielectric film 4 can be formed by sputtering, plasma CVD, MOCVD, sol-gel method, electron beam deposition, or the like. Next, as shown in Fig. 9, the first dielectric film 4 is patterned to expose the conductor pattern 26.

[0033] 10, a conductor pattern 31 is formed on the upper surface of the first region 25A of the conductor pattern 25 via the first dielectric film 4 by using a method similar to that for forming the conductor layer M1. The conductor pattern 31 is also made of a laminate of a seed layer S and a plating layer P. At this time, the first dielectric film 4 covering the second region 25B of the conductor pattern 25 is left exposed. As a result, a first capacitor C1 is formed, with the first region 25A of the conductor pattern 25 as a lower electrode and the conductor pattern 31 as an upper electrode.

[0034] Next, as shown in FIG. 11, a second dielectric film 5 is formed on the entire surface including the upper surface and side surfaces of the conductor pattern 31. The material and the method of forming the second dielectric film 5 may be the same as or different from the material and the method of forming the first dielectric film 4. The thickness of the second dielectric film 5 may be the same as or different from the thickness of the first dielectric film 4, but in the first embodiment, the thickness of the second dielectric film 5 is set to be larger than that of the first dielectric film 4. As a result, the conductor pattern 26 is covered with the second dielectric film 5, and the second region 25B of the conductor pattern 25 is covered with a laminated film of the first dielectric film 4 and the second dielectric film 5.

[0035] 12, by using a method similar to that for forming the conductor layer M1, a conductor pattern 32 is formed on the upper surface of the conductor pattern 26 via the second dielectric film 5, and a conductor pattern 33 is formed on the upper surface of the second region 25B of the conductor pattern 25 via the first dielectric film 4 and the second dielectric film 5. The conductor patterns 32 and 33 are also made of a laminate of a seed layer S and a plating layer P. This completes the conductor layer MM, forming a second capacitor C2 having the conductor pattern 26 as a lower electrode and the conductor pattern 32 as an upper electrode, and forming a third capacitor C3 having the second region 25B of the conductor pattern 25 as a lower electrode and the conductor pattern 33 as an upper electrode.

[0036] Next, as shown in FIG. 13, the second dielectric film 5 is patterned to form a via 5a that exposes a part of the conductor pattern 31. Next, as shown in FIG. 14, an insulating layer 11 is formed to cover the conductor layers M1 and MM, and then the insulating layer 11 is patterned to form vias 31a-33a in the insulating layer 11. As a result, the conductor patterns 31-33 are exposed at the bottoms of the vias 31a-33a, respectively. At this time, the via 31a is the deepest and the via 33a is the shallowest among the vias 31a-33a. In order to reduce such a difference, the conductor layer MM may be formed so that the conductor pattern 31 is the thickest and the conductor pattern 33 is the thinnest.

[0037] Next, as shown in Fig. 15, a conductor layer M3 is formed on the insulating layer 11 by a method similar to that for forming the conductor layer M1. In the cross section shown in Fig. 15, the conductor layer M2 includes conductor patterns 55, 57, and 59. The conductor pattern 55 is connected to the conductor pattern 31 through the via 31a, the conductor pattern 57 is connected to the conductor pattern 32 through the via 32a, and the conductor pattern 59 is connected to the conductor pattern 33 through the via 33a. Thereafter, as shown in Fig. 2, an insulating layer 12 is formed to cover the conductor layer M2, and then terminal electrodes E1 to E4 connected to the conductor patterns 51 to 54, respectively, are formed to complete the electronic component 1 according to the first embodiment.

[0038] By using the manufacturing process for electronic component 1 described above, it is possible to form a first capacitor C1 having the first dielectric film 4 as a capacitive insulating film, a second capacitor C2 having the second dielectric film 5 as a capacitive insulating film, and a third capacitor C3 having a capacitive insulating film that is a laminated film of the first dielectric film 4 and the second dielectric film 5. Moreover, since the lower electrodes of capacitors C1 to C3 are all located on conductor layer M1 and the upper electrodes of capacitors C1 to C3 are all located on conductor layer MM, it is possible to separately manufacture a plurality of capacitors with different withstand voltages without increasing the number of conductor layers.

[0039] FIG. 16 is a schematic cross-sectional view for illustrating the structure of an electronic component 1a according to the second embodiment.

[0040] 16, the electronic component 1a according to the second embodiment differs from the electronic component 1 according to the first embodiment in that the second dielectric film 5 is omitted and instead the film thickness of the first dielectric film 4 varies depending on the planar position. As the other basic configuration is the same as that of the electronic component 1 according to the first embodiment, the same elements are given the same reference numerals and redundant explanations will be omitted.

[0041] In the second embodiment, the thickness of a part of the first dielectric film 4 is reduced. Specifically, the thickness is not reduced in the region 4a, the thickness is reduced by one step in the region 4b, and the thickness is reduced by two steps in the region 4c. Among the conductor patterns belonging to the conductor layer MM, the conductor pattern 31 is formed at a position overlapping the region 4c, the conductor pattern 32 is formed at a position overlapping the region 4b, and the conductor pattern 33 is formed at a position overlapping the region 4a. As a result, as in the first embodiment, the largest capacitance per unit area can be obtained in the first capacitor C1, and the highest dielectric strength voltage can be obtained in the third capacitor C3.

[0042] Next, a method for manufacturing the electronic component 1a according to the second embodiment will be described.

[0043] 17 to 20 are process diagrams illustrating a manufacturing method of an electronic component 1a according to the second embodiment. In the manufacturing process of the electronic component 1a, a large number of electronic components 1a are obtained by using an aggregate substrate, but the manufacturing process shown in Figs. 17 to 20 focuses on one electronic component 1a.

[0044] First, as explained with reference to Fig. 7, a planarization layer 3 and a conductor layer M1 are formed on a substrate 2, and then a first dielectric film 4 is formed on the entire surface including the upper and side surfaces of the conductor layer M1 as shown in Fig. 17. The thickness of the first dielectric film 4 is set to be thicker than that in the first embodiment.

[0045] 18, the portion of the first dielectric film 4 covering the first region 25A of the conductive pattern 25 and the portion covering the conductive pattern 26 are etched to reduce the film thickness by one step. This separates the first dielectric film 4 into a region 4a having the original film thickness and a region 4b whose film thickness is reduced by one step. The second region 25B of the conductive pattern 25 is covered by the region 4a of the first dielectric film 4.

[0046] 19, the portion of the first dielectric film 4 that covers the first region 25A of the conductor pattern 25 is further etched to reduce the film thickness by another step. This divides the first dielectric film 4 into a region 4a having the original film thickness, a region 4b whose film thickness is reduced by one step, and a region 4c whose film thickness is reduced by two steps. The conductor pattern 26 is covered by the region 4b of the first dielectric film 4.

[0047] Next, as shown in Fig. 20, a conductor layer MM consisting of conductor patterns 31-33 is formed on the surface of the first dielectric film 4. The conductor pattern 31 covers the first region 25A of the conductor pattern 25 through the region 4c of the first dielectric film 4, the conductor pattern 32 covers the conductor pattern 26 through the region 4b of the first dielectric film 4, and the conductor pattern 33 covers the second region 25B of the conductor pattern 25 through the region 4a of the first dielectric film 4. This completes the capacitors C1-C3. Thereafter, by performing the process described with reference to Figs. 14 and 15, the electronic component 1a according to the second embodiment is completed.

[0048] By using the manufacturing process for electronic component 1a described above, it is possible to fabricate a plurality of capacitors with different breakdown voltages without using a plurality of dielectric films. Moreover, the thickness of dielectric film 4 can be finely adjusted by the amount of etching.

[0049] FIG. 21 is a schematic cross-sectional view illustrating the structure of an electronic component 1b according to a first modified example.

[0050] As shown in FIG. 21, the electronic component 1b according to the first modification has a conductor layer M1 including conductor patterns 61 and 62, a conductor layer MM including conductor patterns 71 and 72, and a conductor layer M2 including conductor patterns 81 and 82, and has a structure in which a first dielectric film 6 is provided between the conductor patterns 61 and 71, and a second dielectric film 7 is provided between the conductor patterns 72 and 82. As a result, the conductor patterns 61 and 71 and the first dielectric film 6 form a first capacitor, and the conductor patterns 72 and 82 and the second dielectric film 7 form a second capacitor. The first dielectric film 6 and the second dielectric film 7 have different thicknesses. As exemplified by the electronic component 1b according to the first modification, the upper electrode of the first capacitor and the lower electrode of the second capacitor may be located on the same conductor layer (MM).

[0051] FIG. 22 is a schematic cross-sectional view illustrating the structure of an electronic component 1c according to a second modified example.

[0052] As shown in FIG. 22, the electronic component 1c according to the second modification has a conductor layer M1 including conductor patterns 61 and 62, a conductor layer MM including conductor patterns 71 and 72, a conductor layer M2 including conductor patterns 81 and 82, and a conductor layer M3 including conductor patterns 91 and 92, and has a structure in which a first dielectric film 6 is provided between the conductor patterns 61 and 71, and a second dielectric film 8 is provided between the conductor patterns 82 and 92. As a result, the conductor patterns 61 and 71 and the first dielectric film 6 form a first capacitor, and the conductor patterns 82 and 92 and the second dielectric film 8 form a second capacitor. The first dielectric film 6 and the second dielectric film 8 have different thicknesses. As exemplified by the electronic component 1c according to the first modification, the lower electrode and the upper electrode of the first capacitor and the lower electrode and the upper electrode of the second capacitor may be located on different conductor layers (M1, MM, M2, M3).

[0053] Although a preferred embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications are possible without departing from the spirit of the present invention, and it goes without saying that these modifications are also included within the scope of the present invention.

[0054] For example, in the first and second embodiments, capacitors C1 to C3 are constructed using three dielectric films with different thicknesses, but two types of capacitors may be constructed using two dielectric films with different thicknesses, or four or more types of capacitors may be constructed using four or more dielectric films with different thicknesses. [Explanation of symbols]

[0055] 1,1a~1c Electronic components 2. Board 3 Planarization layer 4,6 First dielectric film 4a~4c area 5,7,8 Second dielectric film 5a, 31a~33a, 41~48 via 11,12 Insulating layer 21~26,31~33,51~55,57~59,61,62,71,72,81,82,91,92 Conductor pattern 25A First Area 25B Second Area C1~C3 capacitors E1~E4 terminal electrode L1, L2 inductors M1, MM, M2, M3 conductor layers N internal nodes P plating layer S seed layer

Claims

1. An electronic component comprising a plurality of conductor layers stacked on a substrate, a first capacitor formed by two conductor layers adjacent to each other in a stacking direction among the plurality of conductor layers and a first dielectric film located between the conductor layers; an electronic component comprising: two conductor layers among the plurality of conductor layers adjacent in a stacking direction; and a second capacitor formed by a stacked film of the first dielectric film and the second dielectric film located between the two conductor layers.

2. 2. The electronic component according to claim 1, wherein the first and second capacitors each have a first conductor layer of the plurality of conductor layers as a lower electrode, and each have a second conductor layer of the plurality of conductor layers as an upper electrode.

3. An electronic component as described in claim 2, characterized in that the thickness of the upper electrode constituting the first capacitor is thicker than the thickness of the upper electrode constituting the second capacitor.

4. Further comprising first, second, and third terminal electrodes; the plurality of conductor layers includes a first inductor pattern; the first capacitor is connected between the first terminal electrode and the second terminal electrode via the first inductor pattern; 4. The electronic component according to claim 1, wherein the second capacitor is connected between the first terminal electrode and the third terminal electrode without passing through the first inductor pattern.

5. The plurality of conductor layers further includes a second inductor pattern, The electronic component according to claim 4 , wherein the second inductor pattern and the first capacitor are connected in parallel.

6. The plurality of conductor layers include an inductor pattern, 4. The electronic component according to claim 1, wherein the inductor pattern and the first capacitor are connected in parallel.

7. forming a first conductor layer on a substrate, the first conductor layer having first and second regions; covering the first and second regions of the first conductor layer with a first dielectric film; forming a first capacitor by forming a second conductor layer on the first region of the first conductor layer through the first dielectric film; covering the first dielectric film formed on the second region of the first conductor layer with a second dielectric film; and forming a second capacitor by forming a third conductor layer on the second region of the first conductor layer via the first and second dielectric films.

8. forming a first conductor layer on a substrate, the first conductor layer having first and second regions; covering the first and second regions of the first conductor layer with a first dielectric film; forming a second conductor layer on the first region of the first conductor layer through the first dielectric film; removing the first dielectric film formed on the second region of the first conductor layer, and then covering the second region of the first conductor layer with a second dielectric film; forming a second conductor layer on the second region of the first conductor layer with the second dielectric film interposed therebetween.

9. forming a first conductor layer on a substrate, the first conductor layer having first and second regions; covering the first and second regions of the first conductor layer with a first dielectric film; selectively reducing a thickness of the first dielectric film formed on the second region of the first conductor layer; forming a second conductor layer on the first and second regions of the first conductor layer with the first dielectric film interposed therebetween.

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