Arbitration method, apparatus, device, storage medium, program product, and chip

Abstract

In an embodiment of the present application, an arbitration method is provided. The method includes: obtaining P first requests separately transmitted by P processing modules among M processing modules in an Nth clock cycle; determining P time slot values ​​separately assigned to identifiers (IDs) of the P processing modules from a first time slot table; and determining a target request to be transmitted from the P first requests to a storage module in the Nth clock cycle based on a normalized clock cycle count corresponding to the Nth clock cycle and the P time slot values. Each of the M processing modules is configured to transmit the first request to the storage module via the arbitration module, where M is an integer greater than or equal to P, N is an integer greater than or equal to 0, and P is an integer greater than or equal to 2. In an embodiment of the present application, an apparatus, a device, a storage medium, a program product, and a chip are further provided.

Description

[Technical field]

[0001] This application claims priority to a Chinese patent application entitled "Mediation Method, Apparatus, Device, Storage Medium, Program Product, and Chip", filed on November 13, 2020, and bearing application number CN202011273078.2, the entire contents of which are incorporated herein by reference.

[0002] TECHNICAL FIELD Embodiments of the present application relate to, but are not limited to, electronic technologies, and in particular to arbitration methods, apparatus, devices, storage media, program products and chips. [Background technology]

[0003] With the development of communication technology, more and more tasks are supported by communication devices, and the throughput between the processing module and the storage module in the communication device is also increased, which puts higher requirements on the performance of the arbiter. How to design the arbitration strategy of the arbiter to improve the arbitration efficiency of the arbiter is an urgent problem to be solved in the field. Summary of the Invention

[0004] In the embodiments of the present application, an arbitration method, an apparatus, a device, a storage medium, a program product and a chip are provided.

[0005] In a first aspect, a method of arbitration is provided, the method comprising: Nth clock period Then, obtain P first requests separately sent by P processing modules in the M processing modules; and determine P time slot values ​​separately assigned to identifiers (IDs) of the P processing modules from a first time slot table; Nth clock period Based on the normalized clock period counts and the P time slot values ​​corresponding to Nth clock periodand determining a target request to be sent to the storage module via the arbitration module, wherein each of the M processing modules is configured to send a first request to the storage module via the arbitration module, where M is an integer greater than or equal to P, N is an integer greater than or equal to 0, and P is an integer greater than or equal to 2.

[0006] In a second aspect, a data processing apparatus is provided, comprising M processing modules, an arbitration module and a storage module, each of the M processing modules being configured to send a first request to the storage module via the arbitration module. The arbitration module comprises: Nth clock period obtain P first requests sent by P processing modules in the M processing modules separately; and determine P time slot values ​​assigned to IDs of the P processing modules separately from a first time slot table; and Nth clock period Based on the normalized clock period counts and the P time slot values ​​corresponding to Nth clock period The arbitration module is configured to determine the target requests sent to the storage module by M, where M is an integer greater than or equal to P, N is an integer greater than or equal to 0, and P is an integer greater than or equal to 2. The storage module determines the target requests sent by the arbitration module by Nth clock period The device is configured to receive

[0007] In a third aspect, an arbitration device is provided, comprising an acquisition unit and a first determination unit. The acquisition unit comprises: Nth clock period The first determination unit is configured to obtain P first requests separately transmitted by P processing modules in the M processing modules via the arbitration module. The M processing modules are configured to transmit the first requests to the storage module via the arbitration module, where M is an integer equal to or greater than P, N is an integer equal to or greater than 0, and P is an integer equal to or greater than 2. The first determination unit is configured to determine P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table. The first determination unit: Nth clock periodBased on the normalized clock period counts and the P time slot values ​​corresponding to Nth clock period The target request is further configured to be transmitted to the storage module at

[0008] In a fourth aspect, there is provided an arbitration device comprising an arbitration module, the arbitration module comprising a memory and a processor, the memory configured to store a computer program executable by the processor, the processor configured to execute the computer program to perform the operations of the method set forth above.

[0009] In a fifth aspect, there is provided a computer storage medium having stored thereon one or more programs executable by one or more processors to effectuate operations of the above-described method.

[0010] In a sixth aspect, there is provided a computer program product comprising a computer storage medium having computer program code stored thereon, the computer program code including instructions executable by at least one processor, the instructions being configured, when executed by the at least one processor, to perform operations of the method set forth above.

[0011] In a seventh aspect, there is provided a chip, the chip comprising a processor, the processor calling up and executing a computer program from a memory to cause a device incorporating the chip to perform the operations of the method, or the chip comprising the data processing apparatus.

[0012] In an embodiment of the present application, Nth clock period Based on the normalized clock period count corresponding to the P time slot values ​​determined from the first time slot table, Nth clock period determines the target request to be sent to the storage module. Nth clock period determining a target request to be sent to the storage module; Nth clock period In this way, it is possible to avoid the inability to determine the target request sent to the storage module, and further improve the arbitration efficiency of the arbiter, it is possible to improve the certainty that the target request is determined among the P first requests by the arbitration module, it is possible to avoid the problem of the uncertainty of the selected target request caused by randomly selecting a target request from the P first requests, and it is possible to meet the arbitration needs in different cases.

[0013] In order to make the above objects, features and advantages of the present application more clearly comprehensible, preferred embodiments will be specifically described below in conjunction with the accompanying drawings. [Brief description of the drawings]

[0014] In order to more clearly explain the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings that need to be used in the embodiments. These drawings are incorporated in the specification and constitute a part of this specification. These drawings show the embodiments that are compatible with the present application, and together with the specification, will explain the technical solutions of the present application. [Figure 1] FIG. 1 is a schematic diagram showing the structure of a data processing device according to an embodiment of the present application. [Diagram 2] FIG. 2 is a schematic diagram showing the structure of another data processing apparatus according to an embodiment of the present application. [Diagram 3] FIG. 3 is a pipeline schematic diagram illustrating the operation process of a data processing device according to an embodiment of the present application. [Figure 4] FIG. 4 is a schematic diagram of an arbitration scheme according to the related art. [Diagram 5] FIG. 5 is a schematic diagram of another arbitration scheme according to the related art. [Figure 6] FIG. 6 is a flowchart of an arbitration method according to an embodiment of the present application. [Figure 7] FIG. 7 is a flowchart of another arbitration method according to an embodiment of the present application. [Figure 8] FIG. 8 is a flowchart of yet another arbitration method according to an embodiment of the present application. [Figure 9]FIG. 9 is a flowchart of yet another arbitration method according to an embodiment of the present application. [Figure 10] FIG. 10 is a flowchart of an arbitration method according to another embodiment of the present application. [Figure 11] FIG. 11 is a schematic diagram of simulation results of different types of arbitration methods according to embodiments of the present application. [Figure 12] FIG. 12 is a schematic diagram showing the structure of another data processing apparatus according to an embodiment of the present application. [Figure 13] FIG. 13 is a schematic diagram showing the structure of an arbitration device according to an embodiment of the present application. [Figure 14] FIG. 14 is a schematic diagram of a hardware entity of an arbitration device according to an embodiment of the present application. [Figure 15] FIG. 15 is a schematic diagram showing the structure of a chip according to an embodiment of the present application. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The following describes the technical solutions of the present application in detail with the aid of embodiments and accompanying drawings. Some of the following specific embodiments may be combined with each other. The same or similar concepts or processes may not be repeated in some embodiments.

[0016] In addition, in the embodiments of the present application, the terms "first", "second", etc. are used to distinguish similar objects, not to describe a particular order or priority, and the technical solutions described in the embodiments of the present application may be arbitrarily combined as long as there is no contradiction.

[0017] When multiple requests to access the same physical memory block occur in the same clock cycle, memory contention occurs. To resolve memory contention, the concept of an arbiter (also called a memory arbiter) has been proposed. The arbiter can be coupled to memory blocks and can determine the order of accessing the memory blocks based on a priority scheme. When there are multiple access requests or multiple storage requests to one memory block in one clock cycle, a typical arbiter can allow one access request or one storage request to reach the memory block in one clock cycle, but other access requests or storage requests in this clock cycle cannot reach the memory block, resulting in a pipeline stall, which can be understood as a pipeline blockage.

[0018] 1 is a schematic diagram showing the structure of a data processing device according to an embodiment of the present application. As shown in FIG. 1, the data processing device 100 includes an arbiter 110, at least two processing modules 120, a memory block 130 and an external master 140.

[0019] Nth clock period Then, any one or more of the at least two processing modules 120 and / or the external master 140 may send a first request to the memory block 130 via the arbiter 110. The first request may be a read request to read data from the memory block 130, or may be a write request to write data to the memory block 130. For example, if the first request is a read request, any one or more of the at least two processing modules 120 and the external master 140 may send a first request to the memory block 130 via the arbiter 110. Nth clock period When the first request is sent to the memory block 130 via the arbiter 110, the arbiter 110 Nth clock period In other words, the arbiter 110 can send only one first request to the memory block 130. Nth clock periodOnly one first request can be granted at a time, and other ungranted first requests are put into a waiting state until they are granted at a later clock cycle. The authorization in the embodiment of the present application can be understood as a confirmation.

[0020] FIG. 2 is a schematic diagram showing the structure of another data processing device according to an embodiment of the present application. As shown in FIG. 2, the data processing device 200 includes a vector memory arbiter (VMA) 210, M vector digital signal processing (VDSP) cores 220, Q vector memory blocks (VM blocks) 230, an external master 240, and an external slave 250. M and Q may be integers equal to or greater than 1. Here, the arbiter 110 may include a VMA, and the processing module may include a VDSP core. In another embodiment, the arbiter 110 may include a memory arbiter (MA).

[0021] Here, the M VDSP cores 220 may be VDSP core0, VDSP core1, VDSP coreM-1, etc. The Q VM blocks 230 may be block0, block1, blockQ-1, etc.

[0022] The VMA 210 can be connected to M VDSP cores 220, Q VM blocks 230, an external master 240, and an external slave 250. The VMA 210 provides data access between each VM block (block0, block1, or blockQ-1) and each VDSP core (VDSP core0, VDSP core1, or VDSP coreM-1), provides data access between each VM block (block0, block1, or blockQ-1) and the external master 240, provides data access between the external slave 250 and each VDSP core (VDSP core0, VDSP core1, or VDSP coreM-1), and provides data access between the external slave 250 and the external master 240. For example, any one of the M VDSP cores 220 can transmit a first request to any one of the N VM blocks via the VMA 210, any one of the VDSP cores can transmit a first request to the external slave 250 via the VMA 210, the external master 240 can transmit a first request to any one of the VM blocks via the VMA 210, and the external master 240 can also transmit a first request to the external slave 250 via the VMA 210. The first request may be a read request or a write request.

[0023] Each VDSP core may include a load / store (L / S) unit 221, a write buffer 222, a vector register block (VR block) 223, a vector arithmetic and logic unit (VALU) 224, a coprocessor 225, and a scalar arithmetic and logic unit (SALU) 226. Among them, the SALU 226 may have a scalar resource (SR). The VALU 224 may call the SR of the SALU 226 when performing correlation calculation. The L / S unit in the embodiment of the present application may be one or at least two, and the VREG block may be one or at least two, which are not limited in the embodiment of the present application. For example, in an embodiment corresponding to FIG. 2, the L / S unit 221 includes two L / S units, which are L / S unit 0 and L / S unit 1, respectively, and the VREG block 223 includes VREG block 0, VREG block 1, VREG block T, etc., where T is an integer greater than or equal to 1.

[0024] In the embodiments of this application, unless otherwise stated, a read or a write is a read or a write that occurs in one clock cycle.

[0025] Each VDSP core can simultaneously issue at least one data read request to the VMA 210 through the load port of the L / S unit based on at least one L / S unit included therein, and can issue one data write request to the VMA 210 based on the write buff included therein. Access from the load port and write buff port of the L / S unit may reach the VM through a VM port (vm-port) or may reach the external slave 250 through an external slave-port (es-port). External master 240 including direct memory access (DMA) and other system processors can reach the VM from an external master-port (em-port) to the VM port.

[0026] From the perspective of the VMA 210, the vm-port and es-port are ports used for passive operations, while the load port, write buff port, and em-port are ports used to issue requests. Access from the em-port can be allocated over multiple cycles. All requests are sent from a system bus that connects various master and slave devices. Dedicated requests to a VM can be described as being sent to the VMA 210 in some order, which may be scattershot and random, with some random stages, as they are queued and routed.

[0027] By configuring multiple VM blocks, multiple VM blocks can be accessed simultaneously in the same clock cycle, reducing the possibility of memory contention. When at least two requests attempting to access the same VM block simultaneously occur in the same clock cycle, a block contention (or memory contention) occurs. Therefore, the VMA 210 arbitrates between at least two requests and determines one granted request in this clock cycle. Requests that have not been granted must wait for the next clock cycle until they are granted.

[0028] For adaptability and flexibility, each VM block may include at least two storage areas (banks). For example, the banks included in one VM block in the embodiment of the present application may be bank0, bank1, bank2, bankR-1, etc., respectively, and the value of R may be the same as or different from the value of M. The storage width of one bank may be matched to the data width of a vector lane (vlane) element, so that the width of data that can be read at one time or the width of data that can be stored at one time is the storage width of one bank. In each VM block, the addresses of the banks may be interleaved.

[0029] In some embodiments, when a read request instructs to read data from at least two banks of a VM block, the VMA 210 may allow the read request to read data from one bank of a VM block in the current clock cycle and read data from the other bank in the clock cycle following the current clock cycle, i.e., data from only one bank may be read in one clock cycle.

[0030] The bandwidth of the VM block may be the same as the bandwidth of the L / S unit, or may be the same as the width of the VR block, thereby enabling data to be transmitted between the VR block and the VM block in a single-cycle load operation or a single-cycle store operation.

[0031] One VDSP core may include at least two L / S units. In order to avoid contention caused by one VDSP core accessing the Q VM blocks 230 at full bandwidth, the number of VM blocks may be equal to or greater than the number of L / S units in one VDSP core. For example, as shown in FIG. 2, the number of VM blocks is 3 and the number of L / S units in one VDSP core is 2.

[0032] 3 is a pipeline diagram showing an operation process of a data processing device according to an embodiment of the present application. As shown in FIG. 3, the execution stage of an instruction can be divided into four stages, namely, an instruction fetch stage, an instruction decode stage, an execution stage, and a write back stage.

[0033] In the instruction acquisition stage, the L / S unit acquires an instruction and stores all the acquired instructions in the VR block. In the instruction decode stage, the VALU and / or the coprocessor decodes the instruction in the VR block, and reads one operand from the VR block and registers one operand in the VR block for each decode stage. The instruction execution stage can be divided into Es substages, where Es may be 4. For example, the Es substages can include substages X1, X2, X3, and X4. In each substage, one vlane is processed through one arithmetic and logic unit (ALU) instruction, and the total number of vlanes consumed is Es. In the instruction writeback stage, the execution result is written back to the target VR block cyclically. The target VR block may be the same as or different from the VR block that stores the instruction.

[0034] The length of an instruction cycle can be defined by the number of vlanes (Es), so that for a full pipeline with vector load instructions, ALU instructions, coprocessor instructions and vector store instructions, due to the VDSP core's access model to VM blocks, one VM block can be read or written only once per instruction cycle.

[0035] Continuing to refer to FIG. 3, when executing a vector load instruction, the operation of reading data (or a read instruction) from a VM block is as follows: Third Clock Period (i.e., sub-step X1) and writes the data read in the last clock cycle to the VR block. When executing the ALU instruction, VALU 1st and Second Clock Period It can read data from the VR block in one clock cycle and write the processing result back to the VR block in the last clock cycle. When executing a coprocessor instruction, the coprocessor Second Clock Period In the last clock cycle, the L / S unit reads data from the VR block and writes the processing result back to the VR block. Second Clock Period Read data from the VR block with Third Clock Period Then, the data is written back to the VM block via the write buff. After the execution of the full pipeline is completed in this manner, the multi-core VDSP system (which may be a data processing device corresponding to FIG. 1, FIG. 2, or FIG. 13 below) can then execute the full pipeline in a cyclical manner.

[0036] As can be seen from the above, during the execution of the pipeline, a vector load or vector store instruction is executed every four cycles. The operation of reading data from a VM block is executed in one clock cycle, and then the next clock cycle. Third Clock Period performs an operation to write data to the VM block.

[0037] In a multi-core VDSP system, the VMA mainly resolves contention caused by write or read requests to a VM block sent simultaneously by multiple VDSP cores, and the main goal of designing the VMA is to reduce the stall time (or the number of clock cycles it takes to stall) of unauthorized write or read requests.

[0038] In the following, an arbitration scheme in the related art is introduced which determines the first request to be granted in the current clock cycle based on Equation (1).

number

[0039] JPEG0007602712000002.jpg68155

[0040] 4 is a schematic diagram of an arbitration method according to the related art. The arbitration method may adopt a round robin arbitration method. As shown in FIG. 4, when the number of VDSP cores is four, the four VDSP cores are core0, core1, core2 and core3, respectively, and the read signals sent from core0, core1, core2 and core3 may be core0 RD signal, core1 RD signal, core2 RD signal and core3 RD signal, respectively.

[0041] JPEG0007602712000003.jpg43155

[0042] JPEG0007602712000004.jpg37155

[0043] JPEG0007602712000005.jpg43155

[0044] As can be seen from the above, when the VDSP core receives multiple read requests, it can determine the read signals that are granted in the current clock cycle based on the number of the current clock cycle. The pipeline of the ungranted read signals stops in the current clock cycle, and after several clock cycles, all sub-stages X1 of the pipeline are aligned with the assigned VM slots, i.e., pipeline alignment is achieved, and the contention is resolved. In the embodiment of the present invention, a slot can be understood as a clock cycle, and one slot can be understood as one clock cycle.

[0045] JPEG0007602712000006.jpg31155

[0046] Next, we introduce another related art arbitration scheme that determines the first request to be granted in the current clock cycle based on equation (2).

number

[0047] JPEG0007602712000008.jpg43155

[0048] 5 is a schematic diagram of another arbitration method according to the related art. The arbitration method can adopt a fair-fifo arbitration method. As shown in FIG. 5, take the number of VDSP cores as an example, the four VDSP cores are core0, core1, core2, and core3, respectively, and the read signals sent by core0, core1, core2, and core3 can be core0 RD signal, core1 RD signal, core2 RD signal, and core3 RD signal, respectively.

[0049] JPEG0007602712000009.jpg49155

[0050] In some embodiments, the VDSP core can grant read requests received first. For example, continuing to refer to FIG. 5, the VMA 6th Clock Period When the VDSP core receives the core2 RD signal, the VDSP core accepts the core3 RD signal instead of the core2 RD signal, so the core2 RD signal 6th clock period Pipeline stalls start to occur.

[0051] In an embodiment of the present application, when a pending read request is sent to the VMA, the request granted by the VMA is independent of clock cycles and slot allocation, and since the VMA serves one VDSP core at any given time, there are no empty clock cycles in such an arbitration scheme.

[0052] 4 and 5, it can be seen that the number of occurrences of pipeline stalls is reduced in the second related technology compared to the first related technology.

[0053] However, the solution corresponding to figure 5 has a drawback: if one signal is not granted in the current clock cycle and another signal arrives in the next clock cycle, the other signal will become stalled, i.e. a new stall cycle will be introduced.

[0054] 6 is a flow chart of an arbitration method according to an embodiment of the present application. As shown in FIG. 6, the method can be applied to an arbitration module and includes the following operations:

[0055] S601, Nth clock period Now, obtain the P first requests separately sent by the P processing modules in the M processing modules.

[0056] Each of the M processing modules is configured to send a first request to the storage module via the arbitration module, where M is an integer greater than or equal to P, N is an integer greater than or equal to 0, and P is an integer greater than or equal to 2.

[0057] The arbitration module may be an arbiter. The arbiter in the embodiment of the present application may be the above-mentioned VMA, and in some other embodiments, the arbiter may be an MA. The arbitration module is used to authorize or confirm the obtained first request, and the arbitration module can send the authorized or confirmed first request to the storage module.

[0058] In some embodiments, the storage module may be any one of the above VM blocks, or may include one of a memory block, a read-only memory (ROM), a random access memory (RAM), a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), and a double data rate SDRAM (DDR SDRAM). The storage module in the embodiments of the present application may be any one of the Q VM blocks described above.

[0059] The M processing modules may be the M VDSP cores described above. In some embodiments, any of the M processing modules includes one of a digital signal processing (DSP) core, a microcontroller unit (MCU), a field programmable gate array (FPGA), an advanced reduced instruction set computer (RISC) machine (ARM), a central processing unit (CPU), and an application specific integrated circuit (ASIC).

[0060] In some embodiments, the first request may include a read request to read data from the storage module, while in other embodiments, the first request may include a write request to write data to the storage module.

[0061] Any of the M processing modules may send a first request to the storage module via the arbitration module. In some embodiments, any of the M processing modules may send a read request to the storage module via the arbitration module, or may send a write request to the storage module via the arbitration module. The arbitration module may then determine a read request currently sent to the storage module from the at least two read requests, or the arbitration module may determine a write request currently sent to the storage module from the at least two write requests. The clock cycles during which each processing module sends a read request and a write request are different.

[0062] The M processing modules may include a 0th processing module (corresponding ID is 0), a 1st processing module (corresponding ID is 1) to an M-1th processing module (corresponding ID is M-1). The IDs corresponding to the M processing modules may include 0, 1 to M-1.

[0063] In the embodiment of the present application Nth clock period is as mentioned above. The nth clock period may be the same clock period.

[0064] None of the P first requests may be first requests that have not been granted by the arbitration module.

[0065] In some embodiments, any of the P first requests Nth clock period For example, if M is 4, in the embodiment corresponding to FIG. 5, the arbitration module Fourth Clock PeriodThen, the 0th, 1st and 3rd processing modules Fourth Clock Period The first request may be received.

[0066] In another embodiment, at least one of the P first requests comprises: Nth clock period There are two cases for such an embodiment. In the first case, all of the P first requests are Nth clock period For example, if M is 4, in the embodiment corresponding to FIG. 5th clock period Then, the first processing module and the third processing module each Third Clock Period In the second case, some of the P first requests are Nth clock period and another part of the P first requests is sent Nth clock period is sent before

[0067] In some embodiments, any of the P first requests Nth clock period or at least one of the P first requests is Nth clock period In an embodiment of the present application, the arbitration module Nth clock period Any of the first requests received in Nth clock period The first request received from the processing module or the arbitration module Nth clock period This is the first request received from the processing module before Nth clock period Before that, (NM-1)th from the clock period (N-1)th The period may be any one clock period up to the clock period of the first clock.

[0068] In an embodiment of the present application, Nth clock period When the arbitration module receives a first request sent by one of the M processing modules, the arbitration module may: Nth clock period The target request sent to the storage module can be determined by the arbitration module. Nth clock periodBy granting the first request at Nth clock period Then, the first request can be sent to the storage module.

[0069] S603, determining P time slot values ​​separately assigned to the identifiers (IDs) of the P processing modules from a first time slot table.

[0070] The first time slot table is Nth clock period The time slot tables corresponding to different clock periods may be the same or different, in other words, the time slot table can be continuously updated with the count of clock periods. The time slot table corresponding to each clock period may be a time slot table including M time slot values. The first time slot table includes M time slot values ​​arranged in a specific order. In some embodiments, the arbitration module can store the first time slot table. The M time slot values ​​can correspond to the IDs of the M processing modules. For example, if the IDs of the M processing modules are 0, 1, 2, and 3, respectively, the M time slot values ​​also include 0, 1, 2, and 3. The IDs of the M processing modules can respectively label the M processing modules. The time slot table in the embodiment of the present application can be understood as a clock period table.

[0071] Determining the P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table can include determining the time slot values ​​at the positions of the IDs of the P processing modules in the first time slot table as the P time slot values. For example, if the first time slot table is {3, 1, 2, 4} and the IDs of the P processing modules are 0 and 3, then 0th position Time slot value 3 in 3rd position Let time slot value 4 in be the P time slot values ​​obtained.

[0072] In some embodiments, the ID of one processing module or one processing module can correspond to one time slot value, and a unique corresponding time slot value can be found based on the ID of the processing module, and a unique processing module ID can also be found based on the one time slot value. The arbitration module can determine P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table according to a preset rule. For example, the arbitration module can determine P time slot values ​​separately assigned to the IDs of the P processing modules based on a mapping relationship between the IDs of the processing modules and the time slot values. The mapping relationship may be preset. The mapping relationship may be a list or a mathematical formula. As another example, the IDs of the P processing modules may be the same as the P time slot values ​​included in the time slot table, i.e., when the IDs of the P processing modules are 0, 1, 2, and 3, the P time slot values ​​may be 0, 1, 2, and 3 in any order.

[0073] S605, Nth clock period Based on the normalized clock period counts and the P time slot values ​​corresponding to Nth clock period determines the target request to be sent to the storage module.

[0074] The IDs of the processing modules can correspond to the counts of the normalized clock periods. In some embodiments, the IDs of the M processing modules can be equal to the counts of the M normalized clock periods. For example, if the M normalized clock periods are 0, 1, 2, and 3, respectively, then the IDs of the M processing modules are also 0, 1, 2, and 3, respectively. In other embodiments, the IDs of the M processing modules can be different from the counts of the M normalized clock periods, but the IDs of the M processing modules can correspond to the counts of the M normalized clock periods. For example, the count of the normalized clock periods corresponding to one processing module ID "A" is 0, and the count of the normalized clock periods corresponding to one processing module ID "B" is 1.

[0075] In the embodiments of the present application, the IDs of the M processing modules may each be equal to a count of M normalized clock periods. However, it should be understood that in other embodiments, the IDs of the M processing modules may each be different from a count of M normalized clock periods and still fall within the scope of protection of the present application.

[0076] The purpose of normalization is to process and constrain the actual clock period count to be within a certain range, and the range defined by normalization in the embodiment of the present application is an integer between 0 and M-1. The normalized clock period count is not the actual clock period count N, but rather the actual clock period count N is processed and constrained to be an integer between 0 and M-1.

[0077] The normalized clock period count is equal to the value of N modulo M. In an embodiment of the present application, the normalized clock period count is obtained based on the actual clock period count N modulo the total number M of processing modules. For example, if M is 4 and N is 3, the normalized clock period count is 3%4=3. As another example, if M is 4 and N is 12, the normalized clock period count is 12%4=0.

[0078] In some embodiments, the arbitration module can determine a target timeslot value that is closest to a normalized count of clock periods from the P timeslot values, and take the request sent by the processing module that corresponds to that target timeslot value as the target request.

[0079] In some further embodiments, the arbitration module may determine a first timeslot value that is furthest from a count of normalized clock periods from the P timeslot values, and the request sent by the processing module corresponding to that first timeslot value may be the target request.

[0080] In yet some other embodiments, the arbitration module may determine a second timeslot value that satisfies a preset relationship between the count of normalized clock periods from the P timeslot values, and the request sent by the processing module corresponding to the second timeslot value may be the target request.

[0081] After 605, Nth clock period The storage module may also receive target requests sent by the arbitration module.

[0082] In some embodiments, if the first request is a read request, the arbitration module: (N+3)th In a clock cycle, the storage module may receive request data sent by the processing module that sent the target request, the request data being data for responding to the read request.

[0083] In some embodiments, the arbitration module: (N+4)th At clock intervals or (N+4)th A clock period later, a first request may be received that was sent to the storage module by the processing module that sent the target request.

[0084] In the first related technique, the IDs of the P processing modules are all Nth clock period In the second related art, if the IDs of the P processing modules do not correspond to the normalized clock period count corresponding to Nth clock period If the count of normalized clock periods corresponding to P does not correspond to P, then grant one random first request from P requests, and the granted first request is Nth clock period This is the target request sent to the storage module at

[0085] In an embodiment of the present application, the arbitration module does not randomly determine and grant one first request from the P first requests, but first determines P time slot values ​​corresponding to the IDs of the P processing modules from a first time slot table, respectively, and then, based on the P time slot values ​​and the count of the normalized clock periods, Nth clock period Then, based on the target request to be sent to the storage module, i.e., the first time slot table, the IDs of the P processing modules, and the normalized clock period count, one first request is selected from the P first requests and granted.

[0086] Although the embodiment of the present application illustrates that the target request confirmed by the arbitration module is one first request, the embodiment of the present application is not limited thereto, and in another embodiment, the target request that can be confirmed by the arbitration module may be at least two first requests.

[0087] In an embodiment of the present application, Nth clock periodBased on the normalized clock period count corresponding to the P time slot values ​​determined from the first time slot table, Nth clock period determines the target request to be sent to the storage module. Nth clock period determining a target request to be sent to the storage module; Nth clock period In this way, it is possible to avoid the inability to determine the target request sent to the storage module, and further improve the arbitration efficiency of the arbiter, it is possible to improve the certainty that the target request is determined among the P first requests by the arbitration module, it is possible to avoid the problem of the uncertainty of the selected target request caused by randomly selecting a target request from the P first requests, and it is possible to meet the arbitration needs in different cases.

[0088] 7 is a flow chart of another arbitration method according to an embodiment of the present application. As shown in FIG. 7, the method can be applied to an arbitration module. The difference between the embodiment corresponding to FIG. 7 and the embodiment corresponding to FIG. 6 is that the embodiment corresponding to FIG. 7 further includes:

[0089] S701, the IDs of P processing modules are all Nth clock period , if the count of normalized clock periods corresponding to the P processing modules is not corresponding to the count of normalized clock periods corresponding to the P processing modules, the P time slot values ​​are determined from the first time slot table.

[0090] The IDs of P processing modules are Nth clock period The fact that the IDs of all P processing modules do not correspond to the count of normalized clock periods corresponding to Nth clock period , which may differ from the count of normalized clock periods corresponding to

[0091] S703, if a first ID in the IDs of the P processing modules corresponds to a count of normalized clock periods, a first request sent by a processing module corresponding to the first ID is taken as a target request.

[0092] In some embodiments, the count of normalized clock periods is the same as the value of N modulo M.

[0093] The first one of the IDs of the P processing modules corresponding to the count of normalized clock periods may include the first one of the IDs of the P processing modules being the same as the count of normalized clock periods.

[0094] In addition, in the second related technique, a first ID among the IDs of the P processing modules corresponds to a count of normalized clock periods, and at least one of the P first requests is Nth clock period If the first request is received by the arbitration module before the first request, the arbitration module can randomly select one first request from the at least one first request as the target request. Nth clock period And the arbitration module Nth clock period granting the first request received before Nth clock period The first request received by the arbitration module results in a pipeline stall.

[0095] However, in the embodiment of the present application, the first requirement is Nth clock period Was it received on Nth clock period If the arbitration module determines that a first ID corresponding to the normalized clock period count is present among the acquired IDs of the P processing modules, regardless of whether the first request was received before the first ID, the arbitration module determines that the first request sent by the processing module corresponding to the first ID is the target request.

[0096] In an embodiment of the present application, the arbitration module can minimize disruption of current aligned accesses by consistently granting the first request corresponding to the first ID that is the same as the normalized clock period count.

[0097] 8 is a flowchart of another arbitration method according to an embodiment of the present application. As shown in FIG. 8, the method can be applied to an arbitration module, and includes:

[0098] S801, Nth clock period Now, obtain the P first requests separately sent by the P processing modules in the M processing modules.

[0099] S803, determining P time slot values ​​separately assigned to the IDs of the P processing modules from a first time slot table.

[0100] S805, determine the absolute value of the difference between each of the P time slot values ​​and the normalized clock period count.

[0101] S807, determining a target time slot value corresponding to the minimum value in the absolute value of the difference.

[0102] In some embodiments, the arbitration module may determine a target timeslot value that corresponds to the smaller or larger of the two absolute values ​​of the difference if there are two minimum values ​​in the absolute values ​​of the difference.

[0103] S809, the first request sent by the processing module corresponding to the target time slot value is taken as the target request.

[0104] In an embodiment of the present application, the arbitration module selects a target time slot value from the P time slot values ​​that is closest to the count of normalized clock periods, and takes the first request sent by the processing module corresponding to the target time slot value as the target request. However, in other embodiments, the arbitration module can select a time slot value from the P time slot values ​​that is farthest from the count of normalized clock periods, and select the first request corresponding to the time slot value as the target request. An embodiment may also be that the first time slot value that corresponds to the maximum of the absolute values ​​of the difference is determined, and the first request sent by the processing module corresponding to the first time slot value is taken as the target request.

[0105] In the embodiment of the present application, the IDs of the P processing modules are all Nth clock period In the case where the count of normalized clock periods corresponding to P first requests does not correspond to a count of normalized clock periods corresponding to P first requests, the arbitration module provides a method for determining a target request from the P first requests, thereby increasing the certainty with which the arbitration module determines one first request among the P first requests.

[0106] 9 is a flowchart of yet another arbitration method according to an embodiment of the present application. As shown in FIG. 9, the method can be applied to an arbitration module, and includes:

[0107] S901, Nth clock period Now, obtain the P first requests separately sent by the P processing modules in the M processing modules.

[0108] S903, determining P time slot values ​​separately assigned to the IDs of the P processing modules from a first time slot table.

[0109] S905, based on the count of the normalized clock periods and the P time slot values, from the P first requests Nth clock period determines the target request to be sent to the storage module.

[0110] S907, in the first time slot table i-th position If the time slot value in corresponds to the ID of the processing module that sent the target request, (N+1)th Let us assume that the time slot table corresponds to the clock period of

[0111] The value of i is the same as the count of normalized clock periods, ie, the value of i is N modulo M.

[0112] i-th position The time slot value in corresponds to the ID of the processing module that sent the target request. i-th position may include that the time slot value in is the same as the ID of the processing module that sent the target request.

[0113] In some embodiments, in the first time slot table i-th position The timeslot values ​​preceding each correspond to the first request sent by a processing module that has already been granted.

[0114] S909, in the first time slot table i-th position does not correspond to the ID of the processing module that sent the target request, the first time slot table is updated to obtain the second time slot table.

[0115] i-th position The fact that the time slot value in does not correspond to the ID of the processing module that sent the target request i-th position may include that the time slot value in is different from the ID of the processing module that sent the target request.

[0116] The arbitration module selects a first time slot table. Nth clock period to obtain the second time slot table.

[0117] The arbitration module can update the first time slot table through the following method: The arbitration module determines whether the time slot value corresponding to the ID of the processing module that sent the target request is in the first time slot table; jth position and in the first time slot table i-th position and the time slot value in jth position The time slot values ​​in can be exchanged to obtain a second time slot table.

[0118] Here, there is a time slot value corresponding to the ID of the processing module that sent the target request. jth position has the same time slot value as the ID of the processing module that sent the target request. jth position may include.

[0119] S911, the second time slot table (N+1)th Let us assume that the time slot table corresponds to the clock period of

[0120] Table 1 is an example of a time slot table update method according to an embodiment of the present application. Table 1 is as follows:

[0121] [Table 1]

[0122] As can be seen from Table 1, 0th clock period (the corresponding normalized clock period count is 0), 0th clock period The time slot table corresponding to i is [0, 1, 2, 3], i=N%M=0%4=0, and the ID of the processing module that sent the first request is {0, 3}. The arbitration module calculates the time slot values ​​assigned to the processing module IDs {0, 3} from the time slot table [0, 1, 2, 3] as follows: 0th position Time slot values ​​0 and 3rd position The time slot value is determined to be 3. 0th positionSince the time slot value 0 in is closest to the time slot value 0 in the normalized clock period, the ID 0 of the processing module corresponding to the time slot value 0 is taken as the ID of the processing module that sent the target request. i(i=0)th Since the time slot value 0 at the position is the same as the ID 0 of the processing module that sent the target request, 0th clock period The time slot table corresponding to 1st Clock Period Let us assume that the time slot table corresponds to:

[0123] 1st Clock Period (the corresponding normalized clock period count is 1) 1st Clock Period The time slot table corresponding to i is [0,1,2,3], i=N%M=1%4=1, and the ID of the processing module that sent the first request is {2,3}. The arbitration module calculates the time slot values ​​assigned to the processing module ID {2,3} from the time slot table [0,1,2,3] as follows: Second position Time slot value 2 and 3rd position The time slot value is determined to be 3. Second position Since the time slot value 2 in is closest to the normalized clock period count 1, let the ID 2 of the processing module corresponding to the time slot value 2 be the ID of the processing module that sent the target request. Here, i(i=1)th Since the time slot value 1 at the position and the ID 2 of the processing module that sent the target request are different, 1st position Time slot value 1 in Second position Swap the time slot value 2 in to get the time slot table [0,2,1,3].

[0124] Second Clock Period (the corresponding normalized clock period count is 2) Second Clock Period The time slot table corresponding to i is [0, 2, 1, 3], i=N%M=2%4=2, and the ID of the processing module that sent the first request is {3}. The arbitration module selects the slot assigned to the processing module ID {3} from the time slot table [0, 2, 1, 3] as follows: 3rd positionSince there is only one request, the ID 3 of the processing module corresponding to the time slot value 3 is set as the ID of the processing module that sent the target request. i(i=2)th Since the time slot value 1 at the position and the ID 3 of the processing module that sent the target request are different, Second position Time slot value 1 in 3rd position Swap the time slot value 3 in to get the time slot table [0, 2, 3, 1].

[0125] Third Clock Period (the corresponding normalized clock period count is 3) Third Clock Period The time slot table corresponding to i is [0, 2, 3, 1], i=N%M=3%4=3, the ID of the processing module that transmits the first request is {1}, and the arbitration module calculates the time slot value assigned to the processing module ID {1} from the time slot table [0, 2, 3, 1] by 1st position Since there is only one request, the ID 1 of the processing module corresponding to the time slot value 2 is set as the ID of the processing module that sent the target request. i(i=3)th Since the time slot value 1 at the position is the same as the ID 1 of the processing module that sent the target request, Second Clock Period The time slot table corresponding to Third Clock Period Let us assume that the time slot table corresponds to:

[0126] Fourth Clock Period (the corresponding normalized clock period count is 0) Fourth Clock Period The time slot table corresponding to is [0,2,3,1], the ID of the processing module that sent the first request is {}, and the ID of the processing module that sent the target request and was determined is NA. Fourth Clock Period The time slot table corresponding to 5th clock period Let us assume that the time slot table corresponds to:

[0127] In the embodiment of the present application, by setting a time slot table corresponding to different clock periods, Nth clock periodand recording the first request that was granted; and Nth clock period Through positions authorized in (N+1)th For example, in Table 1, we can find a suitable first request that is granted in Third Clock Period For example, Second Clock Period It can be determined based on the time slot table that the ID of the processing module authorized in is 3.

[0128] Then, when there are at least two first requests in a certain clock period, the arbitration module can select as a target request a first request corresponding to the ID of a processing module whose time slot value is closest to the normalized clock period count among the IDs of the processing modules, thereby not only ensuring the granting of one first request in the current clock period, but also minimizing the stall time of other ungranted first requests after granting the first request.

[0129] 10 is a flow chart of an arbitration method according to another embodiment of the present application. As shown in FIG. 10, the method can be applied to an arbitration module. The arbitration method according to the embodiment of the present application is a dynamic loop (or dynamic round robin) arbitration method. Through a time slot table Nth clock period The dynamic loop arbitration method can determine a first request to be granted in a current clock cycle. Even if a first request sent by a processing module in a current clock cycle does not correspond to the current clock cycle, the first request can still be granted or confirmed in the current clock cycle, and the cost of realignment due to stalling of other first requests can be minimized. The method includes:

[0130] JPEG0007602712000011.jpg12155

[0131] JPEG0007602712000012.jpg37155

[0132] S1003, through a dynamic loop The nth clock periodDetermine which read request signals are granted.

[0133] Determining the read request signal that is granted through the dynamic loop can be implemented via equation (3).

number

[0134] JPEG0007602712000014.jpg69155

[0135] S1005, by the arbitration module Nth clock period It is determined whether the read request signal whose authorization has been confirmed is NULL.

[0136] If the answer is YES, step S1007 is executed, and if the answer is NO, step S1009 is executed.

[0137] S1007, the arbitration module does not grant any read request signal.

[0138] JPEG0007602712000015.jpg5155

[0139] JPEG0007602712000016.jpg5155

number

[0140] JPEG0007602712000018.jpg31155

[0141] JPEG0007602712000019.jpg18155

[0142] JPEG0007602712000020.jpg17155

[0143] In order to illustrate the advantages of the dynamic loop arbitration method in the embodiment of the present application compared with the first related art (round robin arbitration method) and the second related art (fair first-in first-out arbitration method), a simulation is performed using a simulation method.

[0144] Table 2 is the parameter setting of the simulation according to the embodiment of the present application.

[0145] [Table 2]

[0146] In Table 2, the number of processing units may be the number of cores in one or more VDSP systems. The total simulation period may be the clock period of the simulation. The two adjacent memory units may be the xth VM block and the x+1th VM block.

[0147] JPEG0007602712000022.jpg37155

[0148] As can be seen from the simulation results, the number of stalls in the dynamic loop arbitration method is much less than the number of stalls in the round robin arbitration method, and is also less than the number of stalls in the fair first-in first-out arbitration method.

[0149] The engineers discovered that when external stalls occur frequently (e.g., maximum of 20 cycles, average of 1 in 10 cycles), the dynamic loop arbitration method had a stall count of 0.155, a 15.5% decrease over the fair FIFO arbitration method, which had a stall count of 0.179. When external stalls occur infrequently (e.g., maximum of 200 cycles, average of 1 in 100 cycles), the dynamic loop arbitration method had a stall count of 0.911, a 9.8% decrease over the fair FIFO arbitration method, which had a stall count of 1.000.

[0150] In the embodiment of the present application, the dynamic loop arbitration method reduces the average number of stalls of each processing unit and provides low-latency access of the processing units to the storage unit, thereby resolving the contention. In the embodiment of the present application, a time slot table corresponding to different clock periods is introduced, so that unaligned access (or unauthorized access) can be quickly identified and the disruption of the current aligned access can be minimized. For example, as shown in FIG. 5, when the arbitration unit 7th clock period Instead of receiving the CORE2 RD signal, 6th clock period If the CORE2 RD signal is received, it will still be arbitrated through the fair first-in, first-out arbitration method. 6th clock period RD signal is granted to CORE3, which leads to the stall of CORE2 RD signal continuing to occur. However, through the dynamic loop arbitration method in the embodiment of the present application, 6th clock period , which asserts the CORE2 RD signal, resulting in no stalling of the CORE2 RD signal and no disruption to currently aligned accesses.

[0151] Based on the above embodiment, an embodiment of the present application provides a data processing device. Each unit included in the arbitration device and each module included in each unit can be realized by a logic circuit in the data processing device.

[0152] 12 is a schematic diagram showing the structure of another data processing device according to an embodiment of the present application. As shown in FIG. 12, the data processing device 1200 includes M processing modules 1201, an arbitration module 1202 and a storage module 1203.

[0153] Each of the M processing modules is configured to send a first request to the storage module via the arbitration module.

[0154] The arbitration module 1202 is Nth clock periodobtain P first requests sent by P processing modules in the M processing modules separately; and determine P time slot values ​​assigned to IDs of the P processing modules separately from a first time slot table; and Nth clock period Based on the normalized clock period counts and the P time slot values ​​corresponding to Nth clock period and configured to determine a target request to be sent to the storage module by M, where M is an integer greater than or equal to P, N is an integer greater than or equal to 0, and P is an integer greater than or equal to 2.

[0155] The storage module 1203 stores the target request sent by the arbitration module. Nth clock period The device is configured to receive

[0156] In some embodiments, the count of normalized clock periods is the same as the value of N modulo M.

[0157] In some embodiments, the first time slot table is Nth clock period and includes M timeslot values ​​arranged in a particular order. The arbitration module 1202 is further configured to take the timeslot values ​​at the positions of the IDs of the P processing modules in the first timeslot table as the P timeslot values.

[0158] In some embodiments, the arbitration module 1202 is further configured to determine an absolute value of a difference between each of the P timeslot values ​​and the count of the normalized clock period, determine a target timeslot value corresponding to the minimum value of the absolute values ​​of the differences, and take the first request sent by the processing module corresponding to the target timeslot value as the target request.

[0159] In some embodiments, the arbitration module 1202 may include a first time slot table i-th position If the time slot value in corresponds to the ID of the processing module that sent the target request, (N+1)thThe time slot table is further configured to correspond to a clock period of i, where the value of i is equal to the count of the normalized clock periods.

[0160] In some embodiments, the arbitration module 1202 may include a first time slot table i-th position does not correspond to the ID of the processing module that sent the target request, update the first time slot table to obtain a second time slot table, and (N+1)th The time slot table is further configured to correspond to a clock period of i, where the value of i is equal to the count of the normalized clock periods.

[0161] In some embodiments, the arbitration module 1202 determines whether a time slot value corresponding to the ID of the processing module that sent the target request is in the first time slot table. jth position and in the first time slot table i-th position and the time slot value in jth position to obtain a second timeslot table.

[0162] In some embodiments, the arbitration module 1202 is further configured to determine P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table when none of the IDs of the P processing modules correspond to a count of the normalized clock periods.

[0163] In some embodiments, the arbitration module 1202 is further configured to determine, if a first ID in the IDs of the P processing modules corresponds to a count of normalized clock periods, a first request sent by a processing module corresponding to a first ID as the target request.

[0164] In some embodiments, any of the P first requests Nth clock periodor at least one of the first requests in the P first requests is Nth clock period was sent before.

[0165] In some embodiments, any of the M processing modules includes one of a DSP core, an MCU, an FPGA, an ARM, a CPU, and an ASIC.

[0166] The storage module includes one of a memory block, a ROM, a RAM, a DRAM, an SRAM, a SDRAM, and a DDR SDRAM.

[0167] In some embodiments, the first request includes a read request to read data from the storage module or a write request to write data to the storage module.

[0168] In some embodiments, if the first request is a read request, the arbitration module may: (N+3)th Receive at clock cycles.

[0169] In some embodiments, the arbitration module is configured to arbitrate a first request sent to the storage module by the processing module that sent the target request: (N+4)th or at clock cycles (N+4)th The received data is received after 1 clock period.

[0170] In some embodiments, the digital processing device may include Q memory blocks, any of which may be a memory block in any of the embodiments described above.

[0171] In some embodiments, the arbitration module may include a first interface, the first interface being used to communicate with an external master.

[0172] In some embodiments, the arbitration module may include a second interface, the second interface being used to communicate with an external slave.

[0173] The description of the above device embodiment is similar to the description of the above method embodiment, and has similar beneficial effects to the method embodiment. For technical details not disclosed in the device embodiment of the present application, please refer to the description of the method embodiment of the present application for understanding.

[0174] It should be noted that in the embodiments of the present application, the above-mentioned arbitration method may be realized in the form of a software functional module, and may be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, an essential part of the technical solution according to the embodiments of the present application, or a part that contributes to the related art, may be realized as a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing an arbitration device to execute all or part of the method according to each embodiment of the present application. The aforementioned storage medium includes various types of media capable of storing program code, such as a universal serial bus (USB) flash disk, a mobile hard disk, a ROM, a magnetic disk, or an optical disk. The embodiments of the present application are not limited to any specific combination of hardware and software.

[0175] Based on the above-mentioned embodiment, the embodiment of the present application provides an arbitration device. Each unit included in the arbitration device and each module included in each unit can be realized by a logic circuit.

[0176] 13 is a schematic diagram showing the structure of an arbitration device according to an embodiment of the present application. As shown in FIG. 13, the arbitration device 1300 includes an acquisition unit 1301 and a first determination unit 1302.

[0177] The acquisition unit 1301 is Nth clock periodand acquiring P first requests separately transmitted by P processing modules in the M processing modules, each of the M processing modules being configured to transmit the first request to the storage module via the arbitration module, where M is an integer greater than or equal to P, N is an integer greater than or equal to 0, and P is an integer greater than or equal to 2.

[0178] The first determining unit 1302 is configured to determine P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table.

[0179] The first determining unit 1302 is Nth clock period Based on the normalized clock period counts and the P time slot values ​​corresponding to Nth clock period The target request is further configured to be transmitted to the storage module at

[0180] In some embodiments, the count of normalized clock periods is the same as the value of N modulo M.

[0181] In some embodiments, the first time slot table comprises: Nth clock period , and contains M time slot values ​​arranged in a particular order.

[0182] The first determining unit 1302 is further configured to set the time slot values ​​at the positions of the IDs of the P processing modules in the first time slot table as the P time slot values.

[0183] In some embodiments, the first determination unit 1302 is further configured to determine absolute values ​​of differences between each of the P time slot values ​​and the count of the normalized clock period, determine a target time slot value corresponding to the minimum value in the absolute values ​​of the differences, and take the first request sent by the processing module corresponding to the target time slot value as the target request.

[0184] In some embodiments, the arbitration device includes a second determining unit 1303. The second determining unit 1303 determines whether the first time slot table i-th position If the time slot value in corresponds to the ID of the processing module that sent the target request, (N+1)th The time slot table is further configured to correspond to a clock period of i, where the value of i is equal to the count of the normalized clock periods.

[0185] In some embodiments, the second determining unit 1303 determines whether the first time slot in the first time slot table is i-th position does not correspond to the ID of the processing module that sent the target request, update the first time slot table to obtain a second time slot table, and (N+1)th The time slot table is further configured to correspond to a clock period of i, where the value of i is equal to the count of the normalized clock periods.

[0186] In some embodiments, the second determining unit 1303 determines whether a time slot value corresponding to the ID of the processing module that sent the target request is in the first time slot table. jth position Determine and in the first time slot table i-th position and the time slot value placed in jth position to obtain a second time slot table.

[0187] In some embodiments, the first determination unit 1302 is further configured to determine P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table when none of the IDs of the P processing modules correspond to the count of the normalized clock period.

[0188] In some embodiments, the first determination unit 1302 is further configured to determine, when the first ID in the IDs of the P processing modules corresponds to a count of normalized clock periods, the first request sent by the processing module corresponding to the first ID as the target request.

[0189] In some embodiments, any of the P first requests Nth clock period or at least one of the first requests in the P first requests is Nth clock period was sent before.

[0190] In some embodiments, any of the M processing modules includes one of a DSP core, an MCU, an FPGA, an ARM, a CPU, and an ASIC.

[0191] The storage module includes one of a memory block, a ROM, a RAM, a DRAM, an SRAM, a SDRAM, and a DDR SDRAM.

[0192] In some embodiments, the first request includes a read request to read data from the storage module or a write request to write data to the storage module.

[0193] In some embodiments, if the first request is a read request, the arbitration module may: (N+3)th The processing module receives a target request every clock cycle.

[0194] In some embodiments, the arbitration module is configured to arbitrate a first request sent to the storage module by the processing module that sent the target request: (N+4)th or at clock cycles (N+4)th The received data is received after 1 clock period.

[0195] Fig. 14 is a schematic diagram of a hardware entity of an arbitration device according to an embodiment of the present application. As shown in Fig. 14, the arbitration device 1400 includes an arbitration module. The arbitration module includes a memory 1402 that stores a computer program executable on a processor 1401, and the processor 1401 performs the operations of the method of any of the above-mentioned embodiments when executing the program.

[0196] The memory 1402 is configured to store computer programs executable on the processor 1401, to store instructions and applications executable by the processor 1401, and can also cache data (e.g., image data, audio data, voice communication data, video communication data) that is processed or has been processed by the processor 1401 and each module of the arbitration device 14. It can be realized by a flash memory (FLASH) or a RAM.

[0197] When the processor 1401 executes the program, the operation of any one of the arbitration methods described above can be realized. The processor 1401 generally controls the overall operation of the arbitration device 1400.

[0198] In some embodiments, the arbitration device includes one of a modulator, a demodulator, and a modem, where the modem may be an integrated modulator and demodulator.

[0199] The mediation device may refer to a terminal, which may include a server, a mobile phone, a tablet, a laptop, a palmtop computer, a personal digital assistant, an instant media player, a smart speaker, a navigation device, a display device, a wearable device such as a smart handheld, a virtual reality (VR) device, an augmented reality (AR) device, a pedometer, a locator, a tracker, a digital TV, or a desktop computer.

[0200] In an embodiment of the present application, a computer storage medium is provided having stored thereon one or more programs executable by one or more processors to effectuate the operations of any of the methods described above.

[0201] In an embodiment of the present application, a computer program product is provided, comprising a computer storage medium having computer program code stored thereon, the computer program code including instructions executable by at least one processor, the instructions being configured to, when executed by the at least one processor, perform operations of the above-described method.

[0202] In some embodiments, the computer program product can be applied to the arbitration device in the embodiments of the present application, and the computer program instructions enable a computer to execute the corresponding processes implemented by the arbitration device in each method in the embodiments of the present application, which will not be described here for brevity.

[0203] Fig. 15 is a schematic diagram showing the structure of a chip according to an embodiment of the present application. The chip 1500 shown in Fig. 15 includes a processor 1501. The processor 1501 calls and executes a computer program from a memory to realize the operation of the method performed by the arbitration device in the embodiment of the present application.

[0204] In some embodiments, as shown in Fig. 15, the chip 1500 may also include a memory 1502. Here, the processor 1501 may call and execute a computer program from the memory 1502 to realize the operations of the method performed by the arbitration device in the embodiment of the present application.

[0205] Here, the memory 1502 may be a separate device independent of the processor 1501, or may be integrated into the processor 1501.

[0206] In some embodiments, the chip 1500 also includes an input interface 1503. Here, the processor 1501 can control the input interface 1503 to communicate with other devices or chips, and in particular, can obtain information or data sent by other devices or chips.

[0207] In some embodiments, chip 1500 also includes an output interface 1504, where processor 1501 can control output interface 1504 to communicate with other devices or chips, and in particular, can output information or data to other devices or chips.

[0208] In some embodiments, the chip 1500 can be applied to the arbitration device in the embodiments of the present application, and can realize the corresponding process realized by the arbitration device in each method in the embodiments of the present application. For the sake of brevity, it is not described here. The chip 1500 can be a chip in the arbitration device.

[0209] It should be understood that the chip 1500 mentioned in the embodiments of the present application can also be referred to as an on-chip system chip or the like.

[0210] At least one of the processing module, the arbitration module, the processor, and the external master in the embodiments of the present application may include at least one of a DSP core, an MCU, an FPGA, an ARM, a CPU, an ASIC, a digital signal processing device (DSPD), a programmable logic device (PLD), a controller, a microcontroller, and a microprocessor. The electronic device for realizing the above-mentioned processor function may be other, and is not particularly limited in the embodiments of the present application.

[0211] At least one of the above-mentioned storage module, computer storage medium, memory, and external slave may include a register, a memory block, a ROM, a RAM, a DRAM, an SRAM, an SDRAM, a DDR SDRAM, an enhanced SDRAM (ESDRAM), a synch link DRAM (SLDRAM), a direct rambus RAM (DR RAM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), a ferromagnetic RAM (FRAM), a flash memory, a magnetic surface memory, an optical disk, or a compact disc ROM (CD-ROM). That is, the memory in the embodiments of the present application includes, but is not limited to, these and any other suitable types of memory.

[0212] It should be noted that the above-mentioned description of the embodiments of the arbitration apparatus, data processing apparatus, arbitration device, computer storage medium, chip, and computer program product are similar to the description of the above-mentioned method embodiments, and have similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of the present application, please refer to the description of the method embodiments of the present application for understanding.

[0213] Please note that the terms "0th", "1st", "M-1st" and so on described in the embodiments of the present application are stated based on the perspective of a machine. It should be understood by those skilled in the art that the 0th processing unit from the perspective of a machine represents the 1st processing unit in reality, the M-1st processing unit from the perspective of a machine represents the Mth processing unit in reality, and so on, which will not be described one by one in the present application.

[0214] The plural or multiple times referred to in the embodiments of the present application should be understood as two or more and two or more times, unless otherwise stated. Unless otherwise stated, the count of normalized clock periods is Nth clock period Refers to the count of normalized clock periods corresponding to

[0215] The terms "one embodiment", "several embodiments", "one embodiment", "an embodiment", "an embodiment of the present application", or "the above embodiments" referred to throughout the specification mean that the particular features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Thus, the terms "one embodiment", "several embodiments", "one embodiment", "an embodiment", "an embodiment of the present application", or "the above embodiments" appearing in various places throughout the specification do not necessarily refer to the same embodiment. In addition, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the various embodiments of the present application, the magnitude of the numbers of the above steps does not indicate the order of execution. The order of execution of each step should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The numbers of the above embodiments of the present application are for illustrative purposes only and do not indicate the superiority or inferiority of the embodiments.

[0216] Unless otherwise specified, the arbitration device may perform any operation in the embodiments of the present application, and the processor of the arbitration device may perform the operation. Unless otherwise specified, the embodiments of the present application do not limit the order in which the arbitration device performs the following operations. Furthermore, the methods for processing data in different embodiments may be the same or different. It should also be noted that any operation in the embodiments of the present application may be independently performed by the arbitration device, i.e., the arbitration device may not depend on the execution of any other operation when performing any operation in the above-mentioned embodiment.

[0217] In the embodiments of the present application, the quantity / number indicated by a specific non-limiting English letter or character, such as M, Q, i, j, etc., may be determined based on the actual situation and / or context, and the quantity / number represented by a non-limiting English letter or character may be included in the range of an integer.

[0218] It should be understood that in some embodiments of the present application, the disclosed devices and methods may be realized in other forms. The above-described device embodiments are merely exemplary. For example, the division of units is merely a division of logical functions, and may have other division forms when actually realized. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented. Furthermore, the couplings, direct couplings, and communication connections between the components shown or discussed may be indirect couplings or communication connections through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0219] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, and may be located in one place or distributed among multiple network units. Some or all of these units may be selected to achieve the purpose of the present embodiment according to actual needs.

[0220] Furthermore, the functional units in the embodiments of the present application may all be integrated into one processing module, each unit may be integrated separately into one unit, or two or more units may be integrated into one unit. The above integrated units may be realized in the form of hardware, or may be realized in the form of adding a software functional unit to hardware.

[0221] Any method disclosed in any method embodiment of the present application may be combined to obtain a new method embodiment, unless there is a contradiction. Any feature disclosed in any product embodiment of the present application may be combined to obtain a new product embodiment, unless there is a contradiction. Any feature disclosed in any method or device embodiment of the present application may be combined to obtain a new method embodiment or device embodiment, unless there is a contradiction.

[0222] Those skilled in the art can understand that all or part of the operations in the above-mentioned method embodiments can be completed by a program instructing relevant hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it performs the operations in the above-mentioned method embodiments. The storage medium can include various kinds of media that can store program code, such as a mobile storage device, a ROM, a magnetic disk, or an optical disk.

[0223] The above integrated unit may be implemented as a software functional module and stored in a computer-readable recording medium when sold or used as an independent product. According to this understanding, the technical solutions in the embodiments of the present application, whether essential or contributing to the prior art, may be expressed as a software product. The computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The storage medium includes various types of media capable of storing program code, such as a mobile hard disk, a ROM, a magnetic disk, or an optical disk.

[0224] The above is only an embodiment of the present application, and the scope of protection of the present application is not limited thereto. Any modifications or replacements that a person skilled in the art can easily think of within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be determined by the scope of protection of the claims. [Industrial Applicability]

[0225] In the embodiments of the present application, an arbitration method, an apparatus, a device, a storage medium, a program product and a chip are provided. Nth clock period Based on the normalized clock period count corresponding to the P time slot values ​​determined from the first time slot table, Nth clock period determines the target request to be sent to the storage module. Nth clock period determining a target request to be sent to the storage module; Nth clock period In this way, it is possible to avoid the inability to determine the target request sent to the storage module, and further improve the arbitration efficiency of the arbiter, it is possible to improve the certainty that the target request is determined among the P first requests by the arbitration module, it is possible to avoid the problem of the uncertainty of the selected target request caused by randomly selecting a target request from the P first requests, and it is possible to meet the arbitration needs in different cases.

Claims

1. An arbitration method executed by an arbitration module, comprising: obtaining P first requests separately transmitted by P processing modules in M ​​processing modules at an Nth clock period, each of the M processing modules being configured to transmit a first request to a storage module via the arbitration module, where M is an integer equal to or greater than P, N is an integer equal to or greater than 0, and P is an integer equal to or greater than 2; determining P time slot values ​​from a first time slot table that are separately assigned to identifiers (IDs) of the P processing modules; determining a target request to be sent to the storage module in the Nth clock period from the P first requests based on a count of normalized clock periods corresponding to the Nth clock period and the P time slot values, where the count of normalized clock periods is equal to a value of N modulo M; determining a target request to be sent to the storage module in the Nth clock cycle from the P first requests based on the count of normalized clock periods corresponding to the Nth clock cycle and the P time slot values, determining an absolute value of a difference between each of the P time slot values ​​and the normalized count of clock periods; determining a target time slot value corresponding to a minimum of the absolute values ​​of the differences; determining a first request sent by a processing module corresponding to the target time slot value as the target request.

23. An arbitration method comprising:

2. the first time slot table corresponds to the Nth clock period and includes M time slot values ​​arranged in a particular order; The step of determining P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table includes: setting the P time slot values ​​at the positions of the IDs of the P processing modules in the first time slot table as the P time slot values. The method of claim 1 .

3. The arbitration method includes: If a time slot value at the ith position in the first time slot table corresponds to an ID of the processing module that sent the target request, the first time slot table is a time slot table corresponding to an (N+1)th clock period; The value of i is equal to the count of the normalized clock periods. The method of claim 1 .

4. The arbitration method includes: updating the first time slot table to obtain a second time slot table if the time slot value at the ith position in the first time slot table does not correspond to the ID of the processing module that sent the target request; and setting the second time slot table as a time slot table corresponding to the (N+1)th clock period; The value of i is equal to the count of the normalized clock periods.

4. The method of claim 1 or 3.

5. The step of updating the first time slot table to obtain a second time slot table includes: determining a j-th position in the first time slot table for a time slot value corresponding to an ID of the processing module that sent the target request; and exchanging the time slot value at the i-th position and the time slot value at the j-th position in the first time slot table to obtain the second time slot table. The method of claim 4 .

6. The step of determining P time slot values ​​separately assigned to the IDs of the P processing modules from the first time slot table includes: determining, when none of the P processing module IDs correspond to the normalized clock period count, the P time slot values ​​separately assigned to the P processing module IDs from the first time slot table; The method according to any one of claims 1 to 5.

7. The arbitration method includes: and determining, when a first ID in the IDs of the P processing modules corresponds to the count of the normalized clock periods, a first request sent by a processing module corresponding to the first ID as the target request. The method of claim 6 .

8. any of the P first requests are sent separately by the P processing modules in the Nth clock period; or At least one first request in the P first requests was transmitted prior to the Nth clock period. The method according to any one of claims 1 to 7.

9. the first request includes a read request to read data from the storage module or a write request to write data to the storage module. The method according to any one of claims 1 to 8.

10. When the first request is the read request, the arbitration module receives the request data sent from the storage module to the processing module in the (N+3)th clock cycle, and the processing module sends the target request. The method of claim 9 .

11. the arbitration module receives the first request sent to the storage module from the processing module that sent the target request at or after the (N+4)th clock cycle; The method according to any one of claims 1 to 10.

12. 1. An arbitration device comprising an arbitration module, the arbitration module comprises a memory and a processor; The memory is configured to store a computer program executable by the processor, the processor being configured to, when executing the computer program, perform the operations of the method according to any one of claims 1 to 11.

16. An arbitration device comprising:

13. A non-volatile computer storage medium having one or more programs stored thereon, The one or more programs are executable by one or more processors to perform the operations of the method according to any one of claims 1 to 11. A computer storage medium comprising:

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