Circuit for switching downlink / uplink operating modes in a TDD wireless communication system - Patents.com

Abstract

The circuit (C) for downlink / uplink operation mode switching in a TDD wireless communication system includes a field effect transistor (RF FET) and a large-capacity first resistor (R ) operably connected to a power amplifier (PA) in a downlink path (DL) of an RF front end in the TDD wireless communication system. hold ) connected to a first voltage generator (Vgs OFF ) and a second resistor (R Gate ) connected to a second voltage generator (V Gate ) and a large-capacity hold capacitor (C hold ), and a sample and hold circuit, which includes a first voltage generator (Vgs OFF ) is connected to the gate (G) of the field effect transistor (RF FET), and a large capacitance capacitor (C hold ) is the first resistor (R hold ) through the first voltage generator (Vgs OFF ) and the gate (G) of the RF field effect transistor (RF FET) is connected to the hold capacitor (C hold ) and a hold capacitor (C hold ) is the second resistor (R Gate ) through a second voltage generator (V Gate a transmit (Tx) configuration connected to the sample and hold circuit configured to be switched between a transmit (Tx) configuration and a ... connected to the sample and hold circuit.

Description

[Technical field]

[0001] The present invention relates to a circuit for downlink / uplink operating mode switching in a TDD wireless communication system. [Background technology]

[0002] In the field of long distance communications, it is known that efficient and fast switching of DL / UL (Downlink / Uplink) operating modes, i.e. Tx / Rx (Transmit / Receive), is of utmost importance when dealing with Time Division Duplex (TDD) signals.

[0003] In particular, when the system is in Tx mode, the PA (power amplifier) ​​in the DL should be turned on, which can be achieved by placing an LDMOS transistor equipped with an embedded thermal tracker for thermal compensation.

[0004] An example of a high level specification TDD RF front-end designed with high isolation RF switches at the antenna ports is shown in FIG.

[0005] In particular, it is known that an important aspect to take into account during the design phase of an RF power amplifier is its performance variation with temperature. In this respect, one of the main parameters to control is the quiescent current, which we strive to keep constant over a wide temperature range. It is a great challenge in this type of design.

[0006] Quiescent current tends to rise with operating temperature, an effect that reduces linearity. To overcome this difficulty, transistor manufacturers have embedded quiescent current thermal tracking circuits (small integrated LDMOS FETs located close to the active power LDMOS) into modern RF power integrated circuits.

[0007] An example of a thermal tracking device T is shown in FIG.

[0008] A constant current source is applied to the gate voltage V GWhen applied to the gate, the thermal tracking RF FET operates with a constant gate current I G When the temperature changes, the gate-source voltage V GS is the gate current I G As a result, the LDMOS power FET operates in response to the changing gate voltage V GS The quiescent current I DQ The temperature is also kept constant throughout.

[0009] However, the presence of the thermal tracking device T does not allow complete shutdown of the transistors within the Tx / Rx switching time defined in the 3GPP standard (approximately 1 microsecond).

[0010] This means that an RF switch, located at the antenna port and driven by a TDD synchronization signal, is required to communicate between Tx and Rx and must be designed with high isolation performance (see Figure 1).

[0011] However, the above solutions have some known drawbacks.

[0012] The first drawback concerns the high cost of the components, in particular due to the high isolation requirements for the RF switches.

[0013] Another drawback concerns the loss of efficiency in the DL path. In particular, the introduction of an RF switch after the PA increases the insertion loss of the DL path and therefore reduces the overall system efficiency.

[0014] Furthermore, known solutions reduce system reliability due to the high power levels that the RF switches must handle.

[0015] Finally, systems implemented with known solutions are power-intensive, in particular the PA is not completely switched off and draws dormant power even during Rx time slots. Summary of the Invention [Problem to be solved by the invention]

[0016] A primary objective of the present invention is to provide a circuit for efficient and rapid switching of DL / UL (Downlink / Uplink) operating modes in a TDD wireless communication system.

[0017] In particular, when the system is in Tx mode and supports time division duplexed (TDD) signals, the circuit according to the present invention allows turning on / off an LDMOS transistor equipped with an embedded thermal tracking device according to the strict timing requirements defined by the standard.

[0018] Another objective of the present invention is to provide a circuit for downlink / uplink operating mode switching in a TDD wireless communication system, which makes it possible to reduce the overall cost of the components used.

[0019] Another objective of the present invention is to provide a circuit for downlink / uplink operating mode switching in a TDD wireless communication system, which makes it possible to reduce the loss of efficiency in the DL path.

[0020] Another objective of the present invention is to provide a circuit for downlink / uplink operation mode switching in a TDD wireless communication system, which makes it possible to improve the reliability of the system.

[0021] Another objective of the present invention is to provide a circuit for downlink / uplink operation mode switching in a TDD wireless communication system, which makes it possible to reduce power consumption. [Means for solving the problem]

[0022] The above mentioned objective is achieved by means of a circuit for downlink / uplink operating mode switching in a TDD wireless communication system according to the features of claim 1.

[0023] Other features and advantages of the present invention will become more apparent from the description of preferred, but not exclusive, embodiments of a circuit for downlink / uplink operation mode switching in a TDD wireless communication system, illustrated as a non-limiting representation in the accompanying figures, in which: [Brief description of the drawings]

[0024] [Figure 1] FIG. 1 shows a high level standard TDD RF front-end designed with high isolation RF switches at the antenna ports according to known solutions. [Diagram 2] FIG. 1 illustrates a thermal tracking device according to a known solution. [Diagram 3] FIG. 1 shows a high level standard TDD RF front-end designed with high isolation RF switches at the antenna ports according to the present invention. [Figure 4] FIG. 13 illustrates a high level electrical scheme of the switching circuit for RF LDMOS enable / disable in the Rx operating mode configuration. [Diagram 5] FIG. 13 shows an equivalent circuit in an Rx operating mode configuration. [Figure 6] FIG. 13 illustrates a high level electrical scheme of the switching circuit for RF LDMOS enable / disable in a Tx mode of operation configuration. [Figure 7] FIG. 13 shows an equivalent circuit in a Tx mode of operation configuration. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Referring to these examples in detail, generally indicated by the reference character C is a circuit for downlink / uplink mode switching in a TDD wireless communication system.

[0026] Circuit C according to the present invention allows in a high level TDD RF front end to eliminate the RF switch at the antenna port and place the RF switch in the UL path before the LNA as shown in FIG. 3, thereby addressing all the issues in known solutions.

[0027] In particular, circuit C is designed to affect the gate voltage of a power amplifier LDMOS FET while the drain voltage is kept constant.

[0028] From a high level perspective, a circuit C according to the invention: - a voltage generator for setting the quiescent drain current of the power amplifier LDMOS; - a large-capacity resistor in series with the voltage source; A sample-and-hold circuit comprising two analog switches driven by a TDD standard sync signal and a hold capacitor; Equipped with.

[0029] This circuit C allows the LDMOS power amplifier PA to be completely shut down for a very limited time interval, even though the embedded thermal tracking device requires a large resistor in series with the LDMOS gate port to function properly.

[0030] The resistor limits the current supplied to the gate port to cause the LDMOS to change state (ie, from on to off and vice versa), thereby increasing the on / off time and exceeding the limits of the 3GPP standard.

[0031] Furthermore, the long commutation period can make sensitive parasitic effects of surrounding circuit components too severe, resulting in larger damped oscillations of the drain current (which can be significantly larger than the maximum LDMOS current).

[0032] Focusing on the TDD situation, the RF LDMOS used to realize the power amplifier PA needs to be activated only during the Tx phase (DL period). To improve the overall system efficiency while eliminating possible sources of thermal noise at the output of the power amplifier PA, one option is to reduce the quiescent current I DQ The aim of the present invention is to turn off the RF LDMOS during the RX phase (UL phase) by minimizing

[0033] The challenge is to use RF FETs equipped with thermal tracking devices while keeping the latency in the transition from TX to RX phase to less than 1 microsecond, as required by the 3GPP standard.

[0034] The proposed invention realises a circuit C to address the above problems, the high level electrical representation of which is shown in Figures 4 and 6 for the Rx and Tx modes of operation respectively.

[0035] The circuit C comprises at least one field effect transistor RF FET operatively connected to a power amplifier PA in a downlink path (DL) of an RF front-end arrangement in a TDD wireless communication system.

[0036] Additionally, circuit C: at least one large-capacity first resistor R hold A first voltage generator Vgs connected to OFF and; - Second resistor R Gate A second voltage generator V Gate and; - At least one large hold capacitor, C hold and; a sample and hold circuit; Equipped with.

[0037] In detail, the sample and hold circuit: -First voltage generator Vgs OFFis connected to the gate G of the field effect transistor RF FET, and a large capacitance capacitor C hold The first resistor R hold First voltage generator Vgs via OFF A receive (Rx) configuration connected to -The gate (G) of the field effect transistor RF FET is connected to the hold capacitor C hold and a hold capacitor C hold The second resistor R Gate A second voltage generator V Gate A transmit (Tx) configuration connected to The device is configured to be able to switch between

[0038] According to a preferred embodiment of the circuit C, the sample-and-hold circuit comprises a first electronic switch SW1 connected to the gate G of the field effect transistor RF FET and, in the receiving configuration, a first voltage generator Vgs OFF , and in the transmit configuration, the hold capacitor C hold The device is configured to be connected to the

[0039] In addition, the sample-and-hold circuit includes a hold capacitor C hold and in a receiving configuration, a first resistor R hold First voltage generator Vgs via OFF , and in the transmit configuration a second resistor R Gate A second voltage generator V Gate The device is configured to be connected to the

[0040] In detail, during the TDD RX phase (FIG. 4), the gate G of the field effect transistor RF FET is coupled to the first voltage generator Vgs via a first electronic switch SW1 driven by a TDD synchronization signal (TDD CRTL). OFF is connected to.

[0041] First voltage generator Vgs OFFis the gate-source threshold voltage Vgs in a field effect transistor RF FET th The gate-source threshold voltage Vgs of an RF FET is maintained at a constant value less than th is defined as the voltage level corresponding to an activated field effect transistor RF FET (i.e., a small amount of current flowing from drain to source).

[0042] Under these conditions, the drain current I d is close to zero.

[0043] The second electrical switch SW2 connects the large capacitance C hold The first resistor R hold (through a hold resistor) the first voltage generator Vgs OFF Connect to.

[0044] First resistor R hold is the hold capacitor C hold This allows the discharge time of V to be controlled, which can be several orders of magnitude larger than the TDD frame period. chold =Vgs ON is approximately constant throughout the entire RX phase when the system is stable (i.e., outside the initial transition phase). Here, V chold is the hold capacitor C hold The voltage values ​​range from

[0045] Advantageously, the first (hold) resistor R hold The presence of the sample and hold capacitor C ensures that when the system is not fed with any signal (TDD CTRL is not routed to the sample and hold circuit), the circuit C will remain in the sample and hold state for a defined amount of time, i.e., the hold capacitor C hold completes its discharge phase and reaches the idle state if the system does not remain in the last operating state (either Tx or Rx).

[0046] During the TX phase (see Figure 6), the gate of the field effect transistor RF FET is connected to the large hold capacitor C via a first electronic switch SW1 driven by the TDD synchronization signal (TDD CRTL). hold The second electrical switch SW2 is connected to the hold capacitor C hold Insert a second resistor R of appropriate size into Gate Through the second voltage generator V Gate Connect to.

[0047] In detail, the second voltage generator V Gate and a second resistor R Gate are connected in series and act as an equivalent current generator to reduce the quiescent current I of the transistor RF FET over temperature. D This allows the temperature to be kept constant.

[0048] Hold capacitor C hold and the first hold resistor R hold To achieve proper dimensioning of the V ripple The voltage value of the capacitor over time, V, is defined as chold The aim is to minimize the fluctuations in

[0049] At the same time, the voltage value of the capacitor V chold V as much as possible gs A stable value of V gs_SS It should be close to V gs_SS is defined as the upper voltage limit that is reached when the system operates indefinitely in the Tx configuration.

[0050] Voltage fluctuation V ripple is the hold capacitor C hold In this case, the sample-and-hold circuit is configured similarly to that shown in FIG. ripple is defined below.

[0051]

number

[0052] Here, t UL is the maximum duration of the UL period in the 3GPP standard for TDD applications, i.e., the worst case conditions, and V chold is the value obtained at the beginning of the UL period.

[0053] V chold and Vgs OFF The purpose is to use a hold capacitor C hold and hold resistor R hold For optimal selection of the voltage variation V ripple The aim is to minimize

[0054] Preferably, a hold capacitor C hold should be significantly larger (for example, 10 5 The maximum allowable size of the 1000 sq. m channel should be greater than twice as large.

[0055] As mentioned above, the voltage fluctuation V ripple must also satisfy the second requirement, so that the hold capacitor C hold and the first resistor R hold is the hold capacitor C during transmit (Tx) configuration hold The charge phase of the charger should be optimized to minimize the following equation:

[0056]

number

[0057] Here, t DL is the minimum duration of a DL period in the 3GPP standard for TDD applications, and V chold is the voltage value obtained at the beginning of the DL period.

[0058] V chold V gs_SS, the quiescent current actually drawn by the RF FET is close to the expected nominal I q Very close to.

[0059] In the transmit configuration, the sample and hold circuitry implements a configuration equivalent to that shown in FIG.

[0060] Considering the layout of the circuit C and the principle of its functioning explained above, it is assumed that the large capacitance C hold Because of this, the gate measures a low dynamic impedance.

[0061] Similarly, during the time interval when the transistor RF FET is supposed to be off (i.e., the RX period), the first voltage generator Vgs OFF Due to the connection to, the gate also measures a low dynamic impedance.

[0062] In this way, the switching latency of the transistor RF FET is short enough to comply with the limits set by the standards while ensuring a low quiescent current I D Provides accurate thermal compensation throughout the entire temperature range.

[0063] Furthermore, achieving low communication latency between the Tx / Rx phases minimizes the potential for damaging impacts due to sensitive parasitic effects of surrounding circuit components.

[0064] The TDD wireless communication system S according to the present invention, as shown in FIG. 3, comprises a downlink path DL PATH provided with at least one power amplifier PA, at least one uplink path UL PATH provided with at least one low noise amplifier LNA, and at least one antenna ANT connected to the downlink path DL PATH and the uplink path UL PATH.

[0065] The system S further comprises a circuit C for downlink / uplink operation mode switching, as disclosed above, which is operatively interposed between said power amplifier PA and said antenna ANT.

[0066] Furthermore, the system S includes an RF switch, which is disposed in the uplink path UL PATH and connected to the circuit C, and is configured to be switched between a receive (Rx) configuration connected to said low noise amplifier LNA and a transmit (Tx) configuration disconnected from said low noise amplifier LNA.

[0067] In particular, in the transmit (Tx) configuration, the RF switch is connected to a resistor R.

[0068] The benefit introduced in the new system S by the proposed new circuit C with respect to known systems is that it makes it possible to eliminate the RF switch at the antenna port and place an RF switch in the UL path before the LNA, as shown in FIG. 3.

[0069] Therefore, the circuit according to the invention is able to meet the stringent time requirements set by the 3GPP standard for latency in switching TDD operating modes.

[0070] The proposed invention realizes a solution to control LDMOS transistors provided with embedded thermal tracking devices, which are used in RF front-end circuits to realize PA stages for TDD applications.

[0071] In particular, the circuit according to the invention makes it possible to reduce the overall cost of the components used. The isolation requirements of the RF switch can be reduced thanks to the implementation of the proposed invention, which allows the transistor RF FET to be completely switched off.

[0072] Furthermore, the circuit according to the invention makes it possible to reduce the efficiency loss in the DL path: in particular, the implementation of the proposed invention avoids the introduction of an RF switch after the PA in the DL path, thereby reducing the IL of the DL and improving the efficiency of the overall system.

[0073] The circuit according to the invention further improves the reliability of the system: an RF switch is placed in the UL path, thus handling low power levels and improving the reliability of the system.

[0074] Furthermore, the circuit according to the invention makes it possible to reduce power consumption: in particular, the RF FET transistors are completely switched off in the Rx phase, keeping the quiescent current almost zero.

Claims

1. A circuit (C) for downlink / uplink operation mode switching in a TDD wireless communication system, comprising at least one RF field effect transistor (RF FET) operably connected to a power amplifier (PA) of a downlink path (DL) of an RF front-end device in the TDD wireless communication system; At least one large-capacity first resistor (R ｈｏｌｄ ) connected to a first voltage generator (Vgs ＯＦＦ )and, The second resistor (R Ｇａｔｅ ) connected to a second voltage generator (V Ｇａｔｅ )and, At least one large-capacity hold capacitor (C ｈｏｌｄ )and, The first voltage generator (Vgs ＯＦＦ ) is connected to the gate (G) of the field effect transistor (RF FET), and the hold capacitor (C ｈｏｌｄ ) is connected to the second end of the first resistor (R ｈｏｌｄ ) via the first voltage generator (Vgs ＯＦＦ ) and the gate (G) of the field effect transistor (RF FET) is connected to the hold capacitor (C ｈｏｌｄ ) and the hold capacitor (C ｈｏｌｄ The second end of the second resistor (R Ｇａｔｅ ) via the second voltage generator (V Ｇａｔｅ a transmit (Tx) configuration, connected to a sample and hold circuit; A circuit (C).

2. The sample and hold circuit comprises a first electronic switch (SW1) connected to the gate (G) of the field effect transistor (RF FET), the gate (G) being connected to the first voltage generator (Vgs) in the receive (Rx) configuration. ＯＦＦ ) in the transmit (Tx) configuration, and the hold capacitor (C ｈｏｌｄ 2. The circuit (C) according to claim 1, characterized in that it is configured to be connected to the second end of a first terminal of a second terminal of a second terminal of a first ... second terminal of a first terminal

3. The sample and hold circuit includes the hold capacitor (C ｈｏｌｄ a second electronic switch (SW2) connected to a second end of the first resistor (R ｈｏｌｄ ) via the first voltage generator (Vgs ＯＦＦ ) and in the transmit (Tx) configuration, the second resistor (R Ｇａｔｅ ) via the second voltage generator (V Ｇａｔｅ 3. A circuit (C) according to claim 1 or 2, characterized in that it is adapted to be connected to a

4. The first voltage generator (Vgs ＯＦＦ ) is the gate-source threshold voltage (Vgs) of the field effect transistor (RF FET). ｔｈ 4. A circuit (C) according to claim 1, characterized in that the input current Ip is maintained at a constant value lower than Ip.

5. The hold capacitor (C ｈｏｌｄ ) and the first resistor (R ｈｏｌｄ ) is the voltage value of the capacitor over time (V ｃｈｏｌｄ ) fluctuation (V ｒｉｐｐｌｅ 5. A circuit (C) according to claim 1, characterized in that the value is determined by minimizing:

6. The hold capacitor (C ｈｏｌｄ ) and the first resistor (R ｈｏｌｄ ) is the hold capacitor (C ｈｏｌｄ ) voltage value (V ｃｈｏｌｄ ) is the stable value of the gate-source voltage (V ｇｓ＿ＳＳ 6. A circuit (C) according to claim 1, characterized in that the value is determined by keeping it as close as possible to the reference value (C).

7. The hold capacitor (C ｈｏｌｄ ) and the first resistor (R ｈｏｌｄ ) is the hold capacitor (C ｈｏｌｄ ) discharge phase, [0010] Where: V ｒｉｐｐｌｅ is the hold capacitor (C ｈｏｌｄ ) voltage value (V ｃｈｏｌｄ ) is the variation of V ｃｈｏｌｄ is the hold capacitor (C ｈｏｌｄ ) voltage value, Vgs ＯＦＦ is the voltage value of the first voltage generator, t ＵＬ is the maximum duration of the UL period in the 3GPP standard for TDD applications, R ｈｏｌｄ is the value of the first resistor, C ｈｏｌｄ is the value of the hold capacitor, A circuit (C) according to any one of claims 1 to 6, characterised in that the hold capacitor (C hold ) and the first resistor (R hold ) are sized so as to minimise the above equation.

8. The hold capacitor (C ｈｏｌｄ ) and the second resistor (R Gate ) are connected to the hold capacitor (C ｈｏｌｄ ) charging phase, [0025] Where: V ｒｉｐｐｌｅ is the hold capacitor (C ｈｏｌｄ ) voltage value (V ｃｈｏｌｄ ) is the variation of V ｇｓ＿ＳＳ V is defined as the upper limit of the voltage that the system will reach when operating indefinitely in a transmit (Tx) configuration. ｇｓ is a stable value of V ｃｈｏｌｄ is the hold capacitor (C ｈｏｌｄ ) voltage value, t ＤＬ is the minimum duration of a downlink period in the 3GPP standard for TDD applications, Rgate is the value of the second resistor (Rgate); C ｈｏｌｄ is the value of the hold capacitor, A circuit (C) according to any one of claims 1 to 7, characterised in that the hold capacitor (C hold ) and the second resistor (R Gate ) are valued so as to minimise the above equation.

9. A TDD wireless communication system (S) comprising at least one downlink path (DL PATH) provided with at least one power amplifier (PA), at least one uplink path (UL PATH) provided with at least one low noise amplifier (LNA), and at least one antenna (ANT) connected to said downlink path (DL PATH) and said uplink path (UL PATH), A circuit (C) for downlink / uplink operation mode switching according to any one of claims 1 to 8, operatively interposed between said power amplifier (PA) and said antenna (ANT); At least one RF switch (RF SWITCH) configured to be switched between a receive (Rx) configuration connected to the low noise amplifier (LNA) and a transmit (Tx) configuration disconnected from the low noise amplifier (LNA), the RF switch (RF SWITCH) being disposed in the uplink path (UL PATH) and connected to the circuit (C); A TDD wireless communication system (S), comprising:

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