Photoelectric conversion device and method for controlling photoelectric conversion device

Abstract

To provide a photoelectric conversion device capable of correcting a positional deviation at the time of scanning.SOLUTION: In a first mode, a control unit performs control such that a signal output from each of a plurality of pixels is held in a holding unit in a column corresponding thereto. In a second mode, the control unit performs control of outputting a signal from the holding unit corresponding to a pixel in a first column and control of holding a signal based on a pixel in the first column in the holding unit corresponding to a pixel in a second column in parallel in the same period.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and a method for controlling a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses an image reading device equipped with three line sensors. The image reading device of Patent Document 1 has color filters arranged on the optical path from the original to the three line sensors, and can read color information of red (R), green (G), and blue (B).

[0003] In this device configuration, an image is read by mechanically moving the document and the line sensor relative to each other in the sub-scanning direction perpendicular to the main scanning direction in which the line sensor extends. At this time, positional deviations may occur in the image signals of each color due to differences in the physical distances between the pixels of each color of R, G, and B. Patent Document 1 discloses that the positional deviations for each color are corrected by changing the light accumulation timing of the line sensor for each color according to a correction parameter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2012-60493 A Summary of the Invention [Problem to be solved by the invention]

[0005] Due to restrictions on the device configuration, etc., there may be cases where a method for correcting positional deviation during scanning using a method different from that described in Patent Document 1 is required.

[0006] An object of the present invention is to provide a photoelectric conversion device capable of correcting positional deviation during scanning and a method for controlling the photoelectric conversion device. [Means for solving the problem]

[0007] According to one aspect of the present invention, there is provided a photoelectric conversion device comprising: a pixel array including a plurality of pixels arranged in a plurality of columns in a first direction, each of which outputs a signal in response to incident light; a holding unit arranged corresponding to each of the plurality of pixels; and a control unit that performs control to read out signals from the plurality of pixels and hold them in the holding unit, and control to output a signal from the holding unit, at a timing synchronized with a relative position between the plurality of pixels and an image capture object in a second direction perpendicular to the first direction, wherein the control unit is capable of control in either a first mode or a second mode, and in the first mode, the control unit controls so that the signal output from each of the plurality of pixels is held in the corresponding holding unit, and in the second mode, the control unit performs control in parallel to output a signal from the holding unit corresponding to the pixels in the first column and control so that a signal based on the pixels in the first column is held in the holding unit corresponding to the pixels in the second column during the same period.

[0008] According to another aspect of the present invention, there is provided a control method for a photoelectric conversion device having a pixel array including a plurality of pixels arranged in a first direction, each of which outputs a signal in response to incident light, and a holding unit arranged corresponding to each of the plurality of pixels, the control method including the steps of reading out signals from the plurality of pixels and holding them in the holding unit at a timing synchronized with a relative position between the plurality of pixels and an object to be imaged in a second direction perpendicular to the first direction, and outputting a signal from the holding unit, wherein the photoelectric conversion device can be controlled in either a first mode or a second mode, and in the first mode, the signal output from each of the plurality of pixels is held in the holding unit of the corresponding column, and in the second mode, the step of outputting a signal from the holding unit corresponding to the pixels in the first column and the step of holding a signal based on the pixels in the first column in the holding unit corresponding to the pixels in the second column are performed in parallel during the same period. Effect of the Invention

[0009] According to the present invention, a photoelectric conversion device capable of correcting positional deviation during scanning and a method for controlling a photoelectric conversion device are provided. [Brief description of the drawings]

[0010] [Figure 1] 1 is a schematic diagram showing a schematic configuration of an image reading device according to a first embodiment. [Diagram 2] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Diagram 3] 2 is a circuit diagram showing configurations of a pixel array, a column circuit unit, and a memory unit according to the first embodiment. [Figure 4] 4 is a timing chart showing drive timings in a first mode of the photoelectric conversion device according to the first embodiment. FIG. [Diagram 5] 3A and 3B are schematic diagrams illustrating an outline of a driving method in a first mode of the photoelectric conversion device according to the first embodiment. [Figure 6] 5A and 5B are schematic diagrams illustrating an outline of a driving method in a second mode of the photoelectric conversion device according to the first embodiment. [Figure 7] 5 is a timing chart showing drive timings in a second mode of the photoelectric conversion device according to the first embodiment. FIG. [Figure 8] FIG. 11 is a circuit diagram showing configurations of a pixel array, a column circuit unit, and a memory unit according to a second embodiment. [Figure 9] FIG. 11 is a timing chart showing drive timings in a second mode of the photoelectric conversion device according to the second embodiment. [Figure 10] FIG. 13 is a circuit diagram showing configurations of a pixel array, a column circuit unit, and a memory unit according to a third embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The same elements or corresponding elements in multiple drawings are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

[0012] [First embodiment] 1 is a schematic diagram showing a schematic configuration of an image reading device 2 according to this embodiment. The image reading device 2 has a document tray 210, an automatic document feeder 230, a document table 240, and a main body 250. The document tray 210 and the document table 240 are portions on which a user places a document 220, which is an object to be imaged. The automatic document feeder 230 feeds the document 220 placed on the document tray 210.

[0013] The main body 250 has a mirror unit 260, a lens 270, and a photoelectric conversion device 1. The mirror unit 260 has a lamp 261 and mirrors 262, 263, and 264. The lamp 261 is a light source that irradiates light onto the surface (reading surface) of the fed original 220. The mirrors 262, 263, and 264 guide the reflected light from the original 220 to the lens 270. The lens 270 focuses the light on the photoelectric conversion device 1. That is, the mirrors 262, 263, and 264 and the lens 270 are an optical system that guides the reflected light from the original to the photoelectric conversion device 1. The mirror unit 260 is configured to be able to change its position relative to the original 220. The photoelectric conversion device 1 performs imaging based on the incident light at a timing synchronized with this relative position, thereby scanning the reading surface of the original 220.

[0014] The photoelectric conversion device 1 is a line sensor having pixel rows that receive red (R), green (G), and blue (B) light. Each pixel of the photoelectric conversion device 1 converts incident light into an electrical signal for each color, thereby acquiring a color image of the original 220.

[0015] The image reading device 2 can read an image of the original 220 in two modes: an original fixed mode and an original feeding mode. The original fixed mode is a mode in which the image reading device 2 reads the original 220 placed on the original table 240. In the original fixed mode, scanning for reading is performed by moving the mirror unit 260 relative to the fixed original 220. The original feeding mode is a mode in which the image reading device 2 reads the original 220 fed by the automatic original feeder 230. In the original feeding mode, scanning for reading is performed by the automatic original feeder 230 moving the original 220 relative to the stopped mirror unit 260. In either mode, scanning for reading is performed by changing the relative positions of the mirror unit 260 and the original 220.

[0016] Next, the configuration of the photoelectric conversion device 1 will be described in more detail. Fig. 2 is a block diagram showing a schematic configuration of the photoelectric conversion device 1 according to this embodiment. The photoelectric conversion device 1 has a pixel array 10, a column circuit section 20, a memory section 30, a horizontal scanning circuit 40, a common output line 50, an output section 60, and a control section 70.

[0017] The pixel array 10 has a plurality of pixels 11 arranged to form a plurality of columns in a main scanning direction X (first direction) and a plurality of rows in a sub-scanning direction Y (second direction) perpendicular to the main scanning direction X. Each of the plurality of pixels 11 includes a photoelectric conversion unit constituted by a photodiode or the like, and outputs a signal according to incident light. In FIG. 2, the pixel array 10 has three rows and m columns (m is an integer of 2 or more). As shown in FIG. 2, in the first row, pixels 11 (R1 to R(m)) having a red (R) color filter are arranged along the main scanning direction X. In the second row, pixels 11 (G1 to G(m)) having a green (G) color filter are arranged along the main scanning direction X. In the third row, pixels 11 (B1 to B(m)) having a blue (B) color filter are arranged along the main scanning direction X. Note that the number of rows and columns and the arrangement order of each color in the pixel array 10 are not limited to those shown in FIG. 2.

[0018] The interval between the pixels 11 in the main scanning direction X (for example, the interval between the pixels 11 labeled R1 and R2) is, for example, 42 μm. Similarly, the interval between the pixels 11 in the sub-scanning direction Y (for example, the interval between the pixels 11 labeled R1 and G1) is, for example, 42 μm. That is, the physical resolution in the main scanning direction X and the sub-scanning direction Y may be the same. In this case, the original 220 can be read to generate a color image with a resolution of 600 dpi. Note that the pixel interval and resolution described above are merely examples and are not limited to these.

[0019] The column circuit section 20 has column circuits 21 arranged corresponding to each of the multiple pixels 11. The column circuits 21 read out signals from the pixels 11 and output them to the memory section 30. The column circuits 21 perform processes such as removing kTC noise generated when the pixels 11 are driven and amplifying the signals. The memory section 30 has holding sections 31 arranged corresponding to each of the multiple column circuits 21. The holding sections 31 hold signals output from the column circuits 21. In FIG. 2, two holding sections 31 are shown corresponding to one pixel 11, which indicate a pixel signal holding section 31 that holds a pixel signal based on incident light and a reset signal holding section 31 that holds a reset signal based on the reset state of the pixel 11.

[0020] The horizontal scanning circuit 40 controls the memory unit 30 to sequentially output the held signals to the common output line 50. The horizontal scanning circuit 40 may be configured by a shift register or an address decoder. The common output line 50 includes six signal lines each connected to a plurality of holding units 31. The six signal lines transmit an R pixel signal and a reset signal, a G pixel signal and a reset signal, and a B pixel signal and a reset signal, respectively. The output unit 60 has three differential amplifiers 61 corresponding to the three colors of R, G, and B. The differential amplifiers 61 receive the pixel signal and the reset signal of the corresponding color and output a signal based on the difference therebetween to the outside. The control unit 70 controls the operation timing of the pixel array 10, the column circuit unit 20, the memory unit 30, and the horizontal scanning circuit 40.

[0021] FIG. 3 is a circuit diagram showing the configuration of the pixel array 10, the column circuit section 20, and the memory section 30 according to the present embodiment. In FIG. 3, the configuration of the circuits for two columns corresponding to the R pixels 11 (i.e., R(n) and R(n+1) in FIG. 2) arranged in the nth column and the n+1th column is extracted and shown from the circuits included in these blocks (n is an integer of 1 or more and m-1 or less). Although omitted in FIG. 3, the circuits of the pixel array 10, the column circuit section 20, and the memory section 30 corresponding to other columns or other colors have the same configuration. In the following description of FIG. 3, the configuration of the nth column will be described unless otherwise specified, and the description of the n+1th column will be omitted if it is common to the nth column. In the various control signals shown in FIG. 3, column numbers such as en(n) may be added to those in which different potentials can be individually applied to multiple columns.

[0022] The pixel array 10 includes a photoelectric conversion unit PD, a reset transistor M1, an amplifying transistor M2, and a current source 12. These transistors may be configured as N-type MOS transistors having a gate electrode as a control electrode. A control signal PRES is input from the control unit 70 to the gate of the reset transistor M1.

[0023] The photoelectric conversion unit PD is a photoelectric conversion element that generates charges according to incident light by photoelectric conversion and accumulates the charges. The photoelectric conversion unit PD may be composed of a photodiode formed in a semiconductor substrate. The cathode of the photodiode constituting the photoelectric conversion unit PD is connected to a potential line having a power supply potential VDD, and the anode is connected to the drain of the reset transistor M1 and the gate of the amplification transistor M2. This connection node is a floating diffusion FD.

[0024] The charge generated in the photoelectric conversion unit PD is accumulated in the floating diffusion FD. The floating diffusion FD has a capacitance, and due to this capacitance, the potential of the floating diffusion FD changes according to the charge generated in the photoelectric conversion unit PD.

[0025] The source of the reset transistor M1 is connected to a potential line having a reset potential VRES. The drain of the amplification transistor M2 is connected to a potential line having a power supply potential VDD. The source of the amplification transistor M2 is connected to a current source 12. The amplification transistor M2 and the current source 12 form a source follower circuit. This source follower circuit outputs a signal based on the voltage of the floating diffusion FD to the column circuit section 20. The reset transistor M1 resets the potential of the floating diffusion FD by being turned on (connected state).

[0026] The column circuit section 20 has an amplifier 22, a clamp capacitance C0, a feedback capacitance Cf1, and switches SW1, SW2, and SW3. The control signals PCM, PC0R, and PADD are input from the control section 70 to the control terminals of the switches SW1, SW2, and SW3, respectively. The switches SW1, SW2, and SW3 are controlled to be on (connected state) or off (disconnected state) in response to these control signals. A control signal en(n) is input from the control section 70 to the control terminal of the amplifier 22 in the nth column, and a control signal en(n+1) is input from the control section 70 to the control terminal of the amplifier 22 in the n+1th column. The amplifier 22 is controlled to be in an operating state when the control signals en(n) and en(n+1) are at a high level. The amplifier 22 is controlled so that the output has a high impedance when the control signals en(n) and en(n+1) are at a low level. That is, the control signals en(n) and en(n+1) are enable signals that control the amplifier 22 to be in either an operating state or a non-operating state. The amplifier 22, the clamp capacitor C0, and the feedback capacitor Cf1 form an amplifier circuit having an analog gain based on the capacitance value of the clamp capacitor C0 and the capacitance value of the feedback capacitor Cf1.

[0027] A first terminal of the switch SW1 in the nth column is connected to the output terminal of the nth column of the pixel array 10, i.e., the connection node between the source of the amplification transistor M2 in the nth column and the current source 12. A second terminal of the switch SW1 is connected to a first terminal of the clamp capacitance C0. The second terminal of the clamp capacitance C0 is connected to the input terminal of the amplifier 22, a first terminal of the switch SW2, and a first terminal of the feedback capacitance Cf1. The second terminal of the switch SW2, the second terminal of the feedback capacitance Cf1, and the output terminal of the amplifier 22 are connected to each other, and this connection node is an output terminal from the column circuit section 20 to the memory section 30.

[0028] A first terminal of the switch SW3 (first switch) is connected to a connection node of the second terminal of the clamp capacitance C0 of the nth column, the input terminal of the amplifier 22, the first terminal of the switch SW2, and the first terminal of the feedback capacitance Cf1. A second terminal of the switch SW3 is connected to a connection node of the second terminal of the clamp capacitance C0 of the n+1th column, the input terminal of the amplifier 22, the first terminal of the switch SW2, and the first terminal of the feedback capacitance Cf1. In other words, the switch SW3 has a function of controlling connection or disconnection between the wiring in the column circuit 21 corresponding to the pixel 11 of the nth column and the wiring in the column circuit 21 corresponding to the pixel 11 of the n+1th column.

[0029] The memory unit 30 has storage capacitors CTS(n), CTN(n), CTS(n+1), CTN(n+1) and switches SW4, SW5, SW6, SW7. These elements form a sample-and-hold circuit. The control terminals of the switches SW4 and SW5 in the nth column receive control signals PTS(n) and PTN(n) from the control unit 70. The control terminals of the switches SW6 and SW7 in the nth column receive control signals HSR(n) and HSR(n) from the horizontal scanning circuit 40. The control terminals of the switches SW4 and SW5 in the n+1th column receive control signals PTS(n+1) and PTN(n+1) from the control unit 70. The control terminals of the switches SW6 and SW7 in the n+1th column receive control signals HSR(n+1) and HSR(n+1) from the horizontal scanning circuit 40. The switches SW4, SW5, SW6, and SW7 are controlled to be on (connected state) or off (disconnected state) in response to these control signals. The storage capacitors CTS(n) and CTS(n+1) store pixel signals, and the storage capacitors CTN(n) and CTN(n+1) store reset signals.

[0030] The output terminal of the nth column of the column circuit section 20, i.e., the connection node of the second terminal of the switch SW2 of the nth column, the second terminal of the feedback capacitance Cf1, and the output terminal of the amplifier 22, is connected to the first terminal of the switch SW4 of the nth column and the first terminal of the switch SW5. The second terminal of the switch SW4 is connected to the first terminal of the storage capacitance CTS(n) and the first terminal of the switch SW6. The second terminal of the storage capacitance CTS(n) is connected to a potential line having a ground potential. The second terminal of the switch SW6 is an output terminal from the memory section 30 to the common output line 50.

[0031] The second terminal of the switch SW5 is connected to the first terminal of the storage capacitor CTN(n) and the first terminal of the switch SW7. The second terminal of the storage capacitor CTN(n) is connected to a potential line having a ground potential. The second terminal of the switch SW7 is an output terminal from the memory unit 30 to the common output line 50.

[0032] In the above description, the control signals HSR(n) and HSR(n+1) are supplied from the horizontal scanning circuit 40, and the other control signals are supplied from the control unit 70, but this is not limited to the above. For example, control signals other than the control signals HSR(n) and HSR(n+1) may be supplied from unillustrated control circuits such as a vertical scanning circuit and a signal generating circuit that operate based on a timing signal supplied from the control unit 70.

[0033] The photoelectric conversion device 1 of this embodiment is capable of outputting signals in either a first mode or a second mode. The first mode is a mode for outputting signals corresponding to the pixels 11 of each column of the pixel array 10. The second mode is a mode for outputting signals by summing readout in which signals based on a plurality of pixels 11 are summed and outputting a summed signal, or by thinning readout in which signals are output from a portion of the plurality of pixels 11. In the second mode, the number of signals output is reduced compared to the first mode. Therefore, for example, the first mode may be a high-resolution mode in which a high-resolution image is output, and the second mode may be a low-resolution mode in which a low-resolution image is output. In the following description, unless otherwise specified, it is assumed that summing readout is performed in the second mode.

[0034] First, the driving timing of the first mode will be described. FIG. 4 is a timing diagram showing the driving timing of the photoelectric conversion device 1 according to this embodiment in the first mode. FIG. 4 shows the levels of the control signals PRES, PCM, PC0R, PTN, PTS, en, PADD, and HSR, and the potential of the floating diffusion FD. For the control signals PTN, PTS, and en, the nth column and the n+1th column are illustrated separately, and for the control signal HSR, the 1st column, the nth column, and the n+1th column are illustrated separately. For control signals without a column number, the same level of control signal is input to the transistors or switches of the nth column and the n+1th column.

[0035] The control signals en(n) and en(n+1) are at high level throughout the entire period, and the amplifiers 22 in the nth and n+1th columns are in an operating state. The control signal PADD is at low level throughout the entire period, and the switch SW3 is off.

[0036] At time t11, the control signal PRES goes to high level, and at time t12, the control signal PRES goes to low level. This operation temporarily turns on the reset transistor M1. This resets the potential of the floating diffusion FD to a potential based on the reset potential VRES. After time t12, the potential of the floating diffusion FD increases over time due to the charges generated in the photoelectric conversion unit PD by the incident light.

[0037] Furthermore, at time t11, the control signal PC0R goes to high level, and at time t12, the control signal PC0R goes to low level. This operation temporarily turns on the switch SW2. This resets the charge held in the clamp capacitance C0. Note that in FIG. 4, the control signals PRES and PC0R go to high level at the same time, and the floating diffusion FD and the clamp capacitance C0 are reset simultaneously, but this is not essential. It is sufficient that the clamp capacitance C0 is reset by the time the signal is held in the memory unit 30.

[0038] At time t13, the control signal PCM goes to high level, and at time t14, the control signal PCM goes to low level. This operation temporarily turns on the switch SW1. As a result, a potential based on the reset state of the pixel 11 is applied to the clamp capacitor C0 and held there.

[0039] At time t15, the control signals PTN(n) and PTN(n+1) go to high level, and at time t16, the control signals PTN(n) and PTN(n+1) go to low level. This operation temporarily turns on the switches SW5 in the nth and n+1th columns. This causes the reset signals to be held in the holding capacitors CTN(n) and CTN(n+1).

[0040] At time t17, the control signals PTS(n) and PTS(n+1) go to high level, turning on the switch SW4. At time t18, the control signal PCM goes to high level, turning on the switch SW1. At time t19, the control signal PCM goes to low level, turning off the switch SW1. At time t20, the control signals PTS(n) and PTS(n+1) go to low level, turning off the switch SW4. Through this series of operations, the pixel signals based on the potential of the floating diffusion FD at time t19 are held in the storage capacitances CTS(n) and CTS(n+1).

[0041] At time t21, the control signal HSR(1) goes to high level, and the switches SW6 and SW7 of the first column are turned on. As a result, the signal held in the holding unit 31 of the first column is output to the common output line 50. Thereafter, the control signal HSR(1) goes to low level, and the switches SW6 and SW7 of the first column are turned off. Similarly, the control signals HSR(2), HSR(3), ... corresponding to the second column, the third column, ... not shown in Figures 3 and 4 go to high level in a certain cycle in sequence, and horizontal scanning is performed in which the signals held in the holding unit 31 of each column are output to the common output line 50 in sequence. In other words, time t21 is the start time of horizontal scanning.

[0042] After that, at time t22, the control signal HSR(n) goes high, and the switches SW6 and SW7 in the nth column are turned on. As a result, the signal held in the holding unit 31 in the nth column is output to the common output line 50. Similarly, at time t23, the control signal HSR(n+1) goes high, and the switches SW6 and SW7 in the n+1th column are turned on. As a result, the signal held in the holding unit 31 in the n+1th column is output to the common output line 50. During this horizontal scanning period, charge accumulation processing for the next readout is performed in parallel with the horizontal scanning by processing similar to that from time t11 to time t20 described above.

[0043] As described above, in the first mode, the control signal PADD is at a low level throughout the entire period, and the switch SW3 is off. Therefore, the signal generated in the pixel 11 in the nth column is held in the holding unit 31 in the corresponding nth column, and the signal generated in the pixel 11 in the n+1th column is held in the holding unit 31 in the corresponding n+1th column. In this way, in the first mode, the signal output from each pixel 11 is held in the holding unit 31 in the corresponding column, and therefore, additive reading or thinning-out reading of signals is not performed.

[0044] Fig. 5 is a schematic diagram showing an outline of a driving method in a first mode of the photoelectric conversion device 1 according to this embodiment. Fig. 5 shows an outline of the operation of each pixel 11 corresponding to the three colors R, G, and B and the corresponding holding unit 31.

[0045] The timing diagram shown in the lower part of Fig. 5 focuses on the control signals PRES and PCM among the multiple control signals shown in Fig. 4. Here, the subscripts R, G, and B attached to the control signals in Fig. 5 indicate that they are control signals input to the pixels 11 of three colors R, G, and B, respectively.

[0046] The blocks shown in the upper part of Fig. 5 show an outline of the processing performed at each time in the timing diagram in the lower part and the period of that processing. That is, the "Pixel ⇒ Holder" block shows the period during which pixel signals and reset signals are output from the pixels 11 and held in the holder 31. The "Read out sequentially from holder" block shows the horizontal scanning period during which the pixel signals and reset signals held in the holder 31 are output sequentially to the common output line 50. In addition, the R, G, and B subscripts attached to the blocks show which of the three R, G, and B pixels 11 the processing corresponds to.

[0047] At time t1, the control signals PRES_R, PRES_G, and PRES_B go to a low level, turning off the reset transistor M1, thereby releasing the reset of the pixel 11 and starting to accumulate charges. That is, time t1 in FIG. 5 corresponds to time t12 in FIG. 4. At time t2, the control signals PCM_R, PCM_G, and PCM_B go to a low level, turning off the switch SW1, thereby ending the signal output from the pixel 11. That is, time t2 in FIG. 5 corresponds to time t19 in FIG. 4. The period T1 from time t1 to time t2 is an accumulation period during which charges generated in the photoelectric conversion unit PD in response to incident light are accumulated. As shown in FIG. 5, the period T1 is common to the pixels 11 of the three colors R, G, and B, so that charges are accumulated in parallel during the same accumulation period.

[0048] 5, the period T2 in which the R, G, and B "pixel ⇒ retention unit" blocks are shown corresponds to the period from time t15 to time t21 in FIG. 4. As shown in FIG. 5, the period T2 is common to all three colors of R, G, and B. Therefore, pixel signals and reset signals are output in parallel from the pixels 11 of the three colors of R, G, and B during the same period and are retained in the retention unit 31.

[0049] 5, period T3 in which the blocks of "sequentially read from holding unit" for R, G, and B are shown corresponds to the period after time t21 in FIG. 4. In other words, time t3, which is the start time of period T3, corresponds to time t21 in FIG. 4. As shown in FIG. 5, period T3 is common to all three colors of R, G, and B. Therefore, pixel signals and reset signals are output in parallel from the holding units 31 corresponding to the pixels 11 of the three colors of R, G, and B to the common output line 50 in sequence during the same period.

[0050] The R, G, and B pixels 11 are arranged at intervals in the sub-scanning direction Y as shown in FIG. 2. Therefore, a position shift corresponding to the interval between the pixels 11 occurs for each color in the signals of each color output at the same time. Therefore, in order to correct this position shift, a correction process may be performed by a signal processing circuit or the like that may be provided in the photoelectric conversion device 1 or the image reading device 2 to generate an image by shifting the phase for each color by the number of frames corresponding to the interval between the pixels 11. For example, if the interval between the pixels 11 in the sub-scanning direction Y is d, the R signal is delayed by a time equivalent to the interval 2d, and the G signal is delayed by a time equivalent to the interval d, thereby correcting the position shift for each color.

[0051] Next, the driving timing of the second mode will be described. In this embodiment, it is assumed that the second mode performs additive reading of two columns. As a result, the resolution of the second mode is half that of the first mode. For example, when the interval between the pixels 11 is 42 μm, the resolution in the main scanning direction X in the first mode is 600 dpi, and the resolution in the main scanning direction X in the second mode is 300 dpi. On the other hand, in the sub-scanning direction Y, the resolution determined by the physical interval between the pixels 11 remains equivalent to 600 dpi, so that the positional deviation correction may be insufficient by simply delaying the signals of each color in time as described above. In the driving method of the second mode of this embodiment, the accumulation period is shifted for each color, so that the positional deviation correction can be realized in additive reading.

[0052] Fig. 6 is a schematic diagram showing an outline of a driving method in the second mode of the photoelectric conversion device 1 according to this embodiment. The notation of the blocks and timing diagram shown in Fig. 6 is the same as that in Fig. 5, so a description thereof will be omitted. As shown in Fig. 6, the difference between Fig. 6 and Fig. 5 is that the signal holding period shown by the "pixel → holding unit" block of the R and B pixels 11 is different from the signal holding period shown by the "pixel → holding unit" block of the G pixel 11.

[0053] At time t4, the control signals PRES_R and PRES_B go to low level, turning off the reset transistors M1 of the R and B pixels 11. This releases the reset of the R and B pixels 11, and the accumulation of charges in the R and B pixels 11 begins. At time t5, the control signals PCM_R and PCM_B go to low level, turning off the switches SW1 corresponding to the R and B pixels 11. This ends the signal output from the R and B pixels 11. The period T4 from time t4 to time t5 is the accumulation period corresponding to the R and B pixels 11.

[0054] Also, at time t5, the control signal PRES_G goes to low level, turning off the reset transistor M1 of the G pixel 11. This releases the reset of the G pixel 11, and the accumulation of charge in the G pixel 11 begins. At time t6, the control signal PCM_G goes to low level, turning off the switch SW1 corresponding to the G pixel 11. This ends the signal output from the G pixel 11. The period T5 from time t5 to time t6 is the accumulation period corresponding to the G pixel 11.

[0055] 6, the accumulation periods are different for the R and B pixels 11 and the G pixels 11. In other words, in the second mode, period T1, which is the accumulation period in the first mode, is divided into two periods: period T4, which is the first half during which accumulation is performed for the R and B pixels 11, and period T5, which is the second half during which accumulation is performed for the G pixels 11. As a result, period T6, which shows the R and B "pixel → retention unit" block, and period T7, which shows the G "pixel → retention unit" block, are also divided into different periods.

[0056] 5, after time t7, pixel signals and reset signals are output in parallel from the pixels 11 of the three colors R, G, and B during the same period, and are held in the holding unit 31. The period T8 in which the blocks of "reading out sequentially from the holding unit" of R, G, and B are shown is common to the three colors R, G, and B, as in FIG.

[0057] During period T8, accumulation for the R and B pixels 11 for the next readout is started in the same manner as in periods T4 and T5. During period T9, which shows the R and B "pixel ⇒ storage unit" blocks, signals are stored in the storage units 31 corresponding to the R and B pixels 11. That is, periods T8 and T9 overlap, and the storage of signals in the storage units 31 and the output of signals from the storage units 31 are performed in parallel during the same period. A specific method for performing this operation will be described later with reference to FIG. 7.

[0058] 6, the length of the period T4 is the same as the length of the period T5. This allows the lengths of the accumulation periods of the pixels 11 of each color to be the same. However, depending on other driving conditions, the length of the period T4 does not have to be the same as the length of the period T5.

[0059] During the period from time t4 to time t5, the control signal PRES_G is maintained at a high level, but this is not essential. It is sufficient that the G pixels 11 are reset before the start of accumulation in period T5.

[0060] Fig. 7 is a timing chart showing the drive timing in the second mode of the photoelectric conversion device 1 according to this embodiment. Fig. 7 shows the operations of the R and B pixels 11 and the corresponding column circuits 21 and holding units 31. In the following explanation, the explanation of the parts common to Fig. 4 may be omitted or simplified.

[0061] The control signal PADD is at a high level throughout the entire period, and the switch SW3 is on. Therefore, the column circuits 21 of the nth and n+1th columns are shorted at the node between the clamp capacitor C0 and the amplifier 22. As a result, the amplifiers 22 of the nth and n+1th columns add up and output the signals from the pixels 11 of the nth and n+1th columns.

[0062] The control signal en(n) is at a high level during the period from time t31 to time t41, and at a low level during the other periods. The control signal en(n+1) is at a high level during the period after time t41, and at a low level during the other periods. Therefore, during the period from time t31 to time t41, the amplifier 22 of the nth column is in an operating state, and the amplifier 22 of the n+1th column is in a high impedance state. That is, during this period, the signal after the addition is held in the holding unit 31 corresponding to the pixel 11 of the nth column. During the period after time t41, the amplifier 22 of the nth column is in a high impedance state, and the amplifier 22 of the n+1th column is in an operating state. That is, during this period, the signal after the addition is held in the holding unit 31 corresponding to the pixel 11 of the n+1th column. In this way, in the second mode, the signal after the addition of the nth column and the n+1th column is selectively held in one of the holding units 31 of the nth column and the n+1th column.

[0063] The period from time t31 to time t39 corresponds to period T4 in Fig. 6. The operation during this period is generally similar to the operation from time t11 to time t20 in Fig. 4, so a description thereof will be omitted. The period from time t40 to time t50 corresponds to period T5 in Fig. 6. This period is an accumulation period for the G pixels 11, and no particular operation related to the R and B pixels 11 shown in Fig. 6 is performed.

[0064] The period after time t50 corresponds to the period after time t7 in FIG. 6, that is, period T8. At time t50, the control signal HSR(1) goes high, and the switches SW6 and SW7 of the first column are turned on. As a result, the signal held in the holding unit 31 of the first column is output to the common output line 50. Horizontal scanning starts at this time. At time t51, the control signal HSR(n) goes high, and the switches SW6 and SW7 of the nth column are turned on. As a result, the signal held in the holding unit 31 of the nth column is output to the common output line 50. The signal output at this time is the sum of the nth and n+1th column signals held in the holding units 31 corresponding to the pixels 11 of the nth column during the period from time t31 to time t39.

[0065] In parallel with the output of this sum signal, from time t41 to time t49, charge is accumulated in the pixels 11 and the signals are held in the holding units 31. At this time, since the amplifiers 22 in the (n+1)th column are in an operating state, the signals after the addition are held in the holding units 31 corresponding to the pixels 11 in the (n+1)th column. This sum signal is output to the common output line 50 at time t53 in horizontal scanning that starts at time t52.

[0066] In the second mode, since addition reading is performed, signals are not output from some columns. In Fig. 7, pulses at which HSR(1) becomes high level are shown at times t50 and t52, but in reality, HSR(1) may not become high level at one or both of times t50 and t52. In other words, HSR(1) in Fig. 7 is shown to indicate the start time of horizontal scanning, and the actual driving of the first column may not be as shown in Fig. 7.

[0067] As described above, during the period from time t50 to time t49 in the second mode of this embodiment, the holding of signals in the holding units 31 corresponding to the pixels 11 in the n+1th column and the output of signals from the holding units 31 corresponding to the pixels 11 in the nth column are performed in parallel. When performing additive reading of signals, signals are not output from some columns, so that there are holding units 31 that are not used for outputting signals. In this embodiment, by having the holding units 31 of such columns hold signals for the signal output in the next period, it is possible to hold signals in the holding units 31 and output signals from the holding units 31 in parallel during the same period. This allows the accumulation period to be shifted for each color, and positional deviation correction can be achieved even in the second mode in which additive reading and the like are performed.

[0068] In addition, in the above-mentioned method, since the sample-and-hold circuit for holding the horizontal scanning signal also functions as an intermediate memory for shifting the accumulation time, there is no need to provide an additional intermediate memory for shifting the accumulation period for each color. Therefore, in this embodiment, the influence of an increase in circuit size, etc., that may occur when applying a driving method for shifting the accumulation period for each color is mitigated.

[0069] As described above, according to the present embodiment, a photoelectric conversion device 1 capable of correcting misalignment during scanning is provided. Furthermore, by applying such a photoelectric conversion device 1, an image reading device 2 is provided in which image quality degradation caused by misalignment during scanning is reduced.

[0070] In addition, in Figure 7, the operation corresponding to the G pixel 11 is not shown, but this is the same as the operation corresponding to the R and B pixels 11, except that the timing of the accumulation period, etc. is different as shown in Figure 6.

[0071] 7 except that the control signal PADD is at a low level over the entire period and the switch SW3 is off. In this case, the holding unit 31 holds signals based on the pixels 11 of only the corresponding column, rather than the summed signals of the two columns. In this case, the same effect can be obtained.

[0072] As shown in FIG. 7, during the period from time t31 to time t40, the signal is held in the holding unit 31 of the nth column, and during the period from time t41 to time t49, which is the next readout period, the signal is held in the holding unit 31 of the n+1th column. At time t51, a signal is output from the holding unit 31 of the nth column, and at time t53, which is included in the next readout period, a signal is output from the holding unit 31 of the n+1th column. That is, a first operation in which the signal is output from the holding unit 31 of the first column and the signal is held in the holding unit 31 of the second column in parallel, and a second operation in which the signal is output from the holding unit 31 of the second column and the signal is held in the holding unit 31 of the first column in parallel are switched for each readout period. By adopting such a driving method, the processing of this embodiment can be continuously repeated.

[0073] [Second embodiment] The photoelectric conversion device 1 of this embodiment is a modified example in which a switch that controls connection or disconnection of wiring between columns is added to a node between the column circuit section 20 and the memory section 30 in the configuration of the first embodiment. In the description of this embodiment, the description of elements common to the first embodiment may be omitted or simplified.

[0074] Fig. 8 is a circuit diagram showing configurations of a pixel array 10, a column circuit section 20, and a memory section 30 according to the second embodiment. In the circuit of Fig. 8, a switch SW8 is further arranged in addition to the circuit of Fig. 3. A control signal PADD is input to the control terminal of the switch SW8, similar to the switch SW3.

[0075] A first terminal of the switch SW8 (second switch) is connected to a connection node of the second terminal of the switch SW2 in the nth column, the second terminal of the feedback capacitance Cf1, the output terminal of the amplifier 22, and the first terminals of the switches SW4 and SW5. A second terminal of the switch SW8 is connected to a connection node of the second terminal of the switch SW2 in the n+1th column, the second terminal of the feedback capacitance Cf1, the output terminal of the amplifier 22, and the first terminals of the switches SW4 and SW5. In other words, the switch SW8 has a function of controlling connection or non-connection between the wiring between the column circuit 21 corresponding to the pixel 11 in the nth column and the memory unit 30 and the wiring between the column circuit 21 corresponding to the pixel 11 in the n+1th column and the memory unit 30.

[0076] Next, the photoelectric conversion device 1 of this embodiment can output a signal in either the first mode or the second mode, similar to the first embodiment. The driving timing in the driving method in the first mode is the same as that shown in Figures 4 and 5. That is, the control signal PADD is at a low level and the switch SW8 is off throughout the entire period, similar to the first embodiment. Therefore, the driving method in the first mode is the same as the first embodiment, and therefore will not be described.

[0077] A driving method in the second mode will be described with reference to Fig. 9. Fig. 9 is a timing diagram showing the driving timing in the second mode of the photoelectric conversion device 1 according to this embodiment. The only difference from Fig. 7 is that the control signal en(n) is at a high level over the entire period, and the control signal en(n+1) is at a low level over the entire period. Therefore, the amplifier 22 in the nth column is in an operating state over the entire period, and the amplifier 22 in the n+1th column is in a high impedance state over the entire period.

[0078] In this embodiment, the amplifier 22 of the nth column operates both in a period when a signal is held in the holding unit 31 corresponding to the pixel 11 of the nth column and in a period when a signal is held in the holding unit 31 corresponding to the pixel 11 of the (n+1)th column. Therefore, the variation in signal level caused by differences in signal paths, such as differences in gain of the amplifier circuit, is reduced compared to the configuration of the first embodiment. As described above, according to this embodiment, in addition to obtaining the same effects as the first embodiment, the variation in signal level caused by differences in signal paths in the second mode is reduced.

[0079] In the circuit configuration of this embodiment, the drive timing of the control signals en(n) and en(n+1) may be the same as in the first embodiment. In this case, the same effect as in the first embodiment can be obtained.

[0080] [Third embodiment] The photoelectric conversion device 1 of this embodiment is a modified example in which the column circuit section 20 in the configuration of the second embodiment is modified to function as an amplifier circuit having a variable analog gain. In the description of this embodiment, the description of elements common to the second embodiment may be omitted or simplified.

[0081] Fig. 10 is a circuit diagram showing configurations of a pixel array 10, a column circuit unit 20, and a memory unit 30 according to the third embodiment. In the circuit of Fig. 10, the feedback capacitance Cf1 in the circuit of Fig. 8 is modified into a gain variable unit 23. The gain variable unit 23 has a function of varying the gain of an amplifier circuit formed by the amplifier 22, the clamp capacitance C0, and a capacitance within the gain variable unit 23.

[0082] The gain variable section 23 has feedback capacitances Cf1, Cf2, Cf3, and Cf4 and switches SW12, SW13, and SW14. The connection relationship of the feedback capacitance Cf1 is the same as that in FIG. 8. The first terminals of the switches SW12, SW13, and SW14 are connected to the first terminal of the feedback capacitance Cf1. The second terminals of the switches SW12, SW13, and SW14 are connected to the feedback capacitances Cf2, Cf3, and Cf4, respectively. The second terminals of the feedback capacitances Cf2, Cf3, and Cf4 are connected to the second terminal of the feedback capacitance Cf1. A control signal for controlling the switches SW12, SW13, and SW14 is input from the control section 70. In FIG. 10, the gain variable section 23 includes three pairs of switches and feedback capacitances, but the number of pairs of switches and feedback capacitances that can be included in the gain variable section 23 is not limited to those shown in FIG. 10.

[0083] Controlling each of the switches SW12, SW13, and SW14 changes the number of parallel-connected feedback capacitances Cf1, Cf2, Cf3, and Cf4 included in the variable gain section 23. This changes the combined capacitance in the variable gain section 23, and the gain of the amplifier circuit composed of the amplifier 22, the clamp capacitance C0, and the capacitances in the variable gain section 23 changes.

[0084] As an example, the capacitance values ​​of the feedback capacitances Cf1, Cf2, Cf3, and Cf4 are the same, and the gain is G1 when the switches SW12, SW13, and SW14 are all off, and the gain is G2 when the switches SW12, SW13, and SW14 are all on. In this case, G1 / G2 is 4, and the gain can be changed by a factor of four by controlling the switches SW12, SW13, and SW14.

[0085] As a result, in this embodiment, in addition to obtaining the same effects as those of the first or second embodiment, the analog gain of the signal can be changed.

[0086] In the second mode driving method as shown in FIG. 9, the accumulation time is half that in the first mode, and the signal level is reduced to half. In this way, when the second mode driving method is applied, the signal level may be reduced. In such a case, in this embodiment, the signal level can be increased by controlling the gain variable unit 23 to increase the gain. Therefore, it is desirable to control the gain variable unit 23 so that the analog gain is higher in the second mode than in the first mode, and the effect of the reduction in accumulation time caused by applying the second mode driving method can be reduced.

[0087] In this embodiment, an example is shown in which the feedback capacitance Cf1 in the circuit of FIG. 8 is replaced with the variable gain unit 23, but the feedback capacitance Cf1 in the circuit of FIG. 3 may be replaced with the variable gain unit 23, and the same effect can be obtained.

[0088] [Modified embodiment] The present invention is not limited to the above-described embodiments, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention.

[0089] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) for implementing one or more of the functions.

[0090] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0091] 1 Photoelectric conversion device 2. Image reader 10 Pixel Array 11 pixels 20 column circuit section 21 column circuit 30 Memory section 31 Holding part 70 Control section

Claims

1. a pixel array including a plurality of pixels arranged in a plurality of rows in a first direction, each of the pixels outputting a signal in response to incident light; a holding unit arranged corresponding to each of the plurality of pixels; a control unit that performs control to read out signals from the plurality of pixels and hold them in the holding unit, and control to output the signals from the holding unit, at a timing synchronized with a relative position between the plurality of pixels and an image capture object in a second direction orthogonal to the first direction; having The control unit is capable of control in either a first mode or a second mode, In the first mode, the control unit controls so that a signal output from each of the plurality of pixels is held in the corresponding holding unit; In the second mode, the control unit performs control in parallel, during a synchronous period, to output signals from the holding units corresponding to pixels in a first column and to hold signals based on the pixels in the first column in the holding units corresponding to pixels in a second column. A photoelectric conversion device comprising:

2. The plurality of pixels are further arranged in a plurality of rows in the second direction, A plurality of pixels arranged in the same row among the plurality of pixels have color filters of the same color, The pixels in the first row and the pixels in the second row of the plurality of pixels have color filters of different colors.

2. The photoelectric conversion device according to claim 1.

3. The control unit controls the pixels arranged in the same row to output signals simultaneously.

3. The photoelectric conversion device according to claim 2.

4. The control unit controls, in the first mode, to simultaneously output signals from pixels arranged in different rows.

4. The photoelectric conversion device according to claim 2 or 3.

5. The control unit controls, in the second mode, to output signals from pixels arranged in different rows at different timings.

5. The photoelectric conversion device according to claim 2, wherein the first and second electrodes are arranged in a first direction.

6. The control unit performs control so that an accumulation period of charges based on the incident light in the pixels of the first row differs from an accumulation period of charges based on the incident light in the pixels of the second row.

6. The photoelectric conversion device according to claim 2, wherein the first and second electrodes are arranged in a first direction.

7. The length of the accumulation period in the first row of pixels is equal to the length of the accumulation period in the second row of pixels.

7. The photoelectric conversion device according to claim 6.

8. The control unit performs control so that the accumulation period in the pixels in the second row starts after the accumulation period in the pixels in the first row ends.

8. The photoelectric conversion device according to claim 6 or 7.

9. In the second mode, the control unit: a first operation that performs in parallel a control for outputting a signal from the holding unit corresponding to the pixels in the first column and a control for holding a signal based on the pixels in the first column in the holding unit corresponding to the pixels in the second column; a second operation of controlling in parallel to output a signal from the holding unit corresponding to the pixel in the second column and to hold a signal based on the pixel in the second column in the holding unit corresponding to the pixel in the first column; Switches every read cycle 9. The photoelectric conversion device according to claim 1,

10. The pixel circuit further includes a column circuit that is arranged corresponding to each of the pixels and that reads out signals from the pixels and stores them in the storage unit.

10. The photoelectric conversion device according to claim 1,

11. The column circuit includes a first switch that controls connection or disconnection between a wiring corresponding to the pixels in the first column and a wiring corresponding to the pixels in the second column. The photoelectric conversion device according to claim 10 .

12. In the first mode, the first switch is controlled to a non-connected state, and in the second mode, the first switch is controlled to a connected state. The photoelectric conversion device according to claim 11 .

13. a second switch that controls connection or non-connection between a line corresponding to the pixels in the first column and a line corresponding to the pixels in the second column at a node between the column circuit and the holding unit; 13. The photoelectric conversion device according to claim 10, wherein the first and second electrodes are arranged in a first direction.

14. In the first mode, the second switch is controlled to a non-connected state, and in the second mode, the second switch is controlled to a connected state.

14. The photoelectric conversion device according to claim 13.

15. The column circuit includes an amplifier circuit having a variable analog gain.

15. The photoelectric conversion device according to claim 10,

16. The analog gain of the amplifier circuit in the second mode is higher than the analog gain of the amplifier circuit in the first mode.

16. The photoelectric conversion device according to claim 15.

17. The resolution of the image acquired in the second mode is lower than the resolution of the image acquired in the first mode.

17. The photoelectric conversion device according to claim 1,

18. In the second mode, the signal held by the holding unit is a sum signal of the pixels in the first column and the pixels in the second column.

18. The photoelectric conversion device according to claim 1,

19. The photoelectric conversion device according to any one of claims 1 to 18, an optical system that guides reflected light from the image capture target to the photoelectric conversion device; have 1. An image reading apparatus comprising:

20. a pixel array including a plurality of pixels arranged in a plurality of rows in a first direction, each of the pixels outputting a signal in response to incident light; a holding unit arranged corresponding to each of the plurality of pixels; A method for controlling a photoelectric conversion device comprising: reading out signals from the plurality of pixels and storing the signals in the storage unit at a timing synchronized with a relative position between the plurality of pixels and an image capture object in a second direction perpendicular to the first direction; outputting a signal from the holding unit; having The photoelectric conversion device can be controlled in either a first mode or a second mode, In the first mode, a signal output from each of the plurality of pixels is held in the holding unit of a corresponding column, In the second mode, a step of outputting a signal from the holding unit corresponding to the pixels in a first column and a step of holding a signal based on the pixels in the first column in the holding unit corresponding to the pixels in a second column are performed in parallel during a synchronous period. A method for controlling a photoelectric conversion device.

Images