Semiconductor Device

Abstract

To provide a semiconductor device in which controllability of dV / dt is improved and consequently turn-on loss is reduced.SOLUTION: A semiconductor device is provided in which a transistor and a diode are formed on a common semiconductor substrate, the common semiconductor includes a transistor region and a diode region. The diode region comprises: an n-type semiconductor layer provided at a first principal surface side of the semiconductor substrate; an n-type second semiconductor layer provided thereon; a p-type third semiconductor layer provided closer to a first principal surface of the semiconductor substrate than the second semiconductor layer; a first main electrode which applies a first potential to the diode; a second main electrode which applies a second potential to the diode; and a dummy active trench gate which is provided in such a manner that it reaches the second semiconductor layer from the first principal surface of the semiconductor substrate. The dummy active trench gate includes a third semiconductor layer, to which the first potential is not applied and which is consequently in a floating state, at one side of two side faces at least, and a gate potential of the transistor is applied to the dummy active trench gate.SELECTED DRAWING: Figure 23

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, and more particularly to a semiconductor device having a trench gate. [Background technology]

[0002] A typical example of a semiconductor device having a trench gate is an insulated gate bipolar transistor (IGBT).

[0003] An IGBT has a basic configuration in which a trench is provided in one main surface of a semiconductor substrate, the inner surface of the trench is covered with a gate insulating film, and the IGBT has multiple trench gates in which a gate electrode is embedded in the trench whose inner surface is covered with the gate insulating film.

[0004] In contrast, the IGBT disclosed in Patent Document 1 has a configuration in which one or more dummy trench gates that do not function as gates are provided between adjacent trench gates. For example, in Fig. 1 of Patent Document 1, three dummy trench gates are provided between adjacent trench gates, and the central dummy trench gate is given a gate potential to serve as an active dummy trench gate, while the dummy trench gates on both sides of it are given an emitter potential to serve as isolated dummy trench gates.

[0005] These dummy trench gates are covered with a continuous interlayer insulating film, and the p-type base regions between the dummy trench gates are not connected to the emitter potential and are in a floating state.

[0006] By adopting such a configuration, an active dummy trench gate to which a gate potential is applied and floating p-type base regions to which no emitter potential is applied are arranged on both sides of the active dummy trench gate, thereby increasing the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT. The reason for increasing the feedback capacitance (Cgc) is to reduce turn-on loss under conditions where dV / dt, which is the variation in drain voltage V with respect to time t, is constant, and to increase the gate capacitance ratio Cgc / Cge, which is defined as the capacitance ratio of the feedback capacitance (Cgc) to the gate-emitter capacitance Cge. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 6253769 Summary of the Invention [Problem to be solved by the invention]

[0008] As described above, in conventional semiconductor devices, the active dummy trench gate is provided within one main surface of the semiconductor substrate, i.e., above the collector layer. Therefore, holes injected from the collector layer at the time of turn-on fluctuate the potential of the floating p-type base region, causing a displacement current to flow through the active dummy trench gate and biasing the gate voltage. As a result, even if the gate resistance (Rg) is increased, dV / dt cannot be reduced. In other words, the gate resistance controllability of dV / dt decreases, which may lead to an increase in turn-on loss in a region where dV / dt is low.

[0009] The present disclosure has been made to solve the above problems, and has an object to provide a semiconductor device with improved controllability of dV / dt and reduced turn-on loss. [Means for solving the problem]

[0010] A semiconductor device according to the present disclosure includes a transistor and a diode formed on a common semiconductor substrate, the semiconductor substrate having a transistor region in which the transistor is formed and a diode region in which the diode is formed, the diode region including a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate, a second semiconductor layer of the first conductivity type provided on the first semiconductor layer, a third semiconductor layer of a second conductivity type provided closer to the first main surface side of the semiconductor substrate than the second semiconductor layer, a first main electrode for applying a first potential to the diode, a second main electrode for applying a second potential to the diode, and at least one dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate, the at least one dummy active trench gate having the third semiconductor layer in a floating state without being provided with the first potential on at least one of two side surfaces, and a gate potential of the transistor being applied to the at least one dummy active trench gate. a plurality of trench gates provided so as to reach the second semiconductor layer from a first main surface of the semiconductor substrate, the at least one dummy active trench gate being provided so as to be sandwiched between two half trench gates, the at least one dummy active trench gate and the two half trench gates having the third semiconductor layer in a floating state between them, the plurality of trench gates having the third semiconductor layer to which the first potential is applied on both sides of two side surfaces of each of the plurality of trench gates, the two half trench gates having the third semiconductor layer in a floating state on one side of each of the two side surfaces that is the at least one dummy active trench gate side, and the third semiconductor layer to which the first potential is applied on the other side of each of the plurality of trench gates and the two half trench gates having the first potential applied to the first semiconductor layer do. Effect of the Invention

[0011] According to the semiconductor device of the present disclosure, the diode region has a third semiconductor layer on at least one of two sides thereof, which is in a floating state without being supplied with a first potential, and at least one dummy active trench gate to which a transistor gate potential is supplied, thereby improving the controllability of dV / dt, which is the variation in drain voltage V with respect to time t, and obtaining a semiconductor device with reduced turn-on loss. [Brief description of the drawings]

[0012] [Figure 1] FIG. 1 is a plan view showing a semiconductor device which is an RC-IGBT. [Diagram 2] FIG. 1 is a plan view showing a semiconductor device which is an RC-IGBT. [Diagram 3] FIG. 2 is a partial plan view of an IGBT region in the RC-IGBT. [Figure 4]FIG. 2 is a partial cross-sectional view of an IGBT region in an RC-IGBT. [Diagram 5] FIG. 2 is a partial cross-sectional view of an IGBT region in an RC-IGBT. [Figure 6] FIG. 2 is a partial plan view of a diode region in the RC-IGBT. [Figure 7] FIG. 2 is a partial cross-sectional view of a diode region in an RC-IGBT. [Figure 8] FIG. 2 is a partial cross-sectional view of a diode region in an RC-IGBT. [Figure 9] FIG. 2 is a cross-sectional view of a boundary between an IGBT region and a diode region of an RC-IGBT. [Figure 10] FIG. 2 is a cross-sectional view of a boundary between an IGBT region and a termination region of an RC-IGBT. [Figure 11] FIG. 2 is a cross-sectional view of a boundary between an IGBT region and a termination region of an RC-IGBT. [Figure 12] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 13] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 14] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 15] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 16] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 17] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 18] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 19] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 20] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 21] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 22] 1A to 1C are cross-sectional views illustrating a manufacturing method of an RC-IGBT. [Figure 23]1 is a partial cross-sectional view showing a configuration of an RC-IGBT according to a first embodiment. [Figure 24] 10 is a partial cross-sectional view showing a configuration of a modified example of the RC-IGBT according to the first embodiment. FIG. [Diagram 25] FIG. 11 is a partial cross-sectional view showing the configuration of an RC-IGBT according to a second embodiment. [Figure 26] 11 is a partial cross-sectional view showing a configuration of a first modified example of an RC-IGBT according to a second embodiment. FIG. [Figure 27] 11 is a partial cross-sectional view showing a configuration of a second modified example of the RC-IGBT according to the second embodiment. FIG. [Figure 28] FIG. 11 is a partial cross-sectional view showing the configuration of an RC-IGBT according to a third embodiment. [Figure 29] FIG. 11 is a partial cross-sectional view showing a configuration of a modified example of the RC-IGBT according to the third embodiment. [Diagram 30] FIG. 11 is a partial cross-sectional view showing the configuration of an RC-IGBT according to a fourth embodiment. [Diagram 31] FIG. 13 is a plan view showing a semiconductor device according to a fifth embodiment. [Diagram 32] FIG. 13 is a partial cross-sectional view of a diode region in a semiconductor device according to a fifth embodiment. [Diagram 33] FIG. 13 is a partial cross-sectional view of an IGBT region in a semiconductor device according to a fifth embodiment. [Diagram 34] FIG. 13 is a partial plan view of a diode region in a semiconductor device according to a fifth embodiment. [Diagram 35] FIG. 13 is a partial cross-sectional view of a diode region in a semiconductor device according to a fifth embodiment. [Diagram 36] FIG. 13 is a partial cross-sectional view of a diode region in a semiconductor device according to a fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] <Introduction> In the following description, n-type and p-type indicate the conductivity types of semiconductors. In this disclosure, the first conductivity type is described as n-type and the second conductivity type is described as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. - The n-type impurity concentration is lower than that of the n-type. + The term p-type indicates that the impurity concentration is higher than that of n-type. - The impurity concentration is lower than that of p-type, and p + The n-type indicates that the impurity concentration is higher than that of the p-type.

[0014] In addition, the drawings are shown diagrammatically, and the size and positional relationship of the images shown in different drawings are not necessarily described accurately and may be changed as appropriate. In addition, in the following description, similar components are illustrated with the same reference numerals, and their names and functions are also the same. Therefore, detailed description thereof may be omitted.

[0015] In addition, in the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used; however, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and do not relate to the directions in which the embodiments are actually implemented.

[0016] Prior to describing the embodiments, a reverse conducting IGBT (RC-IGBT) in which an IGBT and a free wheeling diode (FWD) are provided on a common semiconductor substrate will be described below.

[0017] Fig. 1 is a plan view showing a semiconductor device that is an RC-IGBT. Fig. 2 is a plan view showing a semiconductor device that is an RC-IGBT with another configuration. The semiconductor device 100 shown in Fig. 1 has IGBT regions 10 and diode regions 20 arranged in a stripe pattern, and may be simply called a "striped type." The semiconductor device 101 shown in Fig. 2 has a plurality of diode regions 20 arranged vertically and horizontally, and the IGBT regions 10 are arranged around the diode regions 20, and may be simply called an "island type."

[0018] (1) Stripe-type overall planar structure In FIG. 1, the semiconductor device 100 includes an IGBT region 10 and a diode region 20 in one semiconductor device. The IGBT region 10 and the diode region 20 extend from one end side to the other end side of the semiconductor device 100, and are alternately provided in stripes in a direction perpendicular to the extending direction of the IGBT region 10 and the diode region 20. In FIG. 1, three IGBT regions 10 and two diode regions are shown, and all the diode regions 20 are sandwiched between the IGBT regions 10. However, the number of the IGBT regions 10 and the diode regions 20 is not limited to this, and the number of the IGBT regions 10 may be three or more or less, and the number of the diode regions 20 may be two or more or less. In addition, the positions of the IGBT regions 10 and the diode regions 20 in FIG. 1 may be interchanged, and all the IGBT regions 10 may be sandwiched between the diode regions 20. In addition, the IGBT regions 10 and the diode regions 20 may be provided adjacent to each other.

[0019] As shown in FIG. 1, a pad region 40 is provided adjacent to the IGBT region 10 on the lower side of the page. The pad region 40 is a region where a control pad 410 for controlling the semiconductor device 100 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 100. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing an FLR (Field Limiting Ring) that surrounds the cell region with a p-type termination well layer of a p-type semiconductor and a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer with a concentration gradient on the first main surface side, which is the front surface side of the semiconductor device 100, and the number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 100. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell and a diode cell may be provided in the pad region 40.

[0020] The control pad 410 may be, for example, a current sense pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, or temperature sense diode pads 410d and 410e. The current sense pad 410a is a control pad for detecting a current flowing in a cell region of the semiconductor device 100, and is electrically connected to a part of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 100, a current that is a fraction to a fraction of a few ten thousandths of the current flowing in the entire cell region flows.

[0021] The Kelvin emitter pad 410b and the gate pad 410c are control pads to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 100. The Kelvin emitter pad 410b is electrically connected to the p-type base layer of the IGBT cell, and the gate pad 410c is electrically connected to the gate trench electrode of the IGBT cell. The Kelvin emitter pad 410b and the p-type base layer are +The temperature sensing diode pads 410d and 410e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 100. The temperature of the semiconductor device 100 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0022] (2) Island-type overall plan structure In Fig. 2, a semiconductor device 101 includes an IGBT region 10 and a diode region 20 within one semiconductor device. A plurality of diode regions 20 are arranged in the vertical and horizontal directions within the semiconductor device, and the diode regions 20 are surrounded by the IGBT regions 10. In other words, a plurality of diode regions 20 are provided in an island shape within the IGBT region 10. In Fig. 2, the diode regions 20 are arranged in four rows in the left-right direction of the page and in four rows in the right-left direction of the page. under Although the configuration is shown in which the diode regions 20 are arranged in a matrix of two rows in the axial direction, the number and arrangement of the diode regions 20 are not limited to this, and it is sufficient that one or more diode regions 20 are interspersed within the IGBT region 10, and each diode region 20 is surrounded by the IGBT region 10.

[0023] As shown in FIG. 2, a pad region 40 is provided adjacent to the lower side of the IGBT region 10. The pad region 40 is a region where a control pad 410 for controlling the semiconductor device 101 is provided. The IGBT region 10 and the diode region 20 are collectively referred to as a cell region. A termination region 30 is provided around the combined region of the cell region and the pad region 40 to maintain the breakdown voltage of the semiconductor device 101. A known breakdown voltage maintaining structure can be appropriately selected and provided in the termination region 30. The breakdown voltage maintaining structure may be configured, for example, by providing an FLR (Field Limiting Ring) that surrounds the combined region of the cell region and the pad region 40 with a p-type termination well layer of a p-type semiconductor and a VLD (Variation of Lateral Doping) that surrounds the cell region with a p-type well layer with a concentration gradient on the first main surface side, which is the front surface side of the semiconductor device 101, and the number of ring-shaped p-type termination well layers used in the FLR and the concentration distribution used in the VLD may be appropriately selected depending on the breakdown voltage design of the semiconductor device 101. In addition, a p-type termination well layer may be provided over almost the entire area of ​​the pad region 40, and an IGBT cell and a diode cell may be provided in the pad region 40.

[0024] The control pad 410 may be, for example, a current sense pad 410a, a Kelvin emitter pad 410b, a gate pad 410c, or temperature sense diode pads 410d and 410e. The current sense pad 410a is a control pad for detecting a current flowing in a cell region of the semiconductor device 101, and is electrically connected to a part of the IGBT cells or diode cells in the cell region so that when a current flows in the cell region of the semiconductor device 101, a current that is a fraction to a fraction of a few ten thousandths of the current flowing in the entire cell region flows.

[0025] The Kelvin emitter pad 410b and the gate pad 410c are control pads to which a gate drive voltage is applied for controlling the on / off of the semiconductor device 101. The Kelvin emitter pad 410b is connected to the p-type base layer and n-type base layer of the IGBT cell. +The Kelvin emitter pad 410b and the p-type base layer are electrically connected to the p-type source layer, and the gate pad 410c is electrically connected to the gate trench electrode of the IGBT cell. + The temperature sensing diode pads 410d and 410e may be electrically connected to the anode and cathode of a temperature sensing diode provided in the semiconductor device 101. The temperature of the semiconductor device 101 is measured by measuring the voltage between the anode and cathode of the temperature sensing diode (not shown) provided in the cell region.

[0026] (3) General structure of IGBT region 10 Fig. 3 is a partially enlarged plan view showing the configuration of an IGBT region of a semiconductor device that is an RC-IGBT. Fig. 4 and Fig. 5 are cross-sectional views showing the configuration of an IGBT region of a semiconductor device that is an RC-IGBT. Fig. 3 is an enlarged view of a region 82 surrounded by a dashed line in the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2. Fig. 4 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 shown in Fig. 3 in the direction indicated by the arrows taken along dashed line AA, and Fig. 5 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 shown in Fig. 3 in the direction indicated by the arrows taken along dashed line BB.

[0027] 3, the active trench gates 11 and the dummy trench gates 12 are provided in a stripe pattern in the IGBT region 10. In the semiconductor device 100, the active trench gates 11 and the dummy trench gates 12 extend in the longitudinal direction of the IGBT region 10, and the longitudinal direction of the IGBT region 10 corresponds to the longitudinal direction of the active trench gates 11 and the dummy trench gates 12. On the other hand, in the semiconductor device 101, there is no particular distinction between the longitudinal direction and the lateral direction of the IGBT region 10, but the longitudinal direction of the active trench gates 11 and the dummy trench gates 12 may be the left-right direction of the paper, or the vertical direction of the paper may be the longitudinal direction of the active trench gates 11 and the dummy trench gates 12.

[0028] The active trench gate 11 is configured by providing a gate trench electrode 11a through a gate trench insulating film 11b in a trench formed in a semiconductor substrate. The dummy trench gate 12 is configured by providing a dummy trench electrode 12a through a dummy trench insulating film 12b in a trench formed in a semiconductor substrate. The gate trench electrode 11a of the active trench gate 11 is electrically connected to the gate pad 410c. The dummy trench electrode 12a of the dummy trench gate 12 is electrically connected to an emitter electrode provided on the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0029] n + The n-type source layer 13 is provided on both sides of the active trench gate 11 in the width direction in contact with the gate trench insulating film 11b. + The source layer 13 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is 1.0×10 17 / cm 3 ~1.0×10 20 / cm 3 n + The p-type source layer 13 is arranged along the extension direction of the active trench gate 11. + The contact layers 14 are alternately arranged. + The contact layer 14 is also provided between two adjacent dummy trench gates 12. + The contact layer 14 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 It is.

[0030] As shown in FIG. 3, in the IGBT region 10 of the semiconductor device 100 or the semiconductor device 101, three active trench gates 11 are arranged next to three dummy trench gates 12, and three active trench gates 11 are arranged next to three dummy trench gates 12. In this way, the IGBT region 10 is configured such that a set of active trench gates 11 and a set of dummy trench gates 12 are arranged alternately. In FIG. 3, the number of active trench gates 11 included in one set of active trench gates 11 is three, but it may be one or more. In addition, the number of dummy trench gates 12 included in one set of dummy trench gates 12 may be one or more, and the number of dummy trench gates 12 may be zero. In other words, all of the trenches provided in the IGBT region 10 may be active trench gates 11.

[0031] 4 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along the dashed line AA in FIG. 3, and is a cross-sectional view of the IGBT region 10. The semiconductor device 100 or the semiconductor device 101 includes a second semiconductor layer made of a semiconductor substrate, i.e., a n-type semiconductor layer. - The n-type drift layer 1 is - The drift layer 1 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 12 / cm 3 ~1.0×10 15 / cm 3 In FIG. 4, the semiconductor substrate is + The source layer 13 and the p + The n-type contact layer 14 extends from the p-type collector layer 16. + The source layer 13 and the p + The upper end of p-type contact layer 14 on the page is called the first main surface of the semiconductor substrate, and the lower end of p-type collector layer 16 on the page is called the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of semiconductor device 100, and the second main surface of the semiconductor substrate is the main surface on the back side of semiconductor device 100. In IGBT region 10, which is the cell region, semiconductor device 100 has an n-type interlayer insulating film between the first main surface and the second main surface facing the first main surface. -The semiconductor device has a type drift layer 1.

[0032] As shown in FIG. 4, in the IGBT region 10, - On the first main surface side of the n-type drift layer 1, - The n-type carrier accumulation layer 2 has a higher concentration of n-type impurities than the n-type drift layer 1. The n-type carrier accumulation layer 2 is a semiconductor layer containing, for example, arsenic or phosphorus as an n-type impurity, and the concentration of the n-type impurity is 1.0×10 13 / cm 3 ~1.0×10 17 / cm 3 In the semiconductor device 100 or the semiconductor device 101, the n-type carrier accumulation layer 2 is not provided, and the n-type carrier accumulation layer 2 region shown in FIG. - The n-type drift layer 1 may be provided. By providing the n-type carrier accumulation layer 2, it is possible to reduce the current loss when a current flows through the IGBT region 10. - The above-mentioned layer and the type drift layer 1 may be collectively referred to as a drift layer.

[0033] The n-type carrier accumulation layer 2 is - The n-type impurity is ion-implanted into the semiconductor substrate constituting the n-type drift layer 1, and then annealed to convert the implanted n-type impurity into n - The doped region is formed by diffusing the doped region into the semiconductor substrate, which is the doped drift layer 1.

[0034] A p-type base layer 15 is provided on the first main surface side of the n-type carrier accumulation layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 The p-type base layer 15 is in contact with the gate trench insulating film 11b of the active trench gate 11. On the first main surface side of the p-type base layer 15, an n-type + A p-type source layer 13 is provided in the remaining region. +A contact layer 14 is provided. + The source layer 13 and the p + The p-type contact layer 14 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 14 is a region having a higher concentration of p-type impurities than the p-type base layer 15. + When it is necessary to distinguish between the p-type contact layer 14 and the p-type base layer 15, they may be referred to individually. + The p-type contact layer 14 and the p-type base layer 15 may be collectively referred to as a p-type base layer.

[0035] In addition, the semiconductor device 100 or the semiconductor device 101 has n - On the second main surface side of the n-type drift layer 1, - An n-type buffer layer 3 having a higher concentration of n-type impurities than the p-type drift layer 1 is provided. The n-type buffer layer 3 is provided to suppress punch-through of a depletion layer extending from the p-type base layer 15 to the second main surface side when the semiconductor device 100 is in an off state. The n-type buffer layer 3 is doped with, for example, phosphorus (P) or protons (H + ) may be injected to form phosphorus (P) and protons (H + The n-type buffer layer 3 may be formed by implanting both n-type impurities. 12 / cm 3 ~1.0×10 18 / cm 3 It is.

[0036] In the semiconductor device 100 or 101, the n-type buffer layer 3 is not provided, and the n-type buffer layer 3 shown in FIG. - The n-type drift layer 1 may be provided. - The above-mentioned layer and the type drift layer 1 may be collectively referred to as a drift layer.

[0037] In the semiconductor device 100 or 101, a p-type collector layer 16 is provided on the second main surface side of the n-type buffer layer 3. -A p-type collector layer 16 is provided between the drift layer 1 and the second main surface. The p-type collector layer 16 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 16 / cm 3 ~1.0×10 20 / cm 3 The p-type collector layer 16 constitutes the second main surface of the semiconductor substrate. The p-type collector layer 16 is provided not only in the IGBT region 10 but also in the termination region 30, and the portion of the p-type collector layer 16 provided in the termination region 30 constitutes a p-type termination collector layer 16a. The p-type collector layer 16 may be provided so that a portion of it protrudes from the IGBT region 10 into the diode region 20.

[0038] As shown in FIG. 4, the semiconductor device 100 or the semiconductor device 101 has an n-type semiconductor layer extending from a first main surface of a semiconductor substrate through a p-type base layer 15. - A trench is formed so as to reach the n-type drift layer 1. A gate trench electrode 11a is provided in the trench via a gate trench insulating film 11b, thereby forming an active trench gate 11. The gate trench electrode 11a is connected to the n-type drift layer 1 through the gate trench insulating film 11b. - The n-type drift layer 1 is opposed to the n-type drift layer 1. A dummy trench electrode 12a is provided in the trench via a dummy trench insulating film 12b, thereby forming a dummy trench gate 12. The dummy trench electrode 12a is connected to the n-type drift layer 1 by the dummy trench insulating film 12b. - The gate trench insulating film 11b of the active trench gate 11 faces the p-type base layer 15 and the n-type drift layer 1. + The active trench gate 11 is in contact with the p-type source layer 13. When a gate drive voltage is applied to the gate trench electrode 11a, a channel is formed in the p-type base layer 15 in contact with the gate trench insulating film 11b of the active trench gate 11.

[0039] As shown in FIG. 4, an interlayer insulating film 4 is provided on the gate trench electrode 11a of the active trench gate 11. A barrier metal 5 is formed on the region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not provided, and on the interlayer insulating film 4. The barrier metal 5 may be, for example, a conductor containing titanium (Ti), and may be, for example, titanium nitride, or may be TiSi obtained by alloying titanium and silicon (Si). As shown in FIG. 4, the barrier metal 5 is a n + Type source layer 13, p + ohmic contact with the contact layer 14 and the dummy trench electrode 12a, + Type source layer 13, p + The barrier metal 5 is electrically connected to the contact layer 14 and the dummy trench electrode 12a. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 may be formed of an aluminum alloy such as an aluminum silicon alloy (Al-Si alloy), or may be an electrode made of a multi-layer metal film formed by electroless plating or electrolytic plating on an electrode formed of an aluminum alloy. The plating film formed by electroless plating or electrolytic plating may be, for example, a nickel (Ni) plating film. In addition, when there is a fine region between adjacent interlayer insulating films 4 where the emitter electrode 6 cannot be satisfactorily embedded, tungsten, which has better embedding properties than the emitter electrode 6, may be disposed in the fine region, and the emitter electrode 6 may be provided on the tungsten. Note that, in the case where the barrier metal 5 is not provided and n + Type source layer 13, p + An emitter electrode 6 may be provided on the contact layer 14 and the dummy trench electrode 12a. +The barrier metal 5 may be provided only on the n-type semiconductor layer such as the n-type source layer 13. The barrier metal 5 and the emitter electrode 6 may be collectively referred to as an emitter electrode. Note that, although FIG. 4 shows a diagram in which the interlayer insulating film 4 is not provided on the dummy trench electrode 12a of the dummy trench gate 12, the interlayer insulating film 4 may be formed on the dummy trench electrode 12a of the dummy trench gate 12. When the interlayer insulating film 4 is formed on the dummy trench electrode 12a of the dummy trench gate 12, the emitter electrode 6 and the dummy trench electrode 12a may be electrically connected in another cross section.

[0040] A collector electrode 7 is provided on the second main surface side of the p-type collector layer 16. The collector electrode 7 may be made of an aluminum alloy or an aluminum alloy and a plating film, similar to the emitter electrode 6. The collector electrode 7 may have a different configuration from the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to the p-type collector layer 16.

[0041] 5 is a cross-sectional view of the semiconductor device 100 or 101 taken along the dashed line BB in FIG. 3, and is a cross-sectional view of the IGBT region 10. The cross-sectional view taken along the dashed line AA in FIG. 4 is a cross-sectional view of the n-type IGBT region 10 provided on the first main surface side of the semiconductor substrate in contact with the active trench gate 11. + 5. The difference is that the n-type source layer 13 is not seen in the cross section taken along the dashed line BB in FIG. + The p-type source layer 13 is selectively provided on the first main surface side of the p-type base layer. + The p-type contact layer 14 and the p-type base layer 15 are collectively referred to as the p-type base layer.

[0042] (4) General structure of diode region 20 Fig. 6 is a partially enlarged plan view showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Figs. 7 and 8 are cross-sectional views showing the configuration of a diode region of a semiconductor device that is an RC-IGBT. Fig. 6 is an enlarged view of a region 83 surrounded by a dashed line in the semiconductor device 100 or the semiconductor device 101 shown in Fig. 1. Fig. 7 is a cross-sectional view in the direction indicated by the arrow at dashed line CC of the semiconductor device 100 shown in Fig. 6. Fig. 8 is a cross-sectional view in the direction indicated by the arrow at dashed line DD of the semiconductor device 100 shown in Fig. 6.

[0043] The diode trench gate 21 extends from one end side of the diode region 20, which is a cell region, to the opposing other end side along the first main surface of the semiconductor device 100 or the semiconductor device 101. The diode trench gate 21 is configured by providing a diode trench electrode 21a via a diode trench insulating film 21b in a trench formed in the semiconductor substrate of the diode region 20. The diode trench electrode 21a is connected to the n-type MOS transistor 100 via the diode trench insulating film 21b. - The p-type drift layer 1 is opposed to the p-type drift layer 1. + A p-type contact layer 24 and a p-type anode layer 25, which is a third semiconductor layer, are provided. + The contact layer 24 is a semiconductor layer containing p-type impurities such as boron or aluminum, and the concentration of the p-type impurities is 1.0×10 15 / cm 3 ~1.0×10 20 / cm 3 The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 12 / cm 3 ~1.0×10 19 / cm 3 It is. + The p-type contact layers 24 and the p-type anode layers 25 are alternately provided in the longitudinal direction of the diode trench gate 21 .

[0044] 7 is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 taken along the dashed line CC in FIG. 6, and is a cross-sectional view of the diode region 20. In the semiconductor device 100 or the semiconductor device 101, the diode region 20 is also an n-type semiconductor substrate, similar to the IGBT region 10. - The n-type drift layer 1 of the diode region 20 - n-type drift layer 1 and IGBT region 10 - The p-type drift layer 1 is integrally formed and is made of the same semiconductor substrate. + The first semiconductor layer is a + The area is the area up to the cathode layer 26. + The upper end of the n-type contact layer 24 in the drawing corresponds to the first main surface of the semiconductor substrate. + The lower end of the type cathode layer 26 on the page is referred to as the second main surface of the semiconductor substrate. The first main surface of the diode region 20 and the first main surface of the IGBT region 10 are flush with each other, and the second main surface of the diode region 20 and the second main surface of the IGBT region 10 are flush with each other.

[0045] As shown in FIG. 7, in the diode region 20, similarly to the IGBT region 10, n - An n-type carrier accumulation layer 2 is provided on the first main surface side of the n-type drift layer 1, - An n-type buffer layer 3 is provided on the second main surface side of the n-type drift layer 1. The n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the diode region 20 have the same configuration as the n-type carrier accumulation layer 2 and n-type buffer layer 3 provided in the IGBT region 10. It is not necessarily required to provide the n-type carrier accumulation layer 2 in the IGBT region 10 and the diode region 20. Even if the n-type carrier accumulation layer 2 is provided in the IGBT region 10, the diode region 20 may not be provided with the n-type carrier accumulation layer 2. As with the IGBT region 10, - The n-type drift layer 1, the n-type carrier accumulation layer 2 and the n-type buffer layer 3 may be collectively referred to as a drift layer.

[0046] A p-type anode layer 25 is provided on the first major surface side of the n-type carrier accumulation layer 2. The p-type anode layer 25 is - The p-type anode layer 25 is provided between the first main surface and the drift layer 1. The p-type anode layer 25 may have the same p-type impurity concentration as the p-type base layer 15 of the IGBT region 10, and the p-type anode layer 25 and the p-type base layer 15 may be formed simultaneously. The p-type anode layer 25 may have a lower p-type impurity concentration than the p-type base layer 15 of the IGBT region 10, so as to reduce the amount of holes injected into the diode region 20 during diode operation. Reducing the amount of holes injected during diode operation can reduce recovery loss during diode operation.

[0047] The first main surface side of the p-type anode layer 25 is + A contact layer 24 is provided. + The concentration of the p-type impurity in the contact layer 24 is + The concentration of the p-type impurity in the p-type contact layer 14 may be the same as or different from the p-type impurity in the p-type contact layer 14. + The p-type contact layer 24 constitutes the first main surface of the semiconductor substrate. + The p-type contact layer 24 is a region having a higher concentration of p-type impurities than the p-type anode layer 25. + When it is necessary to distinguish between the p-type contact layer 24 and the p-type anode layer 25, they may be referred to individually. + The p-type contact layer 24 and the p-type anode layer 25 may be collectively referred to as a p-type anode layer.

[0048] In the diode region 20, on the second main surface side of the n-type buffer layer 3, + A cathode layer 26 is provided. + The cathode layer 26 is an n-type - The n-type drift layer 1 and the n-type drift layer 2 are disposed between the n-type drift layer 1 and the second main surface. + The cathode layer 26 is a semiconductor layer having an n-type impurity such as arsenic or phosphorus, and the concentration of the n-type impurity is 1.0×10 16 / cm 3 ~1.0×10 21 / cm3 As shown in Figure 2, n + The cathode layer 26 is provided on a part or the whole of the diode region 20. + The n-type cathode layer 26 constitutes the second main surface of the semiconductor substrate. + The p-type impurity is further selectively implanted into the region where the n-type cathode layer 26 is formed. + A part of the region where the cathode layer 26 is formed is made into a p-type semiconductor. + A type cathode layer may be provided. + Type cathode layer and p + A diode in which the first and second cathode layers are alternately arranged along the second main surface of the semiconductor substrate is called an RFC (Relaxed Field of Cathode) diode.

[0049] As shown in FIG. 7, in the diode region 20 of the semiconductor device 100 or the semiconductor device 101, a semiconductor device having an n-type anode layer 25 is formed. - A trench is formed so as to reach the n-type drift layer 1. A diode trench electrode 21a is provided in the trench of the diode region 20 via a diode trench insulating film 21b, thereby forming a diode trench gate 21. The diode trench electrode 21a is connected to the n-type drift layer 1 via the diode trench insulating film 21b. - The semiconductor device 1 faces the drift layer 1 .

[0050] As shown in FIG. 7, the diode trench electrodes 21a and p + A barrier metal 5 is provided on the contact layer 24. The barrier metal 5 is a metal that covers the diode trench electrode 21a and the p + The diode trench electrode and the p-type contact layer 24 are in ohmic contact with each other. +The diode trench electrodes 21a and p-type contact layer 24 are electrically connected to the barrier metal 5. The barrier metal 5 may have the same configuration as the barrier metal 5 in the IGBT region 10. An emitter electrode 6 is provided on the barrier metal 5. The emitter electrode 6 provided in the diode region 20 is formed continuously with the emitter electrode 6 provided in the IGBT region 10. As in the case of the IGBT region 10, the barrier metal 5 is not provided and the diode trench electrodes 21a and p-type contact layer 24 are electrically connected to the barrier metal 5. + The contact layer 24 and the emitter electrode 6 may be in ohmic contact with each other. Although FIG. 7 shows a diagram in which the interlayer insulating film 4 is not provided on the diode trench electrode 21a of the diode trench gate 21, the interlayer insulating film 4 may be formed on the diode trench electrode 21a of the diode trench gate 21. When the interlayer insulating film 4 is formed on the diode trench electrode 21a of the diode trench gate 21, the emitter electrode 6 and the diode trench electrode 21a may be electrically connected in another cross section.

[0051] n + A collector electrode 7 is provided on the second principal surface side of the n-type cathode layer 26. Similar to the emitter electrode 6, the collector electrode 7 of the diode region 20 is formed continuously with the collector electrode 7 provided in the IGBT region 10. The collector electrode 7 is + ohmic contact to the n-type cathode layer 26, + The cathode layer 26 is electrically connected to the cathode layer 26 and also functions as a cathode electrode.

[0052] 8 is a cross-sectional view of the semiconductor device 100 or 101 taken along the dashed line DD in FIG. 6, and is a cross-sectional view of the diode region 20 taken along the dashed line CC in FIG. 7. + The difference is that the p-type contact layer 24 is not provided, and the p-type anode layer 25 constitutes the first main surface of the semiconductor substrate. + The type contact layer 24 is selectively provided on the first main surface side of the p-type anode layer 25 .

[0053] (5) Boundary region between IGBT region 10 and diode region 20 9 is a cross-sectional view showing the structure of the boundary between the IGBT region and the diode region of a semiconductor device that is an RC-IGBT, taken along the arrow direction of dashed line GG in the semiconductor device 100 or 101 shown in FIG.

[0054] 9, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided so as to protrude into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. By providing the p-type collector layer 16 so as to protrude into the diode region 20, + The distance between the type cathode layer 26 and the active trench gate 11 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during the freewheeling diode operation, n-type + This can suppress current from flowing through the type cathode layer 26. The distance U1 may be, for example, 100 μm. Depending on the application of the semiconductor device 100 or 101 that is an RC-IGBT, the distance U1 may be zero or less than 100 μm.

[0055] (6) General Structure of Termination Region 30 Fig. 10 and Fig. 11 are cross-sectional views showing the configuration of a termination region of a semiconductor device that is an RC-IGBT. Fig. 10 is a cross-sectional view in the direction indicated by the arrows taken along dashed line EE in Fig. 1 or 2, and is a cross-sectional view from the IGBT region 10 to the termination region 30. Fig. 11 is a cross-sectional view in the direction indicated by the arrows taken along dashed line FF in Fig. 1, and is a cross-sectional view from the diode region 20 to the termination region 30.

[0056] As shown in FIGS. 10 and 11, the termination region 30 of the semiconductor device 100 is formed by dividing the n-type ... -The termination region 30 has a n-type drift layer 1. The first and second main surfaces of the termination region 30 are flush with the first and second main surfaces of the IGBT region 10 and the diode region 20, respectively. - The n-type drift layer 1 is formed in the IGBT region 10 and the diode region 20. - It has the same configuration as the drift layer 1 and is formed continuously and integrally.

[0057] n - The first main surface side of the n-type drift layer 1, i.e., the first main surface of the semiconductor substrate - A p-type termination well layer 31 is provided between the n-type drift layer 1 and the n-type drift layer 1. The p-type termination well layer 31 is a semiconductor layer containing, for example, boron or aluminum as a p-type impurity, and the concentration of the p-type impurity is 1.0×10 14 / cm 3 ~1.0×10 19 / cm 3 The p-type termination well layer 31 is provided to surround the cell region including the IGBT region 10 and the diode region 20. The p-type termination well layer 31 is provided in a plurality of ring shapes, and the number of p-type termination well layers 31 provided is appropriately selected depending on the breakdown voltage design of the semiconductor device 100 or the semiconductor device 101. In addition, on the outer edge side of the p-type termination well layer 31, + A type channel stopper layer 32 is provided, and an n + The p-type channel stopper layer 32 surrounds the p-type termination well layer 31 .

[0058] n -A p-type termination collector layer 16a is provided between the drift layer 1 and the second main surface of the semiconductor substrate. The p-type termination collector layer 16a is formed integrally and continuously with the p-type collector layer 16 provided in the cell region. Therefore, the p-type termination collector layer 16a may be collectively referred to as the p-type collector layer 16. In a configuration in which the diode region 20 is provided adjacent to the termination region 30 as in the semiconductor device 100 shown in FIG. 1, the end of the p-type termination collector layer 16a on the diode region 20 side is provided protruding into the diode region 20 by a distance U2 as shown in FIG. 11. In this way, by providing the p-type termination collector layer 16a protruding into the diode region 20, the n-type collector layer 16a of the diode region 20 can be reduced. + This allows the distance between the type cathode layer 26 and the p-type termination well layer 31 to be increased, thereby preventing the p-type termination well layer 31 from acting as an anode of a diode. The distance U2 may be, for example, 100 μm.

[0059] A collector electrode 7 is provided on the second main surface of the semiconductor substrate. The collector electrode 7 is continuously and integrally formed from a cell region including the IGBT region 10 and the diode region 20 to the termination region 30. On the other hand, an emitter electrode 6 continuing from the cell region and a termination electrode 6a separated from the emitter electrode 6 are provided on the first main surface of the semiconductor substrate in the termination region 30.

[0060] The emitter electrode 6 and the termination electrode 6a are electrically connected via a semi-insulating film 33. The semi-insulating film 33 may be, for example, a semi-insulating silicon nitride (sinSiN) film. + The emitter electrode 6 is electrically connected to the semiconductor device channel stopper layer 32 via a contact hole formed in an interlayer insulating film 4 provided on the first main surface of the termination region 30. A termination protective film 34 is provided in the termination region 30 to cover the emitter electrode 6, the termination electrode 6a and the semi-insulating film 33. The termination protective film 34 may be made of, for example, polyimide.

[0061] (7) Typical manufacturing method for RC-IGBT Fig. 12 to Fig. 22 are diagrams showing a method for manufacturing a semiconductor device which is an RC-IGBT. Fig. 12 to Fig. 19 are diagrams showing steps for forming the front surface side of the semiconductor device 100 or the semiconductor device 101, and Fig. 20 to Fig. 22 are diagrams showing steps for forming the back surface side of the semiconductor device 100 or the semiconductor device 101.

[0062] First, as shown in Figure 12, - A semiconductor substrate constituting the n-type drift layer 1 is prepared. The semiconductor substrate may be, for example, a so-called FZ wafer produced by the FZ (Floating Zone) method or a so-called MCZ wafer produced by the MCZ (Magnetic field applied Czochralski) method, and may be an n-type wafer containing n-type impurities. The concentration of the n-type impurities contained in the semiconductor substrate is appropriately selected depending on the withstand voltage of the semiconductor device to be produced. For example, in a semiconductor device with a withstand voltage of 1200 V, the n-type impurities constituting the semiconductor substrate may be selected from the n-type impurities. - The concentration of n-type impurities is adjusted so that the resistivity of the n-type drift layer 1 is about 40 to 120 Ω·cm. As shown in FIG. 12, in the step of preparing a semiconductor substrate, the entire semiconductor substrate is - In the semiconductor device 100 or 101, a p-type or n-type semiconductor layer is formed by injecting p-type or n-type impurity ions from the first main surface side or the second main surface side of the semiconductor substrate and then diffusing them into the semiconductor substrate by heat treatment or the like, thereby manufacturing the semiconductor device 100 or 101.

[0063] As shown in Figure 12, n -The semiconductor substrate constituting the drift layer 1 includes a region that will become the IGBT region 10 and the diode region 20. Although not shown, a region that will become the termination region 30 is provided around the region that will become the IGBT region 10 and the diode region 20. In the following, a manufacturing method for the configuration of the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101 will be mainly described, but the termination region 30 of the semiconductor device 100 or the semiconductor device 101 may be manufactured by a known manufacturing method. For example, when an FLR having a p-type termination well layer 31 as a breakdown voltage holding structure is formed in the termination region 30, it may be formed by implanting p-type impurity ions before processing the IGBT region 10 and the diode region 20 of the semiconductor device 100 or the semiconductor device 101, or it may be formed by implanting p-type impurity ions at the same time as implanting p-type impurity ions into the IGBT region 10 or the diode region 20 of the semiconductor device 100.

[0064] Next, as shown in FIG. 13, an n-type impurity such as phosphorus (P) is implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 2. Also, a p-type impurity such as boron (B) is implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 15 and a p-type anode layer 25. The n-type carrier accumulation layer 2, the p-type base layer 15 and the p-type anode layer 25 are formed by injecting impurity ions into the semiconductor substrate and then diffusing the impurity ions by heat treatment. The n-type impurity and the p-type impurity are selectively formed on the first main surface side of the semiconductor substrate because they are ion-implanted after a mask process is applied to the first main surface of the semiconductor substrate. The n-type carrier accumulation layer 2, the p-type base layer 15 and the p-type anode layer 25 are formed in the IGBT region 10 and the diode region 20, and are connected to the p-type termination well layer 31 in the termination region 30. The mask process refers to a process of forming a mask on a semiconductor substrate by applying a resist onto the semiconductor substrate, forming openings in predetermined regions of the resist using photolithography technology, and then performing ion implantation or etching on the predetermined regions of the semiconductor substrate through the openings.

[0065] The p-type base layer 15 and the p-type anode layer 25 may be formed by simultaneously implanting p-type impurities. In this case, the p-type base layer 15 and the p-type anode layer 25 have the same depth and p-type impurity concentration, resulting in the same configuration. Alternatively, the p-type base layer 15 and the p-type anode layer 25 may have different depths and p-type impurity concentrations by implanting p-type impurities into them separately using a mask process.

[0066] Also, the p-type termination well layer 31 formed in another cross section may be formed by ion implanting p-type impurities at the same time as the p-type anode layer 25. In this case, the p-type termination well layer 31 and the p-type anode layer 25 have the same depth and p-type impurity concentration, and can be configured to be the same. Also, the p-type termination well layer 31 and the p-type anode layer 25 can be formed by ion implanting p-type impurities at the same time, so that the p-type termination well layer 31 and the p-type anode layer 25 have different p-type impurity concentrations. In this case, the aperture ratio can be changed by using a mesh-shaped mask for one or both of the masks.

[0067] In addition, the p-type termination well layer 31 and the p-type anode layer 25 may be ion-implanted with p-type impurities separately using a mask process, thereby making the depths and p-type impurity concentrations of the p-type termination well layer 31 and the p-type anode layer 25 different. The p-type termination well layer 31, the p-type base layer 15, and the p-type anode layer 25 may be formed simultaneously by ion-implanting p-type impurities.

[0068] Next, as shown in FIG. 14, a mask process is used to selectively inject n-type impurities into the first main surface side of the p-type base layer 15 in the IGBT region 10 to form an n + The n-type source layer 13 is formed. The implanted n-type impurity may be, for example, arsenic (As) or phosphorus (P). In addition, a mask process is used to selectively implant the p-type impurity into the first main surface side of the p-type base layer 15 in the IGBT region 10 to form a p + A p-type contact layer 14 is formed, and a p-type impurity is selectively implanted into the first main surface side of the p-type anode layer 25 in the diode region 20 to form a p +Then, a p-type contact layer 24 is formed. The implanted p-type impurity may be, for example, boron (B) or aluminum (Al).

[0069] Next, as shown in FIG. 15, a semiconductor substrate is formed by passing through the p-type base layer 15 and the p-type anode layer 25 from the first main surface side of the semiconductor substrate. - A trench 8 is formed in the IGBT region 10, reaching the n-type drift layer 1. + The trench 8 penetrating the source layer 13 has n-type sidewalls. + The trench 8 constitutes a part of the type source layer 13. The trench 8 may be formed by depositing an oxide film such as SiO2 on the semiconductor substrate, forming an opening in the oxide film at the portion where the trench 8 is to be formed by mask processing, and etching the semiconductor substrate using the oxide film with the opening formed as a mask. In FIG. 15, the trenches 8 are formed with the same pitch in the IGBT region 10 and the diode region 20, but the pitch of the trenches 8 may be different in the IGBT region 10 and the diode region 20. The pattern of the pitch of the trenches 8 in a plan view can be appropriately changed by changing the mask pattern in the mask processing.

[0070] 16, the semiconductor substrate is heated in an atmosphere containing oxygen to form an oxide film 9 on the inner wall of the trench 8 and on the first main surface of the semiconductor substrate. Of the oxide films 9 formed on the inner walls of the trenches 8, the oxide film 9 formed in the trenches 8 in the IGBT region 10 is the gate trench insulating film 11b of the active trench gate 11 and the dummy trench insulating film 12b of the dummy trench gate 12. In addition, the oxide film 9 formed in the trenches 8 in the diode region 20 is the diode trench insulating film 21b. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later process.

[0071] Next, as shown in FIG. 17, polysilicon doped with n-type or p-type impurities is deposited in trench 8 having oxide film 9 formed on its inner wall by CVD (chemical vapor deposition) or the like to form gate trench electrode 11a, dummy trench electrode 12a, and diode trench electrode 21a.

[0072] Next, as shown in FIG. 18, the oxide film 9 formed on the first main surface of the semiconductor substrate after the interlayer insulating film 4 is formed on the gate trench electrode 11a of the active trench gate 11 in the IGBT region 10 is removed. The interlayer insulating film 4 may be, for example, SiO2. Then, a contact hole is formed in the deposited interlayer insulating film 4 by a mask process. The contact hole is an n + On type source layer 13, p + On the contact layer 14, + It is formed on the mold contact layer 24, the dummy trench electrode 12a and the diode trench electrode 21a.

[0073] 19, a barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4, and an emitter electrode 6 is further formed on the barrier metal 5. The barrier metal 5 is formed by depositing titanium nitride by physical vapor deposition (PDV) or CVD.

[0074] The emitter electrode 6 may be formed by depositing an aluminum silicon alloy (Al-Si alloy) on the barrier metal 5 by PVD such as sputtering or vapor deposition. A nickel alloy (Ni alloy) may be further formed on the formed aluminum silicon alloy by electroless plating or electrolytic plating to form the emitter electrode 6. When the emitter electrode 6 is formed by plating, a thick metal film can be easily formed as the emitter electrode 6, so that the heat capacity of the emitter electrode 6 can be increased and the heat resistance can be improved. When a nickel alloy is further formed by plating after forming the emitter electrode 6 made of an aluminum silicon alloy by PVD, the plating for forming the nickel alloy may be performed after processing the second main surface side of the semiconductor substrate.

[0075] 20, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a predetermined designed thickness. The thickness of the semiconductor substrate after grinding may be, for example, 80 μm to 200 μm.

[0076] 21 , n-type impurities are injected from the second main surface side of the semiconductor substrate to form an n-type buffer layer 3. Furthermore, p-type impurities are injected from the second main surface side of the semiconductor substrate to form a p-type collector layer 16. The n-type buffer layer 3 may be formed in the IGBT region 10, the diode region 20 and the termination region 30, or may be formed only in the IGBT region 10 or the diode region 20.

[0077] The n-type buffer layer 3 may be formed by implanting, for example, phosphorus (P) ions. + ) may be implanted. Furthermore, both protons and phosphorus may be implanted. Protons can be implanted deep into the second main surface of the semiconductor substrate with a relatively low acceleration energy. Also, the depth to which protons are implanted can be changed relatively easily by changing the acceleration energy. For this reason, when forming the n-type buffer layer 3 with protons, if protons are implanted multiple times while changing the acceleration energy, an n-type buffer layer 3 that is wider in the thickness direction of the semiconductor substrate than one formed with phosphorus can be formed.

[0078] Furthermore, since phosphorus can have a higher activation rate as an n-type impurity than protons, punch-through of the depletion layer can be more reliably suppressed even in a thinned semiconductor substrate by forming the n-type buffer layer 3 with phosphorus. In order to further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 3 by implanting both protons and phosphorus, and in this case, the protons are implanted deeper from the second main surface than the phosphorus.

[0079] The p-type collector layer 16 may be formed by, for example, implanting boron (B). The p-type collector layer 16 is also formed in the termination region 30, and the p-type collector layer 16 in the termination region 30 becomes the p-type termination collector layer 16a. After ion implantation from the second main surface side of the semiconductor substrate, the second main surface is irradiated with a laser for laser annealing, whereby the implanted boron is activated and the p-type collector layer 16 is formed. At this time, phosphorus for the n-type buffer layer 3 implanted at a position relatively shallow from the second main surface of the semiconductor substrate is also activated at the same time. On the other hand, since protons are activated at a relatively low annealing temperature of 350°C to 500°C, care must be taken not to raise the temperature of the entire semiconductor substrate to a temperature higher than 350°C to 500°C after the protons are implanted, except in the process for activating the protons. Since laser annealing can raise the temperature only near the second main surface of the semiconductor substrate, it can be used to activate n-type impurities and p-type impurities even after the protons are implanted.

[0080] Next, as shown in FIG. + A cathode layer 26 is formed. + The p-type cathode layer 26 may be formed by implanting phosphorus (P), for example. As shown in FIG. 22, the p-type collector layer 16 and the n-type collector layer 17 are disposed at a distance U1 from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20. + Phosphorus is selectively implanted from the second main surface side by mask processing so that the boundary with the cathode layer 26 is located. + The amount of n-type impurities implanted to form the n-type cathode layer 26 is greater than the amount of p-type impurities implanted to form the p-type collector layer 16. In FIG. + The depth of the n-type cathode layer 26 is shown to be the same. + The depth of the n-type cathode layer 26 is equal to or greater than the depth of the p-type collector layer 16. + The region in which the cathode layer 26 is to be formed must be made into an n-type semiconductor by implanting n-type impurities into the region implanted with p-type impurities. + In the entire region where the cathode layer 26 is to be formed, the concentration of the implanted p-type impurities is made higher than the concentration of the n-type impurities.

[0081] Next, the collector electrode 7 is formed on the second main surface of the semiconductor substrate, thereby obtaining the cross-sectional configuration shown in FIG. 9. The collector electrode 7 is formed over the entire surfaces of the IGBT region 10, the diode region 20, and the termination region 30 on the second main surface. The collector electrode 7 may also be formed over the entire surface of the second main surface of an n-type wafer, which is the semiconductor substrate. The collector electrode 7 is formed by depositing an aluminum silicon alloy ( Al The collector electrode 7 may be formed by depositing a metal such as an aluminum silicon alloy, titanium, nickel, or gold, or may be formed by laminating a plurality of metals such as an aluminum silicon alloy, titanium, nickel, or gold. Furthermore, the collector electrode 7 may be formed by forming a metal film by electroless plating or electrolytic plating on a metal film formed by PVD.

[0082] The above-mentioned steps are used to manufacture the semiconductor device 100 or the semiconductor device 101. Since a plurality of semiconductor devices 100 or semiconductor devices 101 are manufactured in a matrix on one n-type wafer, the semiconductor device 100 or semiconductor device 101 is completed by cutting the wafer into individual semiconductor devices 100 or semiconductor devices 101 by laser dicing or blade dicing.

[0083] <Embodiment 1> <Configuration> Fig. 23 is a partial cross-sectional view showing the configuration of an RC-IGBT1000 according to the first embodiment, and is a cross-sectional view corresponding to the cross-sectional view in the arrow direction taken along dashed line GG in the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2. Note that the same components as those in Fig. 9, which is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 shown in Fig. 9, are designated by the same reference numerals, and duplicated explanations will be omitted.

[0084] 23, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided protruding into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. By providing the p-type collector layer 16 protruding into the diode region 20 in this manner,+ The distance between the type cathode layer 26 and the active trench gate 11 can be increased, and even when a gate drive voltage is applied to the gate trench electrode 11a during the freewheeling diode operation, n-type + This can suppress the flow of current through the cathode layer 26.

[0085] In the RC-IGBT 1000 shown in FIG. 23, the diode region 20 is a first main surface of a semiconductor substrate, i.e., n + Type source layer 13, p + Type contact layer 14, p + The p-type contact layer 24 and the p-type anode layer 25 are shown in FIG. Edge et al., n - The semiconductor device has a plurality of active trench gates 11 reaching the type drift layer 1, a plurality of dummy trench gates 12, a plurality of diode trench gates 21, a plurality of diode half trench gates 22 and a diode dummy active trench gate 41.

[0086] In addition, since the present disclosure is characterized by the configuration of the diode region 20, the following description will mainly focus on the configuration of the diode region 20.

[0087] 23, the diode dummy active trench gate 41 is provided so as to be sandwiched between two diode half trench gates 22, and a p-type anode layer 41c, which is a third semiconductor layer, is provided between the diode dummy active trench gate 41 and the diode half trench gate 22. The two diode half trench gates 22 and the diode dummy active trench gate 41 are covered with a continuous interlayer insulating film 4, and the p-type anode layer 41c is not given an emitter potential, which is a first potential, and is in a floating state.

[0088] The diode trench gate 21 is p + The n-type contact layer 24, the p-type anode layer 25, and the n-type carrier accumulation layer 2 are penetrated by the n- A diode trench electrode 21a is provided in a trench that reaches the type drift layer 1 with a diode trench insulating film 21b interposed therebetween, and the diode trench electrode 21a is electrically connected to the emitter electrode 6.

[0089] The diode half trench gate 22 is connected to the p-type anode layer 25 and the n-type carrier accumulation layer 2 through the n-type - A diode half-trench electrode 22a is provided in a trench that reaches the type drift layer 1 via a diode half-trench insulating film 22b, and the diode half-trench electrode 22a is electrically connected to the emitter electrode 6.

[0090] A p-type anode layer 25 electrically connected to the emitter electrode 6 is provided on one of the two side surfaces of the diode half trench gate 22, and a p-type anode layer 41c in a floating state is provided on the other side without being electrically connected to the emitter electrode 6. A trench gate having such a configuration with a p-type anode layer in a floating state on one side of the trench gate is referred to as a "semi trench gate."

[0091] The diode dummy active trench gate 41 is formed by passing through the p-type anode layer 41c and the n-type carrier accumulation layer 2. - A diode dummy active trench electrode 41a is provided in a trench that reaches the type drift layer 1 via a diode dummy active trench insulating film 41b, and the diode dummy active trench electrode 41a is electrically connected to a gate electrode (not shown).

[0092] A p-type anode layer 41c in a floating state, which is not electrically connected to the emitter electrode 6, is provided on both sides of the side surface of the diode dummy active trench gate 41. In this manner, a configuration in which the trench electrode is electrically connected to the gate electrode and has a p-type anode layer in a floating state on one side of the gate, is called a "dummy active trench gate."

[0093] As described above, in the diode region 20 of the RC-IGBT 1000, an emitter potential E is applied to the diode trench electrode 21a of the diode trench gate 21 and the diode half-trench electrode 22a of the diode half-trench gate 22, and a gate potential G is applied to the diode dummy active trench electrode 41a of the diode dummy active trench gate 41.

[0094] In this way, the displacement current can be suppressed by arranging the diode dummy active trench gate 41 in the diode region. That is, in the diode region, holes are injected from the anode but not from the cathode during diode operation, so that the displacement current flowing through the diode dummy active trench gate 41 can be suppressed without the potential of the p-type anode layer 41c fluctuating due to holes injected from the cathode.

[0095] Furthermore, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided protruding from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20 by a distance U1, but the diode dummy active trench gate 41 is not disposed on the first main surface side corresponding to the region where the p-type collector layer 16 protrudes. This also makes it possible to suppress the displacement current flowing through the diode dummy active trench gate 41.

[0096] In addition, since a dummy active trench gate is not provided in the IGBT region, holes injected from the collector layer at the time of turn-on do not fluctuate the potential of the floating p-type base layer 15, so that the flow of displacement current through the dummy active trench gate is suppressed, and the deterioration of the gate resistance controllability of dV / dt can be suppressed.

[0097] In addition, the diode dummy active trench gate 41 is sandwiched between two diode half trench gates 22, and a p-type anode layer 41c is provided between the diode dummy active trench gate 41 and the diode half trench gate 22. The p-type anode layer 41c is not connected to the emitter potential and is in a floating state.

[0098] Therefore, the diode dummy active trench electrode 41a of the diode dummy active trench gate 41, the diode dummy active trench insulating film 41b, the floating p-type anode layer 41c and the n - A capacitor is formed in the type drift layer 1. This means that a capacitor is formed between the diode dummy active trench electrode 41a and the collector electrode 7, i.e., the cathode electrode that applies the second potential, and this means that the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT is increased. By increasing the feedback capacitance (Cgc), it is possible to reduce turn-on loss under the condition that dV / dt, which is the variation of the drain voltage V with respect to time t, is constant.

[0099] In FIG. 23, the p-type anode layer 41c arranged on both sides of the diode dummy active trench gate 41 is set to a floating potential, but the p-type anode layer 41c may be connected to the emitter electrode 6 in the cell region. Also, the p-type anode layer 41c may or may not be connected to the p-type termination well layer 31 (FIG. 11) in the termination region. In this case, the p-type termination well layer 31 may be electrically connected to the emitter electrode 6. That is, the p-type anode layer 41c may or may not be electrically connected to the emitter electrode 6 in the termination region. By electrically connecting the p-type anode layer 41c to the emitter electrode 6 at a position far away instead of electrically connecting it to the emitter electrode 6 directly above, the p-type anode layer 41c is connected to the emitter electrode 6 via a high resistance, and is in a pseudo-floating state, which can provide the effect of increasing the feedback capacitance (Cgc).

[0100] <Effects> As described above, according to the RC-IGBT 1000 of the first embodiment, the displacement current flowing through the diode dummy active trench gate 41 can be suppressed. Also, by providing the diode dummy active trench gate 41 in the diode region 20 and providing a floating p-type anode layer 41c adjacent to it, the feedback capacitance Cgc between the gate and collector of the IGBT can be increased, so that the turn-on loss can be reduced under the condition that dV / dt is constant.

[0101] <Modification> In the RC-IGBT 1000 shown in FIG. 23, a configuration in which only one diode dummy active trench gate 41 is sandwiched between two diode half trench gates 22 has been disclosed, but this is not limited to this, and multiple diode dummy active trench gates 41 may be provided.

[0102] For example, an RC-IGBT 1001 shown in FIG. 24 has a configuration in which two diode dummy active trench gates 41 are provided between two diode half trench gates 22.

[0103] The diode dummy active trench gate 41 is provided so as to be sandwiched between two diode half trench gates 22. When the diode dummy active trench gate 41 and the diode half trench gate 22 are arranged so as to be adjacent to each other in this way, a gate-emitter capacitance Cge, which is a coupling capacitance, is generated between the diode dummy active trench gate 41 at the gate potential and the diode half trench gate 22 at the emitter potential. When the gate-emitter capacitance Cge is generated, the gate capacitance ratio Cgc / Cge becomes small, which is not desirable for reducing the turn-on loss.

[0104] Therefore, by increasing the number of diode dummy active trench gates 41 as in the RC-IGBT 1001 shown in FIG. 24, the gate capacitance ratio Cgc / Cge can be further increased, and the turn-on loss can be further reduced.

[0105] <Embodiment 2> <Configuration> Fig. 25 is a partial cross-sectional view showing the configuration of an RC-IGBT2000 according to the second embodiment, and is a cross-sectional view corresponding to the cross-sectional view in the arrow direction taken along dashed line GG in the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2. Note that the same components as those in Fig. 9, which is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 shown in Fig. 9, are designated by the same reference numerals, and duplicated explanations will be omitted.

[0106] In the RC-IGBT 2000 shown in FIG. 25, the diode region 20 is a region extending from the top of the page of the p-type anode layer 25, which is the first main surface of the semiconductor substrate, to the n - The semiconductor device has a plurality of diode trench gates 21 reaching the first drift layer 1, and two adjacent diode semi-dummy active trench gates 51. A p-type anode layer 41c is provided between the two diode semi-dummy active trench gates 51. The tops of the two diode semi-dummy active trench gates 51 are covered with a continuous interlayer insulating film 4, and the p-type anode layer 41c is not applied with an emitter potential and is in a floating state.

[0107] The diode semi-dummy active trench gate 51 is formed by passing through the p-type anode layer 41c and the n-type carrier accumulation layer 2. - A diode semi-dummy active trench electrode 51a is provided in a trench that reaches the type drift layer 1 via a diode semi-dummy active trench insulating film 51b, and the diode semi-dummy active trench electrode 51a is electrically connected to a gate electrode (not shown).

[0108] A p-type anode layer 25 electrically connected to the emitter electrode 6 is provided on one of the two side surfaces of the diode semi-dummy active trench gate 51, and a p-type anode layer 41c in a floating state is provided on the other side.

[0109] As described above, in the diode region 20 of the RC-IGBT2000, an emitter potential E is applied to the diode trench electrode 21a of the diode trench gate 21 and the diode half-trench electrode 22a of the diode half-trench gate 22, and a gate potential G is applied to the diode half-dummy active trench electrode 51a of the diode half-dummy active trench gate 51.

[0110] In this way, the displacement current can be suppressed by arranging the diode semi-dummy active trench gate 51 in the diode region. That is, in the diode region, holes are injected from the anode but not from the cathode during diode operation, so that the potential of the p-type anode layer 41c does not fluctuate due to holes injected from the cathode, and the displacement current flowing through the diode semi-dummy active trench gate 51 can be suppressed.

[0111] Furthermore, the p-type collector layer 16 provided on the second main surface side of the IGBT region 10 is provided protruding from the boundary between the IGBT region 10 and the diode region 20 toward the diode region 20 by a distance U1, but the diode semi-dummy active trench gate 51 is not disposed on the first main surface side corresponding to the region where the p-type collector layer 16 protrudes. This also makes it possible to suppress the displacement current flowing through the diode semi-dummy active trench gate 51.

[0112] In addition, since a dummy active trench gate is not provided in the IGBT region, holes injected from the collector layer at the time of turn-on do not fluctuate the potential of the floating p-type base layer 15, so that the flow of displacement current through the dummy active trench gate is suppressed, and the deterioration of the gate resistance controllability of dV / dt can be suppressed.

[0113] In addition, a p-type anode layer 41c is provided between the two diode semi-dummy active trench gates 51, and the p-type anode layer 41c is not connected to the emitter potential and is in a floating state.

[0114] Therefore, the diode semi-dummy active trench electrode 51a of the diode semi-dummy active trench gate 51, the diode semi-dummy active trench insulating film 51b, the floating p-type anode layer 41c and the n - A capacitor is formed in the type drift layer 1. This means that a capacitor is formed between the diode semi-dummy active trench electrode 51a and the collector electrode 7, i.e., the cathode electrode that applies the second potential, and this means that the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT is increased. By increasing the feedback capacitance (Cgc), it is possible to reduce turn-on loss under the condition that dV / dt, which is the variation of the drain voltage V with respect to time t, is constant.

[0115] <Effects> As described above, according to the RC-IGBT2000 of the second embodiment, the displacement current flowing through the diode semi-dummy active trench gate 51 can be suppressed. Also, by providing the diode semi-dummy active trench gate 51 in the diode region 20 and providing the floating p-type anode layer 41c adjacent to it, the feedback capacitance Cgc between the gate and collector of the IGBT can be increased, so that the turn-on loss can be reduced under the condition that dV / dt is constant.

[0116] <Variation 1> In the RC-IGBT2000 shown in FIG. 25, a configuration is shown in which a floating p-type anode layer 41c is provided between the diode semi-dummy active trench gates 51, but a configuration in which a diode dummy active trench gate 41 is provided next to the diode semi-dummy active trench gate 51 may also be used, as in the RC-IGBT2001 shown in FIG. 26.

[0117] As shown in FIG. 26, the diode dummy active trench gate 41 is formed by passing through the p-type anode layer 41c and the n-type carrier accumulation layer 2. -A diode dummy active trench electrode 41a is provided in a trench that reaches the p-type drift layer 1 via a diode dummy active trench insulating film 41b, and the diode dummy active trench electrode 41a is electrically connected to a gate electrode (not shown). The two diode semi-dummy active trench gates 51 and the diode dummy active trench gate 41 are covered with a continuous interlayer insulating film 4, and the p-type anode layer 41c is not applied with an emitter potential and is in a floating state.

[0118] In this way, the displacement current can be suppressed by arranging the diode dummy active trench gate 41 in the diode region so as to be adjacent to the diode semi-dummy active trench gate 51. That is, in the diode region, holes are injected from the anode but not from the cathode during diode operation, so that the displacement current flowing through the diode dummy active trench gate 41 can be suppressed without the potential of the p-type anode layer 41c fluctuating due to holes injected from the cathode.

[0119] In addition, by disposing the diode dummy active trench gate 41, the diode dummy active trench electrode 41a of the diode dummy active trench gate 41, the diode dummy active trench insulating film 41b, the floating p-type anode layer 41c and the n - A capacitor is formed in the type drift layer 1. This makes it possible to further increase the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT. By further increasing the feedback capacitance (Cgc), it is possible to further reduce turn-on loss under the condition that dV / dt, which is the variation of the drain voltage V with respect to time t, is constant.

[0120] In addition, since the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51 to which a gate potential is applied are arranged adjacent to each other, no gate-emitter capacitance Cge, which is a coupling capacitance, occurs between the two, and the gate capacitance ratio Cgc / Cge can be increased, thereby reducing turn-on loss.

[0121] In the RC-IGBT2001 shown in FIG. 26, a configuration in which only one diode dummy active trench gate 41 is sandwiched between two diode semi-dummy active trench gates 51 has been disclosed, but this is not limited to this, and multiple diode dummy active trench gates 41 may be provided.

[0122] By increasing the number of diode dummy active trench gates 41, the gate capacitance ratio Cgc / Cge can be further increased, and the turn-on loss can be further reduced.

[0123] <Variation 2> In the RC-IGBT 2001 shown in FIG. 26, from the top end of the page of the p-type anode layer 25 which is the first main surface of the semiconductor substrate, n - In the above embodiment, a plurality of diode trench gates 21 reaching the n-type drift layer 1 are provided. However, as in the RC-IGBT2002 shown in FIG. 27, instead of the plurality of diode trench gates 21, - A configuration may be provided in which a plurality of diode active trench gates 61 reach the type drift layer 1.

[0124] The diode active trench gate 61 is p + The n-type contact layer 24, the p-type anode layer 25, and the n-type carrier accumulation layer 2 are penetrated by the n - A diode active trench electrode 61a is provided in a trench that reaches the type drift layer 1 via a diode active trench insulating film 61b, and the diode active trench electrode 61a is electrically connected to a gate electrode (not shown).

[0125] Therefore, a capacitor is formed by the diode active trench electrode 61a of the diode active trench gate 61, the diode active trench insulating film 61b, and the p-type anode layer 25 electrically connected to the emitter electrode 6, and a gate-emitter capacitance Cge is generated. - A gate-collector capacitance (feedback capacitance) Cgc is also generated by the capacitor formed in the type drift layer 1. For this reason, in addition to the gate-collector capacitance (feedback capacitance) Cgc obtained by arranging the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51, the feedback capacitance (Cgc) can be further increased, and the turn-on loss can be further reduced under the condition that dV / dt, which is the variation in the drain voltage V with respect to time t, is constant.

[0126] <Embodiment 3> <Configuration> Fig. 28 is a partial cross-sectional view showing the configuration of an RC-IGBT3000 according to the third embodiment, and is a cross-sectional view corresponding to the cross-sectional view in the arrow direction taken along dashed line GG in the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2. Note that the same components as those in Fig. 9, which is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 shown in Fig. 9, are designated by the same reference numerals, and duplicated explanations will be omitted.

[0127] 28, similar to the RC-IGBT2001 shown in FIG. 26, a diode dummy active trench gate 41 is provided next to a diode semi-dummy active trench gate 51, but the distance between the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51 is set shorter than the distance between adjacent diode trench gates 21, or the distance between adjacent active trench gates 11, or the distance between adjacent active trench gates 11 and dummy trench gate 12.

[0128] In addition, in FIG. 28, the number of diode dummy active trench gates 41 arranged is one, but this is not limited thereto, and a plurality of diode dummy active trench gates 41 can be arranged.

[0129] In this case, the interval between the diode dummy active trench gate 41 and the diode half dummy active trench gate 51, and the interval between adjacent diode dummy active trench gates 41 can be set to 1 / 2 to 1 / 4 of the interval between other adjacent trench gates.

[0130] <Effects> By narrowing the distance between the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51, the diode dummy active trench gates 41 and the diode semi-dummy active trench gates 51 can be arranged at a high density. Therefore, by increasing the number of diode dummy active trench gates 41 arranged, the gate-collector capacitance (feedback capacitance) Cgc between the gate and collector of the IGBT can be increased, and turn-on loss can be reduced under conditions where dV / dt, which is the fluctuation in drain voltage V with respect to time t, is constant.

[0131] <Modification> In the RC-IGBT3000 of the third embodiment described above, the distance between the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51 is made narrower than the distance between other adjacent trench gates, and the number of diode dummy active trench gates 41 arranged is increased to increase the feedback capacitance Cgc. However, as in the RC-IGBT3001 shown in FIG. 29, the feedback capacitance Cgc can also be increased by forming the arrangement pattern of the diode dummy active trench gates 41 into a lattice pattern.

[0132] Fig. 29 is a partial plan view showing the configuration of the RC-IGBT3001, and is a view showing a part of the diode region 20 when the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51 are viewed from above. For convenience, the configuration of the emitter electrode 6 and the like is omitted in Fig. 29.

[0133] 29, the diode dummy active trench gate 41 is configured to branch in a direction perpendicular to the extension direction of the trench at multiple portions in the extension direction of the trench and to be connected to adjacent diode semi-dummy active trench gates 51. As a result, the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51 form a lattice-shaped trench gate, and the p-type anode layer 41c becomes a rectangular region in a plan view surrounded by the lattice-shaped trench gates.

[0134] For this reason, the gate-collector capacitance (feedback capacitance) Cgc is increased by arranging the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51, and the turn-on loss can be reduced under the condition that dV / dt, which is the variation of the drain voltage V with respect to time t, is constant.

[0135] The number of p-type anode layers 41c having a rectangular shape in a planar view is not particularly limited as long as it is within a size range in which the diode dummy active trench insulating film 41b and the diode dummy active trench electrode 41a can be formed within the length of the stripe-shaped diode dummy active trench gate 41.

[0136] <Fourth embodiment> <Configuration> Fig. 30 is a partial cross-sectional view showing the configuration of an RC-IGBT4000 according to the fourth embodiment, and is a cross-sectional view corresponding to the cross-sectional view in the arrow direction taken along dashed line GG in the semiconductor device 100 shown in Fig. 1 or the semiconductor device 101 shown in Fig. 2. Note that the same components as those in Fig. 9, which is a cross-sectional view of the semiconductor device 100 or the semiconductor device 101 shown in Fig. 9, are designated by the same reference numerals, and duplicated explanations will be omitted.

[0137] In the RC-IGBT4000 shown in FIG. 30, similarly to the RC-IGBT1001 shown in FIG. 23, the diode dummy active trench gate 41 is provided so as to be sandwiched between two diode half trench gates 22, but the p-type anode layer 41c is not provided in the mesa region between the diode dummy active trench gate 41 and the diode half trench gate 22, and the n - In the semiconductor device, the n-type drift layer 1 is formed, and the n-type carrier accumulation layer 2 is not formed.

[0138] <Effects> When a p-type anode layer 41c is provided in the mesa region between the diode dummy active trench gate 41 and the diode half trench gate 22, a small number of holes due to the reverse recovery current during the recovery operation of the diode may fluctuate the potential of the floating p-type anode layer 41c and generate a displacement current. However, by not forming a p-type semiconductor layer here, the effect of the displacement current on the diode dummy active trench gate 41 can be suppressed.

[0139] <Fifth Preferred Embodiment> <Configuration> Fig. 31 is a plan view showing an island-type semiconductor device 102 as a semiconductor device according to a fifth embodiment, which includes an IGBT region 10 and a diode region 20 in one semiconductor device. In Fig. 31, the extension direction of the trench gate is indicated by an arrow AR. As shown in Fig. 31, the trench gate extends along the arrangement direction of the control pads 410. Note that the same components as those in the semiconductor device 101 shown in Fig. 2 are denoted by the same reference numerals, and duplicated explanations will be omitted.

[0140] Fig. 32 is a cross-sectional view taken along line EE in Fig. 31. The cross-sectional configuration of the IGBT region 10 shown in Fig. 32 is the same as the cross-sectional configuration of the IGBT region 10 shown in Fig. 4, and the same components are denoted by the same reference numerals and redundant description will be omitted.

[0141] 33 is a cross-sectional view taken along line GG in FIG. 31. The cross-sectional configuration of the diode region 20 shown in FIG. T2 The cross-sectional structure is basically the same as that of 001, and the diode dummy active trench gate 41 is provided next to the diode half dummy active trench gate 51. T2 The same components as those in 001 are given the same reference numerals, and duplicated explanations will be omitted.

[0142] As shown in FIG. 31, the IGBT regions 10 and the diode regions 20 are arranged alternately in the extension direction of the trench gate, and the trench gate penetrates the IGBT regions 10 and the diode regions 20 in a plan view.

[0143] In this configuration, in the IGBT region 10, as shown in FIG. 32, for example, the active trench gate 11 has a gate trench electrode 11a electrically connected to a gate pad 410c (FIG. 31), and the active trench gate 11 has two side surfaces on both or one of the outsides of n + A source layer 13 is provided, and + The source layer 13 is electrically connected to the emitter electrode 6 .

[0144] On the other hand, in the diode region 20, as shown in Fig. 33, in the two diode semi-dummy active trench gates 51 and the diode dummy active trench gate 41 provided between them, the diode semi-dummy active trench electrode 51a and the diode dummy active trench electrode 41a are electrically connected to the gate pad 410c (Fig. 31). Note that the p-type anode layer 41c provided between the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51 is not electrically connected to the emitter electrode 6 and is in a floating state.

[0145] <Effects> As described above, the feedback capacitance Cgc can be increased by forming the active trench gate 11 in the IGBT region 10, and the diode dummy active trench gate 41 and the diode semi-dummy active trench gate 51 in the diode region 20 as continuous trench gates. This is because the gate trench electrode 11a, the gate trench insulating film 11b, and the n - This is because a feedback capacitance Cgc generated by the capacitor formed in the drift layer 1 is added.

[0146] <Modification> Fig. 34 is a partial plan view showing an enlarged region 83 surrounded by a dashed line in the diode region 20 in the semiconductor device 102 shown in Fig. 31. As shown in Fig. 34, in the diode region 20, a diode trench gate 21 extends from one end side of the diode region 20, which is a cell region, to the opposing other end side along the first main surface of the semiconductor device 102. Between two adjacent diode trench gates 21, p + A p-type contact layer 24 and a p-type anode layer 25 are provided. A diode dummy active trench gate 41 is provided so as to be sandwiched between the two diode trench gates 21.

[0147] In the extending direction of the diode dummy active trench gate 41, a part of it is formed as a diode active trench gate 61, and the upper part of it is covered with the interlayer insulating film 4. However, the p + The p-type contact layer 24 and the p-type anode layer 25 are partially electrically connected to the emitter electrode.

[0148] On the other hand, the p-type anode layers 41c provided to sandwich the diode dummy active trench gate 41 are covered at the top with the interlayer insulating film 4, are not electrically connected to the emitter electrode, and are in a floating state.

[0149] Fig. 35 is a cross-sectional view taken along the line CC in Fig. 34. As shown in Fig. 35, the upper part of the diode active trench gate 61 is covered with the interlayer insulating film 4, but the outer p + The mold contact layer 24 is electrically connected to the emitter electrode 6 .

[0150] Fig. 36 is a cross-sectional view taken along the line DD in Fig. 34. As shown in Fig. 36, the diode dummy active trench gate 41 and the two diode trench gates 21 sandwiching it are covered with a continuous interlayer insulating film 4, and the p-type anode layer 41c is not applied with an emitter potential and is in a floating state.

[0151] In this way, in the diode region 20, the regions that become the diode dummy active trench gates 41 and the regions that become the diode active trench gates 61 are alternately arranged in the extension direction of the trench gates, and the trench electrodes of these trench gates are electrically connected to the gate pad 410c. In addition, the trench electrodes of these trench gates become the gate trench electrodes 11a of the active trench gates 11 in the IGBT region 10, and the active trench gates 11, the diode dummy active trench gates 41, and the diode active trench gates 61 are configured as continuous trench gates. Note that a diode semi-dummy active trench gate 51 may be provided instead of the diode dummy active trench gate 41.

[0152] <Effects> As described above, the feedback capacitance Cgc can be increased by forming the active trench gate 11 in the IGBT region 10 and the diode dummy active trench gate 41 and the diode active trench gate 61 in the diode region 20 as continuous trench gates. This is because the gate trench electrode 11a, the gate trench insulating film 11b, and the n - This is because a feedback capacitance Cgc generated by the capacitor formed in the drift layer 1 is added.

[0153] <Applicable semiconductor materials> In the above-described first to fifth embodiments, no reference is made to the constituent material of the semiconductor substrate. However, the constituent material of the semiconductor substrate may be silicon (Si) or silicon carbide (SiC).

[0154] Switching elements made of SiC have low switching loss and are capable of high-speed switching operations.

[0155] In addition, switching elements made of SiC have low power loss and high heat resistance, so when configuring a power module equipped with a cooling unit, it is possible to reduce the size of the heat dissipation fins of the heat sink, making it possible to further reduce the size of the semiconductor module.

[0156] In addition, switching elements made of SiC are suitable for high-frequency switching operations, so when they are applied to converter circuits that require higher frequencies, the increased switching frequency can also reduce the size of reactors or capacitors connected to the converter circuits.

[0157] Wide band gap semiconductors other than SiC can also be made of gallium nitride-based materials, gallium oxide-based materials, diamond, or the like.

[0158] In addition, within the scope of the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments. [Explanation of symbols]

[0159] 1n - n-type drift layer, 6 emitter electrode, 7 collector electrode, 10 IGBT region, 11 active trench gate, 16 p-type collector layer, 20 diode region, 25, 41c p-type anode layer, 26 n + a diode half dummy active trench gate; a diode active trench gate;

Claims

1. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a transistor region in which the transistor is formed; a diode region in which the diode is formed; The diode region is a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode for applying a first potential to the diode; a second main electrode for applying a second potential to the diode; at least one dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate; The at least one dummy active trench gate comprises: the third semiconductor layer is provided on at least one of the two side surfaces and is in a floating state without being supplied with the first potential; a gate potential of the transistor is applied to the at least one dummy active trench gate; a plurality of trench gates provided from a first main surface of the semiconductor substrate to reach the second semiconductor layer; the at least one dummy active trench gate is provided so as to be sandwiched between two half trench gates, the third semiconductor layer is provided between the at least one dummy active trench gate and the two half trench gates in a floating state; each of the trench gates has the third semiconductor layer to which the first potential is applied on two side surfaces thereof; the two half trench gates each have the third semiconductor layer in a floating state on one of the two side surfaces that is adjacent to the at least one dummy active trench gate, and the third semiconductor layer to which the first potential is applied on the other side; the first potential is applied to the plurality of trench gates and the two half-trench gates.

2. The at least one dummy active trench gate comprises: The semiconductor device according to claim 1 , wherein a plurality of the half-trench gates are provided between the two half-trench gates.

3. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a transistor region in which the transistor is formed; a diode region in which the diode is formed; The diode region is a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode for applying a first potential to the diode; a second main electrode for applying a second potential to the diode; at least one dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate; The at least one dummy active trench gate comprises: the third semiconductor layer is provided on at least one of the two side surfaces and is in a floating state without being supplied with the first potential; a gate potential of the transistor is applied to the at least one dummy active trench gate; The diode region is a plurality of trench gates provided from a first main surface of the semiconductor substrate to reach the second semiconductor layer; The at least one dummy active trench gate is provided as two half dummy active trench gates arranged opposite to each other, the two semi-dummy active trench gates each have the third semiconductor layer in a floating state on one of two side surfaces that is an opposing side, and have the third semiconductor layer to which the first potential is applied on the other side; each of the trench gates has the third semiconductor layer to which the first potential is applied on two side surfaces thereof; The two half dummy active trench gates are provided with a gate potential of the transistor; The first potential is applied to the trench gates.

4. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a transistor region in which the transistor is formed; a diode region in which the diode is formed; The diode region is a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode for applying a first potential to the diode; a second main electrode for applying a second potential to the diode; at least one dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate; The at least one dummy active trench gate comprises: the third semiconductor layer is provided on at least one of the two side surfaces and is in a floating state without being supplied with the first potential; a gate potential of the transistor is applied to the at least one dummy active trench gate; The diode region is a plurality of trench gates provided from a first main surface of the semiconductor substrate to reach the second semiconductor layer; the at least one dummy active trench gate is provided so as to be sandwiched between two half dummy active trench gates; the third semiconductor layer is provided between the at least one dummy active trench gate and the two half dummy active trench gates in a floating state; each of the trench gates has the third semiconductor layer to which the first potential is applied on two side surfaces thereof; each of the two semi-dummy active trench gates has the third semiconductor layer in a floating state on one of the two side surfaces that is adjacent to the at least one dummy active trench gate, and has the third semiconductor layer to which the first potential is applied on the other side; The two half dummy active trench gates are provided with a gate potential of the transistor; The first potential is applied to the trench gates.

5. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a transistor region in which the transistor is formed; a diode region in which the diode is formed; The diode region is a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode for applying a first potential to the diode; a second main electrode for applying a second potential to the diode; at least one dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate; The at least one dummy active trench gate comprises: the third semiconductor layer is provided on at least one of the two side surfaces and is in a floating state without being supplied with the first potential; a gate potential of the transistor is applied to the at least one dummy active trench gate; The diode region is a plurality of active trench gates and a plurality of trench gates provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate; the at least one dummy active trench gate is provided so as to be sandwiched between two half dummy active trench gates; the third semiconductor layer is provided between the at least one dummy active trench gate and the two half dummy active trench gates in a floating state; each of the active trench gates has the third semiconductor layer to which the first potential is applied on two side surfaces thereof; each of the two semi-dummy active trench gates has the third semiconductor layer in a floating state on one of the two side surfaces that is adjacent to the at least one dummy active trench gate, and has the third semiconductor layer to which the first potential is applied on the other side; a gate potential of the transistor is applied to the active trench gates and the two half dummy active trench gates.

6. The at least one dummy active trench gate comprises:

6. The semiconductor device according to claim 4, wherein a plurality of the half dummy active trench gates are provided between the two half dummy active trench gates.

7. The arrangement intervals of the at least one dummy active trench gate and the two half dummy active trench gates are:

6. The semiconductor device according to claim 4, wherein the distance is narrower than an arrangement interval between the plurality of trench gates.

8. 6. The semiconductor device according to claim 4, wherein the at least one dummy active trench gate branches in a direction perpendicular to the extension direction at a plurality of portions in the extension direction and is connected to the two half dummy active trench gates, and the at least one dummy active trench gate and the two half dummy active trench gates form a lattice-like planar pattern.

9. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a transistor region in which the transistor is formed; a diode region in which the diode is formed; The diode region is a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode for applying a first potential to the diode; a second main electrode for applying a second potential to the diode; at least one dummy active trench gate provided from the first main surface of the semiconductor substrate to reach the second semiconductor layer; a plurality of trench gates provided from the first main surface of the semiconductor substrate to reach the second semiconductor layer; The at least one dummy active trench gate comprises: The gate is sandwiched between two half-trench gates. the second semiconductor layer is provided between the at least one dummy active trench gate and the two half trench gates and is in a floating state without being supplied with the first potential; a gate potential of the transistor is applied to the at least one dummy active trench gate; the first potential is applied to the plurality of trench gates and the two half-trench gates.

10. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a transistor region in which the transistor is formed; a diode region in which the diode is formed; The diode region is a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode for applying a first potential to the diode; a second main electrode for applying a second potential to the diode; at least one dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate; The at least one dummy active trench gate comprises: the third semiconductor layer is provided on at least one of the two side surfaces and is in a floating state without being supplied with the first potential; a gate potential of the transistor is applied to the at least one dummy active trench gate; the transistor regions and the diode regions are alternately arranged in an extension direction of the trench gate; the trench gate is provided to penetrate the transistor region and the diode region in a plan view, The at least one dummy active trench gate comprises: a second semiconductor layer provided in the transistor region from the first main surface of the semiconductor substrate and continuous with an active trench gate to which a gate potential of the transistor is applied.

11. A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate, The semiconductor substrate is a transistor region in which the transistor is formed; a diode region in which the diode is formed; The diode region is a first semiconductor layer of a first conductivity type provided on a second main surface side of the semiconductor substrate; a second semiconductor layer of a first conductivity type provided on the first semiconductor layer; a third semiconductor layer of a second conductivity type provided closer to the first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode for applying a first potential to the diode; a second main electrode for applying a second potential to the diode; at least one dummy active trench gate provided so as to reach the second semiconductor layer from the first main surface of the semiconductor substrate; The at least one dummy active trench gate comprises: the third semiconductor layer is provided on at least one of the two side surfaces and is in a floating state without being supplied with the first potential; a gate potential of the transistor is applied to the at least one dummy active trench gate; the transistor regions and the diode regions are alternately arranged in an extension direction of the trench gate; the trench gate is provided to penetrate the transistor region and the diode region in a plan view, The diode region is a region in which the at least one dummy active trench gate is provided; a region in which at least one active trench gate is provided, the active trench gate being provided so as to extend from the first main surface of the semiconductor substrate to the second semiconductor layer; The at least one dummy active trench gate and the at least one active trench gate include: a second semiconductor layer provided in the transistor region from the first main surface of the semiconductor substrate and continuous with an active trench gate to which a gate potential of the transistor is applied.

12. The semiconductor substrate is 12. The semiconductor device according to claim 1, wherein the semiconductor device is made of a material selected from the group consisting of silicon, silicon carbide, a gallium nitride material, a gallium oxide material, and diamond.

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