Fine tuning for programming analog neural memories in deep learning artificial neural networks

Abstract

To provide a precision tuning algorithm and a device for precisely and quickly depositing a correct amount of charge on a floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network.SOLUTION: A method includes the steps of: programming all cells to a "0" state in a simultaneous program operation (3302); erasing all cells to an intermediate weak erase level in a soft erase operation (3303); executing a hard program to add electrons to floating gates of cells to a very deep programmed state in all non-selection cells (3304); executing a coarse programming method (bringing a cell fairly close to a target) on the selected cell (3305); then, executing a precision programming method on the selected cell (3306); and programming each selected cell with the desired precise value.SELECTED DRAWING: Figure 33A

Description

[Technical field]

[0001] (Priority Claim) This application claims priority to U.S. patent application Ser. No. 16 / 576,533, filed Sep. 19, 2019, and entitled “PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK.”

[0002] FIELD OF THEINVENTION Numerous embodiments are disclosed for a precision-tuned algorithm and apparatus for precisely and rapidly depositing precise amounts of charge onto the floating gates of non-volatile memory cells in vector matrix multiplication (VMM) arrays in artificial neural networks. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain), and are used to estimate or approximate functions that may depend on multiple inputs and are generally unknown. Artificial neural networks generally contain layers of interconnected "neurons" that exchange messages.

[0004] FIG. 1 shows an artificial neural network, where the circles represent layers of inputs or neurons. The connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There is typically one or more intermediate layers of neurons, and an output layer of neurons that provides the output of the neural network. At each level, the neurons make decisions, either individually or together, based on the data they receive from the synapses.

[0005] One of the main challenges in the development of artificial neural networks for high-performance information processing is the lack of suitable hardware technologies. In practice, practical neural networks rely on a very large number of synapses, which allows high connectivity between neurons, i.e., a very high degree of parallelization of computation. In principle, such complexity can be achieved by digital supercomputers or dedicated GPU (Graphics Processing Unit) clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency compared to biological networks, which mainly perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used for artificial neural networks, but most CMOS-implemented synapses are too bulky given the large number of neurons and synapses.

[0006] Applicant previously disclosed an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application Serial No. 15 / 594,439, which is incorporated by reference. The non-volatile memory array operates as an analog neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each memory cell including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed above and insulated from a first portion of the channel region, and a non-floating gate disposed above and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate the first plurality of outputs.

[0007] Each non-volatile memory cell used in an analog neuromorphic memory system must hold a very specific and precise amount of charge, i.e., number of electrons, in its floating gate in response to erasure and programming. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be exhibited by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0008] One challenge in a VMM system is the ability to program selected cells with the precision and granularity required for different values ​​of N. For example, if a selected cell can contain one of 64 different values, then extremely high precision is required in the program operation.

[0009] What is needed is an improved programming system and method suitable for use with a VMM in an analog neuromorphic memory system. Summary of the Invention

[0010] Numerous embodiments are disclosed of precision-tuned algorithms and apparatus for precisely and rapidly depositing precise amounts of charge onto the floating gates of non-volatile memory cells in vector matrix multiplication (VMM) arrays in artificial neural networks, such that selected cells can be programmed with extremely high precision to hold one of N different values.

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[0068] [Brief description of the drawings]

[0069] [Figure 1] FIG. 1 illustrates a prior art artificial neural network. [Diagram 2] 1 shows a prior art split-gate flash memory cell. [Diagram 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Diagram 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] 1 illustrates another prior art split-gate flash memory cell. [Figure 7] 1 shows a prior art stacked gate flash memory cell. [Figure 8] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 9] FIG. 1 is a block diagram illustrating a vector matrix multiplication system. [Figure 10] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more vector-matrix multiplication systems. [Figure 11] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 12] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 13] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 14] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 15] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 16] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 17] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 18]4 illustrates another embodiment of a vector matrix multiplication system. [Figure 19] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 20] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 21] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 22] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 23] 4 illustrates another embodiment of a vector matrix multiplication system. [Figure 24] 4 illustrates another embodiment of a vector matrix multiplication system. [Diagram 25] 1 shows a prior art long-short-term memory system. [Figure 26] An exemplary cell for use in the long- and short-term memory system is shown. [Figure 27] 27 illustrates an embodiment of the exemplary cell of FIG. 26. [Figure 28] 27 illustrates another embodiment of the exemplary cell of FIG. 26. [Figure 29] 1 shows a prior art gated recurrent unit system. [Diagram 30] 1 shows an exemplary cell for use in a gated recurrent unit system. [Diagram 31] 31 illustrates an embodiment of the exemplary cell of FIG. 30. [Diagram 32] 31 illustrates another embodiment of the exemplary cell of FIG. 30. [Figure 33A] 1 illustrates one embodiment of a method for programming a non-volatile memory cell. [Figure 33B] 1 illustrates another embodiment of a method for programming a non-volatile memory cell. [Diagram 34] 1 illustrates one embodiment of a coarse programming method. [Diagram 35] 3 illustrates exemplary pulses used in programming non-volatile memory cells. [Diagram 36] 3 illustrates exemplary pulses used in programming non-volatile memory cells. [Figure 37] 1 illustrates a calibration algorithm for programming non-volatile memory cells that adjusts programming parameters based on the tilt characteristics of the cell. [Figure 38] 38 shows the circuit used in the calibration algorithm of FIG. 37. [Figure 39] 1 illustrates a calibration algorithm for programming non-volatile memory cells. [Diagram 40] 1 illustrates a calibration algorithm for programming non-volatile memory cells. [Diagram 41] 41 shows the circuit used in the calibration algorithm of FIG. 40. [Diagram 42] 4 illustrates an exemplary progression of voltages applied to the control gates of non-volatile memory cells during a programming operation. [Diagram 43] 4 illustrates an exemplary progression of voltages applied to the control gates of non-volatile memory cells during a programming operation. [Diagram 44] 1 illustrates a system for applying programming voltages during programming of non-volatile memory cells in a vector multiplication matrix system. [Diagram 45] 1 shows a vector multiplication matrix system having a modulator, an analog-to-digital converter, and an output block including a summer. [Diagram 46] 1 shows a charge adder circuit. [Figure 47] 2 shows a current adder circuit. [Figure 48] 1 shows a digital adder circuit. [Figure 49A] 1 illustrates one embodiment of an integrated analog-to-digital converter for neuron outputs. [Figure 49B] 49B shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter of FIG. 49A. [Figure 49C] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 49D] 49D shows a graph illustrating the voltage output over time of the integrating analog-to-digital converter of FIG. 49C. [Figure 49E]13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Fig.49F] 13 shows another embodiment of an integrating analog-to-digital converter for neuron outputs. [Figure 50A] 1 shows a successive approximation analog-to-digital converter for neuron outputs. [Figure 50B] 1 shows a successive approximation analog-to-digital converter for neuron outputs. [Figure 51] 1 illustrates an embodiment of a sigma-delta analog-to-digital converter. [Figure 52A] 1 illustrates an embodiment of a ramp-type analog-to-digital converter. [Figure 52B] 1 illustrates an embodiment of a ramp-type analog-to-digital converter. [Figure 52C] 1 illustrates an embodiment of a ramp-type analog-to-digital converter. [Figure 53] 1 illustrates an embodiment of an algorithmic analog-to-digital converter. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0070] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays. [Non-volatile memory cell]

[0071] Digital non-volatile memories are well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A wordline terminal 22 (typically coupled to a wordline) has a first portion disposed above and insulated from (and controls the conductivity of) the second portion of the channel region 18, and a second portion extending upwardly over the floating gate 20. The floating gate 20 and wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline terminal 24 is coupled to the drain region 16.

[0072] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the wordline terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim tunneling from the floating gate 20 to the wordline terminal 22 through the insulator between them.

[0073] The memory cell 210 is programmed (electrons are applied to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. An electron current flows from the source region 14 (source line terminal) towards the drain region 16. The electrons accelerate and are heated when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0074] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and the word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on and current flows through the channel region 18, which is sensed as the erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off and no (or very little) current flows through the channel region 18, which is sensed as the programmed or "0" state.

[0075] Table 1 shows typical voltage ranges that may be applied to the terminals of memory cell 110 to perform read, erase, and program operations. Table 1: Operation of the Flash Memory Cell 210 of FIG. 2 [Table 1] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0076] Figure 3 shows a memory cell 310 similar to memory cell 210 of Figure 2 with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, a low or negative voltage (e.g., 0v / -8V) during erasure, and a low or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are biased similarly to those of Figure 2.

[0077] FIG. 4 shows a four-gate memory cell 410 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, i.e., they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0078] Table 2 shows typical voltage ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 2: Operation of Flash Memory Cell 410 of FIG. [Table 2] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0079] Figure 5 shows a memory cell 510 similar to memory cell 410 of Figure 4, except that memory cell 510 does not include an erase gate (EG) terminal. Erasing is accomplished by biasing the substrate 18 to a high voltage and the control gate CG terminal 28 to a low or negative voltage. Alternatively, erasure is accomplished by biasing the word line terminal 22 to a positive voltage and the control gate terminal 28 to a negative voltage. Programming and reading are similar to those of Figure 4.

[0080] Figure 6 shows another type of flash memory cell, a three-gate memory cell 610. Memory cell 610 is identical to memory cell 410 of Figure 4, except that memory cell 610 does not have a separate control gate terminal. Erase and read operations (where erasure occurs through the use of the erase gate terminal) are similar to those of Figure 4, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage must be applied to the source line terminal during a program operation to compensate for the lack of control gate bias.

[0081] Table 3 shows typical voltage ranges that may be applied to the terminals of memory cell 610 to perform read, erase, and program operations. Table 3: Operation of Flash Memory Cell 610 of FIG. [Table 3] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output to the source line terminal.

[0082] Figure 7 shows another type of flash memory cell, a stacked gate memory cell 710. Memory cell 710 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate terminal 22 (coupled to a wordline) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, programming, and read operations operate in a similar manner as previously described for memory cell 210.

[0083] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 710 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of Flash Memory Cell 710 of FIG. [Table 4]

[0084] "Read 1" is a read mode in which the cell current is output to the bit line. "Read 2" is a read mode in which the cell current is output at the source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, a source line may be coupled to one row of memory cells or to two adjacent rows of memory cells. That is, a source line terminal may be shared by adjacent rows of memory cells.

[0085] In order to utilize a memory array containing one of the non-volatile memory cell types in an artificial neural network as described above, two modifications are made: First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array; Second, a continuous (analog) programming of the memory cells is provided.

[0086] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is analog, or can at a minimum store one of many discrete values ​​(such as 16 or 64 different values), making every cell in the memory array very precisely and individually adjustable, and making the memory array ideal for storing and fine-tuning the weights of the synapses of a neural network.

[0087] The methods and means described herein can be applied to other non-volatile memory technologies, such as, but not limited to, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive RAM), PCM (phase change RAM), MRAM (magnetoresistive RAM), FeRAM (ferroelectric RAM), OTP (bi-level or multi-level one-time programmable) and CeRAM (strongly correlated electron RAM). The methods and means described herein can be applied to, but not limited to, volatile memory technologies used in neural networks, such as SRAM, DRAM, and other volatile synapse cells. [Neural network using non-volatile memory cell array]

[0088] 8 conceptually illustrates a non-limiting example of a neural network utilizing the non-volatile memory array of the present embodiments. This example uses the non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using the non-volatile memory array-based neural network.

[0089] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel being 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping filters (kernels) of 3x3 pixels, applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of the nine pixels in the 3x3 portion of the image (i.e., called filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights, and after summing the outputs of the multiplications, a single output value is determined and given by the first synapse of CB1 to generate one pixel of the layer of feature map C1. The 3x3 filter is then shifted one pixel to the right in the input layer S0 (i.e., add a column of 3 pixels to the right and drop a column of 3 pixels on the left), so that the 9 pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter scans the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps of C1, until all feature maps of layer C1 have been calculated.

[0090] In this example, in layer C1, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input with a kernel, and thus each feature map is a two-dimensional array, and thus in this example layer C1 constitutes 16 layers of two-dimensional arrays (note that layers and arrays referred to herein are logical, not necessarily physical, i.e., arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, etc.

[0091] From layer C1, an activation function P1 (pooling) is applied before going to layer S1, which pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. The purpose of the pooling function is to average nearby positions (or a max function can be used), e.g. to reduce edge position dependency, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e. 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. From layer C2, an activation function P2 (pooling) is applied before going to layer S2, which pools values ​​from non-overlapping, consecutive 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where all neurons in layer C3 connect to all maps in layer S2 through respective synapses in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e. all neurons in layer C3 connect to all neurons in layer S3. The output at S3 contains 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0092] Each layer of synapses is implemented using an array or part of an array of non-volatile memory cells.

[0093] Figure 9 is a block diagram of a system that can be used for this purpose. A vector matrix multiplication (VMM) system 32 includes non-volatile memory cells and is used to control the synapses (Fig. 8In particular, the VMM system 32 includes a VMM array 33 including non-volatile memory cells arranged in rows and columns, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode respective inputs to the non-volatile memory cell array 33. Inputs to the VMM array 33 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 can decode the output of the VMM array 33.

[0094] The VMM array 33 serves two purposes. First, it stores the weights used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs by the weights stored in the VMM array 33 and sums them for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic and is also power efficient with on-the-fly memory computations.

[0095] The outputs of the VMM array 33 are fed to a differential summer (such as a summing op-amp or summing current mirror) 38, which sums the outputs of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive and negative weight inputs to output a single value.

[0096] The summed output values ​​of the differential summer 38 are then fed to an activation function circuit 39 which rectifies the output. The activation function circuit 39 may provide a sigmoid function, a tanh function, a ReLU function, or any other non-linear function. The rectified output values ​​of the activation function circuit 39 become elements of the feature map of the next layer (e.g., C1 in FIG. 8) and are then applied to the next synapse to generate the next feature map layer or the last layer. Thus, in this example, the VMM array 33 constitutes a number of synapses (which receive input from a previous layer of neurons or from an input layer such as an image database), and the summer 38 and the activation function circuit 39 constitute a number of neurons.

[0097] The inputs to the VMM system 32 of FIG. 9 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to appropriate input analog levels) or digital bits (in which case a DAC is provided to convert the digital bits to appropriate input analog levels), and the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0098] FIG. 10 is a block diagram illustrating the use of multiple layers of the VMM system 32, labeled in the figure as VMM systems 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, an input (denoted Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first layer input D / A conversion can be done by using a function or a LUT (look-up table) that maps the input Inputx to an appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be done by an analog-to-analog (A / A) converter to convert an external analog input to a mapped analog input to the input VMM system 32a. The input conversion can also be done by a digital-to-digital pulse (D / P) converter to convert an external digital input to a mapped digital pulse(s) to the input VMM system 32a.

[0099] The output generated by the input VMM system 32a is then provided as an input to the next VMM system (hidden level 1) 32b, which in turn generates an output that is provided as an input to the input VMM system (hidden level 2) 32c, and so on. The various layers of the VMM systems 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can be a standalone physical system that includes a corresponding non-volatile memory array, or the multiple VMM systems can utilize different portions of the same physical non-volatile memory array, or the multiple VMM systems can utilize overlapping portions of the same physical non-volatile memory array. Each of the VMM systems 32a, 32b, 32c, 32d, and 32e can also be time multiplexed to various portions of its array or neurons. The example shown in Figure 10 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example and that the system may instead include more than two hidden layers and more than two fully connected layers. [VMM Array]

[0100] Figure 11 shows a neuron VMM array 1100 that is particularly suited for memory cells 310 shown in Figure 3 and is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of non-volatile memory cells and a reference array 1102 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array could be located at the bottom.

[0101] In the VMM array 1100, control gate lines such as control gate line 1103 run vertically (so that row-wise reference array 1102 is orthogonal to control gate line 1103) and erase gate lines such as erase gate line 1104 run horizontally. Here, inputs to the VMM array 1100 are provided on the control gate lines (CG0, CG1, CG2, CG3) and outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current applied to each source line (SL0, SL1, respectively) performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0102] As described herein for neural networks, the non-volatile memory cells of VMM array 1100, ie, the flash memory of VMM array 1100, are preferably configured to operate in the sub-threshold region.

[0103] The non-volatile reference memory cells and non-volatile memory cells described herein are biased in weak inversion as follows: Ids=Io * e (Vg-Vth) / nVt =w * Io * e (Vg) / nVt In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, and Vt is the thermal voltage=k * where k is the Boltzmann constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), where Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is (Wt / L) * u * Cox * (n-1) * Vt 2where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0104] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io] where wp is the w of the reference or periphery memory cell.

[0105] When using an IV log converter that converts the input current Ids to an input voltage Vg using a memory cell (such as a reference memory cell or a peripheral memory cell) or transistor: Vg=n * Vt * log[Ids / wp * Io]

[0106] where wp is the w of the reference or periphery memory cell.

[0107] For a memory array used as a vector matrix multiplier VMM array, the output current is: Iout=wa * Io * e (Vg) / nVt , i.e. Iout = (wa / wp) * Iin=W * Iin W=e (Vthp-Vtha) / nVt Iin=wp * Io * e (Vg) / nVt where wa=w for each memory cell in the memory array.

[0108] The word line or control gate can be used as the input of the memory cell for an input voltage.

[0109] Alternatively, the non-volatile memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=β * (Vgs-Vth) * Vds; β=u * Cox * Wt / L W α (Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0110] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0111] For an IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region, or resistors can be used to linearly convert input and output currents to input and output voltages.

[0112] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2 * β * (Vgs-Vth) 2 ; β=u * Cox * Wt / L W α (Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0113] The word lines, control gates, or erase gates can be used as inputs for memory cells operating in the saturation region, and the bit lines or source lines can be used as outputs for output neurons.

[0114] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (sub-threshold, linear, or saturation).

[0115] Other embodiments for the VMM array 33 of Figure 9 are described in U.S. Patent Application Serial No. 15 / 826,345, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0116] FIG. 12 shows a neuron VMM array 1200 that is particularly suitable for the memory cells 210 shown in FIG. 2 and used as synapses between an input layer and the next layer. The VMM array 1200 includes a memory array 1203 of non-volatile memory cells, a reference array 1201 of a first non-volatile reference memory cell, and a reference array 1202 of a second non-volatile reference memory cell. The reference arrays 1201 and 1202 arranged in the columns of the array serve to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1214 (only some of which are shown) with current inputs flowing into them. The reference cells are adjusted (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0117] The memory array 1203 serves two purposes. First, it stores the weights used by the VMM array 1200 in each memory cell. Second, it effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert to input voltages and provide to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which are the inputs to the next layer or the last layer. With the memory array 1203 performing the multiplication and addition functions, the need for separate multiplication and addition logic is eliminated and is also power efficient. Here, voltage inputs are provided to word lines WL0, WL1, WL2, and WL3, and outputs appear on bit lines BL0-BLN, respectively, during read (inference) operations. The current placed on each bit line BL0-BLN performs a function of the sum of the currents from all the non-volatile memory cells connected to that particular bit line.

[0118] Table 5 shows the operating voltages for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells, and FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations. Table 5: Operation of VMM Array 1200 in FIG. 12 [Table 5]

[0119] FIG. 13 illustrates a neuron VMM array 1300 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as part of synapses and neurons between an input layer and the next layer. The VMM array 1300 includes a memory array 1303 of non-volatile memory cells, a reference array 1301 of first non-volatile reference memory cells, and a reference array 1302 of second non-volatile reference memory cells. The reference arrays 1301 and 1302 run in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that the word lines run vertically in the VMM array 1300. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3) and outputs appear on the source lines (SL0, SL1) during a read operation. The current applied to each source line performs a function of the sum of all the currents from the memory cells connected to that particular source line.

[0120] Table 6 shows the operating voltages for VMM array 1300. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cells, the bit lines of the unselected cells, the source lines of the selected cells, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 6: Operation of VMM Array 1300 in FIG. 13 [Table 6]

[0121] 14 shows a neuron VMM array 1400 that is particularly suited for the memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between the input layer and the next layer. The VMM array 1400 includes a memory array 1403 of non-volatile memory cells, a reference array 1401 of a first non-volatile reference memory cell, and a reference array 1402 of a second non-volatile reference memory cell. The reference arrays 1401 and 1402 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 to voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second non-volatile reference memory cells are diode-connected through a multiplexer 1412 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. The multiplexers 1412 each include a respective multiplexer 1405 and cascoding transistor 1404 to ensure a constant voltage on the bit line (e.g., BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are adjusted to a target reference level.

[0122] Memory array 1403 serves two purposes. First, it stores the weights used by VMM array 1400. Second, it stores the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3) that reference arrays 1401 and 1402 convert to input voltages to supply to the control gates (CG0, CG1, CG2, and CG3). ) are effectively multiplied by weights stored in the memory cell array, and then all the results (cell currents) are added together to produce an output that appears on BL0-BLN and serves as the input to the next layer or the input to the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current applied to each bit line performs a function of the sum of all the currents from the memory cells connected to that particular bit line.

[0123] The VMM array 1400 performs one-way conditioning of the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be done, for example, using the precision programming techniques described below. If too much charge is added to the floating gate (such as an incorrect value being stored in the cell), the cell must be erased and the series of partial programming operations must be redone. As shown, two rows that share the same erase gate (such as EG0 or EG1) must be erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0124] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 7: Operation of VMM Array 1400 in FIG. 14 [Table 7]

[0125] FIG. 15 shows a neuron VMM array 1500 that is particularly suited for memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between an input layer and the next layer. The VMM array 1500 includes a memory array 1503 of non-volatile memory cells and , No. 1 non-volatile reference memory cell Reference Array 1501and a second reference array 1502 of non-volatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 run vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 run horizontally. VMM array 1500 is similar to VMM array 1400, except that VMM array 1500 implements bidirectional tuning, whereby each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of individual EG lines. As shown, reference arrays 1501 and 1502 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1514), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0-BLN, each of which sums up all the currents from the non-volatile memory cells connected to that particular bit line.

[0126] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table show the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector than the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows show the read, erase, and program operations. Table 8: Operation of VMM Array 1500 in FIG. 15 [Table 8]

[0127] 16 shows a neuron VMM array 1600 that is particularly suited for memory cells 210 shown in FIG. 2 and is used as part of synapses and neurons between an input layer and the next layer. In the VMM array 1600, inputs INPUT0, ..., INPUT Nare bit lines BL0, ..., BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0128] 17 illustrates a neuron VMM array 1700 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0129] 18 illustrates a neuron VMM array 1800 that is particularly suited for memory cells 210 shown in FIG. 2 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M are received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0130] 19 shows a neuron VMM array 1900 that is particularly suited for memory cells 310 shown in FIG. 3 and is used as part of synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M are received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N is generated.

[0131] 20 shows a neuron VMM array 2000 that is particularly suited for the memory cells 410 shown in FIG. 4 and is used as part of the synapses and neurons between the input layer and the next layer. In this example, the input INPUT 0、 ..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0132] 21 shows a neuron VMM array 2100 that is particularly suited for memory cells 410 shown in FIG. 4 and is used as part of synapses and neurons between an input layer and the next layer. In this example, inputs INPUT0, ..., INPUT N are bit lines BL0, ..., BL N , 2901-(N-1) and 2901-N, which are coupled to the source lines SL0 and SL1, respectively. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0133] 22 shows a neuron VMM array 2200 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received at OUTPUT0, ..., OUTPUT N are bit lines BL0, ..., BL N are generated respectively.

[0134] 23 shows a neuron VMM array 2300 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT Mare the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0135] 24 shows a neuron VMM array 2400 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. [Long and short-term memory]

[0136] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any predefined period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell, and the period of time that information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0137] FIG. 25 illustrates an exemplary LSTM 2500. The LSTM 2500 in this example includes cells 2501, 2502, 2503, and 2504. Cell 2501 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 2502 receives an input vector x1, an output vector (hidden state) h0 from cell 2501, and a cell state c0 from cell 2501, and generates an output vector h1 and a cell state vector c1. Cell 2503 receives an input vector x2, an output vector (hidden state) h1 from cell 2502, and a cell state c1 from cell 2502, and generates an output vector h2 and a cell state vector c2. Cell 2504 receives an input vector x3, an output vector (hidden state) h2 from cell 2503, and a cell state c2 from cell 2503, and generates an output vector h3. Additional cells can be used, the LSTM with four cells is just an example.

[0138] Figure 26 shows an example implementation of an LSTM cell 2600 that can be used for cells 2501, 2502, 2503, and 2504 in Figure 25. LSTM cell 2600 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0139] LSTM cell 2600 includes sigmoid function devices 2601, 2602, and 2603, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 2600 also includes tanh devices 2604 and 2605 for applying a hyperbolic tangent function to the input vector, multiplier devices 2606, 2607, and 2608 for multiplying two vectors, and adder device 2609 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0140] 27 shows an example implementation of LSTM cell 2600, LSTM cell 2700. For the convenience of the reader, the same numbering scheme from LSTM cell 2600 is used in LSTM cell 2700. Sigmoid function devices 2601, 2602, and 2603, and tanh device 2604 each include multiple VMM arrays 2701 and activation circuit blocks 2702. It can therefore be seen that VMM arrays are particularly useful in LSTM cells used in certain neural network systems.

[0141] An alternative example of LSTM cell 2700 (and another example of an implementation of LSTM cell 2600) is shown in Figure 28. In Figure 28, sigmoid function devices 2601, 2602, and 2603, and tanh device 2604 may share the same physical hardware (VMM array 2801 and activation function block 2802) in a time-multiplexed manner. LSTM cell 2800 also includes a multiplier device 2803 for multiplying two vectors, an adder device 2808 for adding two vectors, a tanh device 2605 (including activation circuit block 2802), a register 2807 for storing the value i(t) output from sigmoid function block 2802, and a value f(t) output from multiplier device 2803 via multiplexer 2810. * A register 2804 stores c(t-1), and a value i(t) output from the multiplier device 2803 via a multiplexer 2810. * A register 2805 stores u(t) and a value o(t) output from the multiplier device 2803 via a multiplexer 2810. * It includes a register 2806 that stores {tilde over (c)}(t), and a multiplexer 2809.

[0142] Whereas LSTM cell 2700 includes multiple sets of VMM arrays 2701 and respective activation function blocks 2702, LSTM cell 2800 includes only one set of VMM arrays 2801 and activation function blocks 2802, which are used to represent multiple layers in embodiments of LSTM cell 2800. LSTM cell 2800 requires less space than LSTM cell 2700, as it requires ¼ the space for the VMMs and activation function blocks compared to LSTM cell 2700.

[0143] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as an adder and activation circuit block and a high voltage generation block. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself. [Gated Recurrent Unit]

[0144] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are a gating mechanism in recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0145] 29 illustrates an exemplary GRU 2900. The GRU 2900 in this example includes cells 2901, 2902, 2903, and 2904. Cell 2901 receives input vector x0 and generates output vector h0. Cell 2902 receives input vector x1 and output vector h0 from cell 2901 and generates output vector h1. Cell 2903 receives input vector x2 and output vector (hidden state) h1 from cell 2902 and generates output vector h2. Cell 2904 receives input vector x3 and output vector (hidden state) h2 from cell 2903 and generates output vector h3. Additional cells may be used, and a GRU with four cells is merely an example.

[0146] FIG. 30 illustrates an exemplary implementation of a GRU cell 3000 that can be used for cells 2901, 2902, 2903, and 2904 of FIG. 29. The GRU cell 3000 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). The GRU cell 3000 includes sigmoid function devices 3001 and 3002, each of which applies a number between 0 and 1 to the output vector h(t-1) and the components from the input vector x(t). The GRU cell 3000 also includes a tanh device 3003 for applying a hyperbolic tangent function to the input vector, a number of multiplier devices 3004, 3005, and 3006 for multiplying two vectors, an adder device 3007 for adding the two vectors, and a complementary device 3008 for subtracting the input from 1 to generate an output.

[0147] Figure 31 shows GRU cell 3100, which is one implementation of GRU cell 3000. For the convenience of the reader, the same numbering scheme from GRU cell 3000 is used in GRU cell 3100. As can be seen from Figure 31, sigmoid function devices 3001 and 3002 and tanh device 3003 each include multiple VMM arrays 3101 and activation function blocks 3102. It can therefore be seen that VMM arrays are particularly used in GRU cells used in certain neural network systems.

[0148] An alternative example of GRU cell 3100 (and another example of an implementation of GRU cell 3000) is shown in Figure 32. In Figure 32, GRU cell 3200 uses a VMM array 3201 and activation function block 3202, which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much each component of the input vector contributes to the output vector. In Figure 32, sigmoid function devices 3001 and 3002 and tanh device 3003 share the same physical hardware (VMM array 3201 and activation function block 3202) in a time-multiplexed manner. The GRU cell 3200 also includes a multiplier device 3203 for multiplying two vectors together, an adder device 3205 for adding the two vectors together, a complementary device 3209 for subtracting an input from one to generate an output, a multiplexer 3204, and a value h(t-1) output from the multiplier device 3203 via the multiplexer 3204. * A register 3206 holds r(t) and a value h(t-1) output from the multiplier device 3203 via a multiplexer 3204. * A register 3207 holds z(t), and a value h^(t) output from the multiplier device 3203 via a multiplexer 3204. * and a register 3208 that holds (1-z((t)).

[0149] Whereas GRU cell 3100 includes multiple sets of VMM arrays 3101 and activation function blocks 3102, GRU cell 3200 includes only one set of VMM arrays 3201 and activation function blocks 3202 that are used to represent multiple tiers in embodiments of GRU cell 3200. GRU cell 3200 requires less space than GRU cell 3100 because it requires ⅓ the space for the VMM and activation function blocks compared to GRU cell 3100.

[0150] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation circuit blocks and high voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Thus, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0151] The input to the VMM array can be analog levels, binary levels, timing pulses, or digital bits, and the output can be analog levels, binary levels, timing pulses, or digital bits (in this case an output ADC is required to convert the output analog level current or voltage to digital bits).

[0152] For each memory cell in the VMM array, each weight w can be implemented by a single memory cell, by a differential cell, or by two blended memory cells (an average of two or more cells). In the case of a differential cell, two memory cells are required to implement weight w as a differential weight (w=w+-w-). In the case of two blended memory cells, two memory cells are required to implement weight w as an average of two cells. [Embodiments for precision programming of cells in a VMM]

[0153] FIG. 33A illustrates a programming method 3300. Initially, the method begins (step 3301), typically in response to a program command received. Next, a mass program operation programs all cells to a "0" state (step 3302). Then, a soft erase operation erases all cells to an intermediate weak erase level (step 3303), such that each cell draws, for example, about 3-5 μA of current during a read operation. This is in contrast to a deeply erased level, where each cell draws about 20-30 μA of current during a read operation. Then, a hard program is performed (step 3304) on all unselected cells, adding electrons to the floating gates of the cells to a very deep programmed state, ensuring that those cells are truly "off", i.e., they draw a negligible amount of current during a read operation.

[0154] A coarse programming method (bringing the cells fairly close to the target, e.g., 2x to 100x the target) is then performed on the selected cells (step 3305), followed by a fine programming method being performed on the selected cells (step 3306) to program the desired precise value into each selected cell.

[0155] FIG. 33B illustrates another programming method 3310 similar to programming method 3300. However, after the method begins (step 3301), instead of a program operation to program all cells to a "0" state as in step 3302 of FIG. 33A, an erase operation is used to erase all cells to a "1" state (step 3312). A soft program operation (step 3313) is then used to program all cells to an intermediate state (level) such that each cell draws approximately 3-5 uA of current during a read operation. This is followed by the coarse and fine programming methods as in FIG. 33A. A variation of the embodiment of FIG. 33B removes the soft programming method (step 3313) entirely.

[0156] 34 illustrates a first embodiment of the coarse programming method 3305, which is a lookup and execution method 3400. First, a lookup table lookup is performed to find the coarse target current value (I CT ) based on the value intended to be stored in the selected cell (step 3401). This table may be created, for example, by silicon characterization or from wafer test calibration. Let us assume that the selected cell can be programmed to store one of N possible values ​​(e.g., 128, 64, 32, etc.). Each of the N values ​​represents a different desired current value (I D In one embodiment, the lookup table may correspond to a coarse target current value I for a cell selected during the search and execution method 3400. CT , where M is an integer less than N. For example, if N is 8, then M may be 4, meaning there are 8 possible values ​​that the selected cell can store, and one of the four coarse target current values ​​will be selected as the coarse target for the search and perform method 3400. That is, the search and perform method 3400 (which is again an embodiment of the coarse programming method 3305) programs the selected cell to store a desired value (I D ) somewhat close to the value (I CT ) and then the precision programming method 3306 programs the desired value (I D The intention is to more precisely program the selected cells so that they are very close to the

[0157] Examples of cell values, desired current values, and coarse target current values ​​are shown in Tables 9 and 10 for a simple example of N=8 and M=4. Table 9: Example of N desired current values ​​for N=8 [Table 9] Table 10: Example of M target current values ​​for M=4 [Table 10] Offset value I CTOFFSETx is used to prevent overshooting the desired current value during coarse adjustment.

[0158] Rough target current value I CT Once selected, the selected cell is programmed (step 3402) by applying a voltage v0 to the appropriate terminal of the selected cell based on the cell architecture type of the selected cell (e.g., memory cell 210, 310, 410, or 510). If the selected cell is the type of memory cell 310 of FIG. 3, then a voltage v0 is applied to control gate terminal 28, and v0 is programmed to the coarse target current value I CT The value of v0 can be 5-7 V depending on the coarse target current value I CT This can be determined from a voltage lookup table that stores v0 corresponding to

[0159] The selected cell is then connected to the i =v i-1 +v increment where i starts at 1 and increments each time this step is repeated, and v increment is a small, weak voltage that causes programming to a degree commensurate with the granularity of the desired change (step 3403). Thus, the first time step 3403 is performed at i=1, where v is v0+v increment A verify operation is then performed (step 3404), in which a read operation is performed on the selected cell and the current drawn through the selected cell (I cell ) is measured. I cell I CT If so, the search and execute method 3400 is complete and the precision programming method 3306 can begin. cell I CT If not, step 3403 is repeated and i is incremented.

[0160] Thus, at the point where the coarse programming method 3305 ends and the fine programming method 3306 begins, the voltage v i is the final voltage used to program the selected cell, and the selected cell is programmed to the coarse target current value I CT The goal of the fine programming method 3306 is to program the selected cell so that during a read operation the selected cell flows a current I D The goal is to program the current to a point where the selected cell will pull (plus or minus an acceptable amount of deviation, such as + / - 50pA or + / - 30% or less), where this current is the desired current value associated with the value intended to be stored in the selected cell.

[0161] FIG. 35 shows examples of different voltage progressions that may be applied to the control gates of selected memory cells during the coarse and / or fine programming method 3306.

[0162] Under the first approach, to further program the selected memory cell, an increasing voltage is applied to the control gate, starting at v i which is the last voltage applied during the coarse programming method 3305. p1 is applied to v1, and then the voltage v1+v p1 is used to program the selected cell (indicated by the second pulse from the left in progression 3501). p1 v increment (the voltage increment used during the coarse programming method 3305). After each programming voltage is applied, Icell PT1 A verification step (similar to step 3404) is performed in which it is determined whether I is less than or equal to (the first precision target current value, here the second threshold value). PT1 =I D +I PT1OFFSET and I PT1OFFSET is an offset value that is added to prevent program overshoot. If the answer is no, another increment v p1is added to the previously applied programming voltage and the process is repeated. cell I PT1 This portion of the programming sequence stops at some point below. PT1 I D or with sufficient precision, D If it is approximately equal to , the selected memory cell has been successfully programmed.

[0163] I PT1 I D If the voltage is not close enough to V, then further programming with smaller granularity can be done. Here, progression 3502 is used. The starting point of progression 3502 is the last voltage used for programming under progression 3501. The increment V p2 (v p1 (which is less than I) is applied to that voltage, and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, I cell I PT2 A verification step (similar to step 3404) is performed in which it is determined whether I is less than or equal to (a second precision target current value, here a third threshold value). PT2 =ID+I PT2OFFSET and I PT2OFFSET is an offset value added to prevent program overshoot. If the answer is no, another increment V p2 is added to the previously applied programming voltage and the process is repeated. cell I PT2 At some point below this portion of the programming sequence stops, since the target value has now been achieved with sufficient accuracy. PT2 I D or until programming can stop. D It is assumed that the 1601, 1602, and 1603 progressions are sufficiently close to the 1601, 1602, and 1603 progressions. Those skilled in the art will appreciate that additional progressions may be applied using smaller and smaller programming increments. For example, in Figure 36, three progressions (3601, 3602, and 3603) are applied instead of just two.

[0164] A second approach is shown in progression 3503. Here, instead of increasing the voltage applied during programming of a selected memory cell, the same voltage is applied for increasing periods of time duration. p1 and progress 350 2 in v p2 Instead of applying incremental voltages such as t, each applied pulse is t slower than the previous applied pulse. p1 Add an additional time increment t p1 is applied to the programming pulse. After each programming pulse is applied, the same verification steps are performed as described above for progression 3501. Optionally, additional progressions can be applied, where the additional time increments added to the programming pulse are of shorter duration than the previous progression used. Although only one temporal progression is shown, one skilled in the art will understand that any number of different temporal progressions may be applied.

[0165] Further details are now provided for three further embodiments of the coarse programming method 3305.

[0166] 37 shows a first embodiment of the coarse programming method 3305, which is an adaptive calibration method 3700. The method starts (step 3701). The cell is programmed with a default starting value v0 (step 3702). Unlike the search and execute method 3400, v0 here is not obtained from a lookup table, but can instead be a relatively small initial value. The control gate voltage of the cell is measured at a first current value IR1 (e.g., 100 na) and a second current value IR2 (e.g., 10 na), and the subthreshold slope is determined (e.g., 360 mV / dec) and stored based on those measurements (step 3703).

[0167] The new desired voltage v iThe first time this step is performed, i=1, and v1 is determined based on the stored subthreshold slope values ​​and current target and offset values, for example, using a subthreshold equation such as: V i =V i-1 +V increment , V increment is proportional to the slope of Vg Vg=n * Vt * log[Ids / wa * Io] where wa is the w of the memory cell and Ids is the current target plus an offset value.

[0168] If the stored slope value is relatively steep, a relatively small current offset value can be used. If the stored slope value is relatively flat, a relatively high current offset value can be used. Thus, determining the slope information allows a current offset value to be selected that is customized for the particular cell in question. This ultimately makes the programming process shorter. As this step is repeated, i is incremented and v is incremented. i =v i-1 +v increment The cell is then programmed using vi. increment corresponds to the target current value v increment The value of can be determined from a look-up table that stores values ​​of

[0169] A read operation is then performed on the selected cell, and the current drawn through the selected cell (I cell ) is measured and a verification operation is performed (step 3705). cell I CT (here, the crude target threshold value) is less than or equal to (I CT =I D +I CTOFFSET and I CTOFFSETis an offset value added to prevent program overshoot), the adaptive calibration method 3700 is completed, and the precision programming method 33 06 may be started. cell I CT If not, steps 3704-3705 are repeated and i is incremented.

[0170] FIG. 38 illustrates an aspect of an adaptive calibration method 3700. Step 3 7 During 03, a current source 3801 is used to apply exemplary current values ​​IR1 and IR2 to a selected cell (here memory cell 3802), and then the voltage at the control gate of memory cell 3802 (CGR1 for IR1 and CGR2 for IR2) is measured. The slope is (CGR2-CGR1) / dec.

[0171] 39 shows a second embodiment of a programming method 3305, which is an adaptive calibration method 3900. The method starts (step 3901). The cell is programmed with a default starting value, V0 (step 3902). V0 is obtained from a lookup table, such as one created from silicon characterization, and the table values ​​are offset so as not to overshoot the programmed target.

[0172] In the next step 3903, an IV slope parameter is created that is used to predict the next programming voltage, V CGR1 is applied to the selected cell and the resulting cell current IR1 is measured. Then, a second control gate read voltage V CGR2 is applied to a selected cell and the resulting cell current IR2 is measured. A slope is determined based on those measurements and stored, for example, according to the following equation in the subthreshold region (cells operating at subthreshold): Slope=(V CGR1 -V CGR2 ) / (LOG(IR1)-LOG(IR2)) (Step 3903). CGR1 and VCGR2 Example values ​​for are 1.5V and 1.3V, respectively.

[0173] Determining the slope information is customized to the particular cell in question. increment This allows values ​​to be selected quickly, which ultimately makes the programming process shorter.

[0174] Step 3904 is repeated, incrementing i to obtain the new desired programming voltage V i is determined based on the stored slope values ​​and the current target and offset values ​​using the following equation: V i =V i-1 +V increment In the formula, in the case of i-1, V increment = α * Tilt * (LOG(IR1)-LOG(I CT )) and I CT is the target current, and α is a predetermined constant <1 (programming offset value), e.g., 0.9, to prevent overshoot. For example, Vi is the programming voltage of VSLP or VCGP, the source line or control gate.

[0175] The cell is then programmed using Vi. (Step 3904)

[0176] A read operation is then performed on the selected cell, and the current drawn through the selected cell (I cell ) is measured and a verification operation is performed (step 3906). cell I CT (here, the crude target threshold value) is less than or equal to (I CT =I D +I CTOFFSET and I CTOFFSET is an offset value added to prevent program overshoot), the process proceeds to step 3907.4 and i is incremented.

[0177] In step 3907, I cell I CT Less than the threshold value CT2 The purpose is to see if an overshoot has occurred. cell I CT It is to be less than cell I CT If it is much lower than I, then overshoot has occurred and the stored value may actually correspond to an incorrect value. cell I CT2 If not, then no overshoot has occurred and the adaptive calibration method 3900 is complete, at which point the process proceeds to the precision programming method 3306. cell I CT2 If so, then an overshoot has occurred. In that case, the selected cell is erased (step 3908) and the programming process resumes at step 3902. Optionally, if step 3908 is performed more than a predetermined number of times, the selected cell may be considered a bad cell that should not be used.

[0178] The precision program method 3306 consists of multiple verify and program cycles where the pulse width is fixed and the program voltage is incremented by a constant fine voltage to the next pulse, or the program voltage is fixed and the program pulse width is varied or constant.

[0179] Optionally, determining whether the current through the selected non-volatile memory cell during a read or verify operation is less than or equal to the first threshold current value may be performed by applying a fixed bias to a terminal of the non-volatile memory cell, measuring and digitizing the current drawn by the selected non-volatile memory cell to generate a digital output bit, and comparing the digital output bit to a digital bit representative of the first threshold current.。

[0180] duty Optionally, the step of determining whether the current passing through the selected non-volatile memory cell during a read or verify operation is below the first threshold current value may be performed by applying an input to a terminal of the non-volatile memory cell, modulating the current drawn by the selected non-volatile memory cell with an output pulse to generate a modulated output, digitizing the modulated output to generate a digital output bit, and comparing the digital output bit to a digital bit representing the first threshold current.

[0181] FIG. 40 shows a third embodiment of the programming method 3305, which is an absolute calibration method 4000. The method starts (step 4001). The cell is programmed with a default starting value V0 (step 4002). The control gate voltage of the cell (VCGRx) is measured and stored at a current value Itarget (step 4003). A new desired voltage v1 is determined based on the stored control gate voltage and the current target and offset values ​​Ioffset+Itarget (step 4004). For example, the new desired voltage v1 can be calculated as follows: v1=v0+(VCGBIAS-stored VCGR), where VCGBIAS=~1.5V, which is the default read control gate voltage at the maximum target current, and the stored VCGR is the measured read control gate voltage of step 4003.

[0182] The cell then i When i=1, the voltage v1 from step 4004 is used. When i>=2, the voltage v i =v i-1 +V increment is used. increment corresponds to the target current value v increment A read operation is then performed on the selected cell, and the current drawn through the selected cell (I cell) is measured and a verification operation is performed (step 4006). cell I CT If so, the absolute calibration method 4000 is complete and the fine programming method 3306 can begin. cell I CT If not, steps 4005-4006 are repeated and i is incremented.

[0183] FIG. 41 shows a circuit 4100 for implementing step 4003 of the absolute calibration method 4000. A voltage source (not shown) generates a VCGR, which starts at an initial voltage and rises. Here, n + 1 different current sources 4101 (4101-0, 4101-1, 4101-2,..., 4101-n) generate different currents IO0, IO1, IO2,... IOn with increasing magnitudes. Each current source 4101 is connected to an inverter 4102 (4102-0, 4102-1, 4102-2,..., 4102-n) and a memory cell 4103 (4103-0, 4103-1, 4103-2,... 4103-n). As the VCGR rises, each memory cell 4103 draws an increasing amount of current, and the input voltage to each inverter 4102 decreases. Since IO0 < IO1 < IO2 <... < IOn, as the VCGR rises, first the output of inverter 4102-0 switches from low to high. Next, the output of inverter 4102-1 switches from low to high, then the output of inverter 4102-2 switches in the same way, and so on until the output of inverter 4102-n switches from low to high. Each inverter 4102 controls a switch 4104 (4104-0, 4104-1, 4104-2,..., 4104-n), such that when the output of the inverter 4102 is high, the switch 4104 is closed, whereby the VCGR is sampled by the capacitor 4105 (4105-0, 4105-1, 4105-2,..., 4105-n). Thus, the switches 4104 and the capacitors 4105 form a sample-and-hold circuit. The values of IO0, IO1, IO2,... IOn are used as possible values of Itarget, and each sampled voltage is used as the associated value VCGRx in the absolute calibration method 4000 of FIG. 40. Graph 4106 shows the VCGR rising over time, as well as the outputs of inverters 4102-0, 4102-1, and 4102-n switching from low to high at various times.

[0184] FIG. 42 shows an exemplary progression 4200 for programming selected cells during the adaptive calibration method 3700 or the absolute calibration method 4000. In one embodiment, a voltage Vcgp is applied to the control gates of memory cells of a selected row. The number of selected memory cells in the selected row is, for example, 32. Thus, up to 32 memory cells in the selected row can be programmed in parallel. Each memory cell is enabled to couple to a programming current Iprog by a bit line enable signal. When the bit line enable signal is inactive (meaning a positive voltage is applied to the selected bit line), the memory cell is in an inhibit (not programmed) state. As shown in FIG. 42, the bit line enable signal En_blx (x varies from 1 to n, where n is the number of bit lines) is enabled at different times with the Vcgp voltage level desired for that bit line (and therefore for the selected memory on said bit line). In another embodiment, the voltage applied to the control gates of the selected cells can be controlled using an enable signal on the bit line. Each bit line enable signal applies a desired voltage (such as vi in ​​FIG. 40) corresponding to that bit line as Vcgp. The bit line enable signal can also control the programming current flowing into the bit line. In this example, each subsequent control gate voltage Vcgp is higher than its previous voltage. Alternatively, each subsequent control gate voltage may be lower or higher than its previous voltage. Each subsequent increment of Vcgp may be either equal or unequal to its previous increment.

[0185] FIG. 43 shows an exemplary progression 4300 for programming a selected cell during the adaptive calibration method 3700 or the absolute calibration method 4000. In one embodiment, the bit line enable signal enables the selected bit line (meaning the selected memory cell in said bit line) to be programmed with the corresponding Vcgp voltage level. In another embodiment, the voltage applied to the control gate of the selected cell that performs the incremental ramp can be controlled using the bit line enable signal. Each bit line enable signal applies a desired voltage (such as vi in ​​FIG. 40) corresponding to that bit line to the control gate voltage. In this example, each subsequent increment is equal to the previous increment.

[0186] FIG. 44 shows a system for implementing an input and output method for reading or verifying in a VMM array. An input function circuit 4401 receives digital bit values ​​and converts them into analog signals to be used to apply voltages to the control gates of selected cells in the array 4404, as determined via a control gate decoder 4402. At the same time, a word line decoder 4403 is also used to select the row in which the selected cell is located. An output neuron circuit block 4405 performs the output function of each column (neuron) of cells in the array 4404. The output circuit block 4405 can be implemented using an integrating analog-to-digital converter (ADC), a successive approximation register (SAR) ADC, a sigma-delta ADC, or any other ADC scheme.

[0187] In one embodiment, the digital value provided to the input function circuit 4401 includes four exemplary bits (DIN3, DIN2, DIN1, and DIN0), with various bit values ​​corresponding to different numbers of input pulses applied to the control gate. The greater the number of pulses, the greater the output value (current) of the cell. Example bit and pulse values ​​are shown in Table 11. Table 11: Digital bit input and number of generated pulses [Table 11]

[0188] In the above example, there are up to 15 pulses for the 4-bit digital value to read the cell value. Each pulse is equal to one unit of cell value (current). For example, if Icell unit = 1nA, then DIN[3~0] = 0001, Icell = 1 * 1nA=1nA, and for DIN[3~0]=1111, Icell=15 * 1nA=15nA.

[0189] In another embodiment, the digital bit input uses digital bit position summation to read out the cell or neuron (e.g., the value of the bit line output) value, as shown in Table 12. Here, only four pulses or four fixed identical bias inputs (e.g., the word line or control gate inputs) are needed to evaluate the four-bit digital value. For example, a first pulse or a first fixed bias is used to evaluate DIN0, a second pulse or a second fixed bias having the same value as the first value is used to evaluate DIN1, a third pulse or a third fixed bias having the same value as the first value is used to evaluate DIN2, and a fourth pulse or a fourth fixed bias having the same value as the first value is used to evaluate DIN3. Then, the results from the four pulses are added, with each output result multiplied (scaled) by a multiplication coefficient that is 2^n (n is the digital bit position), as shown in Table 13. The digital bit summation formula that is realized is the following: Output=2^0 * DIN0+2^1 * DIN1+2^2 * DIN2+2^3 * DIN3) * In Icell units.

[0190] For example, if Icell unit = 1nA, DIN[3~0] = 0001, Icell total = 0+0+0+1 * 1nA=1nA, and for DIN[3~0]=1111, Icell total=8 * 1nA+4 * 1nA+2 * 1nA+1* 1nA=26nA. Table 12: Digital bit input summation [Table 12] Table 13: Summation of digital input bits Dn and 2^n output multiplication coefficient [Table 13]

[0191] Another embodiment using a hybrid input with multiple digital input pulse ranges and sum of input digital ranges is shown in Table 14 for an exemplary 4-bit digital input. In this embodiment, DINn-0 can be divided into m different groups, each group is evaluated, and the output is scaled by a multiplication factor by the binary position of the group. For example, for a 4-bit DIN3-0, the groups could be DIN3-2 and DIN1-0, with the output of DIN1-0 scaled by 1 (X1) and the output of DIN3-2 scaled by 4 (X4). Table 14: Summation of Hybrid Inputs and Outputs with Multiple Input Ranges [Table 14]

[0192] Another embodiment combines a hybrid input range with a hybrid supercell. A hybrid supercell includes multiple physical x-bit cells to implement a logical n-bit cell with the x-cell output scaled by 2^n binary positions. For example, two 4-bit cells (cell 1, cell 0) are used to implement an 8-bit logical cell. The output of cell 0 is scaled by 1 (X1) and the output of cell 1 is scaled by 4 (X, 2^2). Other combinations of physical x-cells to implement an n-bit logical cell are possible, such as two 2-bit physical cells and one 4-bit physical cell to implement an 8-bit logical cell.

[0193] FIG. 45 illustrates a digital bit input using digital bit position summation to read out a cell or neuron (e.g., the value of the bit line output) current modulated by a modulator 4510 with an output pulse width designed according to the digital input bit position (e.g., converting the current into an output voltage (V=Current * 45 shows another embodiment similar to the system of FIG. 44 except for a bias (applied to an input such as a word line or control gate) for converting a current (cell or neuron) output to a pulse width proportional to the DIN0 bit position, which is in units of 1 (x1), a second input bias for evaluating DIN1, and a current output modulated by modulator 4510 with a pulse width proportional to the DIN1 bit position, which is in units of 2 (x2), a third input bias for evaluating DIN2, and a current output modulated by modulator 4510 with a pulse width proportional to the DIN2 bit position, which is in units of 4 (x4), and a fourth input bias for evaluating DIN3, and a current output modulated by modulator 4510 with a pulse width proportional to the DIN3 bit position, which is in units of 8 (x8). Each converted voltage is then converted to a digital bit for each digital input bit by ADC (Analog-to-Digital Converter) 4511. The total output is then output by adder 4512 as the sum of the four digital outputs generated from the DIN0-3 inputs.

[0194] FIG. 46 shows an example of a charge adder 4600 that can be used to sum the outputs of the VMM during a verification operation or during analog-to-digital conversion of the output neurons to obtain a single analog value representing the output, which can then be optionally converted to a digital bit value. The charge adder 4600 can be used, for example, as the adder 4512. The charge adder 4600 includes a current source 4601 and a sample and hold circuit including a switch 4602 and a sample and hold (S / H) capacitor 4603. As shown in the example of a 4-bit digital value, there are four S / H circuits to hold values ​​from the four evaluation pulses, which are summed at the end of the process. The S / H capacitor 4603 is connected to the 2^nth of the S / H capacitor. * The current sources 4601 are also scaled accordingly.

[0195] 47 shows a current adder 4700 that can be used to sum the outputs of the VMM during a verification operation or analog-to-digital conversion of the output neurons. The current adder 4700 includes a current source 4701, a switch 4702, a switch 4703 and a switch 4704, and a switch 4705. As shown in the example of a 4-bit digital value, there is a current source circuit to hold the values ​​from the four evaluation pulses, and these values ​​are summed at the end of the process. The current source has a current of 2^n * A ratio is multiplied based on the DINn bit position, for example, I_DIN3=x8 Icell units, I_DIN2=x4 Icell units, I_DIN1=x2 Icell units, I_DIN0=x1 Icell unit.

[0196] FIG. 48 shows a digital adder 4800 that receives multiple digital values, sums them together, and generates an output DOUT that represents the sum of the inputs. The digital adder 4800 can be used during a validation operation or during analog-to-digital conversion of an output neuron. As shown in the example of a four-bit digital value, there are digital output bits to hold the values ​​from the four evaluation pulses, which are summed at the end of the process. The digital output is a sum of 2^n * It is digitally scaled based on the DINn bit position, e.g., DOUT3=x8 DOUT0, _DOUT2=x4 DOUT1, I_DOUT1=x2 DOUT0, I_DOUT0=DOUT0.

[0197] FIG. 49A shows a dual slope integrating ADC 4900 applied to an output neuron to convert the cell current to a digital output bit. An integrator consisting of an integrating opamp 4901 and an integrating capacitor 4902 integrates the cell current ICELL against a reference current IREF. As shown in FIG. 49B, for a fixed time t1, the cell current is integrated upwards (Vout rises) and then a reference current is applied such that it is integrated downwards (Vout falls) over a time t2. The current Icell is given by:=t2 / t1 * For example, for t1, with a digital bit resolution of 10 bits, 1024 cycles are used, and the number of cycles for t2 varies from 0 to 1024 cycles depending on the Icell value.

[0198] FIG. 49C shows a single slope integrating ADC 4960 applied to the output neuron to convert the cell current to a digital output bit. An integrator consisting of an integrating opamp 4961 and an integrating capacitor 4962 integrates the cell current ICELL. As shown in FIG. 49D, during time t1, the cell current is integrated upwards (Vout rises until it reaches Vref2), and during time t2, another cell current is integrated upwards. Cell current Icell=Cint *Vref2 / t. A pulse counter is used to count the number of pulses (digital output bits) during the integration time t. For example, as shown, the digital output bits for t1 are less than the digital output bits for t2, which means that the cell current during t1 is greater than the cell current during t2 integration. An initial calibration is performed to calibrate the integration capacitor value with a reference current and fixed time, Cint=Tref * Iref / Vref2.

[0199] FIG. 49E shows a dual slope integrating ADC 4980 applied to the output neuron to convert the cell current to a digital output bit. The dual slope integrating ADC 4980 does not utilize an integrating op-amp. The cell current or a reference current is directly integrated on a capacitor 4982. A pulse counter is used to count the pulses (digital output bits) during the integration time. The current Icell is given by: =t2 / t1 * It is an IREF.

[0200] FIG. 49F shows a single slope integrating ADC 4990 applied to the output neuron to convert the cell current to a digital output bit. The single slope integrating ADC 4980 does not utilize an integrating opamp. The cell current is directly integrated on a capacitor 4992. A pulse counter is used to count the pulses (digital output bits) during the integration time. Cell current Icell=Cint * Vref2 / t.

[0201] FIG. 50A shows a SAR (successive approximation) ADC applied to the output neuron to convert the cell current to a digital output bit. The cell current can be dropped through a resistor and converted to a VCELL. Alternatively, the cell current can be charged up a S / H capacitor and converted to a VCELL. A binary search is used to calculate the bits starting from the MSB bit (most significant bit). A DAC 5002 is used to set the appropriate analog reference voltage to the comparator 5003 based on the digital bit from the SAR 5001. The output of the comparator 5003 is fed back to the SAR 5001 in order to select the next analog level. As shown in FIG. 50B, in the example of a 4-bit digital output bit, there are four evaluation periods, a first pulse to evaluate DOUT3 by setting the analog level to the middle, then a second pulse to evaluate DOUT2 by setting the analog level to the middle of the upper half or the middle of the lower half, and so on.

[0202] Modified binary search such as cyclic (algorithmic) ADCs can be used for cell tuning (e.g., programming) verification or output neuron conversion. Modified binary search such as switched-cap (SC) charge redistribution ADCs can be used for cell tuning (e.g., programming) verification or output neuron conversion.

[0203] Figure 51 shows a sigma-delta ADC 5100 applied to an output neuron to convert the cell current to a digital output bit. An integrator consisting of an opamp 5101 and a capacitor 5105 integrates the sum of the current from the selected cell current and a reference current provided by a 1-bit current DAC 5104. A comparator 5102 compares the integrated output voltage against a reference voltage. A clocked DFF 5103 provides a digital output stream according to the output of the comparator 5102. The digital output stream typically goes to a digital filter before being output to a digital output bit.

[0204] FIG. 52A shows a ramp-type analog-to-digital converter 5200 including a current source 5201 (representing the received neuron current Ineu), a switch 5202, a variable configurable capacitor 5203, and a comparator 5204 that receives a voltage denoted Vneu across the variable configurable capacitor 5203 as a non-inverting input, a configurable reference voltage Vreframp as an inverting input, and generates an output Cout. Vreframp is ramped up at discrete levels every comparison clock cycle. The comparator 5204 compares Vneu with Vreframp, resulting in an output Cout that is "1" when Vneu>Vreframp and "0" otherwise. Thus, the output Cout is a pulse whose width varies in response to Ineu. The larger Ineu is, the longer the period during which Cout is "1", resulting in a wider pulse width at the output Cout. A digital counter 5220 converts each pulse at the output Cout into a digital output bit as shown in FIG. 52B for two different Ineu currents, marked OT1A and OT2A, respectively. Alternatively, the ramp voltage Vreframp is a continuous ramp voltage 5255 as shown in graph 5250 of FIG. 52B. A multiple ramp embodiment is shown in FIG. 52C to reduce the conversion time by utilizing a coarse-fine ramp conversion algorithm. A first coarse reference ramp reference voltage 5271 is ramped quickly to obtain each Ineu subrange. Then, a fine reference ramp reference voltage 5272 for each subrange, Vreframp1 and Vreframp2, respectively, is used to convert the Ineu current in the corresponding subrange. As shown, there are two subranges of the fine reference ramp voltage. More than one coarse / fine step or two subranges are possible.

[0205] FIG. 53 shows an algorithmic analog-to-digital output converter 5300 including a switch 5301, a switch 5302, a sample-and-hold (S / H) circuit 5303, a 1-bit analog-to-digital converter (ADC) 5304, a 1-bit digital-to-analog converter (DAC) 5305, a summer 5306, and a gain of 2 residue operational amplifier (2x opamp) 5307. The algorithmic analog-to-digital output converter 5300 generates a converted digital output 5308 in response to an analog input Vin and control signals applied to switches 5302 and 5303. An input received at the analog input Vin (e.g., Vneu in FIG. 52) is first sampled in the S / H circuit 5303 by the switch 5302, and then a conversion is performed in N clock cycles for N bits. For each conversion clock cycle, the 1-bit ADC 5304 compares the S / H voltage 5309 with a reference voltage (e.g., VREF / 2, where VREF is the full-scale voltage of N bits) and outputs a digital bit (e.g., “0” if input<=VREF / 2, and “1” if input>VREF / 2). This digital bit, which is the digital output signal 5308, is then converted to an analog voltage (e.g., either VREF / 2 or 0V) by the 1-bit DAC 5305 and fed to the summer 5306 to be subtracted from the S / H voltage 5309. The 2× residue opamp 5307 then amplifies the summer difference voltage output to a converted residue voltage 5310, which is fed to the S / H circuit 5303 via the switch 5301 for the next clock cycle. Instead of this 1-bit (i.e., 2-level) algorithmic ADC, a 1.5-bit (i.e., 3-level) algorithmic ADC can be used to reduce the effects of offsets from ADC 5304 and residual opamp 5307, etc. A 1.5-bit algorithmic ADC requires a 1.5-bit or 2-bit (i.e., 4-level) DAC.

[0206] In another embodiment, a hybrid ADC can be used, for example for a 9-bit ADC, the first 4 bits can be generated by a SAR ADC and the remaining 5 bits can be generated using a gradient or ramp ADC.

[0207] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly on" (with no intermediate material, element, or gap disposed between them) and "indirectly on" (with an intermediate material, element, or gap disposed between them). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed between them) and "indirectly adjacent" (with an intermediate material, element, or gap disposed between them), "attached" includes "directly attached" (with no intermediate material, element, or gap disposed between them) and "indirectly attached to" (with an intermediate material, element, or gap disposed between them), and "electrically coupled" includes "directly electrically coupled" (without an intermediate material or element disposed between them that electrically connects the elements together) and "indirectly electrically coupled to" (with an intermediate material or element disposed between them that electrically connects the elements together). For example, forming an element "above a substrate" can include forming the element directly on the substrate, with no intermediate materials / elements between them, and forming the element indirectly on the substrate, with one or more intermediate materials / elements between them.

Claims

1. 1. A method for performing a read or verify operation in a vector matrix multiplication system including an input function circuit, a memory array, and an output circuit block, comprising: receiving, by the input function circuit, a digital bit input value; converting the digital bit input value into an input signal; applying the input signal to control gate terminals of selected cells in the memory array; generating, by the output circuit block, an output value in response to a current received from the memory array; 11. A method according to claim 10, wherein the output value comprises an output component corresponding to a respective bit position in the digital bit input value, each output component being multiplied by a coefficient proportional to the corresponding bit position in the digital bit input value.

2. The method of claim 1 , wherein the output value comprises a set of digital bits.

3. The method of claim 1 , wherein the coefficient is 1 for a first bit position of the digital bit input value.

4. The method of claim 1 , wherein the coefficient is 2 for a second bit position of the digital bit input value.

5. The coefficient is 2 for the nth bit position of the digital bit input value. n The method of claim 1, wherein

6. The method of claim 1 , wherein the input signal is an analog voltage.

7. The method of claim 1 , wherein the input signal comprises one or more digital pulses.

8. The method of claim 1 , wherein the output circuit block includes an integrated analog-to-digital converter.

9. The method of claim 1 , wherein the output circuit block includes a successive approximation analog-to-digital converter.

10. The method of claim 1 , wherein the output circuit block comprises a sigma-delta analog-to-digital converter.

11. 1. A method for performing a read or verify operation in a vector matrix multiplication system including an input function circuit, a memory array, and an output circuit block, comprising: receiving, by the input function circuit, a set of digital input bits; for each digital input bit in the set of digital input bits, converting the digital input bits into an input signal; applying the input signal to a terminal of a selected cell in the memory array; and modulating an output current of a bit line coupled to the selected cell with a pulse width proportional to a bit position of the digital input bit to generate an output voltage.

12. 12. The method of claim 11, further comprising converting the output voltage to a set of digital output bits by an analog-to-digital converter.

13. 13. The method of claim 12, further comprising summing the set of digital output bits generated for the set of digital input bits to generate a digital output.

14. The method of claim 11 , wherein each input signal is a voltage.

15. The method of claim 11 , wherein each input signal comprises one or more digital pulses.

16. The method of claim 12 , wherein the analog-to-digital converter comprises an integrated analog-to-digital converter.

17. The method of claim 12 , wherein the analog-to-digital converter comprises a successive approximation analog-to-digital converter.

18. the analog-to-digital converter comprises a sigma-delta analog-to-digital converter; The method of claim 12.

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