MEMORY CONTROLLER AND ASSOCIATED SYSTEM AND METHOD FOR NON-INTERFERENTIAL ACCESS TO NON-VOLATILE MEMORY BY MULTIPLE DIFFERENT MASTERS - Patent application

Abstract

The apparatus may include a plurality of processing sources and a multiplexer (MUX) configured to assign read requests from the plurality of processing sources to predetermined time division multiplexed (TDM) command slots. A memory controller may generate nonvolatile memory (NVM) commands and address data on a unidirectional command address bus from the read requests received from the MUX during the TDM command slots assigned to the read requests. The address data may include at least a bank address. The apparatus may also receive read data on a unidirectional parallel data bus synchronously with rising and falling edges of a received data clock. The read data may be received in TDM read slots having a predetermined order. A demultiplexer may provide the read data of each TDM read slot to one of the plurality of processing sources in a predetermined order based on the position of the TDM read slot. Related methods and systems are also disclosed.

Description

[Technical field]

[0001] Related Applications This application is an international application of U.S. Provisional Patent Application No. 16 / 719,465, filed December 18, 2019, which claims the benefit of U.S. Provisional Patent Application No. 62 / 883,019, filed August 5, 2019, the contents of both of which are incorporated herein by reference in their entireties.

[0002] Technical Field The present disclosure relates generally to systems having multiple master devices and processes accessing the same non-volatile memory device. [Background technology]

[0003] Many control systems may include multiple processes (e.g., cores), each controlling a different subsystem. Often, such processes desire to access nonvolatile memory (NVM) devices. NVM devices can ensure that important data is stored even in the absence of power. For example, an automobile may include a controller with multiple processor cores, each core dedicated to one particular system or function. The processor cores can read data from and store data to a corresponding NVM device.

[0004] A drawback of conventional systems would be latency. When multiple processes compete for the same NVM device, some arbitration process must be employed to prioritize access. Without such arbitration, conflicts can occur between different processes, which can result in unpredictable latency in access or reduced performance as one process interrupts other processes that have priority access requests.

[0005] One way to address such variable latency in accessing NVM devices may be to increase the number of NVM devices, with some NVM devices dedicated to specific processes. While such an approach can guarantee latency for some processes, it can significantly increase the cost and size of the resulting system. [Brief description of the drawings]

[0006] [Figure 1A] FIG. 2 illustrates time division multiplex (TDM) access to a non-volatile memory (NVM) device by a processor device, according to embodiments. [Figure 1B] FIG. 2 illustrates time division multiplex (TDM) access to a non-volatile memory (NVM) device by a processor device, according to embodiments. [Diagram 2] FIG. 1 is a block diagram of a system according to one embodiment. [Figure 3A] 4 is a table illustrating TDM slot and bank allocations for a processor unit according to embodiments. [Figure 3B] 4 is a table illustrating TDM slot and bank allocations for a processor unit according to embodiments. [Figure 4A] FIG. 11 is a diagram showing data access times according to each embodiment. [Figure 4B] FIG. 11 is a diagram showing data access times according to each embodiment. [Figure 5A] 1A-1C are diagrams illustrating examples of bank allocations to multiple processing cores of a processor device according to embodiments. [Figure 5B] 1A-1C are diagrams illustrating examples of bank allocations to multiple processing cores of a processor device according to embodiments. [Figure 5C] 1A-1C are diagrams illustrating examples of bank allocations to multiple processing cores of a processor device according to embodiments. [Figure 6A]FIG. 1 is a timing diagram illustrating NVM access by a processor unit according to embodiments. [Figure 6B] FIG. 1 is a timing diagram illustrating NVM access by a processor unit according to embodiments. [Figure 7] 1 is a table illustrating various configurations of a processor device according to embodiments. [Figure 8A] 1A-1D are diagrams illustrating processor accesses according to different embodiments. [Figure 8B] 1A-1D are diagrams illustrating processor accesses according to different embodiments. [Figure 8C] 1A-1D are diagrams illustrating processor accesses according to different embodiments. [Figure 8D] 1A-1D are diagrams illustrating processor accesses according to different embodiments. [Figure 9] 11 is a table showing data access performance of the processor device according to each embodiment. [Figure 10] 1 is a flowchart of a method according to one embodiment. [Figure 11] FIG. 1 is a diagram illustrating an automobile control system according to each embodiment. [Figure 12A] FIG. 13 illustrates a read command that may be included in each embodiment. [Figure 12B] FIG. 13 illustrates a read command that may be included in each embodiment. [Figure 13] FIG. 2 is a block diagram of an NVM device that may be included in embodiments. [Figure 14] FIG. 1 is a diagram of an automobile system according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] According to embodiments, the controller device may include multiple processing circuits (e.g., cores). Each processing circuit may issue requests to access a bank of the NVM device. Such access requests may be assigned slots in a time division multiplexed (TDM) configuration. The memory controller circuit may then issue these requests in TDM order as command address values ​​over a command address bus to the NVM device. In the case of a read request, the read data may subsequently be received on a unidirectional double data rate (DDR) data bus in a similar TDM manner. The read data received within a particular TDM slot may correspond to the process that issued the request.

[0008] In some embodiments, each process may be assigned at least one NVM bank of the NVM device, and the process only accesses the NVM bank assigned to it.

[0009] In some embodiments, each process may be assigned to no more than two NVM banks of the NVM device.

[0010] In some embodiments, if a process accesses an NVM bank in one TDM slot, another process cannot access the same NVM bank in the immediately following TDM slot.

[0011] In some embodiments, the controller device can access the NVM device through a parallel memory interface. The parallel memory interface can be compatible with the LPDDR4 standard promulgated by JEDEC.

[0012] In the various embodiments that follow, like items are referred to by the same reference numerals except that the first digit corresponds to the number of the figures.

[0013] 1A and 1B are block diagrams illustrating a processor device 100 and operation according to various embodiments. The processor device 100 may include multiple processing cores 102-0 to 102-3, a multiplexer (MUX) 104, a demultiplexer (DMUX) 106, core allocation data 107-0, TDM allocation data 107-1, and a parallel DDR memory controller 108. The cores (102-0 to 102-3) may each include processing circuitry that may be dedicated for a separate processing task. According to various embodiments, the cores (102-0 to 102-3) may be assigned to one or more NVM banks (not shown) of a corresponding NVM device 112. Thus, once a core (102-0 to 102-3) is assigned to an NVM bank, that core will not require access to a bank that is not assigned to it. Although four cores are illustrated in FIG. 1A / FIG. 1B, the processor device may have more or fewer cores.

[0014] MUX 104 can receive access requests from the cores (102-0 to 102-3) and assign these access requests to predefined TDM command slots in the TDM configuration. According to embodiments, a core (102-0 to 102-3) can be assigned to more than one TDM command slot, but multiple cores (102-0 to 102-3) cannot be assigned to the same TDM command slot. The TDM command configuration can be cycled through in a predefined order. In some embodiments, if an access request is received at MUX 104 before the correct TDM command slot, MUX 104 can wait to service the request until the appropriate time slot. Furthermore, if there is no access request for a given TDM command slot, MUX 104 cannot issue the request.

[0015] MUX 104 may take any suitable form. MUX 104 may include dedicated circuitry, such as a data buffer, that receives access requests, stores them in locations corresponding to TDM command slots, and then outputs them at the appropriate time. However, MUX 104 may also be a coordinated process running on each core (102-0 to 102-3). Each core (102-0 to 102-3) restricts access requests to its own dedicated TDM slot. These are just two examples and should not be considered limiting. Those skilled in the art will appreciate that various other MUX configurations may occur to them.

[0016] The DMUX 106 may take any suitable form. As with the MUX 104, the DMUX 106 may also include dedicated circuitry, such as a data buffer, that receives the read data and stores the read data in locations corresponding to the TDM slots. Such read data may then be read by a corresponding core (102-0 to 102-3). Alternatively, the cores (102-0 to 102-3) may coordinate multiple accesses to read data to read only data in their assigned TDM read slots.

[0017] The core allocation data 107-0 may record which NVM banks are assigned to which cores (102-0 to 102-3). The core allocation data 107-0 may be stored in memory circuitry of the processor device 100, including configuration registers. In the particular embodiment shown, core 0 is assigned to both NVM banks 0 and 1, core 1 is assigned to NVM bank 1, core 2 is assigned to NVM bank 2, and core 3 is assigned to NVM banks 2 and 3. The TDM allocation data 107-1 may record which cores have which TDM command slots. The TDM allocation data 107-1 may be stored in memory circuitry of the processor device 100, including configuration registers. In the particular embodiment shown, core 3 is assigned to TDM slot 0, core 0 is assigned to TDM slot 1, core 2 is assigned to TDM slot 2, and core 1 is assigned to TDM slot 3. Although FIGS. 1A / 1B illustrate four TDM slots, other embodiments may include a different number of TDM slots, as will be shown below.

[0018] Memory controller circuit 108 may include controller circuitry for accessing banks of NVM devices 112. According to embodiments, memory controller circuit 108 may issue command and address data as a sequence of parallel bits over command address bus 110. Read data may be received in the form of sets of parallel bits over unidirectional read data bus 114. Such read data may be received in groups (e.g., bursts) synchronous with falling and rising edges of a data clock.

[0019] FIG. 1A illustrates an example of the initiation of a read operation according to one embodiment.

[0020] As shown in circle 1, the cores (102-0 through 102-3) can issue read requests to the various banks. In the example of FIG. 1A, core 102-0 issues a read request to NVM bank 0, core 102-1 issues a read request to NVM bank 1, core 102-2 issues a read request to NVM bank 2, and core 102-3 issues a read request to NVM bank 3. Such requests are appropriate because they comply with core allocation data 107-0. The various read requests can occur at different times and in different orders.

[0021] As shown in circle 2, MUX 104 can order requests issued by the cores (102-0 to 102-3) based on TDM allocation data 107-1. Read requests can be ordered according to TDM allocation data 107-1 regardless of when these read requests were issued by the cores (102-0 to 102-3). Thus, read requests can be issued to memory controller circuit 108 in the following order: read to bank 3 (issued by core 3) (i.e., TDM slot 0); read to bank 0 (issued by core 0) (i.e., TDM slot 1); read to bank 2 (issued by core 2) (i.e., TDM slot 2); read to bank 1 (issued by core 1) (i.e., TDM slot 3).

[0022] As shown in circle 3, the memory controller circuit 108 can generate the appropriate command and address data on the command address bus 110 in the assigned TDM slot.

[0023] FIG. 1B illustrates the completion of the read operation shown in FIG. 1A according to one embodiment.

[0024] As shown in circle 4, in response to commands and address data issued by processor device 100, NVM device 112 may output the resulting read data in the order in which the commands and address data were received. Such read data may be output in DDR format on unidirectional data bus 114.

[0025] As shown in circle 5, memory controller circuit 108 may receive data read from the NVM devices and provide it to DMUX 106. Each set of read data may be received in a TDM read slot having an order established by TDM allocation data 107-1.

[0026] As shown in circle 6, the DMUX 106 can order the read data for access by the cores (102-0 through 102-3) based on when such read data was received (i.e., the TDM read slot of the read data).

[0027] In this way, it can be ensured that different cores of the same processing unit access different banks of the same memory device via TDM read accesses and the resulting read data.

[0028] FIG. 2 is a block diagram of a system 250 according to one embodiment. The system 250 may include a processor device 200 and an NVM device 212. The processor device 200 may receive command / address values ​​(and optionally write data values) from multiple processes (e.g., cores). In the illustrated embodiment, the command / address data may be received in the form of a set of six parallel bits 216-0 through 216-5 (AX[0] through AX[5]). The command / address values ​​(AX[0] through AX[5]) may be received from multiple different processes or may be generated by request from multiple different processes. Additionally, multiple processes may be assigned to one or more specific banks. Access to the banks may be defined by the upper address bits received in the form of the command / address values ​​(AX[0] through AX[5]).

[0029] The TDM command MUX 204 can apply the command address values ​​(AX[0]-AX[5]) to the physical interface (PHY) 208 in a predefined TDM command order, where the TDM slots are dedicated for a particular process (e.g., core). Examples of various possible TDM allocations will be described in further detail herein.

[0030] PHY 208 can convert the command / address values ​​(AX[0]-AX[5]) into corresponding signals that are driven on command / address bus 210 (i.e., six command / address lines). Such signaling can be compatible with existing parallel data interface standards, and in some embodiments, can be compatible with the LPDDR4 standard. The command / address values ​​(AX[0]-AX[5]) can construct commands that are compatible with existing standards. However, in some embodiments, the command / address values ​​(AX[0]-AX[5]) can be custom commands. That is, commands can be received by standard-compliant signaling, but the bit values ​​transmitted are not part of the existing standard.

[0031] The NVM device 212 may include multiple banks 228-0 through 228-7, an interconnect 230, a command queue 224, a read data queue 226, and a memory PHY 222. Each of the banks (228-0 through 228-7) may include multiple NVM cells. The NVM cells may be any suitable type of non-volatile memory cell that stores data in a non-volatile manner. In some embodiments, the NVM memory cells may be "flash" type memory cells having a NOR type architecture. Within each bank (228-0 through 228-7), the NVM cells may be arranged in one or more arrays and may be accessed by row and column addresses. The banks (228-0 through 228-7) are separately addressable. That is, the physical addressing of the NVM device 212 may have a separate bank address for each bank (228-0 through 228-7). All of the banks (228-0 to 228-7) can be connected to the interconnect 230.

[0032] The interconnect 230 can provide access to the banks (228-0 through 228-7) and can include any suitable circuitry such as decoders, program circuits, and read circuits (e.g., sense amplifiers), just to name a few. In the illustrated embodiment, the interconnect 230 can receive command / address values ​​from the command queue 224 and, in response, access NVM cells in the addressed bank. The interconnect 230 can also receive data read from the banks (228-0 through 228-7) and provide the read data to the read data queue 226.

[0033] The command queue 224 can receive and store command / address values ​​provided to the interconnect 230. In some embodiments, the command queue 224 can provide the command / address values ​​in a first-in, first-out manner. However, it is understood that the command / address data may be received in a TDM order defined by the processor device 200. The read data queue 226 can receive data read from the interconnect 230 and provide it to the memory PHY 222. In some embodiments, the read data queue 226 can provide the read data in the same order as the received command / address values. Thus, the read data may follow the same TDM order defined by the processor device 200.

[0034] Memory PHY 222 may be a PHY counterpart to PHY 208 of processor device 200. Thus, memory PHY 222 can receive command address values ​​transmitted on command address bus 210 and output read data on DDR data bus 214. As with processor PHY 208, memory PHY 222 can generate signals compatible with existing parallel data interface standards, such as the LPDDR4 standard, by way of example only.

[0035] Referring back to the processor device 200, data read from the NVM device 212 may be received by the PHY 208. The resulting data values ​​may be provided to the TDM read data DMUX 206. The TDM data DMUX 206 may provide the read data values ​​(DX[0] through DX

[15] ) to the corresponding processes in the same order as the TDM commands.

[0036] FIG. 3A is a table illustrating TDM command slot allocation according to one embodiment. FIG. 3A illustrates how any number of TDM slots can be created depending on the type of access desired. For example, one master (e.g., core 0 gets slots 0 and 4) can be assigned more TDM command slots than other masters (e.g., core 2 gets only slot 2 while core 0 gets slots 0 and 4). Such a configuration gives one core more bandwidth than the other cores. FIG. 3A illustrates an example in which six TDM command slots are used, but the number of command slots can be increased or decreased as needed. The TDM command allocation can be relatively fixed (e.g., established by a register at power-on or reset), but in other embodiments, the processor unit may include active TDM control that can dynamically allocate TDM command slots.

[0037] TDM command slots may be allocated to any suitable process, and therefore may be allocated according to cores or threads, as just two examples.

[0038] FIG. 3B is a table illustrating bank assignments according to one embodiment. Each process (core in this case) can be assigned to a specific address range within the same NVM device, which includes separately accessible banks. In this way, accesses can be made non-interfering or scheduled to be non-interfering. This ensures that processes can be served within a given maximum latency. In the illustrated example, core 0 and core 1 can access different regions of the same bank (bank 0). core 2 can have independent access to three banks (banks 1, 2, 3) and an access to a portion of bank 4. core 3 can have an access to another portion of bank 4 and independent access to banks 5-7. In some embodiments, accesses to the same bank cannot occur on consecutive TDM command slots.

[0039] In this way, multiple processes can be assigned to different address spaces of a single NVM device, ensuring that all accesses by cores are non-interfering and have a fixed maximum latency.

[0040] 4A is a table showing delay values ​​that can be provided to or determined by the processor unit. The delay values ​​can be TDM IN-TDM OUT values ​​that can indicate the number of cycles between application of a command / address value (corresponding to a read access) and the resulting read data. Such values ​​allow the processor unit to establish an appropriate TDM read slot for the corresponding TDM command slot.

[0041] FIG. 4B illustrates the latency for a read operation according to various embodiments. The processor unit can issue a read command (CMD / ADD IN). The command and address value can reach the NVM device after a latency L_in. The NVM device has its own access latency L_nvm for processing the command and address data, accessing the bank, and driving the read data on the output bus. The read data can be received by the processor unit and available to the process that issued the request after a latency L_out. The total time can be the access time t_access. As shown in more detail herein, accesses to different banks can be overlapped in time, so that the command / address values ​​can be issued at a rate faster than the access time (t_access).

[0042] It is understood that in addition to t_access, the total latency can be included once a TDM time slot for a core becomes available. The TDM command schedule repeats so that if a core misses a slot in the current TDM round, it will be served in the next TDM round. That is, the repetition of the TDM order ensures that the core will be served with some latency.

[0043] 5A-5C are diagrams illustrating various bank allocations according to various embodiments, assuming that the system has assigned four cores (Core 0-Core 3) to eight banks (Bank 0-Bank 7) of the NVM device.

[0044] 5A shows a configuration in which each core is assigned an entire bank: Core 0 is assigned banks 0 / 1, Core 1 is assigned banks 2 / 3, Core 2 is assigned banks 4 / 5, and Core 3 is assigned banks 6 / 7. In such a configuration, TDM command accesses may have no constraints on access order since the accesses cannot interfere.

[0045] FIG. 5B shows a configuration like that shown in FIG. 3B. Core 0 and Core 1 are assigned different portions of Bank 0. Core 2 is assigned all of Bank 1, Bank 2, and Bank 3. Additionally, Core 2 and Core 3 are assigned different portions of Bank 4. Core 3 is also assigned all of Bank 5, Bank 6, and Bank 7. In such a configuration, collisions can be avoided by alternating the order of TDM commands between core pairs that share a bank.

[0046] FIG. 5C illustrates a configuration in which a core (Core 2) is assigned to more than two banks. In particular, Core 2 is assigned to part of Bank 1, Bank 2, and all of Bank 3 and part of Bank 4. In such a configuration, the processor apparatus may employ dynamic TDM scheduling. For example, an access by Core 2 cannot immediately follow (occur in the next TDM slot) an access by Core 1 unless it was an access to Bank 1, and vice versa. Similarly, an access by Core 2 to Bank 4 and an access by Core 3 to Bank 4 would not immediately follow each other. Note that such dynamic scheduling may result in variable latency times since the positions of the cores in the TDM order are not fixed.

[0047] Figure 6A is a timing diagram illustrating scheduling of TDM accesses to an NVM device according to one embodiment. Figure 6A illustrates accesses for a configuration like Figure 5A, where each core is assigned an entire bank (different ones). It is assumed that different banks of the NVM device can be accessed simultaneously (but multiple cores cannot access the same bank simultaneously).

[0048] 6A illustrates a command and address input (command / address) output from a controller device (to an NVM device) and an access operation (bank read) to an addressed bank, where the "bank reads" are understood to be targeted to different banks, although identified by the corresponding core.

[0049] At time t0, an access request can be issued for Core 0.

[0050] At about time t1, the access request for core 0 can begin to be processed by the NVM device as shown by core 0 in "Read Bank." At about the same time, the next access request can be issued for core 1.

[0051] At time t2, bank accesses for core 0 may continue, but in addition, bank accesses for core 1 may begin. These accesses may occur simultaneously, since they are to different banks. This is illustrated by the overlap of bank accesses for core 0 and bank accesses for core 1 between times t2 and t3. Also, at about t2, an access request may be issued for core 2.

[0052] At about t3, the bank access for core 0 may finish. The bank access for core 1 may continue, and the bank access for core 2 may begin. Between times t3 and t4, the bank access for core 1 and the bank access for core 2 may occur simultaneously. Also, at about t3, an access may be issued for core 3.

[0053] Core accesses can continue in a time-overlapping manner until all bank accesses are completed.

[0054] Continuing to refer to Figure 6A, note that the time for command address transactions (command / address) can occur at a faster rate than the bank access times. This can enable high data throughput operation. Furthermore, as described herein, the repeating nature of the TDM sequence allows all access requests to be serviced with a fixed maximum latency.

[0055] FIG. 6B is a timing diagram illustrating the scheduling of TDM accesses to an NVM device according to another embodiment. FIG. 6B illustrates accesses for a configuration like FIG. 5B, where core 0 and core 1 can share one bank, and core 2 and core 3 share one bank. The scheduling of FIG. 6B illustrates the constraint that accesses by cores sharing a bank cannot occur in adjacent TDM slots. This is guaranteed by the TDM ordering, which shows core 0 followed by core 2 (but not core 1) and core 2 followed by core 1 (but not core 3).

[0056] The scheduling of Figure 6B has the same high throughput operation and fixed maximum latency as Figure 6A, but with the added constraint of TDM order (alternating between core pairs that each share the same single NVM bank).

[0057] As described herein, embodiments allow for the TDM command slots to be modified to provide different bandwidth allocations for different processes, i.e., some processes (e.g., cores) can receive increased bandwidth and other processes can receive decreased bandwidth to achieve desired performance. Such an approach employs TDM scheduling to ensure that all processes have access to the NVM device with capped or fixed latency.

[0058] In Figure 7, "Core" indicates the number of processes, "Slot" indicates the number of TDM slots, "Bandwidth" indicates the total memory bandwidth for each core (rounded), "Worst-case Latency" indicates the worst-case latency for each core (in TDM slots), and "TDM Schedule" indicates the TDM slot order per core (from left to right). Figure 7 shows three examples 732-0 to 732-2. Such examples should not be considered limiting.

[0059] The first example 732-0 shows a configuration like that of Figure 6A. Each core is given equal access time in the TDM schedule. The TDM schedule includes four TDM slots. The worst-case latency can be the same for each core.

[0060] A second example 732-1 shows a configuration in which cores 0 and 1 are given more (2x) access than cores 2 and 3. The TDM schedule includes six TDM slots. As shown, the cores with higher bandwidth have lower worst-case latency because their positions in the TDM sequence occur more frequently.

[0061] A third example 732-2 shows a configuration in which core 0 is given four times the bandwidth of cores 2 and 3, and twice the bandwidth of core 1. The TDM schedule includes eight TDM slots. Again, the cores with higher bandwidth have better worst-case latency.

[0062] In this way, TDM access can be allocated to increase the bandwidth for some processes over that of other processes.

[0063] 8A-8D illustrate various NVM accesses by a processor device using TDM command slots as described herein. In the various examples illustrated, it is assumed that a read access to the NVM device can occur in response to a command / address value transmitted over four clocks of a command clock (not shown). Each of FIGS. 8A-8D illustrates a command / address value (Command / Address), a resulting bank access in the NVM device (Bank Access), and a resulting data output (Data Output) from the NVM device. The data output value may be a DDR output, providing data in parallel (e.g., ×16) twice per clock cycle. Additionally, the accesses can occur at a faster rate than bank accesses internal to the NVM device.

[0064] FIG. 8A shows a configuration where access requests are issued at the same rate as the bank access speed. Command / address values ​​can be issued over 4 clocks (each value is shown as “A”). The resulting bank access can take about 8 clocks. Because the command / address values ​​are not received at a rate faster than the bank access values, there is no need to overlap the bank accesses in time. Data can be output from each bank in 8 bursts (each burst is shown as D). It is understood that a burst can be multiple bits (e.g., ×16). In the configuration of FIG. 8A, the time from when a command is issued to when all data is output (transaction latency, trn) can be 28 clock cycles. The worst case latency (twc) can be 60 clock cycles. Thus, the average latency can be about 44 clock cycles. In the configuration of FIG. 8A, the cores can access and share any bank. In a particular example, the interface clock speed (the speed at which command sequences are received) may be 800 MHz, while the internal speed of the NVM device may be 100 MHz (i.e., providing a data burst every 10 ns).

[0065] FIG. 8B illustrates a configuration in which access requests can be issued at a rate faster than the bank access rate. Command / address values ​​can be issued over four consecutive clock periods. Thus, bank accesses overlap in time. In FIG. 8B, data can be output in eight bursts (four cycles at DDR rate). In such a configuration, the transaction latency (trn) can be 24 clock cycles. The worst case latency (twc) can be 40 clock cycles. Thus, the average latency can be about 32 clock cycles. In the configuration of FIG. 8B, subsequent accesses cannot be made to the same bank. In a particular example, the interface clock speed can be 800 MHz, while the effective internal speed of the NVM device can be 200 MHz (i.e., providing a data burst every 5 ns).

[0066] 8C and 8D show configurations that allow command / address values ​​to be input at a faster rate in terms of bank access times than the examples of FIGS. 8A and 8B.

[0067] FIG. 8C shows a configuration in which access requests are issued at twice the bank access rate. A command / address value can be issued over 4 clocks, and the resulting bank access can take approximately 16 clocks. Data can be output in 8 bursts from each bank. In the configuration of FIG. 8C, the transaction latency (trn) can be 44 clock cycles. The worst case latency (twc) can be 80 clock cycles. Thus, the average latency can be approximately 60 clock cycles. In the configuration of FIG. 8C, subsequent accesses cannot be made to the same bank. In a particular example, the interface clock speed can be 1600 MHz, while the effective internal speed of the NVM device can be 200 MHz.

[0068] FIG. 8D illustrates a configuration in which access requests can be issued at four times the bank access rate. Command / address values ​​can be issued over four consecutive clock periods. Thus, bank accesses to different banks overlap in time. In FIG. 8D, data can be output in eight bursts. In such a configuration, the transaction latency (trn) can be 44 clock cycles. The worst case latency (twc) can be 60 clock cycles. Thus, the average latency can be about 52 clock cycles. In the configuration of FIG. 8D, banks cannot be shared between cores. In a particular example, the interface clock speed can be 1600 MHz, while the effective internal speed of the NVM device can be 200 MHz.

[0069] FIG. 9 is a table showing performance parameters for a processor device according to various embodiments. FIG. 9 shows values ​​for various examples of interfaces at speeds of 800 MHz and 1600 MHz (shown in MT / s as well as clock cycle duration (ns)). Read bursts (data out) can be in parallel x16 and DDR format. Read bursts can be 16 bursts (256b) or 8 bursts (128b). Bank sharing possibilities are shown for several examples, including examples of sharing one NVM bank by two cores or four cores. Various components of the total transaction latency are shown as address transfer (time for command address data to be clocked into the device), delay to issue (time for command and address data to be processed by the NVM device), array read (time to access the NVM array), delay to data out (time to get data from the array to the NVM output circuitry) and data out (time to clock data out of the device).

[0070] FIG. 9 also shows the worst-case latency and average latency for different bandwidth sharing by one core (i.e., 50% TDM slots, 33% TDM slots, 25% TDM slots, 12.5% ​​TDM slots).

[0071] As shown, for a system in which multiple cores must compete to access NVM memory, the multiple cores can have high throughput access to the same NVM device while having low worst-case latency and low average latency.

[0072] FIG. 10 is a flow chart of a method 1034 according to one embodiment. The method 1034 may include initiating a TDM operation 1034-0 between a processor device and an NVM device. Such actions may include initiating a particular mode in the processor device and / or configuring the NVM device. According to some embodiments, such actions may include assigning a master to a particular TDM slot. A master may be various processes running on the processor device that need to access storage locations in the NVM. Additionally, such actions may include assigning an address range (e.g., a bank) to the master.

[0073] When a TDM operation is initiated, the method 1034 can determine when command address data is received from a master 1034-1. The received command address data can be assigned to a particular TDM slot based on the master (i.e., the origin of the command / address) 1034-2.

[0074] As the method 1034 cycles through the TDM slots, it may determine 1034-3 whether the current TDM slot is the TDM slot assigned to the received command address data. If the current TDM slot is an assigned TDM slot (Y from 1034-3), the method 1034 may send the command address data to the NVM device 1034-4. If the current TDM slot is not an assigned TDM slot (N from 1034-3), the method 1034 may proceed to the next TDM slot 1034-5. If the TDM operation is not terminated (N from 1034-6), the method 1034 may return to receive command address data from the master 1034-1.

[0075] When TDM operation is started, method 1034 may also start a TDM IN-OUT delay timer 1034-7. Such a timer may indicate when a TDM read data sequence is to begin. If read data is detected in a TDM read data slot (Y from 1034-8), data may be read from its assigned location based on the TDM read slot number of the TDM read data slot 1034-9. If read data is not detected (N from 1034-8), method 1034 may proceed to the next TDM read data slot 1034-10. If the TDM operation is not finished (N from 1034-11), method 1034 may proceed to the next TDM read data slot.

[0076] FIG. 11 is a block diagram of a vehicle control system 1150 according to another embodiment. The system 1150 may be an example of the system shown in FIG. 1A / FIG. 1B or FIG. 2. The system 1150 may include processing cores 1102-0-1102-3, MUX and DMUX 1104 / 1106, memory controller 1108, and system I / O 1136. The cores (1102-0-1102-3) may include processors and associated circuitry (e.g., cache memory, buses, etc.). According to some embodiments, some cores (1102-1-1102-3) may be dedicated for processing tasks (1136-1-1136-3) for one or more systems of the vehicle, while one or more other cores (1102-0) may perform supervisory functions 1136-0 for managing and / or monitoring various operations of the system 1150. Memory controller 1108 can be connected to command address bus 1110 and data bus 1114. System I / O 1138 can be connected to various automotive systems to receive data from and / or transmit data to such other automotive systems. The system I / O can include interfaces for any suitable bus system, including, but not limited to, a Controller Area Network (CAN) type bus.

[0077] The command address bus 1110 may include a chip select CS, an input clock CK_t, and a command address data CA. The data bus may include a first set of data I / O DQ[7:0] that outputs data in synchronization with a first data clock DQS0_t, and a second set of data I / O DQ[15:8] that outputs data in synchronization with a second data clock DQS1_t.

[0078] The NVM device 1112 may include an LPDDR4 I / F 1122, a control circuit 1140, and multiple separately accessible NVM banks 1128-0 through 1128-7. The NVM device 1112 may take a similar form and / or operate in a similar manner to any of the NVM devices described herein and their equivalents. The control circuit 1140 may include a command queue 1124 and a data queue 1126.

[0079] During operation, cores 1102-0 through 1102-3 may be assigned NVM banks 1128-0 through 1128-7 according to any of the embodiments described herein or their equivalents. Additionally, cores (1102-0 through 1102-3) may be assigned TDM slots according to their respective processing requirements, with some cores having higher bandwidth than others. In particular, core 1140-0, which may perform supervisory functions 1136-0, may be assigned a bandwidth appropriate to the supervisory needs of that core, including a given latency guarantee.

[0080] Within the vehicle controller 1100, processes 1136-0 to 1136-3 can issue memory read requests as needed. Such requests can be output by MUX 1104 in assigned TDM slots. The memory controller 1108 can output such requests on the command address bus CA while CS is active. Data on CA can be output in command sequences synchronous to the input clock CK_t. In some embodiments, each command can be input in two CK_t cycles. The signals on the command address bus 1110 can be compatible with the LPDDR4 standard.

[0081] Within the NVM device 1112, TDM requests can be received by the LPDDR4 I / F 1122 and stored in the command queue 1124. The NVM banks (1128-0 to 1128-7) can then be accessed according to such requests. The NVM banks (1128-0 to 1128-7) can be accessed separately as described with respect to each embodiment herein. In response to a request received from the vehicle controller 1100, the NVM device 1112 can output data to the data queue 1126. The data in the data queue 1126 can be driven onto the data bus 1114 by the LPDDR4 I / F 1122. In particular, data on DQ[7:0] can be output on rising and falling edges or on the data clock DQS0_t, and data on DQ[15:8] can be output on rising and falling edges or on the data clock DQS1_t.

[0082] Inside the vehicle controller 1100, the read data received on the data bus 1114 can be organized into TDM read slots. Processes (1136-0 to 1136-3) can read data from their assigned TDM read slots.

[0083] 12A and 12B are diagrams illustrating memory request operations that can be generated by a processor device according to one embodiment. FIG. 12A is a timing diagram illustrating one type of read access via an LPDDR4 interface according to one embodiment. FIG. 12A includes waveforms for an input clock (CK_t), a chip select CS, a command address value (CA), a corresponding command (Command) (generated by the CA value), a data clock DQ_t, and a data value DQ (e.g., a byte, a word, a double word, etc.), which is understood to be a set of parallel data values.

[0084] FIG. 12A shows an example of a custom read command that can be accessed faster than a standard LPDDR4 sequence. As shown, two commands (NVR-1 to NVR-2) can be received over four cycles CK_t (total latency plus three cycles) at the LPDDR4 interface. Following the read latency and clock skew period (RL+tskw), data (DQ) can be output at double data rate synchronous to the data clock (DQ_t). In the illustrated embodiment, data can be output in a burst sequence of eight or more (e.g., 16).

[0085] In some embodiments, the read latency (RL) for accessing NVM cells can be achieved very fast, i.e., less than 20 ns or about 17.5 ns. The tskw value can be less than 4 ns or about 2.5 ns. Thus, for a clock (CK_t) speed of 800 MHz, it can take only 19 clock cycles (t_CMD=3 cycles, RL=14 cycles, tskw=2 cycles) from latching the first command portion to outputting the data. A fast command sequence such as the one shown in FIG. 12A can allow rapid accesses to be performed one after the other.

[0086] FIG. 12B is a table illustrating a command sequence for accessing an NVM cell (e.g., a bank) that can be generated by a processor device in each embodiment. The command sequence can include only two commands, namely, NVR-1 and NVR-2. This is in contrast to conventional LPDDR4 read commands, which can include four commands (Activate1-Activate2-Read1-CAS2). FIG. 12B includes a column COMMAND, which identifies the type of command, a column CS, which identifies the chip select value, a column of command / address bus values ​​(CA0-CA5), and a column of clock values ​​CK. As shown, each command includes a set of bit values ​​that apply to a first clock transition (CK=1) immediately followed by a next clock transition (CK=2) of the same type (e.g., rising edge). Such commands can be received on an LPDDR4 compatible interface and can take the general form of an LPDDR4 command. However, NVR-1 and NVR-2 are not part of the LPDDR4 standard.

[0087] In the particular embodiment shown, the first command NVR-1 may include upper address values ​​(e.g., bank and row values), while the second command NVR-2 may include lower address values ​​(e.g., row and column values). However, this particular bit format of the commands should not be considered limiting.

[0088] 13 is a block diagram of an NVM device 1312 that may be included in a system according to embodiments. The NVM device 1312 may be one of the implementations shown in the embodiments herein. The NVM device 1312 may include an LPDDR4 compatible PHY (referred to as LPDDR4 PHY) 1322, a QSPI compatible PHY (referred to as QSPI PHY) 1340, a number of banks 1328-0 to 1328-7, first access paths 1342-0 to 1342-7 for each bank (1328-0 to 1328-7), second access paths 1344-0 to 1344-7 for each bank (1328-0 to 1328-7), a bank access register 1346, and an embedded operation section 1348.

[0089] The LPDDR4 PHY 1322 can receive a chip select CS, a clock input CK_t, a command address CA input, and can output a first data output DQ[7:0] with a corresponding data clock output DQS0_t and a second data output DQ[15:8] with a corresponding data clock output DQS1_t. In some embodiments, the LPDDR4 PHY 1322 can process some LPDDR4 compatible commands, but cannot process LPDDR4 write commands. The LPDDR4 PHY 1322 can be connected to the banks (1328-0 to 1328-7) via a first bus system 1352. The transfer rate of data read through the LPDDR4 PHY 1322 can be faster than the QSPI PHY 1340. In some embodiments, the LPDDR4 PHY 1322 can communicate with the embedded operation section 1348 to signal access requests through the LPDDR4 PHY 1322.

[0090] The QSPI PHY 1340 can process incoming commands received over the serial data lines. Such commands can include both read and write (e.g., program) commands.

[0091] The bank access register 1346 can store, for each bank (1328-0 to 1328-7), bank access data that can control access to the bank. In some embodiments, if the bank access data for a bank (1328-0 to 1328-7) has one value, the bank can be accessed via the QSPI PHY 1340 and cannot be accessed by the LPDDR4 PHY 1322. If the bank access data has another value, the bank can be accessed by the LPDDR4 PHY 1322 and cannot be accessed by the QSPI PHY 1340.

[0092] Each bank (1328-0 to 1328-7) may include multiple NVM cells arranged in rows and columns and is individually accessible via a unique bank address. In some embodiments, the NVM cells may be group-erasable (e.g., flash-type cells). Read paths (1342-0 to 1342-7) may enable read access to their respective banks (1328-0 to 1328-7) from the LPDDR4 PHY 1322 via the first bus system 1352. Read / write paths (1344-0 to 1344-7) may enable read or write access to their respective banks (1328-0 to 1328-7) from the QSPI PHY 1340 via the second bus system 1354. In some embodiments, the read paths (1342-0 to 1342-7) and the read / write paths (1344-0 to 1344-7) can be enabled or disabled depending on the bank access value. Multiple different banks (1328-0 to 1328-7) can be accessed simultaneously.

[0093] The embedded operation section 1348 may include a write buffer 1348-0, a command processor 1348-1, and a processor section 1348-2. The write buffer 1348-0 may receive and store write data from the QSPI PHY 1340 for subsequent programming into the addressed bank (1328-0 through 1328-7). The command processor 1348-1 may decode command data received on the QSPI PHY 1340 to generate appropriate control signals to execute the command. The processor section 1348-2 may include one or more central processing units (CPUs) to perform various functions for the NVM device 1312. Such functions may include setting bank access values. Additionally, the processor section 1348-2 may provide any of the following: maintenance NVM cells (e.g., wear leveling), sector access control (boot sector), encryption / decryption, just to name a few.

[0094] FIG. 14 illustrates an automobile system 1460 according to one embodiment. The automobile system 1460 can have a number of subsystems, including, but not limited to, a main control subsystem 1478-0, an engine powertrain control system 1478-1, a suspension tire control system 1478-2, and a body control system 1478-3. The main control subsystem 1478-0 can include a processor unit 14000 according to an embodiment disclosed herein and an NVM unit 1412 or equivalent. The main control subsystem 1478-0 can control infotainment functions (navigation, communication, entertainment devices, data storage, digital audio broadcasting) and supervisory monitoring of all other systems. In some embodiments, the main control subsystem 1478-0 can be one of the implementations shown in FIG. 11. In such a configuration, the processor device 1400 may have multiple processes as described herein and their equivalents that may access banks of NVM devices 1412 in a TDM configuration and may receive data read from NVM devices 1412 in a TDM configuration. In particular, the supervisory process may have relatively quick access (LPDDR4 compatible signaling) to the NVM devices 1412, within some maximum latency.

[0095] It should be understood that references throughout this specification to "one embodiment" or "an embodiment" mean that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment of the invention. Thus, it is emphasized and understood that references to "an embodiment" or "one embodiment" or "alternative embodiments" more than once in various parts of this specification do not necessarily all refer to the same embodiment. Furthermore, particular features, structures, or characteristics may be combined as appropriate in one or more embodiments of the invention.

[0096] Similarly, in the foregoing description of exemplary embodiments of the present invention, it should be understood that, for the purpose of streamlining the disclosure to facilitate understanding of one or more of the various inventive aspects, different features of the invention may at times be grouped together in a single embodiment, drawing, or description thereof. However, this method of disclosure should not be interpreted as reflecting an intention that the claims require more features than are expressly recited in each claim. Rather, an inventive aspect lies in less than all features of a single embodiment disclosed above. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the present invention.

Claims

1. Multiple processing sources; A multiplexer (MUX); A memory controller; A demultiplexer (DMUX); An apparatus comprising: the multiplexer (MUX) configured to assign read requests from the multiple processing sources to predefined time division multiplexed (TDM) command slots; the memory controller is configured to generate non-volatile memory (NVM) command and address data on a unidirectional command address bus from a read request received from the MUX during a TDM command slot assigned to the read request, the address data including at least a bank address; the memory controller is configured to receive read data on a unidirectional parallel data bus synchronously with rising and falling edges of a received data clock, the read data being received in TDM read slots having a predetermined order; the demultiplexer (DMUX) is configured to provide the read data of each TDM read slot to one of the plurality of processing sources in the predetermined order based on a position of the TDM read slot; Each processing source issues read requests only to addresses in its assigned bank of the NVM device; A bank is assigned to no more than two processing sources, the MUX is configured to prevent consecutive TDM read slots from being assigned to different processing sources for accessing the same bank; Device.

2. the multiple processing sources being multiple different processing cores of a single host device; 2. The apparatus of claim 1.

3. a plurality of the processing sources being subsystem control processes each controlling a subsystem of a larger system; at least one of the plurality of processing sources is a supervisory process that monitors the subsystem control process; 2. The apparatus of claim 1.

4. the device is a vehicle controller; The subsystem is an automotive subsystem.

4. The apparatus of claim 3.

5. The command address bus and the parallel data bus are compatible with signaling conforming to the LPDDR4 standard.

2. The apparatus of claim 1.

6. 1. A method comprising: Allocating at least one non-volatile memory (NVM) bank to a plurality of different control processes of a controller device, each control process issuing access requests only to its assigned NVM bank; multiplexing access requests from said plurality of processes into predetermined time division multiplexed (TDM) command slots; The memory controller of the controller device operates as follows: generating command and address data on a unidirectional command address bus during an assigned TDM command slot from the access request received from the multiplexer (MUX); receiving read data on a unidirectional parallel data bus synchronously with rising and falling edges of a received data clock, said read data being received in TDM read slots having a predetermined order; demultiplexing the read data from each TDM read slot to one of the plurality of processes in the predetermined order based on a position of the TDM read slot; If a bank is assigned to multiple control processes, requests for access to said bank by different assigned control processes do not occur on consecutive TDM command slots. method.

7. Each control process includes a process executed by a processor core. The method of claim 6.

8. The memory controller receives and transmits data via signaling compatible with the LPDDR4 standard. The method of claim 6.

9. the command and address data is transmitted as a sequence of commands, each command including a command and / or address value transmitted over two clock cycles of an input clock; generating the command and address data includes performing a read operation to a bank with no more than two commands; The method of claim 6.

10. The TDM command slots are repeated over time; at least one of the plurality of control processes is assigned more TDM command slots than other control processes; The method of claim 6.

11. the controller device is an automobile controller device; a plurality of the control processes configured to control subsystems of the vehicle; At least one controlled process is a supervisory process that monitors the other controlled processes; The method of claim 6.

12. A processor unit; An NVM device; A unidirectional command and address bus; A unidirectional data bus; A system comprising: The processor device includes: Multiple processor cores; a multiplexer (MUX) configured to assign read requests from each processor core to a predefined time division multiplexed (TDM) command slot; a memory controller configured to generate non-volatile memory (NVM) command and address data in response to the read request from the MUX and to receive read data in a TDM read slot; a demultiplexer (DMUX) configured to provide the read data of each TDM read slot to one of the plurality of processor cores; Including, the NVM device includes a plurality of separately addressable banks; the unidirectional command and address bus is configured to transmit the command and address data from the processor device to the NVM device; the unidirectional data bus is configured to transmit the read data from the NVM device to the processor device; the TDM command slots each have the same duration; the NVM device has a bank access time that includes a period from receiving the command and address data to outputting the corresponding read data; the duration of the TDM command slot is less than the bank access time; system.

13. A processor device, comprising: An NVM device; A unidirectional command and address bus; A unidirectional data bus; A system comprising: The processor device includes: Multiple processor cores; a multiplexer (MUX) configured to assign read requests from each processor core to a predefined time division multiplexed (TDM) command slot; a memory controller configured to generate non-volatile memory (NVM) command and address data in response to the read request from the MUX and to receive read data in a TDM read slot; a demultiplexer (DMUX) configured to provide the read data of each TDM read slot to one of the plurality of processor cores; Including, the NVM device includes a plurality of separately addressable banks; the unidirectional command and address bus is configured to transmit the command and address data from the processor device to the NVM device; the unidirectional data bus is configured to transmit the read data from the NVM device to the processor device; the processor device includes a configuration storage circuit that assigns the plurality of separately addressable banks of the NVM device to no more than two processor cores; The processor device includes: constraining each processor core to access only one assigned bank of the plurality of separately addressable banks; Prevents accesses in consecutive TDM command slots from being issued to the same separately addressable bank; It is configured as follows: system.

14. the NVM device is configured to access a first bank of the plurality of separately addressable banks while accessing a second bank of the plurality of separately addressable banks in response to read requests to a plurality of different banks being received from the processor device on successive TDM command slots.

14. A system according to claim 12 or 13.

15. the processor device is a vehicle controller device; each of the plurality of processor cores configured to execute a subsystem control process for controlling a vehicle subsystem; at least one processor core is configured as a supervisory process for monitoring said subsystem control process, said supervisory process having at least one dedicated TDM command slot; 14. A system according to claim 12 or 13.

16. The unidirectional command address bus and the unidirectional data bus are compatible with the LPDDR4 standard.

14. A system according to claim 12 or 13.

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