SYSTEMS AND METHODS FOR RADICAL AND THERMAL TREATMENT OF SUBSTRATES - Patent application

Abstract

The present disclosure provides a system and method for processing a channel structure of a substrate, including positioning the substrate in a first processing chamber having a first processing volume. The substrate includes a channel structure having high aspect ratio features, with an aspect ratio greater than about 20:1. The method includes exposing a silicon-containing layer over the channel structure to a hydrogen or deuterium plasma in the first processing volume at a flow rate of about 10 sccm to about 5000 sccm. During the exposure, the substrate is maintained at a temperature of about 100°C to about 1100°C, and the exposure forms a nucleation substrate. After the exposure, the substrate is subjected to a thermal annealing step.

Description

[Technical field]

[0001] TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate generally to systems and methods for manufacturing semiconductor devices. More specifically, the present disclosure is directed to systems and methods for heat treating channel structures of semiconductor devices in a hydrogen radical environment. [Background technology]

[0002] The integrated circuit (IC) market continues to demand larger memory capacity, faster switching speeds, and higher feature density. To enable the manufacture of next generation devices and structures, three-dimensional (3D) stacking of semiconductor memory chips is often used to improve transistor performance. By arranging transistors in three dimensions instead of the traditional two dimensions, multiple transistors can be placed much closer to each other in an integrated circuit. Stacking semiconductor chips in three dimensions reduces wiring length, lowers wiring delays, and increases area device density on a chip. When forming a structure of flash memory, a film stack is placed on a substrate and an etching process is performed to etch a trench in the film stack. This trench is later used to build a silicon channel structure to electrically connect between a source and drain formed nearby. The film stack typically includes alternating layers of conductive and insulating layers. Because a large number of alternating layers are required in the film stack for higher device performance, the film stack with the channel structure often has a high aspect ratio. Also, manufacturers are continually increasing the height of the stack to increase the length of the channel. This limits the speed of the device due to the mobility of electrons in the channel and the increased distance that the electrons must travel.

[0003]

[0003] To increase the mobility of electrons in the channel, conventional methods use only thermal annealing to crystallize and grow the semiconductor grains to aid in electron mobility. However, such a process is not ideal because annealing alone induces a high thermal budget, including operating at high temperatures with long dwell times. Temperature is often limited because above a certain temperature, device defects may occur. Furthermore, long dwell times may impact throughput. If the dwell time and / or temperature is not sufficient, the grain size may not grow to a sufficient level, resulting in a poorly performing device.

[0004] In view of the above, what is needed is a system and method for thermally processing substrates having high aspect ratio features. Summary of the Invention

[0005] In one embodiment, a method for processing a substrate is provided that includes positioning a substrate in a first processing chamber having a first processing space. The substrate includes a 3D memory structure having high aspect ratio features with an aspect ratio of greater than about 20:1. A silicon-containing layer of a channel structure, such as in the 3D memory structure, of the substrate is exposed to a hydrogen or deuterium plasma at a flow rate of about 10 sccm to about 5000 sccm in the first processing space. During the exposure, the substrate is annealed in the first processing space at a temperature of about 100° C. to about 1100° C. to form a nucleation substrate. After exposing the substrate, the nucleation substrate is thermally annealed.

[0006] In another embodiment, a method of fabricating a memory device in a substrate is provided that includes forming channel structures in a film stack by etching channels in the film stack and disposing a channel layer on the inner surface and bottom of the channels. The channels and channel layer form high aspect ratio channel structures in the substrate. Each channel structure has an aspect ratio greater than about 20:1. The method includes exposing the channel structures to hydrogen radicals in a first processing space of a first processing chamber. The channel structures are heated to a temperature of about 100° C. to about 1100° C.

[0007] In another embodiment, a method of treating a substrate is provided that includes forming an amorphous silicon-containing layer on bottom and interior surfaces of a channel formed in a film stack of the substrate. The film stack includes alternating oxide and nitride layers, or alternating oxide and polysilicon layers. The process includes exposing the amorphous silicon-containing layer to hydrogen radicals. The substrate is heated to a first temperature of about 100° C. to about 1100° C. to form a nucleation substrate. The nucleation substrate is further heated to a second temperature.

[0008]

[0008] In order that the above-mentioned features of the present disclosure may be understood in detail, the present disclosure summarized above will now be more particularly described with reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings merely illustrate exemplary embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, which may admit of other equally effective embodiments. [Brief description of the drawings]

[0009] [Figure 1A] FIG. 2 illustrates an exemplary channel formed in a film stack disposed on a substrate, according to certain aspects of the present disclosure. [Figure 1B] FIG. 2 illustrates an example channel structure having a channel layer disposed within a channel of a memory structure formed in a substrate, in accordance with certain aspects of the present disclosure. [Diagram 2]FIG. 2 is a flow diagram illustrating an exemplary method for fabricating a memory device on a substrate in accordance with certain aspects of the present disclosure. [Diagram 3] FIG. 1 is a schematic diagram illustrating an exemplary thermal processing system used to process a channel structure on a substrate, in accordance with certain aspects of the present disclosure. [Figure 4A] FIG. 1 is a schematic diagram illustrating an exemplary thermal radical treatment system used to heat and treat a channel structure on a substrate with radical species, in accordance with certain aspects of the present disclosure. [Figure 4B] FIG. 1 is a schematic diagram illustrating an exemplary thermal radical treatment system used to heat and treat a channel structure on a substrate with radical species, in accordance with certain aspects of the present disclosure. [Diagram 5] FIG. 2 is a flow diagram illustrating an exemplary method for processing a substrate having high aspect ratio features in accordance with certain aspects of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010]

[0015] To facilitate understanding, wherever possible, the same reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0011]

[0016] It should be noted, however, that the attached drawings merely depict exemplary embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, which may also permit other equally effective embodiments.

[0012]

[0017] Certain aspects of the present disclosure provide systems and methods for thermally processing substrates having high aspect ratio features. In particular, the high aspect ratio features may be channel structures formed in certain three-dimensional devices. As vertical structures are made with longer channel lengths, the speed of the devices may become limited by the mobility of electrons in the channel and the increased length the electrons must travel. Thus, there is a need to increase the mobility of electrons in the semiconductor channel to compensate for the increased length the electrons must travel. In particular, increasing the grain size of a semiconductor such as silicon in the channel using a thermal annealing process may help reduce electron scattering at the grain boundaries of the semiconductor and therefore increase the mobility of the electrons.

[0013]

[0018] The annealing process creates a more crystalline structure from regions of the substrate that were previously rendered amorphous. During the crystallization process, semiconductor atoms, such as silicon atoms, are rearranged into an ordered lattice structure. To crystallize an amorphous semiconductor film, heat is typically used as an energy source to provide the atoms with the kinetic energy necessary to rearrange them into an ordered structure. To increase the grain size obtained from the amorphous semiconductor film, the furnace temperature may be increased and / or the furnace anneal time may be increased. The furnace temperature is significantly limited by stringent processing thermal budget requirements, while extended furnace anneal times may impair product throughput. In view of the above, a system and method are needed to process semiconductor substrates having film stacks with high aspect ratio channel structures to obtain uniform and increased grain size in the channels using methods with high throughput and minimal thermal budget to obtain efficient device performance enhancement. The present disclosure provides a system and method for thermally treating substrates with high aspect ratio features to produce high performance devices.

[0014]

[0019] Specifically, the disclosed process and system improves the electron mobility in the channel of a three-dimensional memory structure by increasing the average grain size in the semiconductor channel layer disposed in the channel. The process includes treating the substrate with radical species, such as hydrogen or deuterium radicals, under high temperature conditions to promote an environment that facilitates nucleation and grain growth of the semiconductor channel layer. The radical treatment, such as hydrogen or deuterium doping, may be followed by a furnace annealing treatment at a temperature equal to or higher than the radical treatment to promote grain growth of the nucleated semiconductor channel layer. The furnace annealing of the nucleated channel layer results in a more uniform grain distribution in the semiconductor channel layer, leading to further grain growth. The hydrogen or deuterium radical treatment reduces the activation energy required for the nucleation and incubation stages of the semiconductor grains, allowing for reduced heat and time required for the furnace annealing treatment.

[0015]

[0020] 1A and 1B are diagrams illustrating a memory structure 110 formed on a substrate 100 at various stages of formation according to certain aspects of the disclosure. As shown in the exemplary embodiment illustrated in FIG. 1A and 1B, the substrate 100 has a substantially planar surface, but may alternatively have a substantially planar surface with uneven surfaces or structures formed thereon. A film stack 101 is disposed on the substrate 100 that is used to form memory cell structures in the film stack 101. The manufacturing process of a 3D NAND device begins with depositing multiple alternating film layers, collectively referred to as a "film stack." Creating the film stack includes depositing multiple thin layers of oxide / nitride (ON) pairs or layers of oxide / polysilicon (OP) pairs. The substrate 100 is a silicon-based material, but may also be a germanium-based material, a silicon-germanium alloy, or any suitable insulating, semiconducting, or conductive material, such as a material having elements of periodic groups III, IV, or V. In some embodiments, the substrate 100 may be a material such as doped or undoped single crystal silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers silicon-on-insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, etc. The substrate 100 may have a variety of dimensions, such as rectangular or square panels, as well as substrates of about 200 mm, about 300 mm, about 450 mm, or other diameters.

[0016]

[0021] In at least one embodiment, a film stack 101 disposed on a substrate 100 has several vertically stacked layers, such as 34 or more pairs of layers. The film stack 101 includes a first layer 102 (102a) sandwiched between two nitride layers 103a and 103b. 1 From 102a n ) and the second layer 104 (104a 1 From 104a nThe sandwiched layer is deposited on an aluminum oxygen compound layer 108 disposed on a substrate to form a film stack 101. The layer pairs include alternating first layers 102 and second layers 104 repeated for n number of pairs of first layers 102 and second layers 104. The film stack 101 is part of a memory cell device, such as a three dimensional (3D) memory device, and any predetermined number of repeating pairs of first layers 102 and second layers 104 can be used as desired.

[0017]

[0022] In at least one embodiment, which can be combined with other embodiments, a film stack 101 is used to form multiple memory cell structures for a three-dimensional (3D) memory device. The film stack 101 is composed of alternating oxide and nitride layers (ON), or alternating oxide and polysilicon layers (OP). For example, the film stack 101 can include polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, titanium nitride, composites of oxide and nitride, at least one or more oxide layers sandwiching a nitride layer, and combinations thereof, and the like. As can be seen in FIG. 1A and FIG. 1B, the alternating layers of the film stack 101 include a first layer 102 that functions as an insulating dielectric layer, such as silicon oxide. The alternating layers of the film stack 101 also include a second layer 104, which is a functional layer in which memory storage cells are built. The functional layer includes one or more of silicon, polysilicon, and silicon nitride.

[0018]

[0023] The second layer 104 includes memory storage cells of different structures, such as charge trapping devices (not shown) or floating gate devices. The floating gate devices include a control gate 109, an interpoly dielectric (IPD) layer 106, a floating gate 107, a tunnel oxide layer 105, and a channel layer 170. The floating gate is made of silicon and the tunnel oxide layer is made of silicon oxide. However, other materials are also envisioned. The IPD layer 106 is a stack of layers, such as a three-layer stack. The IPD layer 106 is a stack of one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. The alternating first and second layers 102 and 104 are disposed between nitride layers (e.g., 103a, 103b), such as between a cap layer 103a and a stop layer 103b.

[0019]

[0024] The film stack 101 is patterned to form a channel 150 therein, as shown in FIG. 1A. A hard mask layer (not shown) is formed on the film stack 101 to facilitate the formation of the channel 150 in the film stack 101. The channel 150 is used to form a channel structure 160 in the device structure as the fabrication process proceeds. As used herein, the channel structure 160 includes the channel 150 and a channel layer 170. It should be noted that the device structure and configuration can be modified as needed for different device performance requirements.

[0020]

[0025] The patterning process includes forming a channel 150, shown in FIG. 1A, in the film stack 101, which is later used as a channel structure 160, shown in FIG. 1B. The patterning process uses any suitable patterning gas mixture to etch the first and second layers 102, 104 of the film stack 101. To form the channel structure 160, a channel layer 170 is formed in the channel 150. The channel layer 170 is formed on the inner surface of the channel, along the entire length of the channel, and at the bottom of the channel. The channel layer 170 is formed by a chemical vapor deposition (CVD) process, but may alternatively be formed by an atomic layer deposition (ALD) process, a sputtering process, a coating process, or other suitable process. The channel layer 170 is amorphous after deposition and crystallizes into polysilicon after hydrogen or deuterium radical treatment, and may additionally or alternatively include single crystal silicon, III-V semiconductors, or other semiconductors with high electron mobility and low random telegram noise. The channel layer 170 is crystallized to increase the electrical conductivity of the channel structure 160 and improve overall device performance. The channel 150 formed in the film stack 101 may have sloping sidewalls (e.g., non-perpendicular or at an angle to the horizontal or planar surface of the substrate 100) during the patterning and etching process. An oxide layer (not shown) may fill the remaining space in the channel structure 160 after the channel layer 170 is disposed and the channel structure 160 is heat treated according to the methods of the present disclosure.

[0021]

[0026] In at least one embodiment, which may be combined with other embodiments, the substrate of the present disclosure includes a high aspect ratio feature. For example, the channel 150 formed in the film stack 101 may be referred to as a high aspect ratio feature, or the channel 150 and the channel layer 170 together form a high aspect ratio feature. A high aspect ratio feature has an aspect ratio of greater than about 20:1, 30:1, 40:1, or 50:1, such as an aspect ratio of 50:1 to about 1000:1, such as about 50:1 to about 300:1, such as about 100:1 to about 300:1, or about 200:1 to about 300:1, etc.

[0022]

[0027] Although FIGS. 1A and 1B show a 3D NAND structure, the methods of the present disclosure can be applied to any semiconductor device having a channel structure, such as resistive RAM (ReRAM) and 3D-DRAM.

[0023]

[0028] 2 is a flow diagram illustrating an exemplary method 200 for fabricating a memory device on a substrate according to certain aspects of the disclosure. Step 202 of method 200 includes forming a channel structure in film stack 101. Channel structure 160 is formed by etching a channel 150 in film stack 101 and forming a channel layer 170 on the inner surface and bottom of channel 150 in film stack 101. Channel structure 160 forms a high aspect ratio feature having an aspect ratio of greater than about 20:1. Channel layer 170 is about 100 Angstroms to about 200 Angstroms.

[0024]

[0029] The method 200 includes, at step 204, treating the channel structure 160 with hydrogen or deuterium radicals in a first processing space (e.g., 308 shown in FIGS. 3 and 4) in a first processing chamber (e.g., 328 shown in FIGS. 3 and 4). Channel structures with high aspect ratios are difficult to process using conventional processes using high energy plasmas because conventional processes result in unintended ion etching from ion bombardment and poor uniformity along the channel length. In conventional processes, high energy plasma ions are directed straight to the bottom of the channel instead of the sidewalls. Conventional processes are used for horizontal surfaces but are not suitable for vertical structures such as channels. It has been discovered that the hydrogen process disclosed herein provides non-directional radical treatment along the entire channel length, improving the uniformity of nucleation and grain growth. In particular, hydrogen radicals are delivered to the processing space (e.g., 308 shown in FIGS. 3 and 4) via a showerhead positioned above the substrate. In one embodiment, the showerhead is configured to provide a uniform distribution of radicals on the substrate and promote improved diffusion into the channel 150 formed in step 202.

[0025]

[0030] In some embodiments, which may be combined with other embodiments, in step 204, a first processing chamber (e.g., 328 shown in Figures 3 and 4) is heated to a temperature of about 100°C to about 1100°C, e.g., about 200°C to about 800°C, e.g., about 300°C to about 700°C, e.g., about 400°C to about 600°C, e.g., about 500°C. In at least one embodiment, which may be combined with other embodiments, the substrate having high aspect ratio features is exposed to hydrogen or deuterium radical species for at least about 1 minute, e.g., about 1 minute to 30 minutes, alternatively about 10 minutes to about 1 hour, e.g., about 20 minutes to 40 minutes, e.g., about 30 minutes. Treating the high aspect ratio features with hydrogen or deuterium radical species at the above-mentioned temperatures may be performed in a thermal radical treatment system 400 described with reference to Figures 4A and 4B. However, the use of other thermal treatment systems is also contemplated.

[0026]

[0031] 2, step 206 includes heating the high aspect ratio features after exposure to the hydrogen or deuterium radical species to a temperature of about 400° C. to about 1100° C. In some embodiments, which may be combined with other embodiments described herein, the high aspect ratio features are heated in the second processing space 358 of the second processing chamber 352, as shown in FIG. 3. Alternatively, the high aspect ratio features are heated in the first processing space 308 of the first processing chamber 328.

[0027]

[0032] 3 is a schematic diagram illustrating an exemplary thermal processing system used to process channel structures on a substrate according to certain aspects of the present disclosure. The second processing chamber 352 may be a thermal processing chamber that can be heated at a temperature range from room temperature to about 1100° C. or higher, such as a furnace. In some embodiments, which can be combined with other embodiments, the substrate having high aspect ratio features is heated to a temperature of about 400° C. to about 1100° C., such as about 600° C. to about 1000° C., such as about 700° C., in the second processing chamber. The substrate having high aspect ratio features is annealed in the second processing chamber 352 for at least about 1 minute, such as about 10 minutes to about 1 hour, such as about 20 minutes to 40 minutes, such as about 30 minutes. In at least one embodiment, which can be combined with other embodiments, the second processing chamber 352 is operated at a pressure of about 1 Torr to about 3800 Torr, such as atmospheric pressure or reduced pressure, such as about 1 Torr to about 760 Torr. In some embodiments, the second processing chamber 352 contains nitrogen gas. The pressure is controlled by flowing an inert gas, for example a noble gas such as argon.

[0028]

[0033] FIG. 4A is a schematic diagram illustrating an exemplary thermal radical treatment system 400 used to treat a channel structure 160 on a substrate 100 according to certain aspects of the present disclosure. The thermal radical treatment system 400 includes a first thermal treatment chamber 328, a remote plasma source (RPS) 306, and a gas line 307 coupling the remote plasma source 306 to the first thermal treatment chamber 328. The first thermal treatment chamber 328 may be a conventional heater-based annealing chamber or a rapid thermal processing (RTP) chamber, such as a rapid thermal processing (RTA) chamber. In some embodiments, the first thermal treatment chamber 328 may be any thermal treatment chamber in which delivery of at least metastable radical molecular species and / or radical atomic species to a processing space is desired. For example, in some embodiments, the treatment chamber is a plasma treatment chamber or a plasma-enhanced or plasma-assisted deposition chamber, such as a plasma enhanced chemical vapor deposition (PECVD) chamber or a plasma enhanced atomic layer deposition (PEALD) chamber.

[0029]

[0034] The control module 318 is coupled to the thermal radical treatment system 400 and may control the operating parameters of the first thermal treatment space 308, the RPS 306, the pump 316, and the gas flow in the gas line 307 to the first thermal treatment chamber 328. The control module 318 may include a central processing unit (CPU) 324, a memory 320, and support circuits 322 for the CPU 324. The control module 318 controls the thermal pre-processing system 300 directly or through other computers and / or controllers (not shown) coupled to the first thermal treatment chamber 328, the RPS 306, and / or the gas line 307. The control module 318 is any form of general-purpose computer processor used in an industrial environment to control various chambers and equipment, as well as sub-processors thereon or therein. The memory 320, or computer readable medium, is one or more of readily available memory such as random access memory (RAM), read only memory (ROM), floppy disk, hard disk, flash drive, or any other form of digital storage, local or remote. Support circuits 322 are coupled to the CPU 324 to support the processor. Support circuits 322 include cache, power supplies, clock circuits, input / output circuits and subsystems, etc. Substrate processing parameters are stored in the memory 320 as software routines that are executed or invoked to make the control module 318 a special purpose controller that controls the operation of the thermal radical processing system 300. The control module 318 is configured to perform any of the methods described herein. In some embodiments, a vacuum pump 316 is used to maintain gas pressure in the first thermal processing space 308. The vacuum pump 316 evacuates post-processing gases and / or process by-products via exhaust 309. In some embodiments, the vacuum pump 316 is controlled by the control module 318.

[0030]

[0035] The RPS 306 is coupled to a power source 338. The power source 338 is used as an excitation source to ignite and maintain a plasma in the RPS 306. In at least one embodiment, the RPS 306 includes an inductively coupled plasma (ICP) source, a transformer coupled plasma (TCP) source, and / or a capacitively coupled plasma (CCP) source. In some embodiments, which can be combined with other embodiments, the power source 338 is a radio frequency (RF) source. For example, the RF source provides a power of about 5 kW to about 9 kW, e.g., 7 kW.

[0031]

[0036] The RPS 306 operates at about 50 mT to about 10 T, such as about 100 mT to about 1 T. The RPS 306 is coupled to a first gas source 302 via a first gas conduit 303 and to a second gas source 304 via a second gas conduit 305. For example, the first gas source 302 may include a first gas, the first gas being selected from the group consisting of He, Ne, Ar, Kr, Xe, and N. 2 For example, the first gas source 302 may include Ar gas. In some embodiments, the second gas source 304 may include a non-reactive gas such as hydrogen, nitrogen, or a deuterium-containing species, H 2 , D 2 , N.H. 3 , or a combination thereof. In at least one embodiment, the thermal radical processing system is a twin chamber as shown in FIG. 4B. The twin chamber processes two substrates simultaneously in a chamber body having two process regions. The two spaces are not isolated from each other. However, other configurations are contemplated. The flow rate of the second gas source into the first thermal processing space 308 is about 10 sccm to about 5000 sccm, for example, about 100 sccm to about 1500 sccm. The total flow rate of the first and second gases into the first thermal processing space 308 is about 10 sccm to about 5000 sccm, for example, about 100 sccm to about 1500 sccm.

[0032]

[0037] 4B is a cross-sectional view of an example of a thermal radical treatment system 400 having two chambers according to certain embodiments of the present disclosure. Specifically, FIG. 4B illustrates an example of a first thermal treatment system having two thermal treatment chambers 328A, 328B. Each of the thermal treatment chambers 328A, 328B of the first thermal treatment system 400 includes a substrate holder 312A, 312B. A substrate having high aspect ratio features is positioned in one of the substrate holders (e.g., 312A, 312B) in one of the first processing spaces (e.g., 308A, 308B).

[0033]

[0038] Each of the thermal treatment chambers 328A, 328B includes a remote plasma source 306A, 306B. In some embodiments, the thermal treatment chambers 328A, 328B may share a single RPS (not shown). In some embodiments, each RPS 306A, 306B is coupled to a shared first gas source 302 and a shared second gas source 304. In at least one embodiment, each RPS 306A, 306B may be coupled to a separate first gas source (not shown) and a separate second gas source (not shown). Each of the substrate holders 312A, 312B has an embedded heater element 314A, 314B suitable for controlling the temperature of a substrate supported on the substrate holder 312A, 312B. In at least one embodiment, which may be combined with other embodiments, the substrate holders 312A, 312B may be resistively heated by applying a current from a power source to the heater element 314A, 314B. Each of the thermal treatment chambers 328A, 328B also includes a process kit 310A, 310B. The process kit is one or more components inside the thermal treatment chambers 328A, 328B that are used for on-wafer performance, such as a liner. The liner may be made of quartz, ceramic, or metal.

[0034]

[0039] 5 is a flow diagram illustrating an exemplary method 500 for processing a substrate having high aspect ratio features according to certain embodiments of the present disclosure. The high aspect ratio features have an aspect ratio greater than about 20:1, such as about 20:1 to about 1000:1, such as about 50:1 to about 500:1, such as about 100:1 to about 300:1. The method 500 includes forming a semiconductor layer, such as a silicon-containing layer (e.g., the semiconductor channel layer 170), on a substrate in step 502. The substrate having the semiconductor layer is positioned in a first thermal processing chamber having a first processing space, and the first processing space is in fluid communication with a gas line.

[0035]

[0040] In step 504, the substrate is exposed to hydrogen or deuterium radical species. Forming hydrogen or deuterium radical species includes forming a plasma from a first gas in a remote plasma source 306, flowing the plasma through a gas line 307 to a first thermal treatment chamber 328, and flowing a second gas into the remote plasma source 306 before, simultaneously with, or after ignition of the first gas in the remote plasma source 306. In some embodiments, the plasma and the second gas may mix in the first thermal treatment space 308. A first gas from a first gas source 302, such as argon, flows into the remote plasma source 306 through a first gas conduit 303. A power source 338 is turned on and the mixture from the remote plasma source 306 flows into the first thermal treatment space 308. A second gas, such as hydrogen gas, enters the RPS 306 through a second gas conduit 305, mixes with the plasma, and flows through a gas line 307 to the first thermal treatment space 308. The flow rate of the second gas is about 5% to about 100% of the total flow rate of the first gas and the second gas to the remote plasma source 306. The first gas is ignited into a plasma in the RPS 306 and is used to dissociate the molecules of the second gas into radical species, such as hydrogen radicals, in the mixing space of the remote plasma source and the gas line 307. In some embodiments, which can be combined with other embodiments, the first gas can be turned off and the radical species generated from the second gas can flow into the first thermal treatment space 308. In some embodiments, which can be combined with other embodiments, the first gas can continue to flow into the first thermal treatment space simultaneously with the radical species generated from the second gas. Hydrogen or deuterium radical species are flowed into the first thermal treatment volume 308 to nucleate the amorphous layer of the 3D memory structure of the substrate with the radical species as described in step 506 .

[0036]

[0041] The plasma source is shown in the drawings as a remote plasma source 306, but other excitation sources are contemplated. In some embodiments, which may be combined with other embodiments described herein, the second gas is flowed into an inductively coupled plasma (ICP) source before flowing into the first thermal treatment space, or the second gas is energized in situ by an ICP in the first thermal treatment space. In some embodiments, the second gas may be flowed into a microwave plasma source before flowing into the first thermal treatment space, or the second gas is energized in situ by a microwave plasma source in the first thermal treatment space. In some embodiments, which may be combined with other embodiments, the thermal treatment of the present disclosure is free of all non-hydrogen and / or non-deuterium radical species. It has been discovered that forming a plasma in a remote plasma source uses less energy to form and sustain the plasma than forming a plasma directly in the treatment space.

[0037]

[0042] In certain aspects of the present disclosure that can be combined with other embodiments, forming hydrogen or deuterium radical species includes turning on a power source 338 to the RPS 306 and flowing a second gas from a second gas source 304, such as a hydrogen-containing gas, to the RPS 306 via a second gas conduit 305. The flow rate of the second gas may be about 100% of the total gas flow rate to the remote plasma source 306. Molecules of the second gas are dissociated into radical species, such as hydrogen radicals, in the remote plasma source 306 and gas line 307. The hydrogen or deuterium radical species are flowed into the first thermal treatment space 308 as described in step 504.

[0038]

[0043] Flowing hydrogen and / or deuterium radical species into the first thermal treatment space 308 includes nucleating the semiconductor channel layer 170. Specifically, prior to the hydrogen and / or deuterium radical species treatment, the semiconductor channel layer is an amorphous layer, such as an amorphous and / or semi-crystalline layer used to fabricate 3D memory structures. After exposing the substrate with the amorphous semiconductor channel layer, the semiconductor (e.g., silicon) in the channel layer 170 is nucleated to form a nucleated substrate. Nucleating the substrate includes heating the substrate during exposure to the hydrogen and / or deuterium radical species.

[0039]

[0044] In some embodiments, the substrate in a first processing chamber (e.g., 328 shown in Figures 4A and 4B) is heated to a first temperature of about 100°C to about 1100°C, e.g., about 400°C to about 1100°C, e.g., about 200°C to about 800°C, e.g., about 300°C to about 700°C, about 400°C to about 600°C, e.g., about 500°C, etc. In at least one embodiment, the substrate having high aspect features is exposed to hydrogen and / or deuterium radical species at about 100°C to about 1100°C, e.g., about 400°C to about 600°C, for a first time period of about 1 minute to about 60 minutes, e.g., about 5 minutes to about 20 minutes, e.g., about 5 minutes to about 10 minutes, or about 10 minutes to about 15 minutes.

[0040]

[0045] The flow rate of hydrogen or deuterium radical species into the first thermal treatment space 308 is about 10 sccm to about 5000 sccm, for example, about 100 sccm to about 1500 sccm. The total flow rate of gas containing radical species into the first thermal treatment space 308 is about 10 sccm to about 5000 sccm, for example, about 100 sccm to about 1500 sccm. The first temperature of the first thermal treatment chamber is about 100° C. to about 1100° C. In at least one embodiment, substrates having high aspect ratio features are treated with radical species at about 450° C. to about 550° C. for about 5 minutes to about 10 minutes.

[0041]

[0046] The pressure of the first thermal treatment chamber is at least about 10 mTorr to about 530 Torr, for example, about 10 mTorr to about 10 Torr. The pressure of the first thermal treatment chamber is controlled by increasing the gas flow rate from the gas line to the first thermal treatment chamber and / or decreasing the gas flow rate pumped out of the first thermal treatment chamber. In some embodiments, which can be combined with other embodiments described herein, the hydrogen gas flow is fixed and the pressure is controlled by adjusting (e.g., increasing) the flow rate of the inert gas to the first thermal treatment chamber. The increase in the amount of inert gas in the first thermal treatment increases the chamber pressure of the first thermal treatment chamber, which can absorb and combine radical species in the thermal treatment chamber. Under certain conditions, this reduces etching of the channel layer of the channel structure caused by a large amount of hydrogen and / or deuterium radical species.

[0042]

[0047] Without being bound by theory, it is believed that treating the amorphous or polycrystalline semiconductor material of the semiconductor channel layer 170 with radical species, such as hydrogen and / or deuterium radicals, can lower the activation energy required for nucleation and grain growth of the semiconductor material. Specifically, it is believed that the radicals can be inserted into the semiconductor lattice structure to create "seeds" for grain growth and increase the crystallinity of the semiconductor material during the annealing process. The insertion of hydrogen or deuterium radical species can break / relax semiconductor atomic bonds, such as Si-Si bonds, and cause rearrangements. These rearrangements can reduce the amount of heat typically required to crystallize the material by lowering the activation energy for nucleation. It has been discovered that using high temperatures, such as from about 400° C. to about 1100° C., e.g., 400° C. to about 600° C., during the radical annealing process can result in good semiconductor grain growth for several reasons.

[0043]

[0048] First, high temperatures increase the non-absorption efficiency of H radicals on the semiconductor surface, thus minimizing etching of the semiconductor caused by radical species. Without being bound by theory, it is believed that radical species (e.g., hydrogen and / or deuterium) can react with semiconductor atoms to form volatile hydrogen, semiconductor compounds (e.g., silicon compounds) that can etch the semiconductor channel layer 170 (e.g., Si layer). At high temperatures, non-absorption of radicals such as hydrogen radicals increases, and the radicals do not have time to react with the semiconductor material before leaving the surface of the semiconductor material.

[0044]

[0049] Second, the use of high temperatures during the radical annealing process increases both the diffusion coefficient and the diffusion length of hydrogen or deuterium radical species in the semiconductor layer, which may increase the efficiency of nucleation inside the amorphous semiconductor layer. Third, the high temperatures during the annealing process provide more thermal energy for semiconductor atoms to move and rearrange into a crystalline structure. Silicon, germanium, germanium alloys, silicon alloys, and combinations thereof may benefit as well. Method 500 may optionally include heating the nucleation substrate in a second heat treatment chamber having the first processing space or the second processing space in step 506. The second heat treatment chamber is an oven or furnace, such as a large industrial furnace, a box furnace, a split box furnace, a tube furnace, a split tube furnace, a multi-zone split tube furnace, and / or a small batch furnace. In some embodiments that may be combined with any of the embodiments of the present disclosure, the second heat treatment chamber is the same as the first heat treatment chamber. For example, the radical species treatment in step 506 of method 500 is performed in the same chamber as the heating in step 504. Heating the substrate in the second processing space allows for several substrates to be heated simultaneously, allowing additional substrates to be processed in the first processing chamber, thus increasing the overall process throughput.

[0045]

[0050] The nucleation substrate having high aspect ratio features is heated in the second processing chamber to a second temperature of about 100° C. to about 1100° C., e.g., about 400° C. to about 400° C., or about 600° C. to about 800° C., e.g., about 700° C. As used herein, the term “nucleation substrate” refers to a substrate that has been treated with hydrogen or deuterium radical species to form nucleation sites. Nucleation sites are sites onto which further atoms deposit as crystals grow to form structural patterns characterized in crystalline solids. The nucleation substrate may be partially crystallized or fully crystallized depending on the degree of crystallization introduced by the treatment. The nucleation substrate having high aspect ratio features is annealed in the second processing chamber 352 for a second time period, e.g., at least about 1 minute, e.g., about 10 minutes to about 1 hour, e.g., about 20 minutes to 40 minutes, e.g., about 30 minutes. In at least one embodiment, the second processing chamber can be operated at atmospheric pressure or reduced pressure, such as from about 1 Torr to about 760 Torr. In some embodiments, which can be combined with other embodiments, step 506 can be performed in the first thermal treatment space 308. In some embodiments, the first thermal treatment space 308 can be evacuated via a gas pump 316, and the nucleation substrate can be heated in the first thermal treatment space. The total processing time from step 504 to step 506 is less than about 3 hours, such as from about 0.5 hours to about 2 hours, such as about 1.5 hours. In some embodiments, steps 504 and 506 can be performed in a first processing chamber, and the total processing time for steps 504 and 506 can be at least about 1 minute, such as from about 10 minutes to about 1 hour, such as from about 20 minutes to about 40 minutes, such as about 30 minutes.

[0046]

[0051] In some embodiments, which may be combined with other embodiments described herein, a high dosage of hydrogen or deuterium radical species, such as from about 300 sccm to about 1500 sccm, is used in the first thermal treatment space 308 while heating the substrate at the first temperature in the first thermal treatment chamber for a first time, for example, from about 5 minutes to about 10 minutes, before transferring the substrate to the second thermal treatment space for additional heating at the second temperature for a second time. Alternatively, a high dosage of hydrogen or deuterium radical species, such as a flow rate of from about 300 sccm to about 1500 sccm, is used in the first thermal treatment space 308 while heating the substrate at the first temperature in the first thermal treatment chamber for a first time, and the flow rate of the radical species is turned off or reduced for additional heating at the second temperature for a second time. The dosage of hydrogen or deuterium radical species provided herein is sufficiently high and the duration provided herein is sufficiently long for hydrogen to be inserted into the substrate for nucleation processing without substantially etching the substrate. The doses provided herein are also high enough to account for potential outgassing of hydrogen while the substrate is being heated to the second temperature. Outgassing of hydrogen from the substrate inhibits grain growth. Heating the substrate in a second processing space, such as a furnace, provides the advantage of simultaneously processing multiple substrates in the furnace.

[0047]

[0052] In some embodiments, which may be combined with other embodiments described herein, a low dosage of hydrogen or deuterium radical species, such as from about 10 sccm to about 100 sccm, is used in the first thermal treatment space 308 while heating the substrate at the first temperature in the first thermal treatment chamber for a third period of time, such as a total processing time from steps 504 to 506, such as from about 5 minutes to about 1 hour.

[0048]

[0053] In some embodiments that can be combined with other embodiments described herein, the second temperature is lower than the first temperature. The second temperature disclosed herein has been found to be high enough to promote grain growth and low enough to reduce the possibility of excessive nucleation. "Nucleation" refers to the formation of nucleation sites, and the term "excessive nucleation" refers to the formation of more than the intended number of nucleation sites. It has been found that excessive nucleation in regions of the substrate results in a lower average grain size. In some embodiments that can be combined with other embodiments described herein, the second temperature is about 5% to 50% lower than the first temperature, such as about 10% to about 30% lower, such as about 20% lower. The process disclosed herein provides a conformal grain size from the top to the bottom of the channel structure.

[0049]

[0054] According to at least one embodiment, which may be combined with other embodiments, one or more steps of the above-mentioned method may be included as instructions in a computer-readable medium for execution by a control unit (e.g., a controller module) or any other processing system. The computer-readable medium may include any suitable memory for storing instructions, such as a random access memory (RAM), a read-only memory (ROM), a floppy disk, a hard disk, a flash drive, or any other form of local or remote digital storage. As an example, and in some aspects of the present disclosure, a system is provided that is programmed to execute a method including an algorithm stored in a memory of the system. The algorithm may have a number of instructions that, when executed by a processor, cause the method to be executed. The method may include positioning a substrate in a first processing chamber having a first processing space, the first processing space being in fluid communication with a gas line, the substrate having high aspect ratio features with an aspect ratio greater than about 20:1, such as from about 20:1 to about 1000:1, such as from about 50:1 to about 500:1, such as from about 100:1 to about 300:1. The method 500 may further include forming radical species in the remote plasma source and exposing a substrate in the first processing chamber to the radical species to form a nucleation substrate. The nucleation substrate may be positioned in a second processing chamber having a second processing space, and the substrate may be heated in the second processing chamber, for example, to a temperature higher or lower than that of the first processing chamber.

Claims

1. A method for processing a substrate, comprising the steps of: positioning the substrate including a channel structure having an aspect ratio greater than 20:1 in a first processing chamber including a first processing space; exposing the silicon-containing layer of the channel structure to a hydrogen or deuterium plasma in the first process space at a flow rate of 10 sccm to 5000 sccm, wherein the substrate is maintained at a first temperature of 100° C. to 1100° C. during the exposure, and wherein the exposure forms a nucleation substrate; performing a thermal annealing step on the substrate after said exposing at a second temperature that is 5% to 50% lower than the first temperature; Including, The silicon-containing layer is a polycrystalline silicon-containing layer or an amorphous silicon-containing layer. method.

2. The method of claim 1 , wherein the hydrogen or deuterium plasma is formed from a hydrogen or deuterium containing gas in a remote plasma source.

3. The hydrogen or deuterium-containing gas is He, Ne, Ar, Kr, Xe, N ２ or a combination thereof, and H ２ , D ２ , N.H. ３ or a combination thereof The method of claim 2 , comprising:

4. Positioning the nucleation substrate in a second process chamber including a second process space; performing the thermal annealing process on the substrate; The method of claim 1 further comprising:

5. 5. The method of claim 4, wherein the thermal annealing step is carried out at a pressure of 1 Torr to 3800 Torr for a time period of 10 minutes to 3 hours.

6. 2. The method of claim 1 , wherein exposing the silicon-containing layer in the first process space to the hydrogen or deuterium plasma comprises flowing the hydrogen or deuterium plasma into the first process space at a flow rate between 100 sccm and 1500 sccm.

7. 10. The method of claim 1, wherein exposing the substrate in the first processing space occurs at a pressure of 10 mTorr to 530 Torr for 1 minute to 30 minutes.

8. The method of claim 1 , wherein the hydrogen or deuterium plasma is formed using an inductively coupled plasma source.

9. A system including an algorithm stored in a memory of the system, the algorithm including a number of instructions that, when executed by a processor, causes the system to perform the method of claim 1.

10. 1. A method of fabricating a memory device on a substrate, comprising: forming a channel structure in the membrane stack by etching a channel in the membrane stack and disposing a channel layer on bottom and interior surfaces of the channel, the channel structure in the membrane stack having an aspect ratio of greater than 20:1; exposing the channel structure to hydrogen radicals in a first processing space of a first processing chamber; heating the channel structure to a first temperature of 100° C. to 1100° C.; heating the channel structure in a second processing space at a second temperature that is 5% to 50% lower than the first temperature; Including, The channel layer is an amorphous layer or a polycrystalline layer. method.

11. 11. The method of claim 10, wherein exposing the channel structure to hydrogen radicals and heating the channel structure comprises heating the channel structure in the first processing space at a temperature between 400° C. and 1100° C. for 1 minute to 30 minutes.

12. 11. The method of claim 10, wherein the film stack is a 3D NAND film stack and the channel layer is an amorphous or polycrystalline layer comprising 0 weight percent to 100 weight percent silicon and 0 weight percent to 100 weight percent III, IV, and V elements.

13. 11. The method of claim 10, further comprising forming the film stack, wherein forming the film stack comprises depositing alternating oxide and nitride layers or depositing alternating oxide and polysilicon layers.

14. A method for processing a substrate, comprising the steps of: forming an amorphous silicon-containing layer on a bottom and an inner surface of a channel formed in a film stack of the substrate, the film stack including alternating oxide and nitride layers (ON) or alternating oxide and polysilicon layers (OP); exposing the amorphous silicon-containing layer to hydrogen radicals; heating the substrate to a first temperature of 100° C. to 1100° C. to form a nucleation silicon-containing layer of the substrate; heating the nucleation silicon-containing layer at a second temperature that is 5% to 50% lower than the first temperature; The method includes:

15. 15. The method of claim 14, wherein the amorphous silicon-containing layer and channel of the substrate form high aspect ratio features having an aspect ratio of greater than 20:

1.

16. 15. The method of claim 14, further comprising heating the substrate to the first temperature in a first processing space of a first process chamber and heating the nucleation silicon-containing layer of the substrate to the second temperature in a second processing space of a second process chamber.

17. 17. The method of claim 16, wherein a flow rate of the hydrogen radicals into the first process space is between 10 sccm and 5000 sccm.

18. 17. The method of claim 16, further comprising heating the substrate in the first processing space at a temperature between 400° C. and 1100° C. for 1 minute to 30 minutes.

19. 15. The method of claim 14, further comprising heating the nucleation silicon-containing layer of the substrate at a temperature of 400° C. to 1100° C. at a pressure of 1 Torr to 3800 Torr for 10 minutes to 3 hours.

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