Hybrid Smart Verification for QLC / TLC Dyes

Abstract

To provide a device and a method for smart verification in a memory system having a program mode with four bits per cell (or X4 mode) and having a program mode with three bits per cell (or X3 mode), and a nonvolatile storage system.SOLUTION: In a process X3 mode of state-dependent smart verification in a memory system, a 3-bit gray code based on a 4-bit gray code in an X4 mode is used and the verification of a state in the X3 mode is skipped while using a large portion of a programming logic from the X4 mode, and B state verification is skipped in one X3 mode while the number of memory cells having Vt exceeding an A state verification voltage is less than a threshold value, and in one X3 mode, it is determined whether or not to skip the verification of a first set of data states based on a first test and it is determined whether or not to skip the verification of a second set of data states in a second test.SELECTED DRAWING: Figure 8

Description

[Background technology]

[0001] The present disclosure relates to non-volatile memories.

[0002] Semiconductor memory is widely used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, electronic medical devices, mobile computing devices, servers, solid state drives, non-mobile computing devices, and other devices. Semiconductor memory may include non-volatile memory or volatile memory. Non-volatile memory allows the non-volatile memory to store and retain information even when it is not connected to a power source (e.g., a battery).

[0003] A memory structure in a memory system typically includes many memory cells and various control lines. The memory structure may be three-dimensional. One type of three-dimensional structure has non-volatile memory cells arranged as vertical NAND strings. The memory structure may be organized into units commonly referred to as physical blocks. For example, a block in a NAND memory system includes many NAND strings. A NAND string includes serially connected memory cell transistors, a drain side select gate at one end, and a source side select gate at the other end. Each NAND string is associated with a bit line. A block typically has many word lines that provide voltages to the control gates of the memory cell transistors. In some architectures, each word line connects to the control gate of one memory cell on each respective NAND string in the block.

[0004] In a memory such as NAND, a large set of memory cells is first erased. The set of memory cells erased as a unit is referred to herein as an "erase block." In some cases, an erase block coincides with a physical block. In some cases, an erase block is a portion of a physical block. The memory cells in the erase block are then programmed, one group at a time. The unit of programming is typically referred to as a physical page of memory cells. Non-volatile memory cells may be programmed to store data. Typically, memory cells are programmed into several data states. Using a larger number of data states allows more bits to be stored per memory cell. For example, four data states may be used to store two bits per memory cell, eight data states may be used to store three bits per memory cell, sixteen data states may be used to store four bits per memory cell, etc. Some memory cells may be programmed into a data state by storing a charge. For example, the threshold voltage (Vt) of a NAND memory cell may be set to a target Vt by programming a charge into a charge storage region, such as a charge trapping layer. The amount of charge stored in the charge trapping layer establishes the Vt of the memory cell.

[0005] During a program operation, a series of programming voltage pulses are applied to the control gates of the memory cells. Each voltage pulse may step up in magnitude from the previous program pulse by a step size in a process called incremental step pulse programming. The program voltages may be followed by one or more verify operations to determine if the memory cells have been programmed to the corresponding one or more target data states. In some techniques, only a subset of the target verify states are verified after the program pulse. Each verify operation takes a finite amount of time. Thus, reducing the total number of verify operations reduces programming time. Reducing the total number of verify operations also saves current and / or power.

[0006] However, there are technical challenges in determining which state should be verified after a given program pulse. Over-programming of a memory cell in a target state can occur if verifying the target state is skipped after a program pulse. On the other hand, verifying the target state too early in the programming process can waste time, current and / or power. [Brief description of the drawings]

[0007] Similarly numbered elements refer to common components in different figures. [Figure 1] 1 is a block diagram illustrating one embodiment of a storage system. [Figure 2A] FIG. 2 is a block diagram of one embodiment of a memory die. [Figure 2B] FIG. 1 is a block diagram of one embodiment of an integrated memory assembly. [Figure 3A] 1 illustrates different embodiments of an integrated memory assembly. [Figure 3B] 1 illustrates different embodiments of an integrated memory assembly. [Figure 3C] FIG. 2 is a block diagram illustrating one embodiment of a portion of a column control circuit including several read / write circuits. [Figure 4] 1 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory structure; [Figure 4A] FIG. 2 is a block diagram of one embodiment of a memory structure having two planes. [Figure 4B] FIG. 2 is a block diagram showing a top view of a portion of a physical block from a memory cell. [Figure 4C] FIG. 4C illustrates an embodiment of the stack showing a cross-sectional view along line AA of FIG. 4B. [Figure 4D] A diagram of area 445 of FIG. 4C is shown. [Figure 4E] 1 is a schematic diagram of a portion of one embodiment of a physical block, showing several NAND strings. [Figure 5A]1 illustrates one embodiment of threshold voltage Vth distributions for a four-state memory device in which each memory cell stores two bits of data. [Figure 5B] 1 illustrates one embodiment of threshold voltage Vth distributions for an 8-state memory device in which each memory cell stores 3 bits of data. [Figure 5C] 1 illustrates one embodiment of threshold voltage Vth distributions for a 16-state memory device in which each memory cell stores 4 bits of data. [Figure 6] FIG. 1 is a flow diagram illustrating one embodiment of a process for programming memory cells. [Figure 7A1] 1 is a table of an exemplary Gray code used to represent 16 data states. [Figure 7A2] 7A is a table of example Gray codes used to represent eight data states that may be generated from the example Gray code of FIG. 7A1. [Figure 7A3] 7A illustrates one embodiment of threshold voltage distributions for an 8-state memory device, with each memory cell storing 3 bits of data, programmed using the example Gray code of FIG. 7A2. [Figure 7A4] FIG. 7A illustrates one embodiment of threshold voltage distributions for an 8-state memory device, with each memory cell storing 3 bits of data, programmed using the example Gray code of FIG. 7A2 with adjusted verify levels. [Figure 8] FIG. 13 is a flow diagram of one embodiment of a process for state-dependent smart verify in a memory system using both X3 and X4 modes. [Figure 9] 1 illustrates one possible scheme for verifying a memory cell. [Figure 10A] 1 illustrates a portion of the programming process for two different dies that program at different speeds. [Figure 10B] 1 illustrates a portion of the programming process for two different dies that program at different speeds. [Figure 11] A possible scheme to prevent over-programming is presented, regardless of whether there is a slower or faster programming die. [Figure 12] Shows an embodiment of a smart verification method for X3 programming. [Figure 13] It is a flowchart of an embodiment of a process of combining smart PVC and manual PVC for X3 programming. [Figure 14] It is a flowchart of an embodiment of a process of state-dependent smart verification for X3 programming. [Figure 15] It is a flowchart of another embodiment of a process of state-dependent smart verification for X3 programming. [Figure 16B1] It is a table of exemplary Gray codes used to represent 16 data states. [Figure 16B2] It is a table of exemplary Gray codes used to represent 8 data states that may be generated from the exemplary Gray code of FIG. 16B1. [Figure 16B3] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16B2. [Figure 16B4] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16B2 with an adjusted verification level. [Figure 16C1] It is a table of exemplary Gray codes used to represent 16 data states. [Figure 16C2] It is a table of exemplary Gray codes used to represent 8 data states that may be generated from the exemplary Gray code of FIG. 16C1. [Figure 16C3] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16C2. [Figure 16C4] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16C2 with an adjusted verification level. [Figure 16D1] An exemplary Gray code table used to represent 16 data states. [Figure 16D2] An exemplary Gray code table used to represent 8 data states that may be generated from the exemplary Gray code of FIG. 16D1. [Figure 16D3] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16D2. [Figure 16D4] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16D2 with an adjusted verification level. [Figure 16E1] An exemplary Gray code table used to represent 16 data states. [Figure 16E2] An exemplary Gray code table used to represent 8 data states that may be generated from the exemplary Gray code of FIG. 16E1. [Figure 16E3] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16E2. [Figure 16E4] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16E2 with an adjusted verification level. [Figure 16F1] An exemplary Gray code table used to represent 16 data states. [Figure 16F2] An exemplary Gray code table used to represent 8 data states that may be generated from the exemplary Gray code of FIG. 16F1. [Figure 16F3] Shows an embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16F2. [Figure 16F4]An embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16F2 having an adjusted verification level, is shown. [Figure 16G1] It is a table of an exemplary Gray code used to represent 16 data states. [Figure 16G2] It is a table of an exemplary Gray code used to represent 8 data states that may be generated from the exemplary Gray code of FIG. 16G1. [Figure 16G3] An embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16G2, is shown. [Figure 16G4] An embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16G2 having an adjusted verification level, is shown. [Figure 16H1] It is a table of an exemplary Gray code used to represent 16 data states. [Figure 16H2] It is a table of an exemplary Gray code used to represent 8 data states that may be generated from the exemplary Gray code of FIG. 16H1. [Figure 16H3] An embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16H2, is shown. [Fig. 16H4] An embodiment of the threshold voltage distribution of an 8-state memory device in which each memory cell stores 3-bit data, programmed using the exemplary Gray code of FIG. 16H2 having an adjusted verification level, is shown.

DETAILED DESCRIPTION OF THE INVENTION

[0008] Techniques are disclosed herein for smart verify in a memory system capable of programming data in different multi-bit modes for each cell. In one embodiment, the memory system programs memory cells in a memory structure in a 4-bits-per-cell mode (or X4 mode) and a 3-bits-per-cell mode (or X3 mode). The 4-bits-per-cell mode uses a 4-bit Gray code with 4 pages and 16 data states. The 3-bit Gray code uses a 3-bit Gray code based on the 4-bit Gray code. The 3-bit Gray code is based on 3 of the 4 pages of the 4-bit Gray code. By basing the 3-bit code on 3 of the 4 pages of the 4-bit Gray code, a significant portion of the logic used to program 4 bits per cell can also be used to program 3 bits per cell. However, because the 3-bit Gray code uses only 8 of the 16 states from the 4-bit Gray code, verifying using the 3-bit Gray code poses technical challenges. In particular, the logic that determines which states should be skipped for verify in the X4 programming mode may not be suitable for use to skip verify in the X3 programming mode. Disclosed herein are techniques for skipping verification of states in the X3 programming mode while still allowing a significant portion of the programming logic from the X4 programming mode to be used in the X3 programming mode.

[0009] In one embodiment, in the X3 programming mode, the memory system counts the number of memory cells having a threshold voltage above the verify voltage of the A state (of the A-G states in the X3 mode) after each program pulse. The verify of the B state is skipped on the next program-verify (PV) loop in response to the number of memory cells having a threshold voltage above the verify voltage of the A state falling below the threshold for the PV loop. The verify of the B state begins on the next PV loop after the first time that the number of memory cells having a threshold voltage above the verify voltage of the A state exceeds the threshold. By waiting to verify the B state until a sufficient number of cells have a Vt above the A state verify voltage, the memory system avoids verifying the B state too early. Thus, time, power and / or current are saved. Also, the memory system avoids verifying the B state too late. Thus, over-programming of the B state cells is avoided. The verify can be started for the remaining states based on different factors in various embodiments. In one embodiment, the verify of each other state begins a predetermined number of PV loops after the verify of the preceding state is started.

[0010] In one embodiment, the memory system determines whether to skip verification of a first set of one or more data states in the X3 programming mode based on a first test and determines whether to skip verification of a second set of one or more data states in the X3 programming mode based on a second test. In one embodiment, the first set includes data states that follow an unused state in the 4-bit code, but does not include any data states that follow a used state in the 4-bit code. In one embodiment, the second set includes all data states that follow a used state in the 4-bit code.

[0011] FIG. 1 is a block diagram of one embodiment of a storage system 100 implementing the technology described herein. In one embodiment, the storage system 100 is a solid state drive ("SSD"). The storage system 100 may also be a memory card, a USB drive, or other type of storage system. The proposed technology is not limited to any one type of storage system. The storage system 100 is connected to a host 102, which may be a computer, a server, an electronic device (e.g., a smartphone, tablet, or other mobile device), an appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from the storage system 100, but is connected to the storage system. In other embodiments, the storage system 100 is embedded within the host 102.

[0012] The components of storage system 100 shown in Figure 1 are electrical circuits. Storage system 100 includes a memory controller 120 (or storage controller) connected to non-volatile storage 130 and local high-speed memory 140 (e.g., DRAM, SRAM, MRAM). Local memory 140 is a non-transitory memory that may include volatile or non-volatile memory. Local high-speed memory 140 is used by memory controller 120 to perform certain operations. For example, local high-speed memory 140 may store a logical-to-physical address translation table ("L2P table").

[0013] The memory controller 120 includes a host interface 152 that is connected to and communicates with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVM Express, NVMe) over PCI Express (PCI Express, PCIe). Other interfaces such as SCSI, SATA, etc. may also be used. The host interface 152 is also connected to a network-on-chip (NOC) 154. A NOC is a communication subsystem on an integrated circuit. A NOC can span synchronous and asynchronous clock domains or use unlocked asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, providing significant improvements over traditional buses and crossbar interconnects. NOCs improve the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs compared to other designs. The wires and links of a NOC are shared by many signals. A high level of parallelism is achieved because all links in a NOC can operate simultaneously on different data packets. Thus, as the complexity of integrated subsystems continues to grow, the NOC provides improved performance (e.g., throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, and local memory controller 164 are connected to and in communication with the NOC 154. The local memory controller 164 is used to operate and communicate with the local high-speed memory 140 (e.g., DRAM, SRAM, MRAM).

[0014] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs data encoding and decoding. In one embodiment, the ECC engine 158 is an electrical circuit programmed by software. For example, the ECC engine 158 may be a processor that can be programmed. In another embodiment, the ECC engine 158 is a custom dedicated hardware circuit without any software. In another embodiment, the functionality of the ECC engine 158 is implemented by the processor 156.

[0015] The processor 156 performs various controller memory operations such as programming, erasing, reading, and memory management processes. In one embodiment, the processor 156 is programmed by firmware. In another embodiment, the processor 156 is a custom dedicated hardware circuit without any software. The processor 156 also implements a translation module as a software / firmware process or as a dedicated hardware circuit. In many systems, non-volatile memory is addressed internally to the storage system using physical addresses associated with one or more memory dies. However, the host system uses logical addresses to address various memory locations. This allows the host to assign data to contiguous logical addresses, while the storage system is free to store data between one or more memory die locations at will. To implement this system, the memory controller 120 (e.g., a translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory dies. One exemplary implementation is to maintain a table (i.e., the L2P table described above) that identifies the current translation between logical addresses and physical addresses. Entries in the L2P table may include identifiers for logical addresses and corresponding physical addresses. Although the logical address to physical address table (i.e., L2P table) includes the word "table," it does not have to be a literal table. Rather, the physical address to logical address table (i.e., L2P table) can be any type of data structure. In some examples, the memory space of the storage system is so large that the local memory 140 cannot hold all of the L2P tables. In such cases, the entire set of L2P tables is stored in the storage device 130, and a subset of the L2P tables is cached in the local high-speed memory 140 (the L2P cache).

[0016] Memory interface 160 communicates with non-volatile storage 130. In one embodiment, the memory interface provides a toggle mode interface. Other interfaces may be used. In some example implementations, memory interface 160 (or another portion of controller 120) implements a scheduler and buffers for sending and receiving data from one or more memory dies.

[0017] In one embodiment, the non-volatile storage device 130 comprises one or more memory dies. FIG. 2A is a functional block diagram of one embodiment of a memory die 200 comprising the non-volatile storage device 130. Each of the one or more memory dies of the non-volatile storage device 130 can be implemented as the memory die 200 of FIG. 2A. The components shown in FIG. 2A are electrical circuits. The memory die 200 includes a memory structure 202 (e.g., a memory array) that can include non-volatile memory cells (also referred to as non-volatile storage cells), as described in more detail below. The array demarcation lines of the memory structure 202 include various layers of word lines organized as rows and various layers of bit lines organized as columns. However, other orientations can also be implemented. The memory die 200 includes a row control circuit 220, the output of which is connected to each word line of the memory structure 202. The row control circuit 220 receives a group of M row address signals and one or more various control signals from the system control logic 260 and typically includes circuits such as a row decoder 222, an array driver 224, and a block select circuit 226 for both read and write (programming) operations. The row control circuit 220 may also include read / write circuitry. The memory die 200 also includes a column control circuit 210 that includes a read / write circuit 225. The read / write circuit 225 may include sense amplifiers and data latches. The inputs / outputs of the sense amplifiers are connected to respective bit lines of the memory structure 202. Although only a single block is shown for the structure 202, the memory die may include multiple arrays that can be accessed individually. The column control circuit 210 receives a group of N column address signals and one or more various control signals from the system control logic 260 and typically includes circuits such as a column decoder 212, an array termination receiver or driver circuit 214, and a read / write circuit 225 and an I / O multiplexer.

[0018] System control logic 260 receives data and instructions from memory controller 120 and provides output data and status to the host. In some embodiments, system control logic 260 (comprising one or more electrical circuits) includes a state machine 262 that provides die-level control of memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 is implemented completely in hardware (e.g., electrical circuits) without the use of software. In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor, either on the memory chip or off the memory chip. System control logic 260 also includes a power control module 264 that controls power and voltage supplied to rows and columns of memory structure 202 during memory operations. System control logic 260 includes storage 266 (e.g., RAM, registers, latches, etc.) that may be used to store parameters for operating memory structure 202.

[0019] Commands and data are transferred between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as a "communications interface"). Memory controller interface 268 is an electrical interface for communicating with memory controller 120. Examples of memory controller interface 268 include a toggle mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used.

[0020] In some embodiments, all of the elements of memory die 200, including system control logic 260, may be formed as part of a single die. In other embodiments, some or all of system control logic 260 may be formed on a die different from the die that includes memory structures 202.

[0021] In one embodiment, the memory structure 202 includes a three-dimensional memory array of non-volatile memory cells with multiple memory levels formed on a single substrate, such as a wafer. The memory structure may include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active areas disposed on a silicon (or other type) substrate. In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0022] In another embodiment, the memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells that utilize floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0023] The exact type of memory array architecture or memory cells included in memory structure 202 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. No particular non-volatile memory technology is required for the purposes of the newly claimed embodiments proposed herein. Other examples of technologies suitable for memory cells of memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), etc. Examples of technologies suitable for memory cell architectures of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, etc.

[0024] An example of a ReRAM cross-point memory includes reversible resistance-switching elements arranged in a cross-point array accessed by X- and Y-lines (e.g., word and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state-changing element based on the physical rearrangement of ions in a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes with a thin solid electrolyte film between the two electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper). As the temperature increases, the mobility of the ions also increases, lowering the programming threshold of the conductive bridge memory cell. Thus, a conductive bridge memory element may have a wide range of programming thresholds over temperature.

[0025] Another example is magnetoresistive random access memory (MRAM), which stores data by means of magnetic memory elements. The elements are formed from two ferromagnetic layers, each capable of retaining magnetization, separated by a thin insulating layer. One of the two layers is a permanent magnet set to a specific polarity. The magnetization of the other layer can be changed to match that of an external field to store memory. Memory devices are built from a grid of such memory cells. In one embodiment for programming, each memory cell is between a pair of write lines placed at right angles to each other and parallel to the cell, one above the cell and one below the cell. When a current is passed through them, an induced magnetic field is generated. MRAM-based memory embodiments are discussed in more detail below.

[0026] Phase change memory (PCM) exploits the unique behavior of chalcogenide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply changing the coordination state of the germanium atoms with a laser pulse (or a light pulse from another light source). Thus, the programming dose is the laser pulse. The memory cell can be inhibited by blocking the memory cell from receiving light. In other PCM embodiments, the memory cell is programmed with a current pulse. The use of "pulse" in this document does not require a square pulse, but includes vibrations or bursts of sound (continuous or non-continuous), current, voltage light, or other waves. These memory elements, or bits, within the individual selectable memory cells can include further series elements that are selectors, such as Ovonic threshold switches or metal-insulator substrates.

[0027] Those skilled in the art will appreciate that the technology described herein is not limited to a single particular memory structure, memory architecture, or material composition, but rather covers many related memory structures within the spirit and scope of the technology as described herein and understood by those skilled in the art.

[0028] The elements of FIG. 2A can be grouped into two parts: (1) memory structures 202 and (2) peripheral circuits, which include all of the other components shown in FIG. 2A. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of ​​the memory die of the storage system 100 that is given to the memory structures 202, but this reduces the area of ​​the memory die available for the peripheral circuits. This can impose very severe limitations on these elements of the peripheral circuits. For example, the need to fit sense amplifier circuits within the available area can be a significant limitation on the sense amplifier design architecture. With respect to the system control logic 260, the reduced area availability can limit the available functions that can be implemented on-chip. Thus, a fundamental tradeoff in the design of a memory die for the storage system 100 is the amount of area devoted to the memory structures 202 and the amount of area devoted to the peripheral circuits.

[0029] Another area where memory structure 202 and peripheral circuits often conflict is in the processes involved in forming these regions, as these regions often involve different process technologies and the tradeoffs of having different technologies in a single die. For example, if memory structure 202 is a NAND flash, it is an NMOS structure, but the peripheral circuits are often CMOS based. For example, such sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuits in system control logic 260 often use PMOS devices. Process operations for manufacturing CMOS dies are in many aspects different from process operations optimized for NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures (see, for example, FIG. 4) in particular can benefit from specialized processing operations.

[0030] To remedy these limitations, the embodiments described below may separate the elements of FIG. 2A onto separately formed dies, which are then bonded together. More specifically, the memory structure 202 may be formed on one die (called the memory die), and some or all of the peripheral circuit elements, including one or more control circuits, may be formed on a separate die (called the control die). For example, the memory die may be formed with only memory elements, such as an array of memory cells of Flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory types. Some or all of the peripheral circuitry, even if it includes elements such as decoders and sense amplifiers, may then be moved to a separate control die. This allows each of the memory dies to be individually optimized according to its technology. For example, a NAND memory die may be optimized for an NMOS-based memory array structure without worrying about the CMOS elements being moved onto the control die, which may be optimized for a CMOS process. This allows more space for peripheral elements, which may then incorporate additional functionality that could not be easily incorporated if they were limited to the margins of the same die that holds the memory cell array. The two dies can then be bonded together in a bonded multi-die memory circuit, with the array on one die connected to the peripheral elements on the other die. The following focuses on a bonded memory circuit of one memory die and one control die, although other embodiments can use additional dies, such as, for example, two memory dies and one control die.

[0031] FIG. 2B illustrates an alternative arrangement to that of FIG. 2A that may be implemented using wafer-to-wafer bonding to provide a bonded die pair. FIG. 2B is a functional block diagram of one embodiment of an integrated memory assembly 207. One or more integrated memory assemblies 207 may be used to implement non-volatile storage 130 of storage system 100. Integrated memory assembly 207 includes two types of semiconductor dies (or more simply, "dies"). Memory structure die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuits 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to connect to memory structure 202 in memory structure die 201. In some embodiments, memory structure die 201 and control die 211 are bonded together.

[0032] 2B illustrates an example of peripheral circuitry including control circuitry formed in peripheral circuitry or control die 211 coupled to memory structures 202 formed in memory structure die 201. Common components are labeled similarly to FIG. 2A. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or a portion of column control circuitry 210 and all or a portion of row control circuitry 220 are located on memory structure die 201. In some embodiments, some of the circuitry in system control logic 260 is located on memory structure die 201.

[0033] System control logic 260, row control circuitry 220, and column control circuitry 210 may be formed by common processes (e.g., CMOS processes) such that adding elements and functionality such as ECC more typically found on memory controller 120 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 120 may also be used to fabricate system control logic 260, row control circuitry 220, and column control circuitry 210). Thus, moving such circuitry from a die such as memory structure die 201 may reduce the number of steps required to fabricate such a die, and adding such circuitry to a die such as control die 211 may not require many additional process steps. Control die 211 may also be referred to as a CMOS die due to the use of CMOS technology to implement some or all of control circuitry 260, 210, 220.

[0034] 2B illustrates column control circuitry 210 including read / write circuitry 225 on control die 211 coupled to memory structure 202 on memory structure die 201 through electrical pathways 206. For example, electrical pathways 206 may provide electrical connections between column decoder 212, driver circuitry 214, and R / W circuitry 225 and bitlines of memory structure 202. The electrical pathways may extend from column control circuitry 210 in control die 211 through pads on control die 211 that are bonded to corresponding pads on memory structure die 201 that are connected to the bitlines of memory structure 202. Each bitline of memory structure 202 may have a corresponding electrical pathway in electrical pathways 206 that includes a pair of bond pads that connect to column control circuitry 210. Similarly, row control circuitry 220 including row decoder 222, array driver 224, and block select 226 is coupled to memory structure 202 through electrical pathways 208. Each electrical pathway 208 may correspond to a wordline, a dummy wordline, or a select gate line. Additionally, additional electrical paths may be provided between the control die 211 and the memory structure die 201 .

[0035] For purposes of this specification, the phrase "control circuitry" or "one or more control circuits" may include any one or any combination of memory controller 120, state machine 262, power control 264, all or a portion of system control logic 260, all or a portion of row control circuitry 220, all or a portion of column control circuitry 210, read / write circuitry 225, sense amplifiers, microcontrollers, microprocessors, and / or other similarly functioning circuits. A control circuitry may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is one example of a control circuitry. A control circuitry may include a processor, an FPGA, an ASIC, an integrated circuit, or other types of circuits.

[0036] As used herein, the term "device" may include, but is not limited to, one or more of the memory system 100, memory controller 120, memory device 130, memory die 200, integrated memory assembly 207, and / or control die 211.

[0037] In some embodiments, there are two or more control dies 211 and two or more memory structure dies 201 in the integrated memory assembly 207. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control dies 211 and multiple memory structure dies 201. FIG. 3A shows a side view of one embodiment of an integrated memory assembly 207 (e.g., a stack including a control die 211 and a memory structure die) stacked on a substrate 271. The integrated memory assembly 207 has three control dies 211 and three memory structure dies 201. In some embodiments, there are four or more memory structure dies 201 and four or more control dies 211. In FIG. 3A, there are an equal number of memory structure dies 201 and control dies 211. However, in one embodiment, there are more memory structure dies 201 than control dies 211. For example, one control die 211 can control multiple memory structure dies 201.

[0038] Each control die 211 is affixed (e.g., bonded) to at least one of the memory structure dies 201. Some of the bond pads 282, 284 are shown. There may be more bond pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be made of epoxy or other resin or polymer. This fixing layer 280 protects the electrical connection between the dies 201, 211 and also secures the dies together. A variety of materials may be used for the fixing layer 280, but in an embodiment it may be Hysol epoxy resin from Henkel Corp. with offices in California, USA.

[0039] The integrated memory assemblies 207 may be stacked, for example, with a step offset, with the bond pads on each level uncovered and accessible from above. Wire bonds 270 connected to the bond pads connect the control die 211 to the substrate 271. Several such wire bonds may be formed across the full width of each control die 211 (i.e., within the page of FIG. 3A).

[0040] Memory die through silicon vias (TSVs) 276 may be used to route signals through the memory structure die 201. Control die through silicon vias (TSVs) 278 may be used to route signals through the control die 211. The TSVs 276, 278 may be formed before, during, or after the formation of the integrated circuits in the semiconductor die 201, 211. The TSVs may be formed by etching holes through the wafer. The holes may then be lined with a barrier to metal diffusion. The barrier layer may then be lined with a seed layer, which may be plated with a conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof may be used.

[0041] Solder balls 272 may optionally be affixed to contact pads 274 on the underside of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device, such as a printed circuit board. If integrated memory assembly 207 is used as an LGA package, solder balls 272 may be omitted. Solder balls 272 may form part of an interface between integrated memory assembly 207 and memory controller 120.

[0042] 3B shows a side view of another embodiment of an integrated memory assembly 207 stacked on a substrate 271. The integrated memory assembly 207 of FIG. 3B has three control dies 211 and three memory structure dies 201. In some embodiments, there are four or more memory structure dies 201 and four or more control dies 211. In this example, each control die 211 is bonded to at least one memory structure die 201. Optionally, the control die 211 may be bonded to two or more memory structure dies 201.

[0043] Some of the bond pads 282, 284 are shown. There may be many more bond pads. The space between the two dies 201, 211 bonded together is filled with a solid layer 280, which may be formed from epoxy or other resin or polymer. In contrast to the embodiment of FIG. 3A, the integrated memory assembly 207 of FIG. 3B does not have a step offset. Signals may be routed through the memory structure die 201 using through silicon vias (TSVs) 276 of the memory die. Signals may be routed through the control die 211 using control die through silicon vias (TSVs) 278.

[0044] Solder balls 272 may optionally be affixed to contact pads 274 on the underside of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory assembly 207 to a host device, such as a printed circuit board. If integrated memory assembly 207 is used as an LGA package, solder balls 272 may be omitted.

[0045] As briefly discussed above, the control die 211 and the memory structure die 201 may be bonded together. The bond pads on each die 201, 211 may be used to bond the two dies together. In some embodiments, the bond pads are directly bonded to each other in a so-called Cu-Cu bonding process, without solder or other added materials. In a Cu-Cu bonding process, the bond pads are formed in a highly controlled environment that is controlled to be highly flat and with few surrounding particulates that may otherwise settle on the bond pads and prevent a tight bond. Under such well-controlled conditions, the bond pads are aligned with each other and pressed together to form an interconnect bond based on surface tension. Such bonds may be formed at room temperature, although heat may also be applied. In embodiments using Cu-Cu bonding, the bond pads may be approximately 5 μm square and spaced apart from each other with a pitch of 5 μm to 5 μm. This process is referred to herein as Cu-Cu bonding, although the term may also be applied when the bond pads are formed of materials other than Cu.

[0046] If the bond pads are small in area, it may be difficult to bond the semiconductor dies together. The size of the bond pads and the pitch between the bond pads may be further reduced by providing a film layer on the surface of the semiconductor die that includes the bond pads. The film layer is provided around the bond pads. When the dies are brought together, the bond pads may bond together and the film layers on each die may bond together. Such a bonding technique may be referred to as hybrid bonding. In an embodiment using hybrid bonding, the bond pads may be approximately 5 μm square and spaced apart from each other with a pitch of 1 μm to 5 μm. Bonding techniques that provide bond pads with even smaller size and pitch may be used.

[0047] As mentioned above, some embodiments may include a film on the surfaces of the dies 201, 211. If such a film is not initially provided, the space between the dies may be underfilled with an epoxy or other resin or polymer. The underfill material may be applied as a liquid, which then solidifies into a solid layer. This underfill step protects the electrical connection between the dies 201, 211 and also secures the dies together. A variety of materials may be used as the underfill material.

[0048] 3C is a block diagram illustrating one embodiment of a portion of the column control circuit 210 that includes several read / write circuits 225. Each read / write circuit 225 is divided into a sense amplifier 325 and a data latch 340. A management circuit 330 controls the read / write circuits 225. The management circuit 330 can communicate with a state machine 262. In one embodiment, each sense amplifier 325 is connected to a respective bit line. Each bit line can be connected to one of many different NAND strings at a time. A select gate on the NAND string can be used to connect the NAND string channel to the bit line.

[0049] Each sense amplifier 325 operates to provide a voltage to one of the bit lines (see BL0, BL1, BL2, BL3) during program, verify, erase, and read operations. The sense amplifiers are also used to sense the condition (e.g., data state) of memory cells in the NAND strings connected to the bit lines that connect to the respective sense amplifiers.

[0050] Each sense amplifier 325 may have a sense node. During sensing, the sense node is charged to an initial voltage Vsense_init, such as 3V. The sense node is then connected to a bit line for a sensing time, and the attenuation of the sense node is used to determine whether the memory cell is in a conductive or non-conductive state. The attenuation of the sense node also indicates whether the current Icell in the memory cell exceeds the reference current Iref. A larger attenuation corresponds to a larger current. If Icell≦Iref, the memory cell is in a non-conductive state, and if Icell>Iref, the memory cell is in a conductive state. In one embodiment, the sense node has a capacitor that is precharged and then discharged for the sensing time.

[0051] In particular, the comparison circuit 320 determines the amount of decay by comparing the sense node voltage to the trip voltage after the sense time. If the sense node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is less than or equal to the verify voltage. If the sense node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is greater than the verify voltage. The sense node latch 322 is set to 0 or 1 by the comparison circuit 320, for example, based on whether the memory cell is in a conductive or non-conductive state, respectively. The bits in the sense node latch 322 can also be used in a lockout scan to determine whether to set the bit line voltage to the inhibit level or the program enable level in the next program loop. The bits in the sense node latch 322 can also be used in a lockout mode to determine whether to set the bit line voltage to the sense voltage or the lockout voltage in a read operation.

[0052] The data latches 340 are coupled to the sense amplifiers 325 by a local data bus 346. The data latches 340 include, in this example, four latches (ADL, BDL, CDL, DDL) for each sense amplifier 325. More or less than four latches may be included in the data latches 340. In one embodiment, for programming, each data latch 340 is used to store one bit to be stored in the memory cell, and for reading, each data latch 340 is used to store one bit read from the memory cell. In a four-bits-per-memory cell embodiment, the ADL stores bits of the bottom page of data, the BDL stores bits of the middle page of data, the CDL stores bits of the top page of data, and the DDL stores bits of the top page of data. Each read / write circuit 225 is connected to an XDL latch 348 by an XDL bus 352. In this example, transistor 336 connects the local data bus 346 to the XDL bus 352. The I / O interface 332 is connected to the XDL latch 348. The XDL latch 348 associated with a particular read / write circuit 225 serves as an interface latch for storing / latching data from the memory controller. In one embodiment, latch space is conserved by not including a DDL latch, but instead using an XDL latch 348 for the top page of data for at least a portion of a program operation. However, using an XDL latch 348 for the top page can slow down programming.

[0053] In one embodiment, the memory cells are programmed to 3 bits per cell using at least some of the programming algorithms for programming memory cells to 4 bits per cell. In one embodiment, the 3 bits per cell mode has a similar encoding scheme as the 4 bits per cell mode by using three of the four pages from the 4 bits per cell mode. In one embodiment, one of the latches 340 is set to a default value in the 3 bits per cell mode based on which page of the 4 page code is not used. For example, the 3 bit mode may use encoding from the bottom page, the middle page, and the top page of the 4 page code (thereby not using the top page). In this example, the first page of user data may be stored in the ADL latch, the second page of user data may be stored in the BDL latch, and the third page of user data may be stored in the DDL latch. However, the CDL latch may be set to a default value (e.g., all ones or all zeros). This technique simplifies the logic circuitry by allowing some of the 4 page code programming circuitry to be used for programming with the 3 page code. Techniques for verifying memory cells in a three-page programming mode are disclosed herein.

[0054] The managing circuit 330 performs calculations to determine data stored in the sensed memory cells and stores the determined data in a set of data latches. Each set of data latches 340 is used to store data bits determined by the managing circuit 330 during a read operation and to store data bits imported from the data bus 334 during a program operation that represent write data intended to be programmed into the memory. The I / O interface 332 provides an interface between the XDL latches 348 and the data bus 334.

[0055] During a read, the operation of the system is under the control of a state machine 262 that controls the supply of different control gate voltages to an addressed memory cell. By stepping through various predefined control gate voltages corresponding to various memory states supported by the memory, the sense circuit can trip at one of these voltages and a corresponding output will be provided from the sense amplifier to the managing circuit 330. At that point, the managing circuit 330 determines the resulting memory state by considering the trip event of the sense circuit and information about the applied control gate voltage from the state machine. It then calculates a binary encoding of the memory state and stores the resulting data bit in the data latch 340.

[0056] During a program or verify operation on a memory cell, data to be programmed (write data) may be stored in a set of data latches 340 from the data bus 334 by the XDL latch 348. A program operation applies a series of programming voltage pulses to the control gate of an addressed memory cell under the control of the state machine 262. Each voltage pulse may step up in magnitude from the previous program pulse by a step size in a process called incremental step pulse programming. In one embodiment, each program voltage is followed by a verify operation to determine if the memory cell has been programmed to the desired memory state. In some cases, the managing circuit 330 monitors the read back memory state for the desired memory state. When the two match, the managing circuit 330 sets the bit line in a program inhibit mode, such as by updating its latch. This inhibits further programming of the memory cell coupled to the bit line even if additional program pulses are applied to its control gate. It is noted that the verify phase need not verify all of the data states following each program pulse. Disclosed herein are embodiments for determining which data states should be verified following each program pulse in a three-page code.

[0057] FIG. 4 is a perspective view of a portion of an exemplary embodiment of a monolithic three-dimensional memory array / structure that may comprise a memory structure 202, including a plurality of non-volatile memory cells arranged as a vertical NAND string. For example, FIG. 4 shows a portion 400 of one block of memory. The structure shown includes a set of bit lines BL positioned on a stack 401 of alternating dielectric and conductive layers. As an example, one of the dielectric layers is marked as D and one of the conductive layers (also called word line layers) is marked as W. The number of alternating dielectric and conductive layers may vary based on the specific implementation requirements. In one embodiment, the alternating dielectric and conductive layers are divided into four (or a different number) regions (e.g., sub-blocks) by isolation regions IR. FIG. 4 shows one isolation region IR separating two sub-blocks. Below the alternating dielectric and word line layers is a source line layer SL. Memory holes are formed in the stack of alternating dielectric and conductive layers. For example, one of the memory holes is marked as MH. Note that in FIG. 4, the dielectric layers are shown as see-through so the reader can see the memory holes positioned within the stack of alternating dielectric and conductive layers. In one embodiment, a NAND string is formed by filling the memory holes with a material that includes a charge trapping material to create a vertical column of memory cells. Each memory cell can store one or more bits of data. Further details of a three-dimensional monolithic memory array comprising memory structure 202 are provided below.

[0058] FIG. 4A is a block diagram illustrating one exemplary configuration of memory structure 202 divided into two planes 403 and 405. Each plane is then divided into M physical blocks. In one embodiment, each plane has approximately 2000 physical blocks. However, a different number of physical blocks and planes can be used. In one embodiment, a physical block of memory cells is the unit of erase. That is, all memory cells of a physical block are erased together. In other embodiments, a physical block can be divided into sub-blocks, and a sub-block can be the unit of erase. Memory cells can be grouped into physical blocks for other reasons, such as to organize the memory structure to enable signaling and selection circuits. In some embodiments, a physical block represents a group of memory cells that are connected such that the memory cells of the block share a common set of word lines. For example, all word lines of a physical block are connected to all of the vertical NAND strings of that physical block. Although FIG. 4A shows two planes 403 / 405, more or less than two planes can be implemented. In some embodiments, memory structure 202 includes four planes. In some embodiments, memory structure 202 includes eight planes. In some embodiments, programming may be performed in parallel in a first selected block in plane 403 and a second selected block in plane 405.

[0059] 4B-4E illustrate an exemplary three dimensional ("3D") NAND structure corresponding to the structure of FIG. 4 and can be used to implement memory structure 202 of FIGS. 2A and 2B. FIG. 4B illustrates a top view of portion 407 of block 2. As shown in FIG. 4B, the blocks illustrated in FIG. 4B extend in the direction of arrow 433. In one embodiment, the memory array has many layers. However, FIG. 4B illustrates only the top layer.

[0060] FIG. 4B shows a number of circles representing vertical columns. Each of the vertical columns includes a number of select transistors (also referred to as select gates or selection gates) and a number of memory cells. In one embodiment, each vertical column implements a NAND string. For example, FIG. 4B shows vertical columns 422, 432, 442, 452, and 453. Vertical column 422 implements NAND string 482. Vertical column 432 implements NAND string 484. Vertical column 442 implements NAND string 486. Vertical column 452 implements NAND string 488. Vertical column 453 implements NAND string 486. Vertical column 452 implements NAND string 489. More details about the vertical columns are provided below. Because the physical block shown in FIG. 4B extends in the direction of arrow 433, the physical block includes more vertical columns than shown in FIG. 4B.

[0061] Figure 4B also shows a set of bit lines 415, including bit lines 411, 412, 413, 414, ... 419. Figure 4B shows 24 bit lines because it shows only a portion of a physical block. It is contemplated that more than 24 bit lines are connected to the vertical columns of the physical block. Each of the circles representing the vertical columns has an "x" indicating a connection to one bit line. For example, bit line 414 is connected to vertical columns 422, 432, 442, and 452.

[0062] The physical block shown in FIG. 4B includes a set of isolation regions 402, 404, 406, 408, 410, and 424 formed from SiO2. However, other dielectric materials may also be used. The isolation regions 402, 404, 406, 408, 410, and 424 serve to divide the top layer of the physical block into five regions. For example, the top layer shown in FIG. 4B is divided into regions 420, 430, 440, 450, and 460, which are called sub-blocks. In one embodiment, the isolation regions 402 and 424 separate the physical block 407 from adjacent physical blocks. Thus, the isolation regions 402 and 424 may extend down to the substrate. In one embodiment, the isolation regions 404, 406, and 410 only divide the layers used to implement the select gates so that the NAND strings in different sub-blocks can be selected independently. Referring back to FIG. 4, the IR region may correspond to any of the isolation regions 404, 406, or 408. In one exemplary implementation, a bit line connects to only one vertical column / NAND string in each of the regions (sub-blocks) 420, 430, 440, 450, and 460. In that implementation, each block has 20 active columns, and each bit line connects to five rows in each block. In one embodiment, all five vertical columns / NAND strings connected to a common bit line are connected to the same word line (or set of word lines). Thus, the system uses the drain side select line to select one (or another subset) of the five to be subjected to a memory operation (program, verify, read, and / or erase).

[0063] FIG. 4B shows each region with four vertical columns, five regions (420, 430, 440, 450, 460), and each region with twenty vertical columns in blocks (420, 430, 440, 450, 460), although these exact numbers are exemplary implementations. Other embodiments may include more or fewer regions (420, 430, 440, 450, 460) per block, more or fewer vertical columns of rows per region, and more or fewer vertical columns of rows per block. FIG. 4B also shows that the vertical columns are staggered. In other embodiments, a different pattern of staggering may be used. In some embodiments, the vertical columns are not staggered.

[0064] FIG. 4C illustrates one embodiment of stack 435, showing a cross-sectional view along line AA in FIG. 4B. In addition to data wordline layers WL0-WL111, there is an SGD layer (SGD), an SGS layer (SGS), and four dummy wordline layers DD0, DD1, DS1, and DS0. Each NAND string has a drain side select transistor in the SGD layer. Each NAND string has a source side select transistor in the SGS layer. There may be more than one SGD layer and more than one SGS layer. Dielectric layers DL0-DL118 are also shown.

[0065] Columns 432, 434 of memory cells are shown in a multi-layer stack. The stack includes a substrate 457, an insulating film 454 on the substrate, and a portion of a source line SL. A portion of a bit line 414 is also shown. Note that a NAND string 484 is connected to the bit line 414. The NAND string 484 has a source end at the bottom of the stack and a drain end at the top of the stack. The source end is connected to a source line SL. A conductive via 417 connects the drain end of the NAND string 484 to the bit line 414.

[0066] In one embodiment, the memory cells are arranged in a NAND string. The word line layers WL0-WL111 connect to the memory cells (also referred to as data memory cells). The dummy word line layers DD0, DD1, DS0, and DS1 connect to the dummy memory cells. The dummy memory cells do not store host data (data provided by the host, such as data from a user of the host) and are not eligible to store host data, while the data memory cells are eligible to store host data. In some embodiments, the data memory cells and the dummy memory cells may have the same structure. The drain side select layer SGD is used to electrically connect and disconnect (or isolate) the channel of each NAND string from the bit line. The source side select layer SGS is used to electrically connect and disconnect (or isolate) the channel of each NAND string from the source line SL.

[0067] FIG. 4D shows a diagram of region 445 of FIG. 4C. Data memory cell transistors 570, 571, 572, 573, and 574 are shown in dashed lines. Several layers can be deposited along the sidewalls (SW) of memory hole 432 and / or within each word line layer, for example using atomic layer deposition. For example, each column (e.g., pillar formed by material within the memory hole) can include a blocking oxide / blocking high-k material 470, such as SiN or other nitride, a charge trapping layer or film 463, a tunnel layer 464, a polysilicon body or channel 465, and a dielectric core 466. The word line layer can include a conductive metal 462, such as tungsten, as a control gate. For example, control gates 490, 491, 492, 493, and 494 are provided. In this example, all layers except metal are provided within the memory hole. In other approaches, some of the layers can be within the control gate layer. Additional pillars are similarly formed within different memory holes. The pillars can form the columnar active areas (AA) of the NAND strings.

[0068] When a data memory cell transistor is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell transistor. These electrons are pulled from the channel through the tunnel layer into the charge trapping layer. The Vth of the data memory cell transistor increases in proportion to the amount of stored charge. During an erase operation, the electrons return to the channel.

[0069] Each of the memory holes can be filled with multiple annular layers (also referred to as memory film layers) including a blocking oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. The core region of each of the memory holes is filled with a body material, and the multiple annular layers are between the respective core regions of the memory holes and the WLL. In some cases, the tunnel layer 464 can include multiple layers, such as an oxide-nitride-oxide configuration.

[0070] Figure 4E is a schematic diagram of a portion of memory structure 202. Figure 4E shows physical data word lines WL0-WL111 across the block. The structure of Figure 4E corresponds to portion 407 in block 2 of Figure 4A, including bit lines 411. In one embodiment, within a physical block, each bit line is connected to five NAND strings. Thus, Figure 4E shows bit lines connected to NAND string NS0, NAND string NS1, NAND string NS2, NAND string NS3, and NAND string NS4.

[0071] In one embodiment, there are five drain side select lines (SGD-s0, SGD-s1, SGD-s2, SGD-s3, and SGD-s4) in the physical block. Each respective drain side select line can be selected independently of the others. Each drain side select line connects to a group of NAND strings in the block. Only one NAND string from each group is shown in FIG. 4E. These five drain side select lines correspond to five sub-blocks. The first sub-block corresponds to those vertical NAND strings controlled by SGD-s0. The second sub-block corresponds to those vertical NAND strings controlled by SGD-s1. The third sub-block corresponds to those vertical NAND strings controlled by SGD-s2. The fourth sub-block corresponds to those vertical NAND strings controlled by SGD-s3. The fifth sub-block corresponds to those vertical NAND strings controlled by SGD-s4. As mentioned above, FIG. 4E shows only the NAND strings connected to bit lines 411. However, a complete schematic of the block shows all the bit lines and the five vertical NAND strings connected to each bit line.

[0072] In one embodiment, all of the memory cells on the NAND strings in a physical block are erased as a unit. However, in some embodiments, the physical block is operated as an upper tier and a lower tier, with the upper tier and the lower tier each forming an erase block. For example, the memory cells connected to WL0-WL61 may be in a lower tier and the memory cells connected to WL62-WL111 may be in an upper tier. Thus, the memory cells connected to WL0-WL61 may be in one erase block and the memory cells connected to WL62-WL111 may be in another erase block. The physical block may be operated in more than two tiers. The erase blocks may be formed based on other divisions of the physical block.

[0073] The exemplary memory of FIGS. 4-4E is a three-dimensional memory structure including vertical NAND strings with charge trapping material, although other (2D and 3D) memory structures can also be used with the techniques described herein.

[0074] During any given memory operation, a subset of memory cells are identified to receive one or more portions of the memory operation. Those memory cells identified to receive the memory operation are referred to as selected memory cells. Memory cells that are not identified to receive the memory operation are referred to as unselected memory cells. Depending on the memory architecture, memory type, and memory operation, unselected memory cells may be actively or passively excluded from receiving the memory operation.

[0075] During memory operation, some word lines are connected to selected memory cells and are therefore called selected word lines. Unselected word lines are not connected to selected memory cells. Similarly, selected bit lines are connected to selected memory cells and unselected bit lines are not connected to selected memory cells.

[0076] The memory system described above can be erased, programmed, and read. Each memory cell may be associated with a memory state according to the write data in a program command. Based on its memory state, the memory cell either remains in the erased state or is programmed to a memory state (programmed memory state) different from the erased state.

[0077] For example, in a memory device with 2 bits per cell (sometimes referred to as a multi-level cell (MLC)), there are four memory states including an erased state and three programmed memory states referred to as the A, B, and C memory states. In a memory device with 3 bits per cell (sometimes referred to as a tri-level cell (TLC)), there are eight memory states including an erased state and seven programmed memory states referred to as the A, B, C, D, E, F, and G memory states. In a memory device with 4 bits per cell (sometimes referred to as a quad-level cell (QLC)), there are sixteen memory states including an erased state and fifteen programmed memory states referred to as the Er, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15 memory states.

[0078] FIG. 5A illustrates one embodiment of threshold voltage Vth distributions for a four-state memory device in which each memory cell stores two bits of data. A first threshold voltage Vth distribution 500 is provided for erased (Er state) memory elements. Three threshold voltage Vth distributions 502, 504, and 506 represent programmed memory states A, B, and C, respectively. A two-bit code having a lower bit and an upper bit can be used to represent each of the four memory states. In one embodiment, the "Er", "A", "B", and "C" memory states are represented by "11", "01", "00", and "10", respectively.

[0079] FIG. 5B illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device in which each memory cell stores three bits of data. A first threshold voltage Vth distribution 510 is provided for an Er state storage element. Seven threshold voltage Vth distributions 512, 514, 516, 518, 520, 522, and 524 represent programmed memory states A, B, C, D, E, F, and G, respectively. A three-bit code having lower page, middle page, and upper page bits can be used to represent each of the eight memory states. In one embodiment, the "Er", "A", "B", "C", "D", "E", "F", and "G" memory states are represented by "111", "011", "001", "000", "010", "110", "100", and "101", respectively.

[0080] 5C illustrates one embodiment of threshold voltage Vth distributions for a 16-state memory device in which each memory cell stores four bits of data. A first threshold voltage Vth distribution 530 is provided for erased Er state storage elements. Fifteen threshold voltage Vth distributions 532, 534, 536, 538, 540, 542, 544, 546, 548, 550, 552, 554, 556, 558, and 560 represent programmed memory states S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15, respectively.

[0081] A 4-bit code with bottom page, middle page, top page and top page bits can be used to represent each of the 16 memory states. In one embodiment, the S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14 and S15 memory states are represented by "1111", "1110", "1100", "1101", "1001", "0001", "0101", "0100", "0110", "0010", "0000", "1000", "1010", "1011", "0011" and "0111", respectively.

[0082] The techniques described herein can also be used with other types of programming in addition to full sequence programming (including, but not limited to, multiple stage / phase programming). In some embodiments, the program states (e.g., S1-S15) can overlap, and the controller 120 (FIG. 1) responds to error correction to identify the correct data that is stored.

[0083] FIG. 6 is a flow diagram illustrating one embodiment of a process of programming memory cells. In this specification, the terms program and programming are synonymous with write and write. In an exemplary embodiment, the process of FIG. 6 is performed on memory structure 202 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) described above. In an exemplary embodiment, the process of FIG. 6 is performed by integrated memory assembly 207 using one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of control die 211 to program memory cells on memory structure die 201. The process includes multiple loops, each of which includes a program phase and a verify phase.

[0084] Typically, the program voltage applied to the control gate (via a selected data word line) during a program operation is applied as a series of program pulses (e.g., voltage pulses). Between the programming pulses there is a set of verify pulses (e.g., voltage pulses) to perform the verify. In many implementations, the magnitude of the program pulses increases with each successive pulse by a predetermined step size. In step 602 of FIG. 6, the programming voltage signal (Vpgm) is initialized to a starting magnitude (e.g., about 12-16V or another suitable level) and a program counter PC maintained by state machine 262 is initialized to 1. In one embodiment, a group of memory cells selected to be programmed (referred to herein as selected memory cells) are programmed simultaneously and are all connected to the same word line (selected word line). Other memory cells not selected for programming (unselected memory cells) may also be connected to the selected word line. That is, the selected word line is also connected to memory cells that are supposed to be inhibited from programming. In addition, once the memory cells reach their intended target data state, further programming is inhibited. NAND strings containing memory cells connected to a selected word line that is to be inhibited from programming (e.g., unselected NAND strings) have their channels boosted to inhibit programming. When the channels have a boosted voltage, the voltage difference between the channel and the word line is not large enough to cause programming. To assist in the boosting, in step 604, the control die precharges the channels of the NAND strings containing memory cells connected to the selected word line that is to be inhibited from programming. In step 606, NAND strings containing memory cells connected to the selected word line that is to be inhibited from programming have their channels boosted to inhibit programming. Such NAND strings are referred to herein as "unselected NAND strings." In one embodiment, the unselected word lines receive one or more boosted voltages (e.g., about 7-11 volts) to implement the boosting scheme.A program inhibit voltage is applied to the bit lines coupled to the unselected NAND strings.

[0085] In step 608, a program voltage pulse of the programming voltage signal Vpgm is applied to the selected word line (selected word line for programming). If a memory cell on the NAND string is to be programmed, the corresponding bit line is biased with a program enable voltage. In step 608, a program pulse is applied simultaneously to all memory cells connected to the selected word line, so that all memory cells connected to the selected word line are programmed simultaneously (unless programming is inhibited). That is, the memory cells are programmed at the same time or during overlapping times (both are considered to be simultaneous). In this way, all memory cells connected to the selected word line change their threshold voltages at the same time, unless programming is inhibited.

[0086] In step 610, a program verify is performed and memory cells that have reached their target state are locked out by the control die from further programming. Step 610 includes performing a verify of the programming by sensing at one or more verify reference levels. Disclosed herein are embodiments for determining which data state should be verified at each loop of the programming process. In one embodiment, the verify process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verify reference voltage. After the memory cell has verified that it has reached its target state in step 610 (by testing Vt), the memory cell may be locked. For example, the memory cell may be locked out if it has reached the verify reference voltage. In one embodiment, one or more data latches in the managing circuit 330 are used to indicate whether the memory cell is locked out or should undergo full programming.

[0087] If, at step 612, it is determined that all of the memory cells have reached their target threshold voltages (passed), the programming process is complete and successful because all selected memory cells have been programmed and verified to their target states. A status of "passed" is reported at step 614. Otherwise, if, at step 612, it is determined that all of the memory cells have not reached their target threshold voltages (failed), the programming process proceeds to step 616.

[0088] In step 616, the number of memory cells that have not yet reached their respective target threshold voltage distributions is counted; that is, the number of memory cells that have not yet reached their target state is counted. This counting can be performed by state machine 262, memory controller 120, or another circuit. In one embodiment, there is one total count that reflects the total number of currently programmed memory cells that failed the last verify step. In another embodiment, a separate count is maintained for each data state.

[0089] In one embodiment, in step 616, the number of memory cells having a Vt equal to or greater than a particular verify reference voltage is counted. In one embodiment, verifying the data state depends on whether the count of cells above the verify reference voltage exceeds a particular number. For example, verifying the B state on the next PV loop may depend on whether the count of cells having a Vt above the A state verify voltage is greater than a particular number. Other examples are described in more detail below.

[0090] In step 618, a determination is made whether the count of failed cells from step 616 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by an error correction code (ECC) during a read process for a page of memory cells. If the number of failed cells is less than or equal to the predetermined limit, the programming process can be stopped and a "pass" status reported in step 614. In this situation, a sufficient number of memory cells have been correctly programmed so that the remaining few memory cells that are not fully programmed can be corrected using ECC during the read process. In some embodiments, the predetermined limit used in step 618 is less than the number of bits that can be corrected by an error correction code (ECC) during the read process to allow for future / additional errors. When programming fewer than all memory cells for a page, or when comparing counts for only one data state (or fewer than all states), the predetermined limit can be a fraction (proportional or not) of the number of bits that can be corrected by ECC during a read process for a page of memory cells. In some embodiments, the limit is not predetermined. Instead, the limit value varies based on the number of errors already counted for the page, the number of program-erase cycles performed, or other criteria.

[0091] If the number of failed memory cells is equal to or greater than the predetermined limit value, the programming process proceeds to step 620, where the program counter PC is checked against a program limit value (PL). Example program limit values ​​include 6, 12, 16, 19, 20, and 30, although other values ​​may be used. If the program counter PC is equal to or greater than the program limit value PL, the programming process is deemed to have failed and a fail status is reported in step 624. If the program counter PC is less than the program limit value PL, the process proceeds to step 626, during which the program counter PC is incremented by one and the programming voltage signal Vpgm is stepped up to the next magnitude. For example, the magnitude of the next pulse is greater than the previous pulse by a step size ΔVpgm (e.g., a step size of 0.1 to 1.0 volts). After step 626, the process loops back to step 604, where another program pulse is applied to the selected word line, resulting in another iteration of the programming process of FIG. 6 (steps 604-626).

[0092] Disclosed herein is a technique whereby memory cells in memory structure 202 (on memory die 200 or memory structure die 201) can be programmed in a 4-bits-per-cell mode (also referred to as QLC, X4, or 4-page code) or a 3-bits-per-cell mode (also referred to as TLC, X3, or 3-page code). In one embodiment, system control logic 260 (on either memory die 200 or control die 211) can execute an X4 programming algorithm and an X3 programming algorithm. To reduce the amount of logic circuits for programming, at least some of the logic circuits used for X4 programming are also used for X3 programming. In one embodiment, the logic circuits may implement a QLC programming algorithm (Gray code and logic) to program 4-bit data into the memory cells. In one embodiment, the logic circuits may also implement a TLC programming algorithm (Gray code and logic) based on the QLC programming algorithm to program 3-bit data into the memory cells. However, in the case of TLC programming based on the QLC programming algorithm, technical challenges arise in verifying the memory cells. One embodiment of the logic circuit disclosed herein performs smart verification when the TLC programming is based on a QLC programming algorithm.

[0093] In one embodiment, an existing QLC Gray code is used to generate the TLC Gray code. Figure 7A1 is a table of an exemplary QLC Gray code 700a1 used to represent 16 data states. In particular, the QLC Gray code 700a1 shows values ​​for the lower page (LP) bits, middle page (MP) bits, upper page (UP) bits, and top page (TP) bits for the 16 data states S0, S1...S15. For example, for state S3, the LP, MP, UP, and TP bits are 1101, respectively, and for state S9, the LP, MP, UP, and TP bits are 0010, respectively, and so on.

[0094] The exemplary QLC Gray code 700a1 may be referred to as a "3-4-4-4 code," which refers to the number of read levels per page, where the read levels typically occur at transitions from 0 to 1 or 1 to 0. Thus, in the example of FIG. 7A1, there are three read levels for the LP (S4 to S5 transitions, S10 to S11 transitions, and S13 to S14 transitions), four read levels for the MP (S3 to S4 transitions, S5 to S6 transitions, S8 to S9 transitions, and S14 to S15 transitions), four read levels for the UP (S1 to S2 transitions, S7 to S8 transitions, S9 to S10 transitions, and S11 to S12 transitions), and four read levels for the TP (S0 to S1 transitions, S2 to S3 transitions, S6 to S7 transitions, and S12 to S13 transitions). Those skilled in the art will appreciate that QLC Gray codes other than the example QLC Gray code 700a1 of FIG. 7A1 may be used.

[0095] In an embodiment, a TLC Gray code is generated from a QLC Gray code by setting all bits of one of LP, MP, UP, and TP to 1 or 0. In one embodiment, a control circuit (e.g., one or more of system control logic 260, read / write circuit 225, row decoder 222, and column decoder 212) sets UP=1. QLC Gray code 700a1 shows all data states where UP=1 in dashed lines. FIG. 7A2 is a table of an exemplary TLC Gray code 700a2 that may be generated from the exemplary QLC Gray code 700a1 of FIG. 7A1 by setting UP=1, i.e., UP=1 for QLC data states S0, S1, S8, S9, and S12-S15. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 7A2.

[0096] The exemplary TLC Gray code 700a2 is sometimes referred to as a "2-3-2 code," which refers to the number of read levels per page, where the read levels typically occur at transitions from 0 to 1 or 1 to 0. Thus, in the example of FIG. 7A2, there are three read levels for the LP (S1 to S8 transitions, S9 to S12 transitions, and S13 to S14 transitions), two read levels for the MP (S8 to S9 transitions and S14 to S15 transitions), and two read levels for the TP (S0 to S1 transitions, and S12 to S13 transitions).

[0097] 7A3 illustrates an embodiment of threshold voltage Vth distributions for an X3 programming mode in which each memory cell stores three bits of data, programmed using an exemplary TLC Gray code 700a2 generated from the exemplary QLC Gray code 700a1 of FIG. 7A1 with UP=1. As shown in this example, states S2-S7 and S10-S11 have no memory cells assigned to them. Thus, the following eight states remain: S0, S1, S8, S9, S12, S13, S14, and S15, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0098] In one embodiment, one of the data latches (e.g., the UP data latch) is forced to a value of 1, and then the X4 logic on the die (e.g., 200, 211) implements a QLC programming algorithm to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, as shown in the exemplary threshold voltage Vth distributions of FIG. 7A3 or FIG. 7A4.

[0099] The threshold voltage Vth distribution of FIG. 7A3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv1, Vv8, Vv9, Vv12, Vv13, Vv14, and Vv15 of the seven program data states S1, S8, S9, S12, S13, S14, and S15, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in FIG. 7A4 (with verify levels VvA, VvB, VvC, VvD, VvE, VvF, and VvG).

[0100] In some embodiments, for X4 programming, smart verify is performed. Smart verify can also be referred to as skip verify. In one embodiment of smart verify for X4 programming, the system determines which program loop starts verifying a particular state based on whether the number of memory cells having a Vt above the verify voltage of the previous state exceeds a certain predetermined number. For example, X4 programming verify of the S2 state may be skipped until a predetermined number of memory cells have a Vt above the Vv1 voltage of the S1 state, verify of the S3 state may be skipped until a predetermined number of memory cells have a Vt above the Vv2 voltage of the S2 state, and so on. This smart verify is effective in reducing the total number of verify operations, thereby saving time, power and / or current. This smart verify is also effective in avoiding over-programming of memory cells, which may occur if a particular start verify starts too high in the program loop.

[0101] However, the reuse of at least some of the logic circuits used for X4 programming for one embodiment of X3 programming presents technical challenges for smart verification during X3 programming. With reference to FIG. 7A3, note that in X3 programming mode, 8 of the 16 X4 states are used and 8 of the 16 X4 states are not used. As a result, some of the states in X3 mode follow states in X4 mode that are not used in X3 mode. For example, B state (corresponding to S8) follows S7 from X4 mode. The fact that S7 is not used in X3 mode presents technical challenges for smart verification of B state in X3 programming mode based on X4 programming algorithm. Also, note that D state (corresponding to S12) follows S11 from X4 mode. The fact that S11 is not used in X3 mode presents technical challenges in smart verification of D state in X3 programming mode based on X4 programming algorithm.

[0102] In one embodiment, the system uses smart verification to determine which PV loop to start verifying a particular state in X3 mode if the particular state follows a used state from X4 mode. For example, referring to FIG. 7A3, the C, E, F, and G states each immediately follow a used state from X4 mode. Thus, the system may skip verifying the C state until a predetermined number of memory cells have a Vt above VvB, skip verifying the E state until a predetermined number of memory cells have a Vt above VvD, skip verifying the F state until a predetermined number of memory cells have a Vt above VvE, and skip verifying the G state until a predetermined number of memory cells have a Vt above VvF. The term "smart PCV" is used in FIG. 7A3 to indicate the X3 states for which verification may be performed in this manner.

[0103] In an embodiment, if a particular state in X3 mode follows an unused state in X4 mode, the system may use a different test to determine which PV loop to begin verifying. For example, the system may begin verifying the D state a predetermined number of program loops after verifying the C state begins. Doing so eliminates the need to make a determination based on counting the number of memory cells with Vt above VvC, which simplifies the programming logic in an embodiment that uses at least a portion of the X4 programming logic for X3 programming. The D state in FIG. 7A3 is labeled "Manual PCV" to indicate that D state verification begins a predetermined number of program loops after verifying the C state begins.

[0104] In some cases, using smart verify is important enough to use smart verify even if a particular state follows an unused state from X4 mode. The B state in FIG. 7A3 is an example. In one embodiment, the memory system skips verifying the B state until a predetermined number of memory cells have a Vt above VvA. In one embodiment, the verify is combined with smart verify of the B state, where the verify of a state above the B state begins a predetermined number of PV loops after the verify of the preceding state begins. For example, the verify of the C state may begin one PV loop after the verify of the B state begins, the verify of the D state may begin one PV loop after the verify of the C state begins, and so on. Beginning the verify of a predetermined number of PV loops after the immediately preceding state is referred to herein as manual PCV. Thus, the C, D, E, F, and G states do not need to have smart verify. Instead, manual PCV may be used for the C, D, E, F, and G states in combination with the smart PCV of the B state. In this example, smart verify is used only for the B state, which simplifies the modifications to the X4 programming logic to support efficient and accurate verify in the X3 programming mode, e.g., the number of verify operations can be kept low without significant risk of over-programming.

[0105] FIG. 8 is a flow chart of one embodiment of a process 800 for state-dependent smart verify in a memory system using both X3 and X4 program modes. In one embodiment, the process 800 is used to program NAND memory cells. In one embodiment, one set of blocks is used for TLC data and another set of blocks is used for QLC data. Thus, it is not necessary for the same group of memory cells to be programmed in both X3 and X4 modes. However, optionally, the same group of memory cells can store TLC data and QLC data at different times. In one embodiment, the process 800 is performed by one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the memory die 200. In one embodiment, the process 800 is performed by one or more control circuits (e.g., system control logic 260, column control circuit 210, row control circuit 220) of the control die 211. The steps in the process 800 are shown in a particular order for ease of explanation.

[0106] Step 802 includes programming a first group of memory cells in memory structure 202 using a 4-bit code. An example of a 4-bit code is shown in FIG. 7A1. Step 802 may also include performing smart verify. The 4-bit code has 16 states (e.g., S0-S15) and 4 pages (e.g., LP, MP, UP, TP). In one embodiment of smart verify of step 802, verifying a particular state begins a predetermined number of PV loops after a certain number of cells have a Vt above the verify voltage of the state immediately preceding the particular state. The states are ordered based on threshold voltage. A first state immediately preceding a second state means that the verify voltage of the first state is next lower in threshold voltage.

[0107] Step 804 includes programming a second group of memory cells in the memory structure 202 using the three-bit code. An example of a four-bit code is shown in FIG. 7A2. The three-bit code has eight of the sixteen states of the four-bit code. For example, in FIG. 7A2, the three-bit code has states S0, S1, S8, S9, S12, S13, S14, and S15. These eight states are based on the states from the four-bit code where the unused pages have a default value. In the example of FIG. 7A, the unused pages are UP. The state used is the state where UP has a value of 1 in this example. Examples of where other states from the four-bit code are used with the three-bit code are described below.

[0108] Step 804a includes determining which PV loop should verify each state of the set of states in the 3-bit code. In one embodiment, step 804a performs what is referred to herein as smart PVC. In one embodiment of smart PVC for a particular state, the memory system counts the number of memory cells that have a Vt above the verify voltage just below the particular state. Verification begins with the next PV loop (or some other predetermined number of PV loops) after the count reaches a certain number. For example, verification of the E state may begin with the next PV loop after a certain number of cells have a Vt above the verify voltage of the D state. Step 804 is to begin verification of each particular state on the PV loop determined in step 804a. Once verification of a particular state begins, the particular state is verified with each PV loop until it is determined that the memory cells targeted for that particular state have completed programming (step 804c).

[0109] 9 shows one possible scheme for verifying memory cells. This technique involves verifying all states that have not yet passed verification after each program pulse. An example of this is the TLC case where seven states are verified after pulse 902 and seven states are verified after pulse 904. For illustration purposes, the A state is verified as having finished programming after pulse 904 and not verified after pulse 906. This technique results in a very large number of program pulses and is therefore slow and consumes significant current and / or power.

[0110] A possible improvement to the technique shown in FIG. 9 is to skip the verification of some of the higher Vt states in the earlier PV loops. However, one of the technical challenges of such skipping is that there can be significant die-to-die variation in programming speed. FIGS. 10A and 10B show a portion of the programming process of two different dies that program at different speeds. FIG. 10A shows the case where some of the memory cells have a Vt above VaV (A state verify voltage) after a single program pulse. FIG. 10B shows the case where it takes three program pulses for any of the memory cells with a Vt above VaV. Consider a scheme where the verification of the B state is skipped for the first PV loop and begins on the second PV loop. Such a scheme can work well for the faster programming case of FIG. 10A. However, such a scheme verifies earlier than required for the case of FIG. 10B. Now consider a scheme where the verification of the B state is skipped for the first three PV loops and begins on the fourth PV loop. Such a scheme can work well for the faster and slower cases of FIG. 10B. However, schemes such as may result in over programming in the case of FIG. 10A. Over programming should be avoided because over programming may lead to errors that cannot be corrected by ECC. FIG. 11 shows a possible scheme to prevent over programming, whether there is a slower or faster programming die. FIG. 11 shows eleven program pulses 1102-1 to 1102-11. In FIG. 11, verification of the A state begins after the first program pulse 1102-1, as indicated by verify pulse 1104. Verification of the B state begins after the second program pulse 1102-2, as indicated by verify pulse 1106. Verification of the C state begins after the third program pulse 1102-3, as indicated by verify pulse 1108. Verification of the D state begins after the fourth program pulse 1102-4, as indicated by verify pulse 1110. Verify of the E state begins after the fifth program pulse 1102-5, as indicated by verify pulse 1112.Verification of the F state begins after the sixth program pulse 1102-6, as indicated by verify pulse 1114, and verification of the G state begins after the seventh program pulse 1102-7, as indicated by verify pulse 1116. Verification of a state can stop after all but a few cells have reached that state. The technique shown in FIG. 11 may be relatively simple to implement because verification of each state begins at a given PV loop. However, the technique shown in FIG. 11 has unnecessary verification for faster programming dies, such as the example of FIG. 10A. In practice, a high percentage of dies may program relatively quickly, such as the example of FIG. 10A.

[0111] FIG. 12 illustrates an embodiment of a smart verify scheme for X3 programming. This scheme may be performed by logic on the die that also performs X4 programming. Furthermore, the smart verify scheme allows a significant portion of the X4 programming logic to be used for X3 programming. FIG. 12 illustrates eleven program pulses 1202-1 through 1202-11. One embodiment of the smart verify illustrated in FIG. 12 verifies only the A state for 1 through n program / verify (PV) loops (pulses 1204). Thus, verifying from B states to G states is skipped for 1 through n PV loops, reducing the total number of verify operations. This determination is based on counting memory cells with a Vt above the A state verify level. As an example, n is shown as three PV loops in FIG. 12, but n may be less than or greater than three. After a certain number of memory cells have a Vt above the A state verify, the B state verify (pulse 1206) begins in the next PV loop. Verifying from C states to G states begins a predetermined number of PV loops after verifying begins for the previous state. For example, verification of the C state (pulse 1208) begins one PV loop after verification of the B state begins, verification of the D state (pulse 1210) begins one PV loop after verification of the C state begins, verification of the E state (pulse 1212) begins one PV loop after verification of the D state begins, verification of the F state (pulse 1214) begins one PV loop after verification of the E state begins, and verification of the G state (pulse 1216) begins one PV loop after verification of the F state begins. In this example, the number of PV loops to wait before beginning verification of the next state is one. However, more than one PV loop can be used. Also, not all states need to wait the same number of PV loops after verification of the previous state. Comparing the examples of Figures 11 and 12, it is shown that in each case it took 11 program pulses to complete programming. However, Figure 11 used 29 verify pulses, while Figure 12 only used 17 verify pulses. Thus, the embodiment of FIG. 12 represents a significant savings in time, current and / or power compared to the example of FIG.Furthermore, due to the count of memory cells with a Vt above the A-state verify level, the embodiment of FIG. 12 does not present a significant risk of over-programming.

[0112] The embodiment shown in FIG. 12 may be referred to as using smart PVCs for the B state and manual PVCs for the C, D, E, F, and G states. Thus, this embodiment combines smart and manual PVCs. FIG. 13 is a flow diagram of one embodiment of a process 1300 of combining smart and manual PVCs for X3 programming. Process 1300 provides further details on one embodiment of step 804 of FIG. 8. Step 1302 includes applying a program pulse to a selected word line connected to a memory cell to be programmed. The memory cell may be only a memory cell in one of the sub-blocks connected to the selected word line. The memory cell may be referred to herein as a physical page of memory cells. In one embodiment, a physical page has about 16 kilobytes of memory cells.

[0113] Step 1304 includes applying an A-state verify reference voltage to the selected word line and also includes inhibiting the cell targeted for the A state from undergoing further programming if the Vt of the cell is the A-state verify reference voltage.

[0114] Step 1306 includes counting the number (N) of memory cells having a Vt above the A state verify reference level. Step 1308 is a determination of whether the number (N) of memory cells is greater than a threshold number. The threshold number may vary depending on the implementation. For example, the threshold number is about 10 cells, about 100 cells, or some other number. If the number (N) of memory cells has not yet reached the threshold, then the process returns to step 1302 to apply another program pulse. If the number (N) of memory cells has reached the threshold, then the process proceeds to step 1310 to apply another program pulse.

[0115] Steps 1312 and 1314 involve beginning verification of the B through G states during the programming process. Step 1312 involves beginning verification of the B state for a predetermined number of PV loops after the count (N) reaches a threshold. This is shown in FIG. 12 as starting with the fourth PV loop, but could be as early as the second PV loop or after the fourth PV loop, depending on the count (N).

[0116] Step 1314 includes initiating verification of the C, D, E, F, and G states for a predetermined number of PV loops after verification has been initiated for the previous state. Another way of stating the condition for initiating verification for a particular state is to begin a predetermined number of PV loops after the number of memory cells (N) reaches a threshold number. Note, however, that this only requires that counting is done for the A state verify level, greatly simplifying the design of the logic circuitry. Step 1316 includes testing whether programming has occurred (see, e.g., step 618 of FIG. 6). The process loops through steps 1310-1316 until programming is complete.

[0117] One embodiment includes state-dependent smart verify of X3 programming. For example, smart PVCs can be used for a first set of X3 states and manual PVCs can be used for a second set of X3 states. FIG. 14 is a flow diagram of one embodiment of a process 1400 of state-dependent smart verify of X3 programming. Process 1400 provides further details about one embodiment of step 804 of FIG. 8. Step 1402 includes applying a program pulse to a selected word line connected to a memory cell to be programmed. The memory cell may be only a memory cell in one of the sub-blocks connected to the selected word line.

[0118] Steps 1404-1410 describe verifying or skipping verification for a particular state. Steps 1404-1410 may be performed for each state that has not yet completed verification. Step 1404 is a determination of whether a particular state is in a first set of X3 states or in a second set of X3 states. The first set is a set in which a first test is performed to determine whether to verify or skip verification. The second set is a set in which a second test is performed to determine whether to verify or skip verification. In one embodiment, the first test is a smart PVC test and the second test is a manual PVC test. In one embodiment, the first set of states includes all states that follow a used state in the 4-bit encoding. In one embodiment, the second set of states includes states that follow an unused state in the 4-bit encoding, but does not include any states that follow a used state in the 4-bit encoding. In one embodiment, the B state is in the first set regardless of whether the B state follows a used state or an unused state in the 4-bit code. Some examples are described below for further explanation.

[0119] If the particular state is in the first set, a first test is used to determine whether to validate or skip (step 1406). If the particular state is in the second set, a second test is used to determine whether to validate or skip (step 1408). Step 1410 involves either validating or skipping based on the test results. Step 1412 involves determining whether there is another state to consider. If so, steps 1404-1410 are repeated for the next state. After the validation of this PV loop is performed, a determination is made in step 1414 whether programming is complete. If so, the next PV loop begins in step 1402.

[0120] Figure 15 is a flow diagram of another embodiment of a process 1500 of state-dependent smart verify of X3 programming. Process 1500 provides further details about one embodiment of step 804 of Figure 8. Step 1502 includes applying a program pulse to a selected word line connected to memory cells to be programmed. The memory cells may only be memory cells in one of the sub-blocks connected to the selected word line.

[0121] Steps 1504-1510 describe verifying or skipping verification for a particular state. Step 1504 is a determination of whether a particular state is preceded by an unused state from the 4-bit code. If so, the system determines in step 1506 that verification begins when enough cells have a Vt above the verification criterion of the previous state.

[0122] If the state is preceded by an unused state, the system determines to begin verification of the predetermined number of PV loops after beginning verification of the immediately preceding state in step 1508. In one embodiment, an exception is made for the B state, which is tested as in step 1506 even if the B state follows an unused state.

[0123] Step 1510 involves either verifying validity based on the test results or skipping verification. Step 1512 involves determining whether there is another condition to consider. If so, steps 1504-1510 are repeated for the next condition. After verification of this PV loop is performed, a determination is made in step 1514 whether programming is complete. If so, step 1512 starts the next PV loop.

[0124] As described herein, in some embodiments, the memory system determines whether to use a smart PCV or a manual PCV based on whether an X3 state is preceded by an X4 state, either used or unused. In some embodiments, an X3 state preceded by a used X4 state may receive a smart PCV, and an X3 state preceded by an unused X4 state may receive a manual PCV. However, in one embodiment, an exception is made for the B state, which may receive a smart PCV even if it is preceded by an unused X4 state. Next, several different 4-bit codes and corresponding 3-bit codes are described.

[0125] In the embodiment shown in Figures 7A1-7A4, the TLC Gray code is generated from the QLC Gray code by setting all bits of UP to 1. As described above, in the embodiment, the TLC Gray code is generated from the QLC Gray code by setting all bits of one of LP, MP, UP, and TP to 1 or 0. Thus, in an alternative embodiment, the TLC Gray code may be generated from the QLC Gray code by setting all bits of UP to 0. In one embodiment, the control circuitry (e.g., one or more of system control logic 260, read / write circuitry 225, row decoder 222, and column decoder 212) sets UP=0.

[0126] For example, FIG. 16B1 is a table of an exemplary QLC Gray code 1600b1 used to represent 16 data states, with all data states with UP=0 shown in dashed lines. FIG. 16B2 is a table of an exemplary TLC Gray code 1600b2 that may be generated from the exemplary QLC Gray code 1600b1 of FIG. 16B1 by setting UP=0, i.e., UP=0 for QLC data states S2-S7 and S10-S11. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 16B2.

[0127] FIG. 16B3 illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device, each memory cell storing 3 bits of data, programmed using the exemplary TLC Gray code 1600b2 generated from the exemplary QLC Gray code 1600b1 of FIG. 16B1 with UP=0. As shown in this example, states S0-S1, S8-S9, and S12-S15 have no memory cells assigned to them. Thus, the following eight states remain: S2, S3, S4, S5, S6, S7, S10, and S11, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0128] In one embodiment, one of the data latches (e.g., the UP data latch) is forced to a value of 0, and then the X4 logic on the memory die 200 or the control die 211 implements a QLC program to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, such as the exemplary threshold voltage Vth distribution shown in FIG. 16B3.

[0129] The threshold voltage Vth distribution of FIG. 16B3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv2, Vv3, Vv4, Vv5, Vv6, Vv7, Vv10, and Vv11 of the eight program data states S2, S3, S4, S5, S6, S7, S10, and S11, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in FIG. 16B4.

[0130] Figure 16B3 shows that in one embodiment, smart PCVs are used for the B, C, D, E, and G states because they each follow a used state in the 4-bit encoding. However, manual PCVs are used in one embodiment for the F state because it follows an unused state (S9) from the 4-bit encoding.

[0131] 16C1-16C4 show yet another alternative embodiment in which TLC Gray code is generated from QLC Gray code by setting all bits of TP to 1. In one embodiment, control circuitry (e.g., one or more of system control logic 260, read / write circuitry 225, row decoder 222, and column decoder 212) sets TP=1.

[0132] FIG. 16C1 is a table of an example QLC Gray code 1600c1 used to represent 16 data states, with all data states with TP=1 shown in dashed lines. FIG. 16C2 is a table of an example TLC Gray code 1600c2 that may be generated from the example QLC Gray code 1600c1 of FIG. 16C1 by setting TP=1, i.e., TP=1 for QLC data states S0, S3-S6, and S13-S15. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 16C2.

[0133] FIG. 16C3 illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device, each memory cell storing 3 bits of data, programmed using the exemplary TLC Gray code 1600c2 generated from the exemplary QLC Gray code 1600c1 of FIG. 16C1 with TP=1. As shown in this example, states S1-S2 and S7-S12 have no memory cells assigned to these states. Thus, the following eight states remain: S0, S3, S4, S5, S6, S13, S14, and S15, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0134] In one embodiment, one of the data latches (e.g., the TP data latch) is forced to a value of 1, and then the X4 logic on the memory die implements the QLC program to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, as shown in the exemplary threshold voltage Vth distribution of FIG. 16C3.

[0135] The threshold voltage Vth distribution of FIG. 16C3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv3, Vv4, Vv5, Vv6, Vv13, Vv14, and Vv15 of the eight program data states S3, S4, S5, S6, S13, S14, and S15, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in FIG. 16C4.

[0136] Figure 16C3 shows that in one embodiment, smart PCV is used for the B, C, D, F, and G states because they each follow a used state in the 4-bit encoding. However, manual PCV is used in one embodiment for the E state because it follows an unused state (S12) from the 4-bit encoding.

[0137] 16D1-16D4 show yet another alternative embodiment in which TLC Gray code is generated from QLC Gray code by setting all bits of TP to 0. In one embodiment, control circuitry (e.g., one or more of system control logic 260, read / write circuitry 225, row decoder 222, and column decoder 212) sets TP=0.

[0138] FIG. 16D1 is a table of an example QLC Gray code 1600d1 used to represent 16 data states, with all data states with TP=0 shown in dashed lines. FIG. 16D2 is a table of an example TLC Gray code 1600d2 that may be generated from the example QLC Gray code 1600d1 of FIG. 16D1 by setting TP=0, i.e., TP=0 for QLC data states S1-S2 and S7-S12. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 16D2.

[0139] FIG. 16D3 illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device, each memory cell storing 3 bits of data, programmed using the exemplary TLC Gray code 1600d2, generated from the exemplary QLC Gray code 1600d1 of FIG. 16D1 with TP=0. As shown in this example, states S0, S3-S6, and S13-S15 have no memory cells assigned to these states. Thus, the following eight states remain: S1, S2, S7, S8, S9, S10, S11, and S12, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0140] In one embodiment, one of the data latches (e.g., the TP data latch) is forced to a value of 0, and then the X4 logic on the memory die implements the QLC program to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, as shown in FIG. 16D3.

[0141] The threshold voltage Vth distribution of FIG. 16D3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv1, Vv2, Vv7, Vv8, Vv9, Vv10, Vv11, and Vv12 of the eight program data states S1, S2, S7, S8, S9, S10, S11, and S12, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in FIG. 16D4.

[0142] Figure 16D3 shows that in one embodiment, smart PCVs are used for the C, D, E, F, and G states because they each follow a used state in the 4-bit encoding. The B state follows an unused state (S6). In one embodiment, an exception is made for the B state, where smart PCVs are used despite the B state following an unused state. Optionally, manual PVCs can be used for the B state, since it follows an unused X4 state.

[0143] 16E1-16E4 show yet another alternative embodiment in which TLC Gray code is generated from QLC Gray code by setting all bits of MP to 1. In one embodiment, control circuitry (e.g., one or more of system control logic 260, read / write circuitry 225, row decoder 222, and column decoder 212) sets MP=1.

[0144] FIG. 16E1 is a table of an exemplary QLC Gray code 1600e1 used to represent 16 data states, with all data states with MP=1 shown in dashed lines. FIG. 16E2 is a table of an exemplary TLC Gray code 1600e2 that may be generated from the exemplary QLC Gray code 1600e1 of FIG. 16E1 by setting MP=1, i.e., MP=1 for QLC data states S0-S3, S6-S8, and S15. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 16E2.

[0145] FIG. 16E3 illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device, each memory cell storing 3 bits of data, programmed using the exemplary TLC Gray code 1600e2, generated from the exemplary QLC Gray code 1600e1 of FIG. 16E1, where MP=1. As shown in this example, states S4-S5 and S9-S14 have no memory cells assigned to them. Thus, the following eight states remain: S0, S1, S2, S3, S6, S7, S8, and S15, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0146] In one embodiment, one of the data latches (e.g., the MP data latch) is forced to a value of 1, and then the X4 logic on the memory die implements the QLC program to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, as shown in FIG. 16E3.

[0147] It should be noted that the threshold voltage Vth distribution of FIG. 16E3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv1, Vv2, Vv3, Vv6, Vv7, Vv8, and Vv15 of the eight program data states S1, S2, S3, S6, S7, S8, and S15, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in FIG. 16E4.

[0148] Figure 16E3 shows that in one embodiment, smart PVCs are used for the B, C, E, and F states because they each follow a used state in the 4-bit encoding. Manual PVCs are used for the D state because they follow an unused X4 state (S5). Manual PVCs are also used for the G state because they follow an unused X4 state (S14).

[0149] 16F1-16F4 show yet another alternative embodiment in which TLC Gray code is generated from QLC Gray code by setting all bits of MP to 0. In one embodiment, control circuitry (e.g., one or more of system control logic 260, read / write circuitry 225, row decoder 222, and column decoder 212) sets MP=0.

[0150] FIG. 16F1 is a table of an exemplary QLC Gray code 1600f1 used to represent 16 data states, with all data states with MP=0 shown in dashed lines. FIG. 16F2 is a table of an exemplary TLC Gray code 1600f2 that may be generated from the exemplary QLC Gray code 1600f1 of FIG. 16F1 by setting MP=0, i.e., MP=0 for QLC data states S4-S5 and S9-S14. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 16F2.

[0151] FIG. 16F3 illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device, each memory cell storing 3 bits of data, programmed using the exemplary TLC Gray code 1600f2, generated from the exemplary QLC Gray code 1600f1 of FIG. 16F1, where MP=0. As shown in this example, states S0-S3, S6-S8, and S15 have no memory cells assigned to them. Thus, the following eight states remain: S4, S5, S9, S10, S11, S12, S13, and S14, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0152] In one embodiment, one of the data latches (e.g., the MP data latch) is forced to a value of 0, and then the X4 logic on the memory die implements the QLC program to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, as shown in FIG. 16F3.

[0153] The threshold voltage Vth distribution of FIG. 16F3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv4, Vv5, Vv9, Vv10, Vv11, Vv12, Vv13, and Vv14 of the eight program data states S4, S5, S9, S10, S11, S12, S13, and S14, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in FIG. 16F4.

[0154] Figure 16F3 shows that in one embodiment, smart PCVs are used for the C, D, E, F and G states because they each follow a used state in the 4-bit encoding. The B state follows an unused state (S8). In one embodiment, an exception is made for the B state, where smart PCVs are used despite the B state following an unused state. Optionally, manual PVCs can be used for the B state, since it follows an unused X4 state.

[0155] 16G1-16G4 show yet another alternative embodiment in which TLC Gray code is generated from QLC Gray code by setting all bits of LP to 1. In one embodiment, control circuitry (e.g., one or more of system control logic 260, read / write circuitry 225, row decoder 222, and column decoder 212) sets LP=1.

[0156] In particular, FIG. 16G1 is a table of an exemplary QLC Gray code 1600g1 used to represent 16 data states, with all data states with LP=1 shown in dashed lines. FIG. 16G2 is a table of an exemplary TLC Gray code 1600g2 that may be generated from the exemplary QLC Gray code 1600g1 of FIG. 16G1 by setting LP=1, i.e., LP=1 for QLC data states S0-S4 and S11-S13. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 16G2.

[0157] FIG. 16G3 illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device, each memory cell storing 3 bits of data, programmed using the exemplary TLC Gray code 1600g2, generated from the exemplary QLC Gray code 1600g1 of FIG. 16G1 with LP=1. As shown in this example, states S5-S10 and S14-S15 have no memory cells assigned to them. Thus, the following eight states remain: S0, S1, S2, S3, S4, S11, S12, and S13, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0158] In one embodiment, one of the data latches (e.g., the LP data latch) is forced to a value of 1, and then the X4 logic on the memory die implements the QLC program to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, as shown in FIG. 16G3.

[0159] The threshold voltage Vth distribution of FIG. 16G3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv1, Vv2, Vv3, Vv4, Vv11, Vv12, and Vv13 of the eight program data states S0, S1, S2, S3, S4, S11, S12, and S13, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in FIG. 16G4.

[0160] Figure 16G3 shows that in one embodiment, smart PCVs are used for the B, C, D, F and G states because they each follow used states in the 4-bit encoding. Manual PCVs are used for the E state because they follow the unused X4 state (S10).

[0161] 16H1-16H4 show yet another embodiment in which TLC Gray code is generated from QLC Gray code by setting all bits of LP to 0. In one embodiment, control circuitry (e.g., one or more of system control logic 260, read / write circuitry 225, row decoder 222, and column decoder 212) sets LP=0.

[0162] FIG. 16H1 is a table of an exemplary QLC Gray code 1600h1 used to represent 16 data states, with all data states with LP=0 shown in dashed lines. FIG. 16H2 is a table of an exemplary TLC Gray code 1600h2 that may be generated from the exemplary QLC Gray code 1600h1 of FIG. 16H1 by setting LP=0, i.e., LP=0 for QLC data states S5-S10 and S14-S15. User data is input as three pages of data, LP, MP, and TP, as shown in FIG. 16H2.

[0163] FIG. 16H3 illustrates an embodiment of threshold voltage Vth distributions for an 8-state memory device, each memory cell storing 3 bits of data, programmed using the exemplary TLC Gray code 1600h2, generated from the exemplary QLC Gray code 1600h1 of FIG. 16H1 with LP=0. As shown in this example, states S0-S4 and S11-S13 have no memory cells assigned to them. Thus, the following eight states remain: S5, S6, S7, S8, S9, S10, S14, and S15, which are assigned as TLC states "Er", "A", "B", "C", "D", "E", "F", and "G", respectively.

[0164] In one embodiment, one of the data latches (e.g., the LP data latch) is forced to a value of 0, and then the X4 logic on the memory die implements the QLC program to program the memory cell as a TLC memory cell. Instead of 16 data states, 8 data states result, as shown in FIG. 16H3.

[0165] The threshold voltage Vth distribution of Figure 16H3 may be used as is, or alternatively, the threshold voltage Vth distribution may be more evenly spaced. In one embodiment, the control circuit (e.g., one or more of the system control logic 260, the read / write circuit 225, the row decoder 222, and the column decoder 212) adjusts the verify levels Vv5, Vv6, Vv7, Vv8, Vv9, Vv10, Vv14, and Vv15 of the eight program data states S5, S6, S7, S8, S9, S10, S14, and S15, respectively, so that the threshold voltage Vth distribution is more evenly spaced, such as the exemplary threshold voltage Vth distribution shown in Figure 16H4.

[0166] Figure 16H3 shows that in one embodiment, smart PCVs are used for states B, C, D, E and G because they each follow used states in the 4-bit encoding. Manual PCVs are used for state F because they follow the unused X4 state (S13).

[0167] Techniques are disclosed herein for a memory system with smart verification for the X3 programming mode. The X3 mode uses a 3-bit Gray code based on the 4-bit Gray code of the X4 mode. By basing the 3-bit Gray code on the 4-bit Gray code, a significant portion of the logic used for X4 programming can also be used for X3 programming. However, because the 3-bit Gray code only uses 8 of the 16 states from the 4-bit Gray code, verification using the 3-bit Gray code creates technical challenges. In particular, logic that determines which states should skip verification in the X4 programming mode may not be suitable for use to skip verification in the X3 programming mode. Techniques are disclosed herein for skipping verification of states in the X3 programming mode while still allowing a significant portion of the programming logic from the X4 programming mode to be used in the X3 programming mode.

[0168] In view of the above, a first embodiment includes one or more control circuits configured to connect to a memory structure comprising non-volatile memory cells, the one or more control circuits configured to program a first group of memory cells in the memory structure using a 4-bit code having 16 states and 4 pages. The one or more control circuits configured to program a second group of memory cells in the memory structure using a 3-bit code based on three of the four pages. The 3-bit code includes 8 of the 16 states of the 4-bit code, with an unused page of the 4-bit code including a default value. The one or more control circuits are configured to initiate verification during programming using the 3-bit code during a program verify loop that determines, for each particular state of the first set of one or more states of the 8 states, whether a number of memory cells having a threshold voltage above a verify voltage of a state immediately preceding the particular state in a threshold voltage is greater than a predetermined number.

[0169] In a second embodiment, to facilitate the first embodiment, the one or more control circuits are further configured to initiate verification during programming using the 3-bit code for each particular state of the second set of one or more states of the eight states during a program verify loop determined based on a predetermined number of program verify loops after beginning to verify the state immediately preceding the particular state at the threshold voltage.

[0170] In a third embodiment, to facilitate the first or second embodiment, the eight states include an erased state, and states A, B, C, D, E, F, and G at increasing threshold voltages. The first set includes the B state.

[0171] In a fourth embodiment, to further any of the first to third embodiments, the second set includes states C, D, E, F, and G.

[0172] In a fifth embodiment, to facilitate any of the first to fourth embodiments, the first set includes all states in the 3-bit code that immediately follow a state in the 4-bit code that is also used in the 3-bit code.

[0173] In a sixth embodiment, to facilitate any of the first to fifth embodiments, the eight states include an erased state, and A, B, C, D, E, F, and G states at increasing threshold voltages. A first set includes a B state whether the B state follows a state in a 4-bit code that is also used in the 3-bit code, or whether the B state follows a state in a 4-bit code that is not used in the 3-bit code.

[0174] In a seventh embodiment, to facilitate any of the first to sixth embodiments, the second set includes states in the 3-bit code that immediately follow states in the 4-bit code that are not used in the 3-bit code, but do not include any states in the 4-bit code that are also used in the 3-bit code.

[0175] In an eighth embodiment, to facilitate any of the first to seventh embodiments, programming a second group of memory cells in a memory structure using a 3-bit code based on three of the four pages of the 4-bit code further includes the one or more control circuits being configured to load the three data pages into a corresponding third set of data latches associated with the memory cells, and to load a default value into a fourth set of data latches associated with the memory cells, the default value being the same for all data latches in the fourth set of data latches.

[0176] In a ninth embodiment, to facilitate the eighth embodiment, the one or more control circuits are further configured to program the three data pages into the memory cells based on a programming algorithm that takes into account the three data pages in the corresponding three sets of data latches and a default value in the fourth set of data latches.

[0177] One embodiment includes a method of operating a non-volatile storage device, the method including loading three data pages into three corresponding sets of data latches. The method includes loading a default value into a fourth set of data latches, the default value being the same for all latches in the fourth set. The method includes programming the three data pages into a group of memory cells in the non-volatile storage device, the three data pages being programmed into eight threshold voltage distributions including A and B states, including i) skipping verification of the B state each program verify loop before a predetermined number of memory cells have a threshold voltage above the verify voltage of the A state, and ii) beginning verification of the B state in the next program verify loop after a predetermined number of memory cells have a threshold voltage above the verify voltage of the A state.

[0178] One embodiment includes a non-volatile storage system including a memory structure including NAND memory cells and one or more control circuits in communication with the memory structure. The one or more control circuits are configured to program a first group of NAND memory cells in the memory structure using a four-page Gray code having sixteen data states. The one or more control circuits are configured to program a second group of NAND memory cells in the memory structure using a three-page Gray code based on eight of the sixteen data states, the eight data states being sequentially ordered in the three-page Gray code. The one or more control circuits are configured to determine whether to skip verification of a particular program verify loop for a first set of one or more data states of the three-page Gray code based on a first test. The one or more control circuits are configured to determine whether to skip verification of a particular program verify loop for a second set of one or more data states of the three-page Gray code based on a second test.

[0179] For purposes of this specification, references to "an embodiment," "one embodiment," "some embodiments," or "another embodiment" in the specification may be used to describe different or the same embodiments.

[0180] For purposes of this specification, a connection may be a direct connection or an indirect connection (e.g., through one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element, or indirectly connected to the other element through one or more intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are in "communication" if they are directly or indirectly connected such that they can exchange electronic signals between each other.

[0181] For purposes of this specification, the term "based on" may be read as "based at least in part on."

[0182] For purposes of this specification, the use of numerical terms such as "first" object, "second" object, and "third" object, without additional context, does not imply an ordering of the objects, but instead may be used for discriminatory purposes to distinguish between different objects.

[0183] For purposes of this specification, the term "set" of objects may refer to a "set" of one or more objects.

[0184] The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The described embodiments have been selected to best explain the principles of the proposed technology and its practical application, thereby enabling those skilled in the art to best utilize this technology in various embodiments, with various modifications as appropriate for the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.

Claims

1. An apparatus comprising: one or more control circuits configured to couple to a memory structure comprising non-volatile memory cells, the one or more control circuits comprising: programming a first group of memory cells in the memory structure using a 4-bit code having 16 states and 4 pages; programming a second group of memory cells in the memory structure using a 3-bit code based on three of the four pages, the 3-bit code including eight of the sixteen states of the 4-bit code, with unused pages of the 4-bit code including default values; and The apparatus is configured to perform, for each particular state of a first set of one or more states of the eight states, beginning verification during programming using the 3-bit code during a program verify loop determined based on whether a number of memory cells having a threshold voltage above a verify voltage of a state immediately preceding the particular state at a threshold voltage is greater than a predetermined number.

2. the one or more control circuits 2. The apparatus of claim 1, further configured to: for each particular state of a second set of one or more states of the eight states, begin verification during programming using the 3-bit code during a program verify loop determined based on a predetermined number of program verify loops after beginning to verify a state immediately preceding the particular state at a threshold voltage.

3. the eight states include an erased state, and states A, B, C, D, E, F, and G at increasing threshold voltages; the first set includes the B state; 3. The apparatus of claim 2.

4. the second set includes the C state, the D state, the E state, the F state, and the G state; 4. The apparatus of claim 3.

5. The first set comprises:

3. The apparatus of claim 2 including all states in said 3-bit code immediately following a state in said 4-bit code that is also used in said 3-bit code.

6. the eight states include an erased state, and states A, B, C, D, E, F, and G at increasing threshold voltages; the first set includes the B state whether the B state follows a state in the 4-bit code that is also used in the 3-bit code, or whether the B state follows a state in the 4-bit code that is not used in the 3-bit code; 6. The apparatus of claim 5.

7. The second set comprises:

6. The apparatus of claim 5, including a state in the 3-bit code that immediately follows a state in the 4-bit code that is not used in the 3-bit code, but does not include any state in the 4-bit code that is also used in the 3-bit code.

8. Programming the second group of memory cells in the memory structure using the 3-bit code based on three of the four pages of the 4-bit code includes the one or more control circuits: loading the three data pages into a corresponding third set of three data latches associated with the memory cells; and 2. The apparatus of claim 1 , further configured to load the default value into a fourth set of data latches associated with a memory cell, the default value being the same for all data latches in the fourth set of data latches.

9. the one or more control circuits 9. The apparatus of claim 8, further configured to program the three data pages into the memory cells based on a programming algorithm that takes into account the three data pages in the corresponding three third set of data latches and the default values ​​in the fourth set of data latches.

10. 1. A method of operating a non-volatile storage device, comprising: loading three pages of data into three corresponding sets of data latches; loading a default value into a fourth set of data latches, the default value being the same for all latches in the fourth set; programming the three data pages into a group of memory cells in the non-volatile storage device, the three data pages being programmed as eight threshold voltage distributions including an A state and a B state; i) skipping the B-state verify of each program verify loop before a predetermined number of memory cells have a threshold voltage above the A-state verify voltage; and ii) programming, the method including beginning verification of the B state in a next program verify loop after the predetermined number of memory cells have a threshold voltage above the verify voltage of the A state.

11. initiating verification for each respective state having a threshold voltage above the B state based on a number of program loops executed after initiating verification of the B state; The method of claim 10 further comprising:

12. loading four pages of data into four corresponding sets of said data latches; programming the four data pages into the group of memory cells in the non-volatile storage device according to a four page Gray code, the four data pages being programmed as 16 threshold voltage distributions corresponding to 16 states of the four page Gray code, eight threshold voltage distributions corresponding to eight of the 16 states, the eight states being a three page Gray code; The method of claim 10 further comprising:

13. starting verification of a particular state following an unused state in the four-page Gray code based on the number of program loops executed after starting verification of the state in the three-page Gray code immediately preceding the particular state, the particular state having a threshold voltage greater than the B state and at a threshold voltage; The method of claim 12 further comprising:

14. initiating verification of a particular state following a used state in the four page Gray code based on counting the number of memory cells having a threshold voltage greater than the B state and greater than a verify voltage of a state immediately preceding the particular state in threshold voltage; The method of claim 12 further comprising:

15. 1. A non-volatile storage system, comprising: a memory structure including NAND memory cells; and one or more control circuits in communication with the memory structure, the one or more control circuits comprising: programming a first group of the NAND memory cells in the memory structure using a four page Gray code having 16 data states; programming a second group of the NAND memory cells in the memory structure using a three page Gray code based on eight of the sixteen data states, the eight data states being sequentially ordered within the three page Gray code; determining whether to skip verification of a particular program verify loop for a first set of one or more data states of the three page Gray code based on a first test; and and determining whether to skip verification of a particular program verify loop for a second set of one or more data states of the three page Gray code based on a second test.

16. the first test includes determining whether a predetermined number of memory cells have a threshold voltage that is greater than a verify reference voltage of a previous data state in the three page Gray code in a previous program verify loop; the second test includes determining whether a predetermined number of program pulses have been applied to the memory cell after the program verify loop in which verification of the previous data state in the three page Gray code was initiated. The non-volatile storage system according to claim 15.

17. the eight data states include an erased state, and states A, B, C, D, E, F, and G at increasing threshold voltages; the first set includes the B state, the second set includes the C state, the D state, the E state, the F state, and the G state; 17. The non-volatile storage system according to claim 16.

18. the first test includes determining whether a predetermined number of memory cells have a threshold voltage that is greater than a verify reference voltage of a previous data state in the three page Gray code in a previous program verify loop; the first set includes all data states following a used state in the four page Gray code; The non-volatile storage system according to claim 15.

19. the first test is used for the B state, regardless of whether the B state is preceded by a used data state or an unused data state from the four page Gray code; 20. The non-volatile storage system according to claim 18.

20. the second test includes determining whether a predetermined number of program pulses have been applied to the second group of memory cells after the program verify loop in which verification of a previous data state in the three page Gray code was initiated; the second set includes a data state following an unused state in the four page Gray code and does not include any data state following a used state in the four page Gray code. The non-volatile storage system according to claim 15.

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