Bridge Circuit

Abstract

To solve the problem in which, when using a series connection of switches to configure an inverter for a high voltage, components to be added to maintain the balance of a voltage applied to each switch become large, and when using a flying capacitor type circuit, a capacitor with a relatively large capacitance is required as a component to be added as well.SOLUTION: In the flying capacitor type circuit, by switching series switches almost simultaneously. The function as a multilevel circuit is abolished, and only the handling of high voltage is realized. In this way, the adaptation of smaller capacitance will be sufficient to reduce the size of the device, lower the cost, and improve the power conversion efficiency.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a special configuration of a flying capacitor power converter and a method of switching the switches in the converter. [Background technology]

[0002] A bridge circuit is known that is used in inverters and has as its main components two switches connected in series between both poles of a DC voltage section. The withstand voltage of the two switches used in the bridge circuit must be higher than the voltage of the DC voltage section. Furthermore, since a surge voltage is superimposed during switching, the withstand voltage must be higher than the maximum voltage applied to both ends of the switches during operation of the bridge circuit. For example, if the steady-state voltage of the DC voltage section is 400V, the withstand voltage of the switch must be approximately 600V, and if it is 800V, approximately 1200V. If a single switch cannot meet the withstand voltage, a switch group in which multiple switches are connected in series can be used. Such a configuration is shown in Patent Document 1, for example. FIG. 14 shows the configuration of the main part.

[0003] That is, for the voltage E of the DC voltage section, the switches Q1 and Q2 constitute the switch group on the positive side (upper arm), and the switches Q3 and Q4 constitute the switch group on the negative side (lower arm). In this way, when a single switch cannot handle the voltage E of the DC voltage section, it is possible to handle it by distributing the applied voltage by connecting multiple switches in series. However, it is difficult to always keep the voltages of multiple switches equal due to individual differences in the characteristics of the switches, and to address this, it is common to connect voltage balance circuits SN1 to SN4 in parallel to each switch.

[0004] In the example shown in the figure, the voltage balance circuit consists of an RC series circuit for transient voltage balance at the moment of switching, and resistors for steady voltage balance at other times. Even when a voltage balance circuit is provided in this way, even a slight deviation in the switching timing can make it difficult to maintain voltage balance, and in the worst case, a voltage higher than the withstand voltage can be applied to a single switch, leading to the destruction of the switch. To avoid this, it is necessary to increase the capacitance of the capacitors used in the voltage balance circuit or increase the power consumption of the resistors in accordance with the maximum value of the deviation in switching timing, which leads to reduced efficiency due to increased component size and generated losses, increased costs, and larger equipment size.

[0005] Multilevel converters are a circuit method that addresses these issues. Multilevel converters are generally used primarily to reduce harmonics in the generated voltage by increasing the level of the stepped voltage generated at the input and output terminals of a bridge circuit. In addition, in many of these methods, an additional circuit is added to multiple switches connected in series, so that a divided voltage from the DC voltage section is applied to each switch, making it possible to realize a power converter that can handle high voltages that a single switch would not be able to withstand.

[0006] There are several types of multilevel converters, one of which is the flying capacitor type multilevel circuit (hereafter referred to as FC circuit). An example of the configuration of an FC circuit is shown in Fig. 15. As in Fig. 14, switches Q1 to Q4 are connected in series across the DC voltage section of voltage E, but instead of connecting a voltage balance circuit to each switch, a capacitor FC1 is connected between the connection points of switches Q1 and Q2 (upper arm of the bridge circuit), and switches Q3 and Q4 (lower arm of the bridge circuit). The voltage across capacitor FC1 is usually controlled so as to be maintained at 1 / 2 of the voltage E of the DC voltage section, i.e., E / 2, on average.

[0007] In addition to this, by appropriately controlling the switching of the four switches Q1 to Q4, the steady voltage applied to each switch can be approximately E / 2. Also, the connection point U between the switches Q2 and Q3 is an input / output terminal of the FC circuit, and three levels of voltage, 0, power supply voltage E, and E / 2, can be generated in a stepped waveform as the voltage of the input / output terminal U with respect to the negative pole N of the DC power supply. The FC circuit is publicly known, and is disclosed, for example, in Patent Document 2, including the above-mentioned switching control, so a detailed description will be omitted here. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2005-167535 A [Patent Document 2] International Publication No. 2015 / 030152 Summary of the Invention [Problem to be solved by the invention]

[0009] In a multilevel converter, the main focus is basically on reducing harmonics in the output voltage as described above, so there is a reasonable period during which an intermediate voltage (E / 2 in the example in Figure 15) is output. In the FC circuit, during this period, capacitor FC1 is charged or discharged by input / output current I. Each switch normally switches repeatedly at a constant cycle Tc, and the period during which E / 2 is continuously output is taken as t. If we consider the output current I to be constant during period t, then the voltage fluctuation width ΔVcf of the voltage Vcf across capacitor FC1 (capacitance Cf) is given by the following equation 1.

[0010] (Formula 1) ΔVcf = (I × t) / Cf (where t <Tc) ΔVcf must be kept within a specified value, due to restrictions on the withstand voltage of the switch and from the standpoint of output voltage control. If the restriction values ​​are 1 / 100 of E, E is 3000V, Tc is 1ms, the maximum value of period t is 300μs, and the maximum value of I is 500A, then from formula 1 the required capacitance Cf is 5mF. A minimum of (E+ΔVcf) / 2 is applied to capacitor FC1, so in this example a withstand voltage of 1600V or more is required, including a margin, and such a high-voltage capacitor with a capacitance of 5mF would be large in volume and mass, and would also be expensive.

[0011] Therefore, the problem to be solved by the present invention is to make the FC circuit suitable for application to high voltages by reducing the capacitance of the capacitors used in the FC circuit while limiting the voltage applied to each switch to a predetermined value. [Means for solving the problem]

[0012] In order to achieve the above object, the bridge circuit according to the present invention is a bridge circuit characterized in that in an FC circuit, in each of the upper and lower arms, the switches belonging to the upper and lower arms are turned on and off substantially simultaneously. Effect of the Invention

[0013] According to the present invention, it is possible to apply an FC circuit using a capacitor with a small capacitance and volume, without increasing the capacitance, and therefore the volume, of the capacitor connected between the upper and lower arms of the FC circuit. [Brief description of the drawings]

[0014] [Figure 1] An example of a flying capacitor circuit and the capacitor charging and discharging paths [Diagram 2] Multi-stage flying capacitor circuit [Diagram 3] FIG. 1 is a schematic diagram showing a method for generating a switching signal for controlling a capacitor voltage in a flying capacitor circuit; [Figure 4]Switch control section in a flying capacitor circuit (block diagram of switching signal generation and capacitor voltage control) [Diagram 5] An example of the capacitor charge / discharge path in a multi-stage flying capacitor circuit [Figure 6] Switch control section in a multi-stage flying capacitor circuit (block diagram of switching signal generation and capacitor voltage control) [Figure 7] An explanatory diagram of the principle of microsurge suppression using a flying capacitor circuit [Figure 8] A schematic diagram (time chart) showing how to generate a switching signal to control the capacitor voltage when outputting a staircase wave in a flying capacitor circuit. [Figure 9] A switch control section that balances the charging and discharging of the capacitors in the flying capacitor circuit that outputs a staircase wave [Figure 10] A schematic diagram (time chart) showing an example of the capacitor charge / discharge path when outputting a staircase wave in a multi-stage flying capacitor circuit, and a method of generating a switching signal for controlling the capacitor voltage. [Figure 11] A switch control section that balances the charging and discharging of the capacitors in the multi-stage flying capacitor circuit that outputs a staircase wave [Figure 12] Another schematic diagram (time chart) showing how to generate a switching signal to control the capacitor voltage when outputting a staircase wave in a flying capacitor circuit. [Figure 13] Another schematic diagram (time chart) showing a method of generating a switching signal to control the capacitor voltage when outputting a staircase wave in a flying capacitor circuit. [Figure 14] A bridge circuit consisting of switches connected in series [Figure 15] Flying Capacitor Circuit DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, an embodiment of the present invention will be described.

[0016] FC circuits are usually intended to be used as multilevel circuits, that is, by making the voltages at the input and output terminals of the bridge circuit step-like as described above, harmonics are reduced, and filter circuits such as reactors required to improve the output current waveform can be made smaller. If the FC circuit is not given the function of reducing harmonics in the input and output terminal voltages by using intermediate voltages, but is instead configured to specialize in another advantage of the FC circuit, that is, being able to handle high voltages by connecting low-voltage switches in series, then the following major benefits can be enjoyed.

[0017] The first embodiment will be described. FIG. 1 is a diagram showing a current path when the capacitor FC1 in the FC circuit in the first embodiment is charged and discharged. In the following description, the switches Q1 to Q4 may be simply referred to as Q1 to Q4, omitting the word "switch". The switches Q1 to Q4 operate according to an on / off command generated by a switch control unit. The case is shown in which the direction of the current at the input / output terminal is a polarity that flows into the bridge circuit. In this case, as is well known, when Q2 and Q4 are on and Q1 and Q3 are off (mode M2), the capacitor FC1 is charged, and conversely, when Q2 and Q4 are off and Q1 and Q3 are on (mode M1), the capacitor FC1 is discharged. In either case, the voltage at the input / output terminal U is E / 2 with respect to the negative pole N of the power supply voltage. The above-mentioned formula 1 represents the voltage fluctuation of the capacitor FC1 in this case. On the other hand, although not shown in the figure, when Q1 and Q2 are on and Q3 and Q4 are off (mode P), the voltage at input / output terminal U is E, and when Q1 and Q2 are off and Q3 and Q4 are on (mode N), the voltage at input / output terminal U is 0. In either case, no current flows through capacitor FC, so there is no charging or discharging.

[0018] From this, in theory, if mode M1 and mode M2 ​​are not used, that is, if Q1 and Q2, and Q3 and Q4 are always switched simultaneously, the capacitor FC1 will not be charged or discharged, and therefore the voltage of the capacitor will not fluctuate. However, in reality, such simultaneous switching cannot be achieved due to the variation in the characteristics of the switches and control circuits, and the switching timing will be shifted. However, the shift is generally short, and for general IGBTs and MOS-FETs, the shift is less than a few microseconds and 1 microsecond, respectively. In formula 1, if ΔVcf is 30V, Tc is 1ms, I is 500A, and t is 10μs, as above, it can be derived that the capacitance Cf of capacitor FC1 is only 167μF. This is only 1 / 30 of the 5mF calculated in the above example, and it is possible to significantly reduce the size of capacitor FC1. In addition, since the only elements used in an FC circuit other than the switches are capacitors, it is more efficient than those that have resistive elements that involve losses as shown in Figure 14, and no heat dissipation means are required to dissipate the heat generated by the resistors.

[0019] Figure 2 shows another form of the FC circuit. As is well known, an FC circuit is configured by configuring the upper and lower arms of a bridge with two or more switches in series, and by connecting capacitors to the connection terminals of each switch between the upper and lower arms, centered on the input / output terminals that are the connection points of the upper and lower arms, any number of stages can be configured in theory. In general, the more stages, i.e., the more series switches in one arm, the higher the voltage that can be supported. The present invention is applicable regardless of the number of stages in an FC circuit, and by switching the switches in one arm substantially simultaneously, the effects of variations in the switches and peripheral circuits can be mitigated by the action of the capacitors, while the voltage applied to each switch can be operated so as not to exceed its withstand voltage.

[0020] As described above, in an FC circuit, by performing the switching of the switches belonging to the upper and lower arms essentially simultaneously, it is possible to significantly reduce the capacitance of the capacitor, and therefore its volume and cost.

[0021] Here, it is also necessary to specify the capacitance of the capacitor. The voltage fluctuation of the capacitor becomes the voltage applied to both ends of the switch as it is, and also directly affects the voltage appearing at the input / output terminals. Therefore, if it is not limited to a specified value, problems will arise in terms of the switch's withstand voltage and control of the output waveform. It is considered appropriate to suppress this voltage fluctuation range to less than about 10% of the switch's withstand voltage. The reason for this is that the maximum value of the jump in the voltage across the switch during switching is generally set with a margin of up to about 10% of the switch's withstand voltage, so it can be said that a similar idea is appropriate. On the other hand, the aforementioned switching timing deviation becomes an error in the output voltage, and the ratio of this is determined by the ratio of the deviation to the switching period, so it is common to design to suppress this. Since the allowable value of the output voltage error is almost always 10% or less, it can be said that it is safe to assume a maximum of 10% of the switching period for the switching timing deviation assumed in this technical idea. From the above, and taking into account Equation 1, it can be said that setting the capacitance of the capacitor (FC1 in Figure 1) to the following value is an indicator for achieving stable circuit operation to obtain the effects of the present invention.

[0022] Capacitor capacitance value: The value at which the voltage change due to charging and discharging the amount of charge equivalent to the current at the input / output terminals of the FC circuit multiplied by 10% of the switching operation period is 10% or less of the withstand voltage of the switch to which the voltage across the capacitor is applied.

[0023] Next, a more specific embodiment will be described.

[0024] As described above, if switching is performed substantially simultaneously and the effects of timing errors that actually occur are absorbed by a capacitor, the capacitor voltage will fluctuate significantly while the circuit is operating due to cumulative charging and discharging at each switching in accordance with Equation 1. In order to avoid this, it is effective to control the switching timing, and in this case, it is necessary to intentionally shift the switching timing in order to ensure a certain range of control over the timing. As is clear from Equation 1, the larger the intentional shift is, the greater the voltage fluctuation in the capacitor will be (or the larger the capacitance of the capacitor required to keep the voltage fluctuation range within a specified value will be), so it must be set carefully.

[0025] As mentioned above, the switching timing error is at most a few microseconds, so it is practically desirable to set the intentional deviation to about 10 microseconds. When operating as a multilevel circuit, the period t during which the input / output terminal outputs E / 2 must be a fraction of the switching period, so even if a fairly short switching period of 100 μs is assumed for a high-voltage circuit, several tens of μs is still required. Therefore, if the switching deviation of 10 μs is specified as above, the circuit will not function as a multilevel circuit and will fall within the scope of the present invention. Therefore, this value (10 μs) can be said to be suitable when the FC circuit is not operated as a multilevel circuit and is used for the purpose of applying to high voltages.

[0026] FIG. 3 shows an example of a method for generating switching command signals when shifting the switching timing for the four switches Q1 to Q4 in the circuit of FIG. 1. In a normal two-level full-bridge circuit, the switches are controlled so that the upper and lower arm switches are not turned on at the same time. The same is basically true for the FC circuit; if Q2 and Q3 are turned on at the same time, the capacitor FC1 will be short-circuited, and if Q1 and Q4 are turned on at the same time, the power supply voltage E will be applied to the capacitor FC1, which is charged at approximately E / 2, so these must be avoided. Then, as shown in FIG. 1, when Q1 and Q3, and Q2 and Q4 are turned on at the same time, the capacitor FC1 is charged or discharged depending on the polarity of the output current I.

[0027] Therefore, the key to switching Q1 to Q4 is to control charging and discharging by turning on Q1 and Q3 or Q2 and Q4 simultaneously for a short time so that Q1 and Q4 and Q2 and Q3 are not turned on at the same time, and Q1 and Q2 and Q3 and Q4 are turned on and off almost simultaneously, and the voltage of the capacitor FC1 is maintained at approximately E / 2. To achieve this effectively, as shown in Fig. 3, the PWM method of comparing carrier waves (triangular waves, sawtooth waves, etc.) is used as a basis, and the on and off of Q1 to Q4 can be determined by a square wave signal obtained by comparing the Q1, Q4 signal waves and the Q2, Q3 signal waves that control the switching of Q1 and Q4 and Q2 and Q3, respectively, with a triangular wave. Furthermore, by setting a slight magnitude relationship in the amplitude of both signal waves, a switch state that charges and discharges the above-mentioned capacitor FC1 is created, and charging and discharging can be switched by switching the magnitude relationship.

[0028] An example of the configuration of a control system that generates the waveform shown in Fig. 3, charges and discharges the capacitor FC1, and maintains the voltage at a specified value is explained using Fig. 4. The voltage command value to be output by the FC circuit is compared with a carrier wave such as a triangular wave or a sawtooth wave by a comparator, and furthermore, dead time is added so that the on periods of Q1 and Q4, and Q2 and Q3 do not overlap, and switching command signals for Q1 to Q4 are obtained.

[0029] Here, Q1 and Q4, and Q2 and Q3 are turned on and off complementarily, so for each combination, there is a complementary signal generation section that passes a NOT element on one side (Q4 and Q3) of the comparator output. According to the above explanation, Q1 and Q2, and Q3 and Q4 are in principle switched simultaneously, that is, the same switching signal is given. Here, a further measure is added to control charging and discharging by turning on Q1 and Q3, or Q2 and Q4, simultaneously for a short time so that the voltage of capacitor FC1 is maintained at approximately E / 2. This can be done by making the Q1 and Q4 signal waves the same value for the voltage command value, while correcting the Q2 and Q3 signal waves according to the voltage Vcf of capacitor FC1.

[0030] This correction is performed by the signal correction section. That is, a reference value for Vcf, for example E / 2, is set, and the difference between this and the detected value of Vcf is taken. This difference is input to a regulator, for example a proportional regulator (P regulator), to obtain a correction value. Depending on this correction value, if the detected value is smaller than the reference value of Vcf, capacitor FC1 must be charged, and if the opposite is true, it must be discharged. Also, whether charging or discharging occurs depending on the state of a certain switch depends on the direction of the current at the input / output terminals, so the sign of the correction value must be inverted accordingly.

[0031] As mentioned above, when the direction of the current at the input / output terminals is such that it flows into the FC circuit, capacitor FC1 is charged when Q2 and Q4 are on and Q1 and Q3 are off (mode M2). Therefore, when it is necessary to charge capacitor FC1, that is, when the reference value - detection value of Vcf is positive, the correction value of the Q2, Q3 signal waves should be positive so that the Q2, Q3 signal waves become larger than the Q1, Q4 signal waves (see Figure 3). Therefore, a multiplier should be provided to assign a sign to the output of the P regulator in Figure 4 so that the current at the input / output terminals is positive in the direction that it flows into the FC circuit.

[0032] In addition, as mentioned above, if the deviation in the switching timing becomes too large, the voltage fluctuation of the capacitor may become larger than expected, so a method of avoiding this is to provide a limiter for the correction value. With the above configuration, it is possible to generate a voltage according to the voltage command value at the input / output terminals of the FC circuit, while appropriately controlling the switching timing to maintain the voltage of the capacitor FC1 at a predetermined value.

[0033] In the above, the voltage control and switch operation in the case where there is one capacitor FC1, i.e., two switches in series in one arm, have been explained, but by expanding this concept, it is possible to handle any number of capacitors. This will be explained next as a second embodiment using Figures 5 and 6.

[0034] First of all, as a basic principle, the operation principle of an FC circuit is that (1) two switches in symmetrical positions in the upper and lower arms (for example, Qp4 and Qn1, or Qp2 and Qn3 in Figure 5) must not be turned on at the same time (they are always complementary during operation, i.e., if one is on, the other is off). This is to avoid connecting (short-circuiting) a charged capacitor to a different voltage, as described in the explanation of Figure 3 above. In addition, another principle of an FC circuit is that (2) whether a capacitor is in a charged, discharged, or uncharged state is determined only by the state of the switch connected to one end of the capacitor, and does not depend on the state of the other switches. However, it is important to note that charging and discharging are reversed depending on the polarity of the current at the input and output terminals. Note that the premise of principle (2) is that if the state of one switch is determined by the complementary operation of the two switches described in principle (1), the state of the other switch is also determined.

[0035] This will be explained with a specific example using FIG. 5. In FIG. 5, the switch Qp1 of the upper arm is on. Therefore, Qn4, which is in the symmetrical position of the lower arm, is off. Next, Qp2 is off. Similarly, Qn3 is on. Also, for the input / output terminal U, the polarity of the current is in the direction flowing into the FC circuit. In the above state, regardless of the state of the remaining switches Qp3, Qp4, Qn1, and Qn2, the capacitor FC11 is in a discharging state. In other words, the current path in the FC circuit is a switch or a series circuit of a switch and a capacitor, and the current is not divided anywhere or disappears. Therefore, if Qp1 is on and Qp2 is off, the current flowing in from the input / output terminal always passes through the capacitor FC11 and flows through Qp1, which becomes the discharging polarity due to the steady charging polarity of FC11. For example, if the current polarity at the input and output terminals is the same and Qp1 is off and Qp2 is on, the polarity of the current flowing through FC11 is reversed, resulting in charging, and if Qp1 and Qp2 are both on or both off, the charge and discharge of FC11 will be zero. Using the same concept, the charge and discharge states of the other capacitors FC12 and FC13 are also determined by the state of the switches connected to each of them.

[0036] From the above, it can be seen that in order to determine the charge / discharge state of the capacitor, it is necessary to control only the polarity of the current and the state of the connected switch. When a control system is configured based on this idea, it looks like Figure 6. Note that in this figure, the NOT element and dead time block shown on the right side of Figure 4, as well as the correction value limiter, are omitted because they are the same as in Figure 4. As explained above, in order to control the voltage of FC11, it can be determined by only two elements: whether the switching timing of Qp2 (Qn3) is early or late relative to the switching timing of Qp1 (Qn4), and the polarity of the current at the input / output terminals.

[0037] Therefore, as in the case of FIG. 4, the error of the detected value with respect to the reference value of the voltage Vcf1 of FC11 is input to the P regulator, the sign of the value is determined by the polarity of the current at the input / output terminal, and the voltage command value of Qp2 (Qn3) is determined by adding the value to the voltage command value of Qp1 (Qn4). Then, in exactly the same way, for the switch Qp3 (Qn2) inside Qp2 (Qn3), the voltage command value of Qp2 (Qn3) is adjusted based on the voltage Vcf2 of FC12 and the polarity of the current to generate a voltage command value. The same is true for the capacitor FC13. In this way, even if the capacitor is in multiple stages, it is sufficient to adjust the switching timing of the adjacent switches in order, so that, as shown in FIG. 6, a control system for controlling the capacitor voltage to a predetermined value can be configured by adding control blocks in a cascade manner, one stage at a time, to the voltage command value for the switch on the outside of the input / output terminal.

[0038] Next, a third embodiment of the present invention will be described. As described with reference to FIG. 3, the voltage of the capacitor FC1 can be controlled so as to coincide on average with a certain command value (reference value). That is, it is also possible to set a value higher or lower than 1 / 2 of the DC voltage E as the Vcf reference value in FIG. 3. For example, if the Vcf reference value is E / 4, it is possible to suppress the voltage applied to the switches Q2 and Q3 to be lower than when the Vcf reference value is E / 2, and this makes it possible to use switches with low withstand voltage as Q2 and Q3. In this case, the withstand voltage relationship is that Q2 and Q3 are lower than Q1 and Q4. In general, the withstand voltage of a switch is not continuous but has large jumps. For example, since it is common that the voltage above 1.7 kV is 3.3 kV, when the DC voltage is a value that is slightly insufficient for a switch with a withstand voltage of 1.7 kV, it is necessary to use a switch with a withstand voltage of 3.3 kV. This causes a problem that the margin of withstand voltage is too large, and the conduction loss and cost (both of which generally increase monotonically with respect to the withstand voltage) increase.

[0039] Therefore, in the FC circuit, if a 1.7 kV withstand voltage switch is used for Q1 and Q4, and a low withstand voltage switch (for example, 600 V) is used for Q2 and Q3 to compensate for the insufficient voltage, and the voltage of the capacitor FC1 is controlled to a voltage suitable for the withstand voltage of 600 V, the withstand voltage of the combination of switches can be optimized and a conversion circuit with reduced conduction loss can be realized. Since a certain capacitance is required for the capacitor FC1, the lower the withstand voltage of the capacitor, the smaller its volume becomes. Therefore, in the circuit of FIG. 1, among Q1 and Q2 (Q4 and Q3), if Q2 (Q3) is a low withstand voltage switch and Q1 and Q4 are high withstand voltage switches, the size and cost of the capacitor FC1 can be reduced. Furthermore, as disclosed in this application, by using the FC circuit as a substantially two-level circuit rather than a multilevel circuit, uneven voltage levels do not become a major problem. In this case, the control of the bridge circuit can be performed in the same way by setting the Vcf reference value in FIG. 4 to a certain value other than E / 2.

[0040] Next, a fourth embodiment, which is yet another embodiment of the present invention, will be described. In general, when a motor is driven by an inverter, a problem of so-called microsurge may occur. That is, when the cable connecting the inverter and the motor is long, its distributed constant behavior cannot be ignored, and since the cable and the motor generally do not have impedance matching, when a rectangular wave voltage is applied to the cable by the inverter, a voltage jump (microsurge) occurs at the motor end. This microsurge causes stress to the motor's insulator, especially the insulator of the winding coating, and deteriorates the insulation, and if the deterioration progresses, it may lead to insulation breakdown and cause the motor to burn out. This problem becomes more noticeable as the voltage increases, and is particularly problematic in high-voltage converters that require switches to be connected in series.

[0041] This problem can be suitably alleviated by adjusting the output period of the stepped output voltage in the FC circuit, as described below. Here, the circuit in Fig. 1, in which one side of the switch group has two switches, is used as an example. When the potential of the input / output terminals of the FC circuit is shifted, for example, from the negative potential of the DC voltage section to the positive potential, an intermediate voltage can be generated during the period of slight deviation in the switching timing, as described above. In this case, by setting the generation period t of the intermediate voltage to exactly 1 / 2 the period 2T of the vibration at the motor terminal, i.e., T, the vibration waveform at the motor terminal can be cancelled out, and the microsurge can be suppressed.

[0042] Generally, the period T is about several microseconds, and the technical idea of ​​outputting a stepped voltage for only a short time, as in the present invention, is well suited to this. The above will be explained in more detail with reference to Fig. 7. First, a stepped waveform with an amplitude of E / 2 is generated as the inverter input and output terminal voltage. The period t is an extremely short time in the order of microseconds. At this time, the terminal voltage (load terminal voltage) of the load (representatively a motor) rises after a delay time from the first step (first step) of the stepped wave caused by the length and characteristics of the cable to the load.

[0043] This first step generates an oscillatory waveform (microsurge) component (voltage due to the first step) in the load terminal voltage that has an amplitude greater than E / 2. The period of this oscillatory waveform component is 2T, and as described above, the interval between the step waves of the inverter input / output terminal voltage is set to 1 / 2 that, T. The next step wave step (second step) is generated a period T after the first step. Similarly, the second step generates an oscillatory waveform component (voltage due to the second step) similar to the first step in the load terminal voltage. The actual load terminal voltage is a composite waveform of the voltage due to the first step and the voltage due to the second step described above, so that the two oscillatory waveforms cancel each other out due to the time difference of period T, resulting in a voltage waveform of amplitude E with suppressed microsurges.

[0044] In the above, the period T is set to 1 / 2 of the vibration period of the microsurge, but even if this is slightly deviated, the effect of suppressing the microsurge can be obtained and is included in the scope of this technical idea. In addition, a content similar to the technical idea described above is presented in Patent Gazette No. 5800133 for a different circuit method. However, the circuit shown in the publication is premised on operating as a multilevel circuit, and requires additional switches and potential division of the capacitors to generate an intermediate voltage. In contrast, in this embodiment, the circuit is not operated as a multilevel circuit, and additional switches and potential division of the capacitors are not required to generate an intermediate voltage, and the purpose is to realize a substantially two-level circuit of high voltage using low-voltage withstand switches, so that the purpose of suppressing the microsurge by generating a stepped voltage for several microseconds can be preferably realized at low cost using a capacitor with small capacitance.

[0045] However, when the inverter input / output terminal voltage is intentionally made step-shaped, for example when suppressing microsurges as described above, as this causes the capacitor to be frequently charged and discharged, as already explained, it becomes necessary to take measures to maintain the capacitor voltage at a specified value. This will be explained next.

[0046] FIG. 8 shows how to apply a signal wave when generating a step wave at both the inverter input and output terminals U for the circuit configuration of FIG. 1, and the resulting voltage (U potential) at the inverter input terminal U. As explained for FIG. 3, when the current I flows in the input and output terminals, the capacitor FC1 is charged when Q2 and Q4 are turned on simultaneously (mode M2), and the capacitor FC1 is discharged when Q1 and Q3 are turned on simultaneously (mode M1). When the polarity of the current I is reversed, the charging and discharging with respect to the switch state is also reversed. In both modes M1 and M2, the U potential is E / 2. From this, in order to generate a step wave as the U potential, that is, to output E / 2 for a predetermined period T, and to maintain the voltage of the capacitor FC1 at a predetermined value, it is effective to alternate between the states M1 and M2 of the two switches to balance the charging and discharging. In Figure 8, by swapping the magnitude relationship between the Q1, Q4 signal waves and the Q2, Q3 signal waves during the ascending and descending of the triangular wave carrier, M1 and M2 are alternately swapped when the U terminal outputs E / 2. In this way, it is possible to easily achieve a balance between charging and discharging.

[0047] Figure 9 shows an example of the configuration of a control system for balancing charging and discharging as described above for the circuit configuration of Figure 1. The configuration of the signal correction unit is similar to that shown in Figure 4, but it differs in that an intermediate voltage generation period addition unit is newly provided, and the correction value, which is the output value of the signal correction unit, is not directly added to the Q2 and Q3 signal waves. That is, in Figure 9, in the intermediate voltage generation period addition unit, the correction value output by the signal correction unit is added to the value obtained by converting the aforementioned intermediate voltage generation period t into a ratio to the voltage command value by voltage conversion.

[0048] By multiplying this value by 1 / 2 and multiplying it by the carrier half-cycle synchronized square wave, a square wave synchronized with the carrier half cycle and having an amplitude corresponding to 1 / 2 of the value obtained by adding the correction value to the period t is generated. By adding this square wave to the Q1, Q4 signal waves and the Q2, Q3 signal waves with their polarities inverted, a square wave of opposite polarity that changes at the peaks and valleys of the carrier wave is superimposed on the two signal waves as shown in Figure 8. When the correction value is zero, a square wave of opposite polarity corresponding to t / 2 is superimposed on each of the two signal waves, so that the output period of the intermediate voltage of the resulting step wave is t (= T), and the waveform described in Figure 7 is output. When the correction value is not zero, that is, when the capacitor voltage has an error with respect to the set value, the output period of the intermediate voltage is changed so that this error is reduced by the correction value. If this change amount is a small value with respect to t, the capacitor voltage can be maintained close to the set value while maintaining the microsurge suppression effect.

[0049] Although the above describes a flying capacitor circuit with one capacitor as shown in Fig. 1, a similar concept can also be applied to a multi-stage flying capacitor circuit with multiple capacitors, such as that shown in Fig. 5. That is, by outputting a multi-stage step-like voltage that holds an intermediate voltage for only a very short period T, and by configuring a feedback control system similar to that shown in Fig. 9 to correct the output period of the intermediate voltage so that the voltages of multiple capacitors (FC11, FC12, and FC13 in Fig. 5) are maintained at predetermined values, it is possible to maintain the capacitor voltage at a value close to the set value while maintaining the microsurge suppression effect, even in a multi-stage flying capacitor circuit.

[0050] This is shown in Figures 10 and 11. Figure 10 shows (a) the current path in a certain switch state in the flying capacitor circuit with four series elements on one side shown in Figure 5, and (b) the method of generating the operation command value for each switch, the U potential, and the charge / discharge operation of the capacitor. As shown in (b), by swapping the magnitude relationship of the signal waves (e.g., Qp1 and Qn4 signal waves) for providing on / off signals to the four switches on one side, as in the waveforms shown in Figure 8, it is possible to provide a time difference between the on / off signals provided to each switch. As a result, the waveform appearing in the U potential becomes a multi-stage staircase waveform. The two current paths shown in Figure 10(a) are at the timing added to the graph of the charge / discharge waveforms of FC11 to FC13 in Figure 10(b).

[0051] FIG. 11 is a control block diagram for realizing the operation shown in FIG. 10. The basic principle is the same as that of FIG. 9. The difference is that the output signal waves increase according to the number of switches in series, and a multistage intermediate voltage generation period addition unit and a multistage signal correction unit are provided corresponding to this. The multistage signal correction unit obtains the error with respect to the voltage command value for each of the capacitors FC11, FC12, and FC13, generates a correction value as in FIG. 9, and provides it to the multistage intermediate voltage generation period addition unit. The multistage intermediate voltage generation period addition unit, also as in FIG. 9, shifts the switching timing of adjacent switches by a period of time t plus the correction value. Note that, as shown in FIG. 10(b), the signal waves to each switch are evenly distributed on both the positive and negative sides of the reference value of the voltage command, so that the average value of the voltage of the U potential is set to a value corresponding to the reference value of the voltage command value. To achieve this, the Qp2, Qn3 signal waves and the Qp3, Qn2 signal waves are shifted positively or negatively by an amount equivalent to t / 2 relative to the reference value, and the Qp1, Qn4 signal waves and the Qp4, Qn1 signal waves, which should be shifted further by an amount equivalent to the period t, are configured in the same manner.

[0052] Next, as shown in Fig. 12, the magnitude relationship between the Q1, Q4 signal waves and the Q2, Q3 signal waves can be switched over in one cycle instead of half a cycle of the carrier. In this case, mode M1 and mode M2 ​​are each generated twice in succession and repeated. Therefore, while the cycle of charge and discharge adjustment is doubled compared to the case of Fig. 8, when the ripple caused by the switching of the input / output current I that controls charging and discharging is large, the ripple of this current usually repeats over one cycle of the carrier wave, improving the balance between charge and discharge compared to the case of Fig. 8. Note that the control system in this case is realized by changing the signal of the "carrier half cycle synchronous square wave" in the intermediate voltage generation period addition part to the "carrier one cycle synchronous square wave" in the case of Fig. 9.

[0053] Figure 13 shows the operation described above in more detail. The signal waves supplied to the switch switch between large and small in one cycle of the triangular carrier wave. Current I has a ripple corresponding to the switching cycle, which causes an imbalance in the charging and discharging currents of the capacitor, whose magnitude is determined by its instantaneous value. By switching the signal wave between large and small in each cycle of the carrier wave, charging and discharging are performed by roughly the same current, making it possible to alleviate the imbalance. Note that Figure 13 shows a case in which the charging and discharging times are equal in the first two cycles, the former is longer in the next two cycles, and the latter is longer in the final two cycles.

[0054] In the drawings used in the description of the above embodiments, each switch is configured with a MOSFET and a diode, but other switches such as IGBTs may also be used.

[0055] Furthermore, when shifting the timing of the switching operation, the timing of the switching operation of the outer switches may be shifted with respect to the inner switches using the input / output terminals as a reference. [Explanation of symbols]

[0056] Q1~Q4... Switch SN1~SN4: Voltage balance circuit FC1 Capacitor

Claims

1. A DC voltage section; Two switch groups connected in series between the positive and negative electrodes of the DC voltage unit; one or more capacitors connected between two of the switch groups; A bridge circuit in which a connection point between two of the switch groups serves as an input / output terminal, The two switch groups each include an equal number of switches connected in series, Both terminals of the capacitor are connected to connection points between the switches that are symmetrical with respect to the input / output terminals, The switching operations of the switches constituting each of the switch groups are performed substantially simultaneously, A bridge circuit characterized in that the capacitance of the one or more capacitors is a value such that a voltage change due to charging and discharging of an amount of charge equivalent to a current flowing from an input / output terminal during normal operation of the bridge circuit multiplied by 10% of a period of a switching operation is 10% or less of the withstand voltage of a switch to which the voltage across the capacitor is applied.

2. 2. The bridge circuit of claim 1, A bridge circuit characterized in that the voltage of the capacitor is maintained at a predetermined value by shifting the timing of the switching operation of the switch inside and the switch outside the connection point where both terminals of the capacitor are connected.

3. In the bridge circuit of claim 2, A bridge circuit, characterized in that the difference in timing is 10% or less of a switching operation period.

4. 4. The bridge circuit according to claim 1, In each of the switch groups, the switches constituting the switch group include one or more switches having different withstand voltages, and in the two switch groups, the switches having different withstand voltages are arranged symmetrically with respect to the input / output terminals.

5. A DC voltage section; Two switch groups connected in series between the positive and negative electrodes of the DC voltage unit; one or more capacitors connected between two of the switch groups; A bridge circuit in which a connection point between two of the switch groups serves as an input / output terminal, The two switch groups each include an equal number of switches connected in series, Both terminals of the capacitor are connected to connection points between the switches that are symmetrical with respect to the input / output terminals, The switching operations of the switches constituting each of the switch groups are performed substantially simultaneously, Further, a switch control unit is provided. The switch control unit includes: a complementary signal generating unit that complementarily turns on and off a pair of switches that are symmetrically positioned with respect to an input / output terminal in each of the two switch groups; and a signal correction unit that corrects the on / off timing of the two sets of switches connected to both ends of the capacitors in accordance with the difference between the voltage of each capacitor and a predetermined value.

6. A DC voltage section; Two switch groups connected in series between the positive and negative electrodes of the DC voltage unit; one or more capacitors connected between two of the switch groups; A bridge circuit in which a connection point between two of the switch groups serves as an input / output terminal, The two switch groups each include an equal number of switches connected in series, Both terminals of the capacitor are connected to connection points between the switches that are symmetrical with respect to the input / output terminals, The switching operations of the switches constituting each of the switch groups are performed substantially simultaneously, An electric device having an electric resonance element is connected to the input / output terminals, When the potential of the input / output terminal is changed from the positive electrode to the negative electrode or from the negative electrode to the positive electrode of the DC voltage section, a step-like potential change occurs, and the duration of one step in the step-like change is defined as a period t. A bridge circuit, characterized in that the period t is set to a value that suppresses vibration occurring at the terminals of the electrical equipment.

7. 6. The bridge circuit according to claim 5, wherein the switch control section comprises: When the potential of the input / output terminal is changed from the positive electrode to the negative electrode or from the negative electrode to the positive electrode of the DC voltage section, a step-like potential change occurs, and the duration of one step in the step-like change is defined as a period t. a signal correcting section for correcting the period t based on a correction value output from the signal correcting section,

8. In the bridge circuit according to claim 7, the switch control section comprises: By comparing the voltage command value with a carrier wave of a specified period, on / off signals for each switch are generated. the intermediate voltage generation period adding unit adds or subtracts an amount corresponding to a period t corrected based on a correction value output from the signal correcting unit, for every half cycle, one cycle, or several cycles of the carrier wave, to or from the voltage command value.

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