Electrostatic protection circuit and semiconductor integrated circuit

Abstract

To adequately protect inner circuits from occurrence of electrostatic discharge (ESD).SOLUTION: An ESD protection circuit 65 comprises: a pair of signal output terminals 92a and 92b; a pair of diodes 30a and 30b respectively connecting the pair of signal output terminals 92a and 92b to a common first node X1; a potential generation circuit 21 connected with the pair of signal output terminals 92a and 92b to generate a midpoint potential of the pair of signal output terminals 92a and 92b at the first node X1; and a clamp circuit 60 that connects the first node X1 to a ground wire, depending on the midpoint potential.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to an electrostatic protection circuit and a semiconductor integrated circuit. [Background technology]

[0002] Conventionally, an output circuit that modulates an output signal according to an input voltage signal has been used as a circuit built into an optical transmission module or the like. In such an output circuit, electrostatic discharge (ESD) can be a problem. The output circuit described in Patent Document 1 below is an open-drain type output circuit, and includes a signal output terminal, a floating line, a diode that passes a current from the signal output terminal to the floating line, and an ESD protection circuit that connects the floating line to a ground potential when an ESD current flows into the floating line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-173214 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the above-mentioned conventional output circuit, an ESD protection circuit is connected to the floating line, so there is a limit to the operating speed when connecting the floating line to the ground potential when ESD occurs, and the internal circuitry may not be sufficiently protected.

[0005] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide an electrostatic protection circuit that can adequately protect an internal circuit against the occurrence of ESD, and a semiconductor integrated circuit including the same. [Means for solving the problem]

[0006] In order to solve the above problems, an electrostatic protection circuit according to one aspect of the present disclosure includes a pair of output terminals, a pair of diode circuits connecting each of the pair of output terminals to a common node, a potential generating circuit connected to the pair of output terminals and generating an intermediate potential between the pair of output terminals at the common node, and a clamp circuit connecting the common node to a ground wiring in response to the intermediate potential. Effect of the Invention

[0007] According to the present disclosure, the internal circuitry can be adequately protected against the occurrence of ESD. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing a schematic configuration of a drive circuit 200 according to an embodiment. [Diagram 2] FIG. 2 is a circuit diagram showing a configuration of the output circuit 100 in FIG. [Diagram 3] FIG. 3 is a circuit diagram showing a state in which the output circuit 100 of FIG. 1 is connected to an external load. [Figure 4] FIG. 4 is a block diagram showing a configuration of an optical transmission module 400 according to the embodiment. [Diagram 5] FIG. 5 is a block diagram showing a configuration of an optical transceiver module 500 according to the embodiment. [Figure 6] FIG. 6 is a circuit diagram showing a configuration of an output circuit 100 according to a modified example. [Figure 7] FIG. 7 is a circuit diagram showing a configuration of an output circuit 100 according to a modified example. [Figure 8] FIG. 8 is a circuit diagram showing a configuration of an output circuit 100 according to a modified example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] An electrostatic protection circuit according to one aspect of the present disclosure includes a pair of output terminals, a pair of diode circuits connecting each of the pair of output terminals to a common node, a potential generating circuit connected to the pair of output terminals and generating an intermediate potential between the pair of output terminals at the common node, and a clamp circuit connecting the common node to a ground wiring in response to the intermediate potential.

[0010] According to the above aspect, when a positive ESD voltage occurs at a pair of output terminals, the clamp circuit operates to cause a discharge current to flow from the pair of diode circuits toward the ground wiring via the common node, thereby preventing dielectric breakdown of the internal circuit and providing ESD protection.

[0011] In the above aspect, the potential generating circuit preferably includes a first voltage dividing resistor connected between one of the pair of output terminals and the common node, and a second voltage dividing resistor connected between the other of the pair of output terminals and the common node. In this case, a potential can be generated at the common node with a simple circuit configuration, thereby improving the reliability of ESD protection.

[0012] In the above aspect, it is also preferable that the clamp circuit includes a detection circuit that generates a trigger signal when the intermediate potential exceeds a predetermined value, and a switching circuit that connects the common node to a ground line in response to the trigger signal. In this case, the common node is connected to the ground line in response to a change in the potential of the common node, thereby more reliably achieving ESD protection.

[0013] In the above aspect, it is also preferable that the detection circuit includes a detection resistor connected between the common node and the detection node, and a capacitor connected between the detection node and a ground wiring, and the detection circuit generates a trigger signal when a potential difference between the common node and the detection node becomes larger than a predetermined value. With this configuration, it is possible to detect a change in the potential of the common node and generate a trigger signal, thereby improving the reliability of ESD protection.

[0014] Furthermore, in the above aspect, it is also preferable that the detection circuit includes an inversion circuit that inverts the potential of the detection node to generate the trigger signal. In this case, the trigger signal can be generated by detecting a change in the potential of the common node, thereby improving the reliability of ESD protection.

[0015] Furthermore, in the above aspect, it is also preferable that the detection circuit generates a trigger signal for a predetermined delay time when the intermediate potential rises. With this configuration, it is possible to detect a change in the potential of the common node and generate a trigger signal for a predetermined time, thereby improving the reliability of ESD protection.

[0016] In the above aspect, it is also preferable that the switching circuit includes a switching element that switches between a conductive state between the common node and the ground wiring and a non-conductive state between the common node and the ground wiring in response to a trigger signal. In this way, the connection between the common node and the ground wiring can be switched in response to the trigger signal, thereby achieving stable ESD protection.

[0017] Furthermore, in the above aspect, it is also preferable that the pair of diode circuits each include a first diode and a second diode, the cathode of the first diode and the cathode of the second diode are connected to a common node, the anode of the first diode is connected to one of the pair of output terminals, and the anode of the second diode is connected to the other of the pair of output terminals. In this case, when a positive ESD voltage occurs at the pair of output terminals, a current can be caused to flow toward the common node via the pair of diode circuits, thereby realizing stable ESD protection.

[0018] According to another aspect of the present disclosure, a semiconductor integrated circuit includes the electrostatic protection circuit described above and a differential amplifier circuit electrically connected to a pair of output terminals. According to this aspect, it is possible to prevent dielectric breakdown of an internal circuit of the differential amplifier circuit and achieve ESD protection.

[0019] In the above-mentioned other aspect, it is preferable that the differential amplifier circuit generates differential output signals in response to differential input signals and outputs the differential output signals to a pair of output terminals, in which case ESD protection can be achieved when an ESD voltage occurs at the pair of output terminals.

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the description of the drawings, the same elements are given the same reference numerals, and duplicated description will be omitted.

[0021] 1 is a block diagram showing a configuration of a driving circuit 200 according to an embodiment. The driving circuit 200 is built into an optical communication device such as an optical transmission module, and is, for example, a semiconductor integrated circuit (IC) with a size of 2 mm×4 mm manufactured by a SiGe BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process, and amplifies and outputs an input voltage signal. The driving circuit 200 has a pair of input terminals 130a, 130b, a pair of output terminals 131a, 131b, an input circuit 110, and an output circuit 100.

[0022] The input terminals 130a and 130b receive an input of a differential signal consisting of two signals having the same amplitude and inverted phases. The input circuit 110 amplifies the input differential signal and sends it to the output circuit 100. The output circuit 100 further amplifies the differential signal sent from the input circuit 110 and outputs it to the outside of the drive circuit 200.

[0023] The circuit configuration of the drive circuit 200 may be changed as appropriate, the input circuit 110 may be omitted, or various other circuits may be added. In addition, the signal transmission path (channel) is not limited to one, and a configuration in which multiple channels (for example, four channels) are arranged in parallel may be used.

[0024] Next, the configuration of the output circuit 100, which is a semiconductor integrated circuit according to this embodiment, will be described with reference to FIGS.

[0025] Fig. 2 is a circuit diagram showing the configuration of the output circuit 100 of Fig. 1. The output circuit 100 is a differential amplifier circuit that modulates an output current based on a differential signal that is an input voltage signal, and is an integrated circuit formed on a Si substrate using a SiGe BiCMOS process. The maximum power supply voltage of the integrated circuit on which the output circuit 100 is mounted is, for example, 3.3V, and the input differential signal and the output signal are, for example, 32QAM signals modulated by quadrature amplitude modulation (QAM) with 32 signal points, and the modulation speed of these signals is 100GBaud. The output circuit 100 includes bipolar transistors 10a, 10b, 11a, 11b, and 12, resistor elements 20a, 20b, 21a, 21b, and 22, diodes (diode circuits) 30a, 30b, 35a, and 35b, a capacitor 40, MOS (Metal Oxide Semiconductor) transistors 50, 55, and 56, signal input terminals 91a and 91b, signal output terminals 92a and 92b, ground terminals 80a, 80b, 80c, and 80d, and bias supply terminals 93 and 94. Of these components, the resistor element 22, the capacitor 40, and the MOS transistors 50, 55, and 56 form a clamp circuit 60. The clamp circuit 60, the diodes 30a, 30b, 35a, and 35b, the resistor elements 21a and 21b, and the ground terminals 80b, 80c, and 80d form an ESD protection circuit (electrostatic protection circuit) 65. The bipolar transistors 10a, 10b, 11a, 11b, and 12, the resistive elements 20a and 20b, the signal input terminals 91a and 91b, the bias supply terminals 93 and 94, and the ground terminal 80a constitute an internal circuit 67, which is a differential amplifier circuit electrically connected to a pair of signal output terminals 92a and 92b.

[0026] First, the components that make up the internal circuit 67 will be described.

[0027] In the bipolar transistors 10a and 10b, the bases are connected to a pair of signal input terminals 91a and 91b, the collectors are connected to the emitters of the bipolar transistors 11a and 11b, and the emitters are connected to one end of the resistance elements 20a and 20b. The bipolar transistors 10a and 10b may be, for example, NPN-type heterojunction bipolar transistors (HBTs). The bipolar transistors 10a and 10b may be, for example, n-type MOS transistors.

[0028] In the bipolar transistors 11a and 11b, the bases of the bipolar transistors 11a and 11b are connected to the bias supply terminal 94, the emitters of the bipolar transistors 10a and 10b are connected to the collectors of the bipolar transistors 10a and 10b, and the collectors of the bipolar transistors 11a and 11b are connected to a pair of signal output terminals 92a and 92b. These bipolar transistors 11a and 11b are cascode transistors whose bases are applied with a DC voltage supplied to the bias supply terminal 94. With this configuration, the voltage amplitude at the collectors of the bipolar transistors 10a and 10b is suppressed, and the mirror capacitance of the bipolar transistors 10a and 10b is reduced, so that the bandwidth of the output circuit 100 can be increased. In addition, the presence of the bipolar transistors 11a and 11b increases the output resistance of the output circuit 100, so that the voltage gain of the output circuit 100 can be improved. The bipolar transistors 11a and 11b may be replaced with, for example, n-type MOS transistors. In addition, if the bandwidth of the output circuit 100 is sufficiently wide, the bipolar transistors 11a and 11b may be omitted.

[0029] The resistor elements 20a and 20b have one end connected to the emitters of the bipolar transistors 10a and 10b, respectively, and the other end connected to the collector of the bipolar transistor 12. These resistor elements 20a and 20b are degeneration resistors, and enable the linear input range of the output circuit 100 to be expanded. The resistor elements 20a and 20b are, for example, n-type polysilicon resistors. Note that, when the linear input range of the output circuit 100 is sufficiently wider than the range of use, the resistor elements 20a and 20b may be omitted.

[0030] The bipolar transistor 12 functions as a current source, with its collector connected to the other end of the resistance elements 20a and 20b, its base connected to the bias supply terminal 93, and its emitter connected to the ground terminal 80a. The bipolar transistor 12 generates a current according to the voltage of the bias supply terminal 93, and the current value is, for example, 60 mA. The bias supply terminal 93 may be configured to apply the base voltage of another diode-connected bipolar transistor. In this case, a current mirror is configured, making it easy to adjust the amount of current generated by the bipolar transistor 12. A MOS transistor may be used instead of the bipolar transistor 12. The bipolar transistor 12 may be replaced by a resistance element or a circuit including a resistance element and an inductor.

[0031] The output circuit 100 including the internal circuit 67 of the above configuration includes a pair of bipolar transistors 10a, 10b whose bases are connected to the pair of signal input terminals 91a, 91b, respectively, and which are connected in parallel between the ground potential and the pair of signal output terminals 92a, 92b, and functions as a differential amplifier circuit that amplifies the differential signal input from the pair of signal input terminals 91a, 91b and outputs the amplified differential signal to the pair of signal output terminals 92a, 92b. Here, the output circuit 100 is called an open collector circuit because the collectors of the bipolar transistors 11a, 11b are connected to the signal output terminals 92a, 92b without being terminated, that is, without being connected to an internal power supply via a resistor inside (for example, inside an IC in which the output circuit 100 is mounted) or without being grounded. Note that, in the case of a configuration in which the bipolar transistors 10a, 10b, 11a, 11b are replaced with MOS transistors, the output circuit 100 is called an open drain circuit.

[0032] 3 shows a configuration in which the output circuit 100 is connected to an external load. As shown in FIG. 3, the output circuit 100 mounted on the IC 101 has signal output terminals 92a and 92b connected to an external load 102 to which a predetermined voltage (for example, 5.0 V) is applied by an external power supply 106. That is, the pair of signal output terminals 92a and 92b are connected to connection terminals 103a and 103b of the external load 102 via electric wiring 105a and 105b, respectively. The external load 102 has load resistors 104a and 104b with a predetermined resistance value (for example, 30Ω) between the two connection terminals 103a and 103b and the connection terminal 103c, respectively, and the connection terminal 103c is connected to the external power supply 106 via the electric wiring 105c. As a result, the signal output terminal 92a is terminated at the external power supply 106 via the load resistor 104a, and the signal output terminal 92b is terminated at the external power supply 106 via the load resistor 104b. With such a connection configuration, the voltage value of the differential signal at the signal output terminals 92a, 92b is determined mainly by the voltage of the external power supply 106, the resistance values ​​of the load resistors 104a, 104b, and the output current of the output circuit 100.

[0033] Next, the components of the ESD protection circuit 65 will be described.

[0034] The resistive elements (first and second voltage dividing resistors) 21a and 21b constitute a potential generating circuit 21 that generates an intermediate potential between a pair of output terminals, i.e., the signal output terminals 92a and 92b. That is, the resistive elements 21a and 21b are resistive elements having approximately the same resistance value that are connected in series between the pair of signal output terminals 92a and 92b and a connection point (second node) X2. The resistive elements 21a and 21b constitute the potential generating circuit 21 that outputs the second node X2. When ESD is not occurring (when the internal circuit 67 is in a balanced state (unmodulated state) or performing a modulation operation), the potential generating circuit 21 generates an output common-mode voltage that is an intermediate potential between the pair of output terminals, i.e., the signal output terminals 92a and 92b, at the second node X2. Further, when ESD occurs, the potential generating circuit 21 generates a potential at the second node X2 that is approximately equal to the intermediate potential of the signal output terminals 92a, 92b until the diodes 30a, 30b described later are turned on. After the diodes 30a, 30b are turned on, the potential at the second node X2 is no longer the intermediate potential of the signal output terminals 92a, 92b. The resistance values ​​of the resistive elements 21a, 21b are preferably at least 10 times, more preferably 100 times, the resistance values ​​of the load resistors 104a, 104b of the external load 102. In the former case, the combined load resistance is about 90% of the resistance value of the load resistors 104a, 104b, and in the latter case, the combined load resistance is about 99% of the resistance value of the load resistors 104a, 104b, so that the influence on the signal voltage output during the modulation operation is suppressed. In this embodiment, for example, the resistance values ​​of the resistive elements 21a, 21b are set to 5 kΩ. The output common mode voltage generated by the resistor elements 21a and 21b is, for example, 4.0V.

[0035] The pair of diodes 30a, 30b are ESD protection diodes that connect the pair of signal output terminals 92a, 92b to a connection point (first node) X1, respectively, and have their anodes connected to the signal output terminals 92a, 92b and their cathodes connected to the common connection point (first node) X1. These diodes 30a, 30b are, for example, PN junction diodes formed in a P-type well. The diodes 30a, 30b serve as a discharge path when a positive ESD voltage occurs at the signal output terminals 92a, 92b. In this embodiment, the second node X2 and the first node X1 are electrically connected to each other, and approximately the same potential is generated.

[0036] The pair of diodes 35a, 35b are ESD protection diodes, with their cathodes connected to the signal output terminals 92a, 92b and their anodes connected to the ground terminals 80c, 80d. These diodes 35a, 35b are, for example, PN junction diodes formed in an N-type well. The diodes 35a, 35b serve as a discharge path when a negative ESD voltage occurs at the signal output terminals 92a, 92b.

[0037] The clamp circuit 60 has a function of grounding the first node X1 by setting a low resistance between the first node X1 and the ground terminal 80b when a positive ESD voltage occurs at the first node X1 as a trigger. Here, the clamp circuit 60 is a circuit for preventing dielectric breakdown of the internal circuit 67 in the output circuit 100 by suppressing an increase in the ESD potential at the signal output terminals 92a and 92b. A commonly used clamp circuit is often used by connecting it between an internal power supply and the ground. On the other hand, the output circuit 100 of this embodiment is an open collector circuit, and is terminated by an external power supply having a power supply voltage of, for example, 5.0 V. In addition, the internal power supply voltage of the output circuit is, for example, 3.3 V, which is smaller than the output common mode voltage (for example, 4.0 V). As a result, it is difficult to adopt a configuration in which the clamp circuit 60 is biased by the internal power supply, because the diodes 30a and 30b are turned on and a large current flows from the signal output terminals 92a and 92b to the internal power supply. It is possible to avoid turning on the diodes by using a configuration in which diodes are connected in series in multiple stages, but in this case, the voltage at the signal output terminals 92a and 92b increases when ESD occurs, and ESD protection may become insufficient. Therefore, in this embodiment, a configuration is used in which a clamp circuit 60 is connected between the first node X1, where the output common-mode voltage is generated, and the ground terminal 80b. Note that the clamp circuit 60 is configured with internal element selection and circuit design so that it can be used with the voltage of the first node X1.

[0038] The clamp circuit 60 includes a detection circuit 70 and a switching circuit 71. The detection circuit 70 detects the ESD voltage based on the intermediate potential. The detection circuit 70 includes a resistive element 22, a capacitor 40, and MOS transistors 50 and 55.

[0039] The resistive element 22 and the capacitor 40 form a low-pass filter. That is, the resistive element (detection resistor) 22 is connected between a first node X1 and a node (detection node) Y. The capacitor 40 is connected between the detection node Y and a ground terminal 80b. With this configuration, when a step-like voltage pulse occurs at the first node X1, a voltage approximately equal to that at the first node X1 occurs at the node Y between the resistive element 22 and the capacitor 40 after a delay time of about a time constant determined by the product of the resistance value of the resistive element 22 and the capacitance of the capacitor 40.

[0040] The MOS transistors 50 and 55 constitute an inverter circuit (inverting circuit). The MOS transistor 50 is a P-type MOS transistor, and its source is connected to the first node X1, its drain is connected to the node Z, and its gate is connected to the node Y. The MOS transistor 55 is an N-type MOS transistor, and its source is connected to the ground terminal 80b, its drain is connected to the drain of the MOS transistor 50 via the node Z, and its gate is connected to the node Y. In this inverter circuit, when a voltage is generated at the first node X1 and the voltage difference between the first node X1 and the node Y is larger than the threshold voltage of the inverter circuit, the MOS transistor 50 is turned on, and the output of the inverter circuit at the node Z becomes a voltage approximately equal to that of the first node X1. On the other hand, when the voltage difference between the first node X1 and the node Y is smaller than the threshold voltage, the MOS transistor 55 is turned on, and the output of the inverter circuit becomes a voltage approximately equal to that of the ground terminal 80b. In this way, the inverter circuit constituted by the MOS transistors 50 and 55 inverts the potential of the node Y to generate a trigger signal. Here, in this embodiment, the inverter circuit has a single stage configuration, but may be changed to a configuration of an odd number of stages, which may be three or more stages.

[0041] The detection circuit 70 detects a change in the intermediate potential, i.e., in response to the intermediate potential, and outputs a trigger signal to the node Z in response to the potential difference between the first node X1 and the node Y. The detection circuit 70 also generates the trigger signal during a delay time of approximately a time constant determined by the product of the resistance value of the resistive element 22 and the capacitance of the capacitor 40, i.e., a predetermined delay time. Furthermore, the detection circuit 70 generates the trigger signal when the potential difference of the node Y with respect to the first node X1 becomes larger than the threshold value of the inverter circuit, i.e., a predetermined value.

[0042] The MOS transistor 56 is a switching element formed of an N-type MOS transistor, and has a drain connected to the first node X1, a source connected to the ground terminal 80b, and a gate connected to a node Z which is an output node of the inverter circuit. The MOS transistor 56 constitutes a switching circuit 71 which turns on / off according to the output of the inverter circuit using the output as a trigger signal, and turns on when the gate-source voltage is higher than the threshold voltage of the MOS transistor 56, so as to lower the drain-source resistance. On the other hand, the MOS transistor 56 turns off when the gate-source voltage is lower than the threshold voltage of the MOS transistor 56, so as to increase the drain-source resistance. With this configuration, the MOS transistor 56 uses the potential of the node Z as a trigger to switch according to the potential of the first node X1, and when the potential of the first node X1 rises, switches to a state in which the first node X1 and the ground wiring are connected with low resistance (conductive state). On the other hand, when the potential of the first node X1 is not rising, the MOS transistor 56 switches the first node X1 to a state where the first node X1 and the ground wiring are connected with high resistance (non-conductive state). Note that the timing at which the MOS transistor 56 turns on and the potential at the first node X1 required to turn on the MOS transistor 56 can be appropriately adjusted by designing the detection circuit, the inverter circuit, and the switching circuit.

[0043] The ESD protection operation in the output circuit 100 configured as above will be described. Note that ESD may occur in either one or both of the signal output terminals 92a and 92b. For example, in FIG. 3, when the electric wiring 105a is connected to the signal output terminal 92a, ESD may occur in the signal output terminal 92a. Similarly, when the electric wiring 105b is connected to the signal output terminal 92b, ESD may occur in the signal output terminal 92b. Furthermore, when the electric wiring 105c is connected to the connection terminal 103c with the electric wiring 105a and 105b connected, ESD may occur in both the signal output terminals 92a and 92b. In either case, the ESD protection operation is the same, so hereinafter, no distinction will be made between them.

[0044] First, when a negative ESD voltage occurs at the signal output terminals 92a and 92b, a current flows from the ground terminals 80c and 80d to the signal output terminals 92a and 92b via the diodes 35a and 35b. This makes it possible to suppress an increase in the negative ESD voltage at the signal output terminals 92a and 92b and prevent dielectric breakdown of the output circuit 100.

[0045] Next, when a positive ESD voltage occurs at the signal output terminals 92a, 92b, a current flows from the signal output terminals 92a, 92b to the first node X1 through the diodes 30a, 30b and the resistor elements 21a, 21b, and the voltage at the first node X1 rises. The detection circuit of the clamp circuit 60 causes the voltage rise at the node Y to be delayed compared to the first node X1. This causes the MOS transistor 50 of the inverter circuit of the clamp circuit 60 to turn on, and the voltage at the node Z rises. As a result, the MOS transistor 56 turns on, suppressing the voltage rise at the first node X1 and suppressing the voltage rise at the signal output terminals 92a, 92b. In this way, it is possible to prevent dielectric breakdown of the output circuit 100.

[0046] In the output circuit 100 of this embodiment, as described above, a current flows from the signal output terminals 92a, 92b to the first node X1 via the diodes 30a, 30b and the resistive elements 21a, 21b. Therefore, the voltage rise of the first node X1 becomes faster and the MOS transistor 56 turns on at an earlier timing than when there are no resistive elements 21a, 21b, such as in the output circuit described in the conventional document (JP Patent Publication 2015-173214). As a result, the voltage rise of the first node X1 is further suppressed, and the reliability of the output circuit 100 can be improved.

[0047] In addition, when the output circuit 100 is in a normal operating state (as shown in FIG. 3), the voltages of the first node X1 and the node Y are the same, and the MOS transistor 56 is off. Therefore, the clamp circuit 60 does not cause any problems in using the output circuit 100. Here, even when the output circuit 100 is in a normal operating state, the voltage of the first node X1 may fluctuate due to, for example, the modulation operation of the output circuit 100 or voltage fluctuations of the external power supply 106. For this reason, it is desirable to appropriately design the threshold voltage, etc. of the clamp circuit 60 so that such voltage fluctuations do not erroneously turn on the MOS transistor 56.

[0048] In the output circuit 100 of this embodiment, the power supply voltage side (first node X1) of the clamp circuit 60 is biased by the output common mode voltage generated by the resistive elements 21a and 21b. As a result, when the output circuit 100 is in a balanced state (unmodulated state), the anode-cathode voltage of the diodes 30a and 30b is 0V. Therefore, if the voltage change of the signal output terminals 92a and 92b is smaller than the rising voltage of the diodes 30a and 30b (for example, 0.6V), the diodes 30a and 30b do not turn on and remain high resistance. When the voltage change of the signal output terminals 92a and 92b is ±0.6V, the maximum amplitude of the output signal is 1.2V in single end and 2.4V in differential. Even if the diodes 30a and 30b do not turn on, if the forward voltage of the diodes 30a and 30b increases, the depletion layer shrinks and the parasitic capacitance increases. As a result, the operating band of the output circuit 100 decreases as the forward voltage increases, so it is desirable to set the forward voltages of the diodes 30a and 30b to be small.

[0049] On the other hand, for example, as in the output circuit described in the above-mentioned conventional document, if the power supply voltage side of the clamp circuit 60 (the node corresponding to the first node X1) is not biased and is made floating, the diodes 30a and 30b may be turned on by the modulation operation of the output circuit 100, causing a problem of distorting the output signal waveform. This may cause a problem of deteriorating the linearity of the output signal. In addition, since the forward voltages of the diodes 30a and 30b are large and the parasitic capacitance is large, a problem of reducing the operating band of the output circuit 100 may occur.

[0050] Specifically, in the case where the first node X1 is floating, the voltage of the first node X1 is lower than that of the signal output terminals 92a, 92b by the rise voltage of the diodes 30a, 30b in the output circuit 100 in a balanced state due to a leakage current from the first node X1 to the ground terminal 80b. As a result, the voltage of the first node X1 becomes a voltage (e.g., 3.4V) that is lower by a rise voltage (e.g., 0.6V) from the output common mode voltage (e.g., 4.0V). At this point, the anode-cathode forward voltages of the diodes 30a, 30b are large (e.g., 0.6V), so that the parasitic capacitance increases and the operating band of the output circuit 100 may be reduced.

[0051] In the case of a floating configuration, when the voltage of the signal output terminal 92a or 92b rises due to the modulation operation of the output circuit 100, the forward voltage of the diode 30a or 30b becomes large (for example, 0.6V or more), and the diode 30a or 30b turns on. This causes a current (charging current) to flow from the signal output terminal 92a or 92b to the first node X1, which may cause a problem such as distortion of the output signal waveform. The charging current stops when the voltage of the first node X1 rises and the forward voltage of the diodes 30a and 30b becomes equal to or lower than the rising voltage. For this reason, this problem is particularly likely to occur immediately after the output circuit 100 goes from an equilibrium state to a modulation operation. However, since the voltage of the first node X1 gradually drops due to the leakage current, the charging current may continue to be generated at a constant amount and frequency until the forward voltage of the diodes 30a and 30b becomes equal to or lower than the rising voltage again.

[0052] The above-mentioned problem with the charging current in the case of the floating configuration may become more serious when the input / output signal of the output circuit 100 is an analog signal (e.g., a sine wave) rather than a digital signal (e.g., a square wave). For example, when the input / output signal is a square wave, the input / output signal is a differential signal, so that one of the signal output terminals 92a, 92b is high (maximum voltage) except for the transition between high and low, and the first node X1 is charged quickly via the diode 30a or the diode 30b. On the other hand, when the input signal is a sine wave, the input / output signal is almost always in a transition state and lower than the maximum voltage, so that the first node X1 is charged slowly via the diode 30a or the diode 30b. As a result, problems such as distortion of the output signal waveform may occur frequently over a long period of time with analog signals compared to digital signals.

[0053] Similarly, the above-mentioned problems associated with the charging current in the case of the floating configuration may become more serious when the input / output signals of the output circuit 100 are multi-level amplitude modulated signals (e.g., 4-PAM (Pulse Amplitude Modulation) signals) rather than constant amplitude modulated signals (e.g., NRZ (Non Return to Zero) signals). This is because the input / output signals are less frequently at maximum in the multi-level amplitude modulated signals compared to the constant amplitude modulated signals. As a result, the charging of the first node X1 via the diode 30a or diode 30b becomes slower, and problems such as distortion of the output signal waveform may occur more frequently over a long period of time in the multi-level amplitude modulated signals compared to the constant amplitude modulated signals.

[0054] In this embodiment, for example, a QAM signal is used as the input / output signal. That is, since the input / output signal is a multi-level analog modulated signal, the problem associated with the charging current in the case of the floating configuration may become more serious. However, in this embodiment, the first node X1 is electrically connected to the second node X2, and the first node X1 is biased by the output common mode voltage by the resistive elements 21a and 21b, so that such a problem is unlikely to occur. Note that, when the voltage change at the signal output terminals 92a and 92b due to the output signal is larger than the rise voltage of the diodes 30a and 30b, it is possible to avoid the diodes from turning on by adopting a configuration in which the number of diode stages is increased, for example, by adopting a configuration in which the diodes 30a and 30b include two stages of diodes.

[0055] In this way, according to the configuration of the output circuit 100, the discharge path when ESD occurs is composed of the ESD protection diode and the resistance element, so that the ESD protection of the output circuit 100 is more reliable and the reliability can be improved. In addition, by biasing the clamp circuit 60 with the output common mode voltage, it is possible to prevent the parasitic capacitance of the ESD protection diode from increasing and being turned on, and high-quality high-speed signal modulation is possible. As a result, it is possible to realize a highly reliable output circuit 100 capable of high-quality high-speed modulation operation.

[0056] FIG. 4 shows the configuration of an optical transmission module 400 according to this embodiment. The optical transmission module 400 includes the above-mentioned drive circuit 200 and optical modulation device 300. The drive circuit 200 amplifies and outputs, for example, four input differential signals, and the optical modulation device 300 generates an optical signal modulated based on the four differential signals output from the drive circuit 200, and outputs, for example, one optical signal modulated by polarization multiplexing QAM. The optical transmission module 400 is, for example, an optical module in which the drive circuit 200 and the optical modulation device 300 are integrated and mounted in a ceramic package, and has an external size of, for example, 30 mm×15 mm×5 mm. According to the optical transmission module 400 configured as above, the drive circuit 200 equipped with the output circuit 100 is used, so that a highly reliable optical transmission module capable of high-quality high-speed modulation is realized.

[0057] 5 shows the configuration of an optical transmitting / receiving module 500 according to this embodiment. The optical transmitting / receiving module 500 includes a receiving circuit 600 and an optical receiving device 700 in addition to the driving circuit 200 and the optical modulation device 300 described above. The optical receiving device 700 receives an optical signal input from the outside via an optical transmission line, and separates and outputs four signals (receiving currents) from, for example, a polarization multiplexed QAM modulated optical signal. The receiving circuit 600 converts the four receiving currents into voltages, amplifies them, and outputs them. According to the optical transmitting / receiving module 500 having the above configuration, since the driving circuit 200 equipped with the output circuit 100 is used, a highly reliable optical transmitting / receiving module capable of high-quality high-speed modulation is realized.

[0058] According to the ESD protection circuit 65 of the present embodiment described above, when a positive ESD voltage occurs at the pair of signal output terminals 92 a, 92 b, the clamp circuit 60 operates to cause a discharge current to flow from the pair of diodes 30 a, 30 b to the ground terminal 80 b via the first node X1, thereby preventing dielectric breakdown of the internal circuit 67 and achieving ESD protection.

[0059] Moreover, the first node X1 and the second node X2, which is the output of the potential generating circuit 21, are electrically connected to each other. With this configuration, when a positive ESD voltage occurs at the pair of signal output terminals 92a, 92b, the potential of the first node X1 can be quickly increased, improving the reliability of ESD protection. In addition, during modulation operation, it is possible to prevent a decrease in the operating band of the output circuit 100 due to an increase in the parasitic capacitance of the diodes 30a, 30b, and also to reduce distortion of the output signal waveform.

[0060] Moreover, the potential generating circuit 21 of the ESD protection circuit 65 includes a resistive element 21a connected between the signal output terminal 92a and the second node X2, and a resistive element 21b connected between the signal output terminal 92b and the second node X2. With such a simple circuit configuration, a potential can be generated at the second node X2, thereby improving the reliability of ESD protection.

[0061] Furthermore, the clamp circuit 60 includes a detection circuit 70 that generates a trigger signal when the intermediate potential exceeds a predetermined value, and a switching circuit 71 that connects the first node X1 to a ground wiring in response to the trigger signal. In this case, the first node X1 is connected to the ground wiring in response to a change in the potential of the first node X1, so that ESD protection can be achieved more reliably.

[0062] The detection circuit 70 also includes a resistive element 22 connected between the first node X1 and a node Y, and a capacitor 40 connected between the node Y and a ground wiring, and generates a trigger signal when the potential difference between the first node X1 and the node Y becomes greater than a predetermined value. With this configuration, the detection circuit 70 can detect a change in the potential of the first node X1 and generate a trigger signal, thereby improving the reliability of ESD protection.

[0063] Furthermore, the detection circuit 70 generates a trigger signal for a predetermined delay time when the intermediate potential rises. With this configuration, it is possible to detect a change in the potential of the first node X1 and generate a trigger signal for a predetermined time, thereby improving the reliability of ESD protection.

[0064] The detection circuit 70 also includes an inverter that generates a trigger signal by inverting the potential of the node Y. In this case, the trigger signal can be generated by detecting a change in the potential of the first node X1, thereby improving the reliability of ESD protection.

[0065] The switching circuit 71 also includes a switching element that switches between a state in which the first node X1 is conductive with the ground wiring and a state in which the first node X1 is non-conductive with the ground wiring in response to a trigger signal. With this configuration of the switching circuit 71, the first node X1 is connected to the ground wiring in response to a change in the potential of the first node X1, thereby making it possible to more reliably achieve ESD protection.

[0066] The ESD protection circuit 65 also includes diodes 30a and 30b, the cathode of the diode 30a and the cathode of the diode 30b are connected to the first node X1, the anode of the diode 30a is connected to the signal output terminal 92a, and the anode of the diode 30b is connected to the signal output terminal 92b. In this case, when a positive ESD voltage occurs at the pair of signal output terminals 92a and 92b, a current can be caused to flow toward the first node X1 via the pair of diodes 30a and 30b, and stable ESD protection can be realized.

[0067] Additionally, in the output circuit 100 including the ESD protection circuit 65 and the internal circuit 67 of this embodiment, the ESD protection circuit 65 provides stable ESD protection, and the internal circuit 67 can be adequately protected.

[0068] Moreover, it is preferable that the internal circuit 67 generates a differential output signal in response to the differential input signal and outputs the differential output signal to the pair of signal output terminals 92a, 92b. In this case, ESD protection can be achieved when an ESD voltage occurs at the pair of signal output terminals 92a, 92b.

[0069] Although the principles of the present disclosure have been illustrated and described in the above preferred embodiments, it will be recognized by those skilled in the art that the present disclosure may be modified in arrangement and detail without departing from such principles. The present disclosure is not limited to the specific configurations disclosed in the present embodiments. Accordingly, we claim all modifications and changes that come within the scope and spirit of the following claims.

[0070] The configuration of the clamp circuit 60 in the ESD protection circuit 65 may be changed as appropriate. For example, the detection circuit configured as a low-pass filter may be changed to a high-pass filter in which the connection positions of the resistor element and the capacitor are interchanged, or to a capacitive voltage divider circuit in which a capacitor is connected in series. In this case, the output voltage of the detection circuit changes almost simultaneously with the first node X1, and returns to zero after a certain period of time has passed. Therefore, in the clamp circuit 60, the inverter circuit is omitted, or the inverter circuit is configured with an even number of stages, two or more.

[0071] Furthermore, although the output circuit 100 of the present embodiment is configured as an open collector circuit, a resistive element may be inserted between the signal output terminals 92a, 92b and the internal power supply or the ground terminal if the operation of the output circuit 100 is not affected. For example, a resistor (e.g., 300Ω) that is 10 times or more larger than the load resistors 104a, 104b of the external load 102 can be inserted between the signal output terminal 92a and the internal power supply (e.g., 3.3V) and between the signal output terminal 92b and the internal power supply. In this case, the combined load resistance is about 90% of the load resistors 104a, 104b. Such a circuit can also be considered as a substantially open collector circuit.

[0072] 6, a resistive element 23 may be inserted between the first node X1 and the ground terminal 80b. In this configuration, the resistive element 23 and the resistive elements 21a and 21b function as pull-down resistors to prevent the signal output terminals 92a and 92b from being charged. This makes it possible to prevent a malfunction that may occur when the electric charge stored in the signal output terminals 92a and 92b is discharged to the outside, thereby improving the reliability of the output circuit 100.

[0073] 7 shows the configuration of another modified example of the output circuit 100. This modified example differs from the above embodiment in that a resistive element 25 and an ESD protection circuit 66 for the bipolar transistors 11a and 11b are added.

[0074] 7, the ESD protection circuit 66 includes diodes 31 and 36, a clamp circuit 61, ground terminals 80e and 80f, and a power supply terminal 81. The diode 31 is connected between the bias supply terminal 94 and the power supply terminal 81, the diode 36 is connected between the bias supply terminal 94 and the ground terminal 80e, and the clamp circuit 61 is connected between the power supply terminal 81 and the ground terminal 80f. In addition, the resistive element 25 is connected between the second node X2 and the bias supply terminal 94.

[0075] In the output circuit 100 of the above embodiment, the bases of the bipolar transistors 11a and 11b are separated from the external power supply, so that the base-collector voltage exceeds the maximum rating when ESD occurs, and the bipolar transistors 11a and 11b may break down. On the other hand, in the output circuit 100 of this modification, a resistive element 25 (e.g., a resistor of 1 kΩ) is inserted between the bias supply terminal 94 and the second node X2. As a result, for example, when a positive ESD voltage occurs at the signal output terminals 92a and 92b, the bases of the bipolar transistors 11a and 11b are also charged via the resistive elements 21a, 21b, and 25, so that the rise in the collector-base voltage is suppressed. In addition, when the base-emitter voltage of the bipolar transistors 11a and 11b rises, the collector current flows and the emitter is also charged, so that the rise in the base-emitter voltage is also suppressed. Furthermore, the ESD protection circuit 66 suppresses the rise in the base voltage itself. In this way, it is possible to reduce the risk of failure of the bipolar transistors 11a and 11b.

[0076] Here, a voltage of, for example, 2.5 V is supplied to the bias supply terminal 94, and a voltage of, for example, 3.3 V is supplied to the power supply terminal 81 from the internal power supply. In this case, the reverse bias voltage between the anode and cathode of the diode 31 is, for example, 0.8 V, and the diode 31 does not turn on. Note that a plurality of diodes may be connected in series between the bias supply terminal 94 and the power supply terminal 81.

[0077] In this manner, in this modification, it is possible to reduce the risk of failure of the bipolar transistors 11a and 11b compared to the above embodiment, thereby making it possible to realize a highly reliable output circuit capable of high-quality high-speed modulation.

[0078] 8 shows the configuration of another modified example of the output circuit 100. This modified example differs from the above embodiment in the configuration of a clamp circuit 60A.

[0079] As shown in FIG. 8, the clamp circuit 60A includes bipolar transistors 51 and 52, a resistor element 26, and diodes 37a, 37b, and 37c. The clamp circuit 60A is a so-called diode triggered thyristor (DTSCR: Diode Triggered Silicon Controlled Rectifier). The bipolar transistor 51 is a PNP type bipolar transistor, the emitter is connected to the second node X2, and the collector is connected to the ground terminal 80b via the resistor element 26. The bipolar transistor 52 is an NPN type bipolar transistor, the collector is connected to the base of the bipolar transistor 51, the emitter is connected to the ground terminal 80b, and the base is connected to the collector of the bipolar transistor 51. The diodes 37a, 37b, and 37c are connected in series between the base of the bipolar transistor 51 and the ground terminal 80b.

[0080] In the clamp circuit 60A configured as above, when the voltage of the second node X2 rises, a current flows from the emitter of the bipolar transistor 51 through its base and the diodes 37a, 37b, and 37c. This turns on the thyristor formed by the bipolar transistors 51 and 52, and a current flows from the emitter of the bipolar transistor 51 through its collector, the base of the bipolar transistor 52, and its emitter. As a result, the internal circuit 67 is protected from ESD. When the ESD current flowing from the signal output terminal 92a or 92b flows into the thyristor and then becomes zero, the thyristor automatically recovers to the off state.

[0081] Even with such a modified configuration, a highly reliable output circuit capable of high-quality high-speed modulation can be realized. Note that, instead of the diode-triggered thyristor, a ggNMOS (gate-grounded NMOS) or a Zener diode can be used. [Explanation of symbols]

[0082] 91a, 91b...Signal input terminals 92a, 92b…Signal output terminal 93,94...Bias supply terminals 10a, 10b, 11a, 11b, 12, 51, 52...Bipolar transistors X1…first node X2…Second node Y...node (detection node) Z...node 20a, 20b, 23, 25, 26...resistance elements 21a, 21b...resistance elements (first and second voltage dividing resistors) 30a, 30b...Diodes (diode circuits) 31, 35a, 35b, 36, 37a, 37b, 37c...Diodes 21...Potential generation circuit 60, 60A, 61...Clamp circuit 65...ESD protection circuit (electrostatic protection circuit) 22...Resistance element (detection resistor) 40…Capacitor 56...MOS transistor (switching circuit) 50, 55...MOS transistor (inverter circuit) 66…ESD protection circuit 67...Internal circuit (differential amplifier circuit) 70…Detection circuit 71...Switching circuit 80a, 80b, 80c, 80d, 80e, 80f…ground terminal 81…Power terminal 100...Output circuit 102…External load 103a, 103b, 103c...Connection terminals 104a,104b…Load resistance 105a, 105b, 105c...Electrical wiring 106...External power supply 110...Input circuit 130a, 130b...Input terminals 131a, 131b...Output terminals 200...Drive circuit 300...Optical modulation device 400...Optical transmitter module 500...Optical transceiver module 600…Receiver circuit 700…Light receiving device

Claims

1. A pair of output terminals whose voltage is determined by being connected to an external power supply via a pair of external load resistors; a pair of diode circuits each connecting the pair of output terminals to a common node; a potential generating circuit connected to the pair of output terminals and configured to generate an intermediate potential between the pair of output terminals at the common node; a clamp circuit that connects the common node to a ground line in response to the intermediate potential. Electrostatic protection circuit.

2. The potential generating circuit includes: a first voltage dividing resistor connected between one of the pair of output terminals and the common node; a second voltage dividing resistor connected between the other of the pair of output terminals and the common node; Equipped with 2. The electrostatic protection circuit of claim 1.

3. The clamp circuit includes: a detection circuit for generating a trigger signal when the intermediate potential exceeds a predetermined value; a switching circuit that connects the common node to the ground wiring in response to the trigger signal.

3. The electrostatic protection circuit according to claim 1.

4. The detection circuit includes: a detection resistor connected between the common node and a detection node; a capacitor connected between the detection node and the ground wiring, the detection circuit generates the trigger signal when a potential difference between the common node and the detection node becomes greater than a predetermined value.

4. The electrostatic protection circuit according to claim 3.

5. the detection circuit includes an inversion circuit that inverts a potential of the detection node to generate the trigger signal; 5. The electrostatic protection circuit according to claim 4.

6. the detection circuit generates the trigger signal for a predetermined delay time when the intermediate potential rises; The electrostatic protection circuit according to any one of claims 3 to 5.

7. The switching circuit includes: a switching element that switches between a conductive state between the common node and the ground wiring and a non-conductive state between the common node and the ground wiring in response to the trigger signal; The electrostatic protection circuit according to claim 3 .

8. each of the pair of diode circuits includes a first diode and a second diode; a cathode of the first diode and a cathode of the second diode are connected to the common node; an anode of the first diode is connected to one of the pair of output terminals; the anode of the second diode is connected to the other of the pair of output terminals; The electrostatic protection circuit according to claim 1 .

9. The electrostatic protection circuit according to any one of claims 1 to 8, a differential amplifier circuit electrically connected to the pair of output terminals; A semiconductor integrated circuit comprising:

10. the differential amplifier circuit generates a differential output signal in response to a differential input signal, and outputs the differential output signal to the pair of output terminals; 10. The semiconductor integrated circuit according to claim 9.

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