Semiconductor devices, electronic devices, and methods of forming semiconductor devices - Patents.com

Abstract

To provide a semiconductor device in which a nanowire device and a high voltage transistor are integrally formed.SOLUTION: A semiconductor device 100 includes a substrate 101, a first transistor 172A including a vertical stack of a first semiconductor channel on the substrate, and a first gate dielectric 112A surrounding each first semiconductor channel. The first gate dielectric has a first thickness TA. The semiconductor device further includes a second transistor 172B on the substrate. The second transistor includes a second semiconductor channel 115. The second semiconductor channel includes a pair of side walls and a top surface. The second gate dielectric 112B is on the pair of side walls and the top surface of the second semiconductor channel. The second gate dielectric has a second thickness TB that is greater than the first thickness.SELECTED DRAWING: Figure 1A

Description

[Technical field]

[0001] TECHNICAL FIELD Embodiments of the present disclosure relate to semiconductor devices, and more particularly, to semiconductor devices having nanoribbon transistors integrated with high-voltage thick-gate tri-gate transistors. [Background technology]

[0002] As integrated device manufacturers continue to shrink the size of transistor device features to achieve greater circuit density and higher performance, there is a need to address transistor drive current while reducing short channel effects, parasitic capacitance, and off-state leakage in next generation devices. Non-planar transistors such as fin and nanowire-based devices allow for improved control of short channel effects. For example, in nanowire-based transistors, the gate stack wraps around the complete perimeter of the nanowire, allowing for a more complete reduction in the channel area, reducing short channel effects due to a steeper lower threshold current swing (SS) and smaller drain-induced barrier lowering (DIBL).

[0003] Different functional blocks within a die may need to be optimized with respect to different electrical parameters. In some instances, high voltage transistors for power applications need to be implemented in conjunction with high speed transistors for logic applications. High voltage transistors usually suffer from high leakage currents. In nanowire devices, thicker oxides result in reducing the spacing between nanowires to the point where little or no gate metal can be disposed between the nanowires. [Brief description of the drawings]

[0004] [Figure 1A] 1 is a cross-sectional view of a first transistor and a second transistor on a substrate, where the first transistor is a gate-all-around (GAA) transistor and the second transistor is a tri-gate transistor, according to one embodiment.

[0005] [Figure 1B] FIG. 1B is a cross-sectional view of the first transistor of FIG. 1A according to one embodiment.

[0006] [Figure 1C] FIG. 1B is a cross-sectional view of the second transistor of FIG. 1A according to one embodiment.

[0007] [Figure 2A] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 2B] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 2C] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 2D] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 2E] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 2F] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment.

[0008] [Figure 3A] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 3B]1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 3C] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment. [Figure 3D] 1A-1C are cross-sectional views illustrating forming a first region including an alternating stack of channel layers and sacrificial layers and a second region including a single channel layer according to one embodiment.

[0009] [Figure 4A] FIG. 2 is a cross-sectional view after the first region and the second region have been patterned to form a first fin and a second fin, according to one embodiment.

[0010] [Figure 4B] FIG. 2 is a cross-sectional view depicting a profile of a first fin and a second fin according to one embodiment.

[0011] [Figure 5A] 4A-4D are cross-sectional views illustrating a process of forming a first transistor and a second transistor from a first fin and a second fin according to one embodiment. [Figure 5B] 4A-4D are cross-sectional views illustrating a process of forming a first transistor and a second transistor from a first fin and a second fin according to one embodiment. [Figure 5C] 4A-4D are cross-sectional views illustrating a process of forming a first transistor and a second transistor from a first fin and a second fin according to one embodiment. [Figure 5D] 4A-4D are cross-sectional views illustrating a process of forming a first transistor and a second transistor from a first fin and a second fin according to one embodiment. [Figure 5E] 4A-4D are cross-sectional views illustrating a process of forming a first transistor and a second transistor from a first fin and a second fin according to one embodiment. [Figure 5F] 4A-4D are cross-sectional views illustrating a process of forming a first transistor and a second transistor from a first fin and a second fin according to one embodiment. [Figure 5G] 4A-4D are cross-sectional views illustrating a process of forming a first transistor and a second transistor from a first fin and a second fin according to one embodiment.

[0012] [Figure 6] 1 illustrates a computing device according to an exemplary implementation of an embodiment of the present disclosure.

[0013] [Figure 7] 1 is an interposer implementing one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] A nanoribbon transistor integrated with a high voltage thick gate tri-gate transistor according to various embodiments is described herein. In the following description, exemplary implementations of various aspects are described using terms commonly used by those skilled in the art, so as to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations are set forth to provide a thorough understanding of the exemplary implementations. However, it will be apparent to those skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features have been omitted or simplified so as not to obscure the exemplary implementations.

[0015] Similarly, various operations will be described as multiple separate operations as is most useful in understanding the invention, however, the order of description should not be construed as to imply that these operations are necessarily sequential, and in particular, these operations do not have to be performed in the order they are presented.

[0016] Nanoribbon devices are described in more detail below. However, it should be understood that substantially similar devices may be formed with nanowire channels. Nanowire devices may include devices in which the channels have substantially similar width and thickness dimensions, while nanoribbon devices may include channels with width dimensions that are substantially greater than or substantially less than the thickness dimensions. As used herein, "high voltage" may refer to a voltage of about 1.0 V or greater.

[0017] As noted above, integrating thick-gate dielectric nanoribbon transistors with standard thickness gate dielectric nanoribbon transistors is problematic. In particular, the thicker gate dielectric may fit between the nanoribbons; that is, the gate dielectric blocks the gaps between the nanoribbons and prevents the gate metal from filling in the gaps. Therefore, gate-all-around (GAA) control of thick-gate dielectric nanoribbon transistors is not always possible.

[0018] Thus, embodiments disclosed herein include the integration of GAA devices with non-planar transistors, such as tri-gate devices. Tri-gate devices (also sometimes referred to as "FinFET" devices) allow for thick gate dielectrics because there are no gaps between portions of the channel, as is the case with nanoribbon devices. GAA devices require a gate metal (and gate dielectric) that wraps around the entire perimeter of the channel, whereas in tri-gate devices the gate metal (and gate dielectric) typically covers three surfaces of the channel (e.g., a pair of sidewalls and the top surface).

[0019] Furthermore, thick gate devices are typically used for analog or other high voltage applications. Such applications typically do not require the additional scaling (e.g., better short channel effects) provided by GAA devices. In addition, the switching frequencies for thick gate devices are typically below those required for logic applications. Thus, the embodiments disclosed herein leverage the additional performance improvements of GAA devices while maintaining the ease of manufacturing of thick gate devices using tri-gate devices.

[0020] In embodiments, integration of GAA and Tri-Gate devices with one another is implemented by forming different devices on different regions of a substrate. GAA devices may be formed from fins in regions of the substrate that include alternating stacks of channel layers and sacrificial layers, and Tri-Gate devices may be formed from fins in regions of the substrate that include a single channel layer. The embodiments disclosed herein provide different process flows to provide a substrate that includes both first and second regions that are used to form various transistor types.

[0021] 1A, a cross-sectional view of a semiconductor device 100 is shown, according to one embodiment. The semiconductor device 100 includes a first transistor 172, both formed on a substrate 101. A and the second transistor 172 B In the illustrated embodiment, the first transistor 172 A The second transistor 172 is connected to the substrate 101 by a break 104. B The break 104 is separated from the first transistor 172. A and the second transistor 172 B may be located in different regions of the substrate 101 and may not be adjacent to each other and / or oriented in the same direction.

[0022] In an embodiment, the substrate 101 may include a semiconductor substrate and a separation layer (not shown) on the semiconductor substrate 101. In an embodiment, the underlying semiconductor substrate 101 represents a typical processing object used to manufacture integrated circuits. The semiconductor substrate 101 often comprises a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates 101 include, but are not limited to, monocrystalline silicon, polycrystalline silicon, and silicon-on-insulator (SOI), as well as similar substrates formed of other semiconductor materials, such as substrates including germanium, carbon, or III-V materials.

[0023] The illustration of FIG. 1A shows two transistors 172 A and 172 B In a particular embodiment, the first transistor 172 A is a high speed transistor (e.g., suitable for logic operations), and the second transistor 172 B is a high voltage transistor (e.g., suitable for analog and / or power operations). A The second transistor 172 is a GAA transistor (e.g., a nanoribbon transistor). B is a tri-gate transistor.

[0024] In an embodiment, the first transistor 172 A The gate dielectric 112 may include a plurality of nanoribbon channels 110 arranged in a vertical stack. The nanoribbon channels 110 may include any suitable semiconductor material. For example, the nanoribbon channels 110 may include silicon or a III-V material. The nanoribbon channels 110 may have a spacing S between them. The spacing S may be optimized for high speed switching applications. For example, the spacing S may be about 10 nm or less. The first gate dielectric 112 A The first gate dielectric 112 may wrap around the entire outer surface of each nanoribbon channel 110. A is the first thickness T A The first thickness T AA first gate dielectric 112 is disposed between the nanoribbon channel 110. A For example, the first thickness T A may be about 3 nm or less. Thus, the first gate dielectric 112 A There is a gap between adjacent surfaces of the first gate dielectric 112. A The first gate dielectric 112 is deposited by a conformal deposition process (e.g., atomic layer deposition (ALD)). The conformal deposition process also deposits a first gate dielectric 112 on the inner surfaces of the spacers 122 and on the surface of the substrate 101. A However, in other embodiments, the first gate dielectric 112 may be deposited A In such an embodiment, the first gate dielectric 112 is grown (e.g., by an oxidation process). A may not be present on the inner surface of the spacer 122. That is, the gate electrode 130 may be in direct contact with the spacer 122.

[0025] In an embodiment, the gate electrode 130 may fill the gaps between the nanoribbon channels 110 to wrap around the entire outer surface of each nanoribbon channel 110. This is the first transistor 172. A In an embodiment, the first transistor 172 A may also include a pair of source / drain regions 120. The source / drain regions 120 may be separated from the gate electrode 130 by a pair of spacers 122. The nanoribbon channel 110 may pass through the spacers 122 to contact the source / drain regions 120.

[0026] In an embodiment, the second transistor 172 Bmay include a single semiconductor channel 115. In an embodiment, the semiconductor channel 115 may be fin-shaped. As used herein, the semiconductor channel 115 may be referred to as a fin channel 115. The fin channel 115 may include any suitable semiconductor material. For example, the fin channel 115 may include silicon or a III-V material. The fin channel 115 may extend up from the substrate 101. In an embodiment, the second gate dielectric 112 B is disposed on the surface of the fin channel 115, and a gate electrode 130 is disposed on the second gate dielectric 112. B In an embodiment, the second gate dielectric 112 B The second gate dielectric 112 may be deposited by a conformal deposition process (e.g., ALD) that also deposits a second gate dielectric 112 on the interior surfaces of the spacers 122. B However, in other embodiments, the second gate dielectric 112 may be deposited. B In such an embodiment, the second gate dielectric 112 is grown (e.g., by an oxidation process). B The second gate dielectric 112 may not be present on the inner surface of the spacer 122. That is, the gate electrode 130 may be in direct contact with the spacer 122. In some embodiments, the second gate dielectric 112 B is the first gate dielectric 112 A In another embodiment, the second gate dielectric 112 B is the first gate dielectric 112 A Contains materials different from.

[0027] In an embodiment, the second transistor 172 B The second transistor 172 includes a pair of source / drain regions 120 formed on either end of the fin channel 115. B The second gate dielectric 112 may also include a pair of spacers 122. BAnd the gate electrode 130 may be disposed between the inner surfaces of the spacers 122. The fin channel 115 may pass through the spacers 122 to contact the source / drain regions 120.

[0028] In the diagram shown in FIG. 1A, the second gate dielectric 112 B and the gate electrode 130 is on top of the fin channel 115 but is separated from the second gate dielectric 112 B The gate electrode 130 also serves as a second transistor 172 B It should be understood that the tri-gate control will extend along the sidewalls (into and out of the plane of FIG. 1A) providing tri-gate control of the .lambda.

[0029] In an embodiment, the second gate dielectric 112 B is the second thickness T B The second thickness T B is the first thickness T A For example, the second thickness T B may be about 3 nm or more. It should be noted that the fin channel 115 does not include gaps between portions of the channel (as is the case with the nanoribbon channel 110). Therefore, the second gate dielectric 112 B can be deposited (or grown) to a greater thickness without concern for pinching that would prevent the gate electrode 130 from filling around the surface of the fin channel 115. In an embodiment, the first thickness T A Second thickness T B The increase in B For example, the second transistor 172 B may have an operating voltage of about 1.0 V or higher.

[0030] In an embodiment, the first transistor 172 A and the second transistor 172 B may have different channel lengths. For example, the first transistor 172 A is the first channel length L gAand the second transistor 172 B is the first channel length L gA The larger second channel length L gB The larger second channel length L gB allows for high voltage support, while the shorter first channel length L gA supports fast switching frequencies. In an embodiment, the second channel length L gB may be about 50 nm or more, or may be about 100 nm or more.

[0031] In an embodiment, the first gate dielectric 112 A and a second gate dielectric 112 B The material selected for the first gate dielectric 112 may be any suitable high dielectric constant material. For example, A and a second gate dielectric 112 B may be any suitable oxide, such as, for example, silicon dioxide or a high-k gate dielectric material. Examples of high-k gate dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0032] In an embodiment, the material selected for the gate electrode 130 may be any suitable work function metal to provide a desired threshold voltage for operation as a P-type or N-type transistor. For example, if the metal gate electrode 130 will function as an N-type work function metal, the gate electrode 130 preferably has a work function between about 3.9 eV and about 4.2 eV. N-type materials that may be used to form the metal gate electrode 130 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and metal carbides containing these elements, such as titanium carbide, zirconium carbide, tantalum carbide, hafnium carbide, and aluminum carbide. Alternatively, if the metal gate electrode 130 will function as a P-type work function metal, the gate electrode 130 preferably has a work function between about 4.9 eV and about 5.2 eV. P-type materials that may be used to form the metal gate electrode 130 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, such as ruthenium oxide. The gate electrode 130 may also include a work function metal and a fill metal (e.g., tungsten) on the work function metal.

[0033] In an embodiment, the source / drain regions 120 may include an epitaxially grown semiconductor material. The source / drain regions 120 may include a silicon alloy. In some implementations, the source / drain regions 120 include a silicon alloy, which may be in-situ doped silicon germanium, in-situ doped silicon carbide, or in-situ doped silicon. In alternative embodiments, other silicon alloys may be used. For example, alternative silicon alloy materials that may be used include, but are not limited to, nickel silicide, titanium silicide, cobalt silicide, and may be doped with one or more of boron and / or aluminum. In other embodiments, the source / drain regions 120 may include alternative semiconductor materials (e.g., semiconductors including III-V elements and their alloys), or conductive materials.

[0034] 1B and 1C, according to one embodiment, a first transistor 172 along lines B-B' and C-C' of FIG. 1A, respectively, is shown. A and the second transistor 172 B A cross-sectional view of is shown.

[0035] 1B, according to one embodiment, a first transistor 172 A As shown, the first gate dielectric 112 A The gate electrode 130 wraps around the entire periphery of each of the nanoribbon channels 110. In addition, the gate electrode 130 is in contact with the first gate dielectric 112. A The gate electrode 130 may be separated from the substrate 101 by an isolation layer 103. In some embodiments, the top surface of the isolation layer 103 may also be in contact with the first gate dielectric 112. A (e.g., the ALD process may cover the first gate dielectric 112 A (when used for deposition of

[0036] Referring now to FIG. 1C, according to one embodiment, a second transistor 172 B A cross-sectional view across the channel region of the fin 115 is shown. As shown, the fin channel 115 includes sidewalls 117 and a top surface 118. The second gate dielectric 112 B The gate electrode 130 is disposed on the upper sidewall 117 and on the top surface 118 of the isolation layer 103. B Thus, the three surfaces of the fin channel 115 cover the second tri-gate transistor 172. B In some embodiments, the top surface of the isolation layer 103 is also controlled to provide a second gate dielectric 112. B (e.g., the ALD process may cover the second gate dielectric 112 B (when used for deposition of

[0037] 2A-2F, a series of cross-sectional views are shown illustrating a process for forming an electronic device 200 having a first region and a second region, according to one embodiment. The first region may include a stack of alternating channel layers and sacrificial layers to form a nanoribbon device. The second region may include a single channel layer to form a tri-gate device.

[0038] 2A, a cross-sectional view of an electronic device 200 is shown, according to one embodiment. The electronic device 200 includes a substrate 201. The substrate 201 may be a semiconductor substrate, such as that described above in connection with FIG. 1A.

[0039] 2B, a cross-sectional view of the electronic device 200 is shown after a stack 250 of alternating channel layers 211 and sacrificial layers 231 has been formed, according to one embodiment. In an embodiment, the channel layer 211 is a material selected for use as a nanoribbon. The channel layer 211 and the sacrificial layer 231 may each be a material such as, but not limited to, silicon, germanium, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In a particular embodiment, the channel layer 211 is silicon and the sacrificial layer 231 is SiGe. In another particular embodiment, the channel layer 211 is germanium and the sacrificial layer 231 is SiGe. The channel layer 211 and the sacrificial layer 231 may be grown by an epitaxial growth process.

[0040] In the illustrated embodiment, there are four channel layers 211. However, it should be understood that there may be any number of channel layers 211 in the stack 250. In an embodiment, the top layer of the stack 250 is a sacrificial layer 231. In other embodiments, the top layer of the stack 250 may be a channel layer 211.

[0041] 2C, a cross-sectional view of electronic device 200 is shown after a mask layer 255 has been disposed on stack 250 and patterned, according to one embodiment. In an embodiment, mask layer 255 may be a resist or a hard mask. Mask layer 255 defines a first region 241 (below mask 255) and a second region 242 (outside mask 255). First region 241 is the region where nanoribbon transistor devices will be formed, and second region 242 is the region where tri-gate transistor devices will be formed.

[0042] 2D , a cross-sectional view of the electronic device 200 after the stack 250 has been patterned is shown, according to one embodiment. In an embodiment, the stack 250 may be patterned by an etching process (e.g., a dry etching process). The etching process may include another different chemistry to etch through both the exposed channel layer 211 and the sacrificial layer 231. The etching process provides an opening 244 in the second region 242. The opening 244 exposes the substrate 201 in some embodiments.

[0043] 2E, a cross-sectional view of electronic device 200 is shown after a single channel layer 213 has been disposed on substrate 201 in second region 242, according to one embodiment. In an embodiment, channel layer 213 may be the same material as substrate 201, or channel layer 213 may be a different material than substrate 201. Channel layer 213 may be grown by an epitaxial growth process.

[0044] In embodiments, the channel layer 213 is grown to a thickness at least equal to the top surface of the stack 250. As shown, the top surface 214 of the channel layer 213 may be above the top surface 209 of the highest channel layer 211 in the stack 250. In embodiments in which the top layer of the stack 250 is a channel layer, the top surface 209 of the highest channel layer 211 may be substantially coplanar with the top surface of the channel layer 213.

[0045] 2F, a cross-sectional view of electronic device 200 is shown after capping layer 256 is disposed on stack 250 and channel layer 213, according to one embodiment. Capping layer 256 may be disposed after removal of mask layer 255. In an embodiment, capping layer 256 is an oxide or the like. Capping layer 256 may be used to protect underlying layers during the fin patterning process.

[0046] 3A-3D, a series of cross-sectional views are shown illustrating a process for forming an electronic device 300 having a first region and a second region, according to one embodiment. The first region may include a stack of alternating channel layers and sacrificial layers to form a nanoribbon device. The second region may include a single channel layer to form a tri-gate device.

[0047] 3A, there is shown a cross-sectional view of an electronic device 300, according to one embodiment. In an embodiment, the electronic device 300 includes a substrate 301. The substrate 300 may be a material substantially similar to the substrate 101 of FIG. 1A.

[0048] 3B, a cross-sectional view of electronic device 300 is shown after a mask layer 355 has been disposed on substrate 300 and the substrate has been patterned, according to one embodiment. In an embodiment, mask layer 355 defines first region 341 (an uncovered region of substrate 301) and second region 342 (a covered region of substrate 301). Mask layer 355 is used to pattern substrate 301 to form opening 344. Opening 344 results in channel layer 313 being left behind below mask layer 355.

[0049] 3C, a cross-sectional view of the semiconductor device 300 is shown after the stack 350 is disposed in the opening 344, according to one embodiment. In an embodiment, the stack 350 may include alternating channel layers 311 and sacrificial layers 331. In an embodiment, the channel layers 311 and sacrificial layers 331 may be similar to those described above in connection with FIG. 2B. In an embodiment, the top surface 309 of the top channel layer 311 may be below the top surface 314 of the channel layer 313.

[0050] 3D, a cross-sectional view of the semiconductor device 300 is shown after a capping layer 356 is disposed on the stack 350 and on the channel layer 313, according to one embodiment. The capping layer 356 may be disposed after removal of the mask layer 355. In an embodiment, the capping layer 356 is an oxide or the like. The capping layer 356 may be used to protect underlying layers during a fin patterning process.

[0051] 4A, a cross-sectional view of an electronic device 400 after a first fin 406 and a second fin 416 have been patterned is shown, according to one embodiment. In an embodiment, the first fin 406 is formed from a first region having a stack of alternating channel layers (e.g., channel layer 211 or 311) and sacrificial layers (e.g., sacrificial layer 231 or 331). The patterning to convert the first region into a fin 406 results in the channel layer (e.g., channel layer 211 or 311) being converted into a nanoribbon channel 410. That is, the fin 406 may include a stack 451, which is a fin in the form of alternating layers of nanoribbon channels 410 and sacrificial layers 431. The second fin 416 is formed from a second region having a single channel layer (e.g., channel layer 213 or channel layer 313). Patterning to convert the second region into fin 416 results in a single channel layer (eg, channel layer 213 or channel layer 313) being converted into a fin channel 415.

[0052] In Figure 4A, the profile of fin 416 is an idealized representation of the fin formation. For example, in Figure 4A, fin 416 has substantially vertical sidewalls 417 and a top surface 418 that is parallel to the surface of the underlying substrate 401. However, it should be understood that the profiles of first fin 406 and second fin 416 may have different variations due to manufacturing limitations or other design choices.

[0053] 4B, a cross-sectional view of a pair of second fins 416 is shown according to an additional embodiment. As shown, the sidewall surface 417 may be tapered to some extent. That is, in some embodiments, the sidewall surface 417 may not be perfectly perpendicular to the substrate 401. In embodiments, the bottom of the fin 416 closest to the substrate 401 may have a footing 419 or other similar structural feature typical of high aspect ratio structures formed by dry etching processes. In addition, the profile of all fins may not be uniform. For example, a nested fin may have a different profile than a separate fin or a fin that is the outermost fin of a collection of fins. For example, the fin 416 in FIG. 4B may be considered an outermost fin and may exhibit an asymmetric profile. As shown, the sidewall surface 417 facing toward the neighboring fin 416 may be shorter than the sidewall surface 417 facing outward due to etch limitations. In embodiments, the top surface 418 of the fin 416 may also be rounded or otherwise non-flat. FIG. 4B illustrates an example of the second fin 416, but it should be understood that a substantially similar profile may be exhibited in the first fin 406 as well.

[0054] 5A-5G, a series of cross-sectional views are shown illustrating the formation of a first nanoribbon transistor and a second tri-gate transistor in a single processing run, according to one embodiment. In each of FIGs. 5A-5G, a cross-sectional view is provided along the length of a first transistor channel and a second transistor channel. Each of FIGs. 5A-5G also provides a pair of cross-sections across the channels for each of the first and second transistors.

[0055] 5A, a set of cross-sectional views of an electronic device 500 is shown after a first fin 506 and a second fin 516 have been patterned, according to one embodiment. In an embodiment, the first fin 506 and the second fin 516 may be patterned from a process including the process flow of FIGS. 2A-2F or 3A-3D. The first fin 506 includes a stack 551 on a substrate 501. The stack 551 includes alternating nanoribbon channels 510 and a sacrificial layer 531. The second fin 516 may include a fin channel 515. The fin channel 515 may extend up from the substrate 501. A separation layer 503 may be disposed on a surface of the substrate 501 on the sides of the first fin 506 and the second fin 516.

[0056] 5B, a set of cross-sectional views of electronic device 500 is shown after sacrificial gate 533 and spacers 522 have been formed, according to one embodiment. FIG. 5B also shows recesses in portions of first fin 506 and second fin 516 that provide source / drain openings 546. Sacrificial gate 533 covers the tops of fins 506 and 516 and wraps down along the sidewalls of fins 506 and 516. Spacers 522 may be disposed on either side of sacrificial gate 533. Nanoribbon channel 510 and fin channel 515 extend through spacer 522.

[0057] 5C, a set of cross-sectional views of the electronic device 500 after source / drain regions 520 have been formed is shown, according to one embodiment. In an embodiment, the source / drain regions 520 may be grown by an epitaxial growth process. The source / drain regions 520 may be doped in situ during growth to provide N-type or P-type source / drain regions 520. Suitable materials and dopants for the source / drain regions 520 are described in more detail above.

[0058] 5D, a set of cross-sectional views of electronic device 500 after sacrificial gate 533 has been removed is shown, according to one embodiment. Sacrificial gate 533 may be removed by a suitable etching process. Removal of sacrificial gate 533 exposes nanoribbon channel 510 and fin channel 515.

[0059] 5E, a set of cross-sectional views of electronic device 500 is shown after sacrificial layer 531 has been selectively removed to release nanoribbon channels 510, according to one embodiment. Removal of sacrificial layer 531 clears a spacing S between each of nanoribbon channels 510. In an embodiment, spacing S may be about 10 nm or less.

[0060] The sacrificial layer 531 may be removed using any known etchant that is selective to the nanoribbon channel 510. In an embodiment, the selectivity is greater than 100:1. In an embodiment in which the nanoribbon channel 510 is silicon and the sacrificial layer 531 is silicon germanium, the sacrificial layer 531 is selectively removed using a wet etchant such as, but not limited to, an aqueous carboxylic acid / citric acid / HF solution and an aqueous citric acid / nitric acid / HF solution. In an embodiment in which the nanoribbon channel 510 is germanium and the sacrificial layer 531 is silicon germanium, the sacrificial layer 531 is selectively removed using a wet etchant such as, but not limited to, an aqueous ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediaminepyrocatechol (EDP), or potassium hydroxide (KOH) solution. In another embodiment, the sacrificial layer 531 is removed by a combination of wet and dry etching processes.

[0061] 5F, a set of cross-sectional views of the electronic device 500 are shown after a gate dielectric 512 is disposed over the nanoribbon channel 510 and the fin channel 515, according to one embodiment. In an embodiment, the first gate dielectric 512 Ais disposed on the nanoribbon channel 510. In particular, the A-A′ cross section shows that the nanoribbon channel 510 is provided with a first gate dielectric 512 to enable GAA control of the nanoribbon channel 510. A The first gate dielectric 512 is completely surrounded by A is the first thickness T A In an embodiment, the first thickness T A may be about 3 nm or less. In an embodiment, the first gate dielectric 512 A The first gate dielectric 512 may be deposited by an ALD process or grown by an oxidation process. A In an embodiment in which the first gate dielectric 512 is deposited by an ALD process, as shown in FIG. A may also be disposed on the interior sidewalls of the spacers 522 or on portions of the insulating layer 503 .

[0062] In an embodiment, the second gate dielectric 512 B is disposed on the fin channel 515. In particular, cross section B-B′ shows that the fin channel 515 is surrounded on the sidewall and top surfaces to enable tri-gate control of the fin channel 515. B is the second thickness T B In an embodiment, the second thickness T B is the first thickness T A For example, the second thickness T B may be about 3 nm or more. In an embodiment, the second gate dielectric 512 B The second gate dielectric 512 may be deposited by an ALD process or grown by an oxidation process. B In an embodiment in which the second gate dielectric 512 is deposited by an ALD process, as shown in FIG. B may also be disposed on the interior sidewalls of the spacers 522 or on portions of the insulating layer 503 .

[0063] In an embodiment, the first gate dielectric 512 A is the second gate dielectric 512B In another embodiment, the first gate dielectric 512 may be the same material as the first gate dielectric 512. A is the second gate dielectric 512 B In some embodiments, the first gate dielectric 512 may be a different material. A may be deposited (or grown) by a first process, and the second gate dielectric 512 B may be deposited (or grown) by a second process that is different from the first process. A is the second gate dielectric 512 B In such an embodiment, the first gate dielectric 512 may be deposited (or grown) in parallel with A The desired first thickness T A Once this is reached, the first gate dielectric 512 A The masking may be turned off and the process continues with the second gate dielectric 512. B The thickness of the desired second thickness T B The number of ions may continue to increase to 100.

[0064] 5G, according to one embodiment, a gate electrode 530 is disposed on a gate dielectric 512. A and 512 B 5 shows a set of cross-sectional views of the electronic device 500 after being disposed on the gate electrode 530. In an embodiment, the gate electrode 530 may be disposed by a suitable deposition process (e.g., ALD, chemical vapor deposition (CVD), etc.). The gate electrode 530 may be configured to define a transistor 572 as a P-type or N-type transistor. A and 572 B The gate electrode 530 may include a work function metal appropriate for the process of FIG. 1. As shown in cross section A-A', the gate electrode 530 fills the sidewalls of the nanoribbon channels 510 as well as the gaps G between the nanoribbon channels 510, thus providing GAA control of the nanoribbon channels 510. As shown in cross section B-B', the gate electrode 530 wraps around a pair of sidewalls and the top surface of the fin channels 515 to provide tri-gate control of the fin channels 515.

[0065] 6 illustrates a computing device 600 according to one implementation of an embodiment of the present disclosure. The computing device 600 houses a board 602. The board 602 may include multiple components, including but not limited to a processor 604 and at least one communication chip 606. The processor 604 is physically and electrically coupled to the board 602. In some implementations, the at least one communication chip 606 is also physically and electrically coupled to the board 602. In further implementations, the communication chip 606 is part of the processor 604.

[0066] Computing device 600 may include other components that may or may not be physically and electrically coupled to board 602, depending on its application. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, crypto-processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, Global Positioning System (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (such as hard disk drives, compact discs (CDs), digital versatile discs (DVDs), etc.).

[0067] The communications chip 606 enables wireless communication for data transfer to and from the computing device 600. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc. that may communicate data using modulated electromagnetic radiation over a non-solid medium. The term does not imply that the associated devices are completely wire-free, although in some embodiments they may not be. The communications chip 606 may implement any of a number of wireless standards or protocols, including, but not limited to, Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G and beyond. The computing device 600 may include multiple communications chips 606. For example, a first communications chip 606 may be dedicated to short-range wireless communications such as Wi-Fi® and Bluetooth®, and a second communications chip 606 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX®, LTE, Ev-DO, and others.

[0068] The processor 604 of the computing device 600 includes an integrated circuit die packaged within the processor 604. In an embodiment, as described herein, the integrated circuit die of the processor 604 may include a nanoribbon transistor having a first gate dielectric thickness and a tri-gate transistor having a second gate dielectric thickness greater than the first gate dielectric thickness. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that may be stored in registers and / or memory.

[0069] The communications chip 606 also includes an integrated circuit die packaged within the communications chip 606. In an embodiment, the integrated circuit die of the communications chip 606 may include a nanoribbon transistor having a first gate dielectric thickness and a tri-gate transistor having a second gate dielectric thickness greater than the first gate dielectric thickness, as described herein.

[0070] In a further implementation, another component contained within computing device 600 as described herein may include a nanoribbon transistor having a first gate dielectric thickness and a tri-gate transistor having a second gate dielectric thickness greater than the first gate dielectric thickness.

[0071] In various implementations, computing device 600 may be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In further implementations, computing device 600 may be any other electronic device that processes data.

[0072] FIG. 7 illustrates an interposer 700 including one or more embodiments of the present disclosure. The interposer 700 is an intervening substrate used to bridge a first substrate 702 to a second substrate 704. The first substrate 702 may be, for example, an integrated circuit die. The second substrate 704 may be, for example, a memory module, a computer motherboard, or another integrated circuit die. In an embodiment, one of both the first substrate 702 and the second substrate 704 may include a nanoribbon transistor having a first gate dielectric thickness and a tri-gate transistor having a second gate dielectric thickness greater than the first gate dielectric thickness according to an embodiment described herein. In general, the purpose of the interposer 700 is to extend connections to a wider pitch or reroute one connection to a different connection. For example, the interposer 700 may bond an integrated circuit die to a ball grid array (BGA) 706, which in turn may be bonded to the second substrate 704. In some embodiments, the first and second substrates 702 / 704 are attached to opposite sides of the interposer 700. In other embodiments, the first and second substrates 702 / 704 are attached to the same side of the interposer 700. In further embodiments, three or more substrates are interconnected by the interposer 700.

[0073] Interposer 700 may be formed of a polymeric material such as epoxy, fiberglass reinforced epoxy, a ceramic material, or polyimide, etc. In further implementations, interposer 700 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials.

[0074] The interposer 700 may include metal wiring 708 and vias 710, including but not limited to through silicon vias (TSVs) 712. The interposer 700 may further include embedded devices 714, including both passive and active devices. Such devices include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices, such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices, may also be formed on the interposer 700. According to an embodiment of the present disclosure, an apparatus or process disclosed herein may be used in the manufacture of the interposer 700.

[0075] Thus, embodiments of the present disclosure may include a semiconductor device including a nanoribbon transistor having a first gate dielectric thickness and a tri-gate transistor having a second gate dielectric thickness greater than the first gate dielectric thickness, and a plurality of resulting structures.

[0076] The above description of illustrated implementations of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific implementations of, and examples for, the invention have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the art will recognize.

[0077] These modifications may be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific implementations disclosed in the specification and claims. Rather, the scope of the invention shall be determined solely by the following claims, which shall be construed in accordance with established doctrines of claim interpretation.

[0078] Example 1: A semiconductor device comprises a substrate; a first transistor on the substrate, the first transistor including a vertical stack of first semiconductor channels; a first gate dielectric around each of the first semiconductor channels, the first gate dielectric having a first thickness; a second transistor on the substrate, the second transistor including a second semiconductor channel, the second semiconductor channel including a pair of sidewalls and a top surface; and a second gate dielectric on the pair of sidewalls and on the top surface of the fin, the second gate dielectric having a second thickness greater than the first thickness.

[0079] Example 2: The semiconductor device of example 1, wherein the first semiconductor channel is a nanoribbon or a nanowire.

[0080] Example 3: The semiconductor device of example 1 or example 2, wherein the second semiconductor channel is part of a fin extending upwardly from the substrate.

[0081] Example 4: The semiconductor device of Examples 1-3, wherein the first thickness is about 3 nm or less and the second thickness is about 3 nm or more.

[0082] Example 5: The semiconductor device of Examples 1-4, wherein the spacing between the first semiconductor channels is less than or equal to about 10 nm.

[0083] Example 6: The semiconductor device of Examples 1-5, wherein the first transistor has a first channel length and the second transistor has a second channel length that is greater than the first channel length.

[0084] Example 7: The semiconductor device of example 6, wherein the second channel length is greater than or equal to about 50 nm.

[0085] Example 8: The semiconductor device of Examples 1-7, wherein the first transistor is a logic transistor and the second transistor is a high voltage transistor.

[0086] Example 9: The semiconductor device of Examples 1-8, wherein the top surface of the second semiconductor channel is above the top surface of the uppermost first semiconductor channel in the vertical stack of first semiconductor channels.

[0087] Example 10: A method of forming a semiconductor device comprising: forming a first region and a second region on a substrate, the first region including an alternating stack of first channel layers and sacrificial layers and the second region including a single second channel layer; patterning the first region and the second region to form a first fin in the first region and a second fin in the second region; forming a first transistor from the first fin, the forming including removing the sacrificial layer from the first fin and disposing a first gate dielectric around each of the first channel layers, the first gate dielectric having a first thickness; and forming a second transistor from the second fin, the forming including disposing a second gate dielectric on sidewall surfaces and a top surface of the second fin, the second gate dielectric having a second thickness greater than the first thickness.

[0088] Example 11: The method of Example 10, wherein forming the first region and the second region includes forming an alternating stack of a first channel layer and a sacrificial layer, masking portions of the alternating stack, the masked portions of the alternating stack defining the first region and the unmasked portions of the alternating stack defining the second region, removing the unmasked portions of the alternating stack to expose the substrate, and growing a second channel layer up from the substrate.

[0089] Example 12: The method of Example 10, wherein forming the first region and the second region includes masking the substrate, where the masked portion of the substrate defines a second channel layer in the second region and the unmasked portion of the substrate defines the first region; etching the substrate in the first region; and growing an alternating stack of the first channel layer and a sacrificial layer in the first region.

[0090] Example 13: The method of Examples 10-12, wherein the top and bottom layers of the alternating stacks are sacrificial layers.

[0091] Example 14: The method of examples 10-13, wherein the first channel layer in the first fin is a nanoribbon or a nanowire.

[0092] Example 15: The method of examples 10-14, wherein the first thickness is about 3 nm or less and the second thickness is about 3 nm or more.

[0093] Example 16: The method of examples 10-15, wherein the spacing between the first channel layers is less than or equal to about 10 nm.

[0094] Example 17: A semiconductor device comprising: a substrate; a gate-all-around (GAA) transistor on the substrate, the GAA transistor including a first gate dielectric having a first thickness; and a tri-gate transistor on the substrate, the GAA transistor including a second gate dielectric having a second thickness greater than the first thickness.

[0095] Example 18: The semiconductor device of example 17, wherein the GAA transistor is a nanowire transistor or a nanoribbon transistor.

[0096] Example 19: The semiconductor device of example 17 or example 18, wherein the first thickness is about 3 nm or less and the second thickness is about 3 nm or more.

[0097] Example 20: The semiconductor device of Examples 17-19, wherein the GAA transistor has a first channel length and the tri-gate transistor has a second channel length greater than the first channel length.

[0098] Example 21: The semiconductor device of Examples 17-20, wherein the GAA transistor is a logic transistor and the Tri-Gate transistor is a high voltage transistor.

[0099] Example 22: The semiconductor device of example 21, wherein the operating voltage of the high voltage transistor is about 1.0 V or more.

[0100] Example 23: An electronic device comprising: a board; a semiconductor package electrically coupled to the board; and a die electrically coupled to the semiconductor package, the die including: a substrate; a gate-all-around (GAA) transistor on the substrate, the GAA transistor including a first gate dielectric having a first thickness; and a tri-gate transistor on the substrate, the tri-gate transistor including a second gate dielectric having a second thickness greater than the first thickness.

[0101] Example 24: The electronic device of example 23, wherein the GAA transistor is a logic transistor and the tri-gate transistor is a high voltage transistor.

[0102] Example 25 The electronic device of example 23 or example 24, wherein the first thickness is less than or equal to about 3 nm and the second thickness is greater than or equal to about 3 nm.

Claims

1. A substrate; a first transistor on the substrate, the first transistor including a vertical stack of first semiconductor channels; a first gate dielectric around each of the first semiconductor channels, the first gate dielectric having a first thickness; a second transistor on the substrate, the second transistor including a second semiconductor channel, the second semiconductor channel including a pair of sidewalls and a top surface; a second gate dielectric on the pair of sidewalls and on the top surface of the fin, the second gate dielectric having a second thickness greater than the first thickness; the top surface of the second semiconductor channel is above or flush with a top surface of a top first semiconductor channel in the vertical stack of first semiconductor channels; Semiconductor device.

2. The semiconductor device of claim 1 , wherein the first semiconducting channel is a nanoribbon or a nanowire.

3. The semiconductor device of claim 1 or 2, wherein the second semiconductor channel is part of a fin extending up from the substrate.

4. The semiconductor device of claim 1 , wherein the first thickness is less than or equal to 3 nm and the second thickness is greater than or equal to 3 nm.

5. 5. The semiconductor device of claim 1, wherein the spacing between the first semiconductor channels is 10 nm or less.

6. 6. The semiconductor device of claim 1, wherein the first transistor has a first channel length and the second transistor has a second channel length that is greater than the first channel length.

7. The semiconductor device of claim 6 , wherein the second channel length is greater than or equal to 50 nm.

8. 8. The semiconductor device of claim 1, wherein the first transistor is a logic transistor and the second transistor is a high voltage transistor.

9. The first transistor is a gate-all-around (GAA) transistor; The second transistor is a tri-gate transistor. A semiconductor device according to any one of claims 1 to 8.

10. The semiconductor device of claim 9 , wherein the GAA transistor is a nanowire transistor or a nanoribbon transistor.

11. 11. The semiconductor device of claim 9 or 10, wherein the GAA transistor is a logic transistor and the Tri-Gate transistor is a high voltage transistor.

12. 12. The semiconductor device of claim 11, wherein the high voltage transistor has an operating voltage of 1.0V or greater.

13. Board and a semiconductor package electrically connected to the board; A die electrically coupled to the semiconductor package, the die comprising the semiconductor device of claim 1 ; An electronic device comprising:

14. 1. A method of forming a semiconductor device, comprising: forming a first region and a second region on a substrate, the first region including an alternating stack of first channel layers and sacrificial layers, and the second region including a single second channel layer; patterning the first region and the second region to form a first fin in the first region and a second fin in the second region; forming a first transistor from the first fin, the forming including removing the sacrificial layer from the first fin and disposing a first gate dielectric around each of the first channel layers, the first gate dielectric having a first thickness; forming a second transistor from the second fin, the forming including disposing a second gate dielectric on sidewall surfaces and a top surface of the second fin, the second gate dielectric having a second thickness greater than the first thickness; Equipped with The step of forming the first region and the second region includes: forming said alternating stack of first channel layers and sacrificial layers; masking portions of the alternating stacks, the masked portions of the alternating stacks defining the first regions and the unmasked portions of the alternating stacks defining the second regions; removing the unmasked portions of the alternating stacks to expose the substrate; and growing the second channel layer upwardly from the substrate. method.

15. A method for forming a semiconductor device, comprising the steps of: forming a first region and a second region on a substrate, the first region including an alternating stack of first channel layers and sacrificial layers, and the second region including a single second channel layer; patterning the first region and the second region to form a first fin in the first region and a second fin in the second region; forming a first transistor from the first fin, the forming including removing the sacrificial layer from the first fin and disposing a first gate dielectric around each of the first channel layers, the first gate dielectric having a first thickness; forming a second transistor from the second fin, the forming including disposing a second gate dielectric on sidewall surfaces and a top surface of the second fin, the second gate dielectric having a second thickness greater than the first thickness; Equipped with The step of forming the first region and the second region includes: masking the substrate, the masked portion of the substrate defining a second channel layer in the second region and the unmasked portion of the substrate defining the first region; Etching the substrate in the first region; and growing an alternating stack of first channel layers and sacrificial layers in the first region. method.

16. A method for forming a semiconductor device, comprising the steps of: forming a first region and a second region on a substrate, the first region including an alternating stack of first channel layers and sacrificial layers, and the second region including a single second channel layer; patterning the first region and the second region to form a first fin in the first region and a second fin in the second region; forming a first transistor from the first fin, the forming including removing the sacrificial layer from the first fin and disposing a first gate dielectric around each of the first channel layers, the first gate dielectric having a first thickness; forming a second transistor from the second fin, the forming including disposing a second gate dielectric on sidewall surfaces and a top surface of the second fin, the second gate dielectric having a second thickness greater than the first thickness; Equipped with the top and bottom layers of the alternating stack are sacrificial layers; method.

17. 17. The method of claim 14, wherein the first channel layer in the first fin is a nanoribbon or a nanowire.

18. 18. The method of any one of claims 14 to 17, wherein the first thickness is less than or equal to 3 nm and the second thickness is greater than or equal to 3 nm.

19. 19. The method of claim 14, wherein the spacing between the first channel layers is 10 nm or less.

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