Vertical transport CMOS transistors with asymmetric threshold voltages

Abstract

A semiconductor structure for triggering an asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including a SiGe layer and a second material layer formed on the SiGe layer, a first high-κ metal gate disposed on the first set of fins, and a second high-κ metal gate disposed on the second set of fins. Along the channel of the VTFET, an asymmetric threshold voltage exists in a region defined at the bottom of the first set of fins and the second set of fins, and the Ge content of the second material layer is greater than the Ge content of the SiGe layer.

Description

[Technical field]

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to an asymmetric threshold voltage vertical transport field effect transistor (VTFET) with intrinsic dual channel epitaxy, and a method for fabricating a VTFET device. [Background technology]

[0002] In recent years, the demand for miniaturization of semiconductor devices has increased with the increase in integration, functionality, and speed of semiconductor devices. To meet this demand, various device structures have been proposed to reduce the area occupied by transistors on a substrate. In particular, the field effect transistor with fin-type structure (FinFET) has attracted attention. FinFET is a three-dimensional structure that stands on a substrate and looks like a fin. It is desirable to improve the fabrication of FinFET transistors to improve the quality of the transistor contacts. The VTFET is an example of a FinFET device, which orients a vertical fin-type channel structure disposed on top of bottom source and bottom drain electrodes. Furthermore, top source and top drain electrodes are disposed on top of the fin channel. The VTFET is being explored as a promising device option for the ongoing complementary metal-oxide-semiconductor (CMOS) scaling beyond the 7 nanometer (nm) technology node. Summary of the Invention

[0003] An embodiment of the present disclosure relates to a semiconductor structure for triggering an asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET), the semiconductor structure including a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including a SiGe layer and a second material layer formed on the SiGe layer, a first high-κ metal gate disposed on the first set of fins, and a second high-κ metal gate disposed on the second set of fins, where an asymmetric threshold voltage exists along the channel of the VTFET in a region defined at a bottom of the first set of fins and the second set of fins, and the Ge content of the second material layer is greater than the Ge content of the SiGe layer.

[0004] Another embodiment of the present disclosure relates to a method for triggering an asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET), the method including forming a first set of fins including a SiGe layer and a first material layer over the SiGe layer, forming a second set of fins including a SiGe layer and a second material layer over the SiGe layer, forming a first high-κ metal gate over the first set of fins, and forming a second high-κ metal gate over the second set of fins, where an asymmetric threshold voltage exists along the channel of the VTFET in a region defined at a bottom of the first set of fins and the second set of fins, and the Ge content of the second material layer is greater than the Ge content of the SiGe layer.

[0005] It should be noted that the exemplary embodiments are described in relation to different subject matters. Specifically, some embodiments are described in relation to method type claims, and other embodiments are described in relation to device type claims. However, a person skilled in the art will infer from the above and following description that, unless otherwise specifically known, in addition to any combination of features belonging to one type of subject matter, any combination of features related to different subject matters, specifically between features of method type claims and features of device type claims, is also considered to be described herein.

[0006] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings.

[0007] The above summary is not intended to describe each illustrative embodiment or every implementation of the present disclosure. [Brief description of the drawings]

[0008] The drawings included in this application are incorporated in and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the description, explain the principles of the present disclosure. The drawings are merely illustrative of certain embodiments and are not intended to limit the disclosure.

[0009] [Figure 1] FIG. 1 is a cross-sectional view of a semiconductor structure having a fin structure including a channel epi and a low Ge content SiGe layer formed over a semiconductor substrate, according to one embodiment. [Diagram 2] 2 is a cross-sectional view of the semiconductor structure of FIG. 1 with a hardmask formed over the semiconductor structure according to one embodiment. [Diagram 3] 3 is a cross-sectional view of the semiconductor structure of FIG. 2 with multiple fins formed over the semiconductor structure according to one embodiment. [Figure 4] 4 is a cross-sectional view of the semiconductor structure of FIG. 3 with bottom source / drain regions formed therein according to one embodiment. [Diagram 5] 5 is a cross-sectional view of the semiconductor structure of FIG. 4 with bottom spacers formed on the bottom source / drain regions according to one embodiment. [Figure 6] FIG. 6 is a cross-sectional view of the semiconductor structure of FIG. 5 with a high-κ metal gate formed over the multiple fins according to one embodiment. [Figure 7] FIG. 7 is a cross-sectional view of the semiconductor structure of FIG. 6 in which the high-κ metal gate is recessed to expose the tops of the multiple fins, according to one embodiment. [Figure 8] 8 is a cross-sectional view of the semiconductor structure of FIG. 7 with gate encapsulation performed according to one embodiment. [Figure 9] FIG. 9 is a cross-sectional view of the semiconductor structure of FIG. 8 with upper source / drain regions formed on and in direct contact with the exposed upper portions of the multiple fins, according to one embodiment. [Figure 10] 10 is a cross-sectional view of the semiconductor structure of FIG. 9 with metallization of the upper source / drain regions according to one embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] DETAILED DESCRIPTION OF THE DRAWINGS

[0013] Embodiments according to the present disclosure provide methods and devices for forming asymmetric threshold voltage vertical transport field effect transistors with intrinsic dual channel epitaxy.

[0011] The lateral asymmetric channel (LAC) doping profile technique provides one of the most effective ways to improve the electrical characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs). For a lateral asymmetric channel (LAC) MOSFET, the doping concentration on the source side in the channel is higher than that on the drain side. When the device operates, due to the non-uniform channel doping, the channel potential change in the source side channel region is much steeper than that in other channel regions. Such a steep potential distribution near the source side enhances the lateral channel electric field and results in high carrier mobility. However, this technique suffers from dopant diffusion and dopant fluctuation in the channel. Moreover, it is difficult to design short channel devices.

[0012] The present embodiment provides a structure and method for fabricating vertical transport FETs with graded threshold voltage using channel engineering to improve device performance by electric field enhancement. In the present embodiment, the mechanism of graded threshold voltage in VTFETs can be realized by a dual channel configuration. For Vt control of nFETs, low Ge content (LGC, Ge≦20%) SiGe is used near the source and Si is used for the main channel, while Vt of pFETs is controlled by LGC·SiGe (Ge≦20%) near the source and high Ge content (HGC, Ge≧40%) SiGe is used as the main channel.

[0013] Generally, vertical transport FET devices (VTFETs) employ doped source and drain regions, and the doped source / drain regions for the VTFET can be formed above the vertical semiconductor fin, and the doped source / drain regions can be formed below the vertical semiconductor fin. Additionally, the vertical source / drain (S / D) contacts for the vertical FET devices can be disposed adjacent to the vertical semiconductor fin as elongated bar contacts. The vertical S / D contacts can be formed to contact the top surface of the underlying S / D region, and can be disposed sufficiently far from the vertical semiconductor fin so that the vertical S / D contacts do not electrically short to the vertical metal gate structure formed above the vertical semiconductor fin.

[0014] In certain embodiments, methods and devices using the techniques are provided for fabricating or constructing vertical transport field effect transistors (VTFETs) with graded threshold voltages that improve device performance through electric field enhancement. The graded threshold voltages of the VTFETs in exemplary embodiments of the invention can be achieved by a dual channel configuration. For Vt control of the nFET, low Ge content (LGC, Ge≦20%) SiGe is used near the source and Si is used for the main channel, while the Vt of the pFET is controlled by LGC·SiGe (Ge≦20%) near the source and high Ge content (HGC, Ge≧40%) SiGe is used as the main channel. The steep potential distribution near the source side enhances the lateral channel electric field and thus improves carrier mobility. In certain embodiments, the asymmetric threshold voltages exist in regions defined at the bottom (i.e., sides closest to the substrate) of the first and second set of fins along the channel of the VTFET.

[0015] Examples of semiconductor materials that can be used to form these structures include silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), carbon-doped silicon (Si:C), carbon-doped silicon-germanium carbide (SiGe:C), III-V compound semiconductors, or II-VI compound semiconductors, or combinations thereof. III-V compound semiconductors are materials that contain at least one element from group III of the periodic table of elements and at least one element from group V of the periodic table of elements. II-VI compound semiconductors are materials that contain at least one element from group II of the periodic table of elements and at least one element from group VI of the periodic table of elements.

[0016] Although the present embodiment will be described using a given architecture, it is understood that other architectures, structures, substrate materials, and process steps / blocks can vary within the scope of the present disclosure. Note that for clarity, certain features may not be shown in every figure. This is not intended to be construed as a limitation of any particular embodiment, or example, or the scope of the claims.

[0017] Referring now to the figures, and initially to FIG. 1, which is a cross-sectional view of a semiconductor structure 100 including a channel epi on a semiconductor substrate at an intermediate stage of a fabrication process, according to certain embodiments. In various exemplary embodiments, the semiconductor structure 100 includes a semiconductor substrate 102. A low Ge content (LGC) layer 104 is formed by epitaxial growth on the substrate 102. As previously mentioned, the LGC material of the LGC layer 104 can have a germanium content of, for example, Ge≦20%. A first material layer 106 and a second material layer 108 are then epitaxially grown on the LGC layer 104.

[0018] The substrate 102 can be crystalline, semi-crystalline, or microcrystalline. The substrate 102 can be essentially (e.g., except for impurities) a single element (e.g., silicon), can be predominantly (e.g., with doping), such as a single element of silicon (Si) or germanium (Ge), or the substrate 102 can include a compound, such as GaAs, SiC, or SiGe. The substrate 102 can also have multiple layers of material. In some embodiments, the substrate 102 includes semiconductor materials, including, but not necessarily limited to, silicon (Si), silicon-germanium (SiGe), Si:C (carbon-doped silicon), carbon-doped silicon-germanium (SiGe:C), III-V (e.g., GaAs, AlGaAs, InAs, InP, etc.), II-VI compound semiconductors (e.g., ZnSe, ZnTe, ZnCdSe, etc.), or other similar semiconductors. Additionally, multiple layers of semiconductor materials can be used as the semiconductor material of the substrate 102. In some embodiments, the substrate 102 includes both semiconductor and dielectric materials.

[0019] In a particular example, the first material layer 106 can be, for example, a Si or carbon-doped silicon (Si:C) material, and the second material layer 108 can be, for example, a high Ge content (HGC) silicon-germanium (SiGe) material. As mentioned above, the HGC material of the second material layer 108 can have a germanium content of, for example, Ge≧40%. In a particular example, the concentrations of carbon (C) and germanium (Ge) are low enough to prevent defects.

[0020] 2, which is a cross-sectional view of the semiconductor structure 100 of FIG. 1 at a next stage in the fabrication process, where a hard mask 110 is formed over the first material layer 106 and the second material layer 108. The material of the hard mask 110 may be any suitable material that allows for subsequent etching and fin formation of the semiconductor structure 100.

[0021] Referring now to FIG. 3, which is a cross-sectional view of the semiconductor structure 100 of FIG. 2 at a next stage in the fabrication process, where, according to one embodiment, a plurality of fins are formed on the semiconductor substrate 102. In various exemplary embodiments, the first material layer 106 and the second material layer 108 are etched to form a plurality of fins (i.e., the first material layer 106 and the high aspect ratio remaining portion of the LGC layer 104 therebelow, and the second material layer 108 and the high aspect ratio remaining portion of the LGC layer 104 therebelow). In a particular embodiment, the SiGe layer has a length in the vertical extension direction (see arrows in FIG. 3) of the first set of fins that is 20-50% of the total channel length of the semiconductor structure in the vertical extension direction. The first set of fins including the first material layer 106 are formed from Si or Si:C, and the second set of fins including the second material layer 108 are formed from the SiGe layer of the HGC (e.g., Ge≧40%). After etching the fins, portions of the hard mask 110 remain over the first and second sets of fins. The first set of fins, including the first material layer 106, allows for the formation of n-type field effect transistors (nFETs) in the nFET region 112, and the second set of fins, including the second material layer 108, allows for the formation of p-type field effect transistors (pFETs) in the pFET region 114.

[0022] In general, the fins (i.e., the fins including the first material layer 106 and the fins including the second material layer 108) can be formed from semiconductor materials including, but not limited to, Si, strained Si, Si:C, SiGe, SiGe:C, Si alloys, Ge, Ge alloys, GaAs, InAs, InP, and other III / V and II / VI compound semiconductors. However, as previously described herein, in certain embodiments, the composition of the second material layer 108 is a SiGe layer of the HGC (e.g., Ge≧40%) versus a low Ge content (e.g., Ge≦20) of the LGC layer 104. The fins can be etched using a dry etching process, such as reactive ion etching, plasma etching, ion etching, or laser ablation. Etching can further include a wet chemical etching process in which one or more etchants are used to remove portions of the layers.

[0023] The hard mask 110 may be fabricated of silicon nitride (SiN), for example, deposited using low pressure chemical vapor deposition (LPCVD). In other exemplary embodiments, the hard mask 110 may include, but is not limited to, hafnium oxide (HfO2), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the hard mask 110 may include multiple layers, for example, silicon nitride over silicon oxide. In some embodiments, the vertical thickness of the hard mask 110 ranges from about 30 nm to about 150 nm. The hard mask 110 may be formed by any suitable patterning technique, including, but not limited to, sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), lithography and subsequent etching, and the like.

[0024] Referring now to Figure 4, which is a cross-sectional view of the semiconductor structure of Figure 3 at a next stage in a fabrication process in which a bottom source / drain region is formed, according to one embodiment. As shown in Figure 4, in various exemplary embodiments, bottom source / drain regions 116, 118 are formed. The source / drain region 116 may be formed in the nFET region 112, and the source / drain region 118 may be formed in the pFET region 114. Additionally, a shallow trench isolation (STI) region 120 may be formed between the nFET region 112 and the pFET region 114. The STI region 120 may separate the source / drain region 116 of the nFET from the source / drain region 118 of the pFET.

[0025] The bottom source / drain regions 116, 118 may be epitaxially grown on the substrate 102. The source / drain regions 116, 118 may be, for example, Si:P for nFETs (nFET region) and SiGe:B for pFETs (pFET region 114). It should be understood that the term "source / drain region" is used herein to mean that a given source / drain region may be either a source region or a drain region depending on the application. In one exemplary embodiment, the source / drain regions 116 are formed between the Si:C fins (i.e., including the first material layer 106) of the nFET region 112, and the source / drain regions 118 are formed between the SiGe fins (i.e., including the second material layer 108) of the HGC of the pFET region 114.

[0026] The terms "epitaxial growth" and "epitaxial deposition" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, where the grown semiconductor material has substantially the same crystalline properties as the semiconductor material on the deposition surface. The term "epitaxial material" refers to a material formed using epitaxial growth. In some embodiments, when the chemistry is controlled and the system parameters are set correctly, the depositing atoms arrive at the deposition surface with enough energy to move around the surface and orient themselves in the crystalline arrangement of the atoms on the deposition surface. Thus, in some embodiments, an epitaxial film deposited on a {100} crystal plane will adopt a {100} orientation.

[0027] Shallow trench isolation (STI) regions 120 are formed in the substrate 102 to electrically isolate regions of adjacent semiconductor devices formed over the substrate 102. The STI regions 120 may include an oxide (STI oxide), and the STI regions 120 may have a corresponding STI step height.

[0028] Referring now to FIG. 5, which is a cross-sectional view of the semiconductor structure of FIG. 4 at a next stage in the fabrication process, according to one embodiment, a bottom spacer is formed over the bottom source / drain regions. As shown in FIG. 5, in various embodiments, a bottom spacer 122 can be formed over the bottom source / drain regions 116, 118 of the nFET region 112 and the pFET region 114. The bottom spacer 122 can include a low-κ dielectric formed according to known processes. The term "low-κ dielectric" generally refers to an insulating material having a dielectric constant less than silicon dioxide, e.g., less than 3.9. Exemplary low-κ materials include, but are not limited to, nitride dielectrics (e.g., SiN, SiBCN), oxynitride dielectrics (e.g., SiOCN, SiCO), or any combination thereof, and the like.

[0029] Reference is now made to FIG. 6, which is a cross-sectional view of the semiconductor structure of FIG. 5 at a next stage in the fabrication process, according to one embodiment, where a high-κ metal gate is formed over the multiple fins. As shown in FIG. 6, in various embodiments, a high-κ metal gate is formed over the multiple fins. A high-κ layer 124 of the high-κ metal gate extends over the first set of fins (i.e., including the first material layer 106) and the second set of fins (i.e., including the second material layer 108). Next, a metal gate 125 of the nFET region is formed over the high-κ layer 124 of the nFET region 112, and then a metal gate 126 of the pFET region is formed over the high-κ layer 124 of the pFET region 114. Thus, the metal gate 125 of the nFET region extends to a defined location 127 above the STI region 120, and the metal gate 126 of the pFET region extends from the location 127 above the STI region 120 to the pFET region 114.

[0030] The high-κ layer 124 may include hafnium oxide (HfO2) deposited to a thickness of about 2 mm. The high-κ layer 124 may be formed using atomic layer deposition (ALD), which typically involves the deposition of successive monolayers over a substrate in a deposition chamber maintained at subatmospheric pressure. It should be further appreciated that "high-κ" generally refers to a dielectric material having a dielectric constant (κ) greater than silicon oxide. Preferably, high-κ materials have a dielectric constant greater than 5, and more preferably greater than about 10. Exemplary high-κ materials include, without limitation, HfO2, ZrO2, Al2O3, TiO2, Ta2O5, lanthanide oxides and mixtures thereof, silicates, and materials such as YSZ (yttria stabilized zirconia), BST, BT, ST, and SBT.

[0031] The metal gate 125 (or nWFM layer) of the nFET region may be selectively grown on the high-κ layer 124 and may include an aluminum (Al) or aluminum / titanium (Al / Ti) multi-layer stack, where the thickness of the Al / Ti may be adjusted for a target composition ratio to achieve a desired work function. Both Al and Ti may be selectively grown. In other exemplary embodiments, the metal gate 125 of the nFET region may be, for example, TiN, TiAlC, TaN, etc. In one embodiment, the metal gate 125 of the nFET region is a multi-layer stack including TiN / TiAlC / TiN.

[0032] The metal gate 126 of the pFET region (or the pWFM layer) may be selectively grown on the high-κ layer 124 and may include TiN. In certain embodiments, the second high-κ metal gate (i.e., the metal gate 126 of the pFET region) may be composed of a different material than the first high-κ metal gate (i.e., the metal gate 125 of the nFET region).

[0033] Thus, the high-κ layer 124 can be formed followed by work function metal (WFM) layers (i.e., metal gate 125 in the nFET region and metal gate 126 in the pFET region) for one polarity device (e.g., nFET or pFET) and another polarity device (e.g., pFET or nFET) on the wafer. It is recognized that nFETs use one type of WFM and pFETs use another type of WFM. In one embodiment, the metal gate 126 in the pFET region can be TiN for pFETs and the metal gate 125 in the nFET region can be Al-doped TiN or TAN or a multi-layer stack including TiN / TiAlC / TiN for nFETs.

[0034] Referring now to Figure 7, which is a cross-sectional view of the semiconductor structure 100 of Figure 6 at a next stage in the fabrication step, according to one embodiment, of recessing the high-κ metal gate to expose the tops of the fins. As shown in Figure 7, in various exemplary embodiments, an organic planarization layer (OPL) 128 is deposited between the first set of fins (i.e., the fins including the first material layer 106 in the nFET region 112) and the second set of fins (i.e., the fins including the second material layer 108 in the pFET region 114). The OPL 128 and the high-κ metal gate (i.e., the high-κ material layer in the nFET region 112 and the metal gate 125 in the nFET region, and the high-κ material layer 124 in the pFET region 114 and the metal gate 126 in the pFET region) are then recessed to expose the tops 106' and 108' of the fins. The recess can extend a distance "HI". Additionally, the recess creates an opening 130 between the exposed top portions 106' and 108' of the fins. The recess exposes a sidewall 132 of the fin top portion 106'. The recess further exposes a sidewall 138 of the fin top portion 108'. Additionally, the hard mask 110 remains over the fins. Thus, a top surface 136 and sidewalls 134 of the hard mask 110 are exposed.

[0035] Referring now to FIG. 8, which is a cross-sectional view of the semiconductor structure 100 of FIG. 7 at a next stage in the manufacturing process, where gate sealing is performed, according to one embodiment. As shown in FIG. 8, in various exemplary embodiments, gate sealing is performed. Gate sealing can include deposition of a first gate sealing layer 140 and a second gate sealing layer 142. The first gate sealing layer 140 can be, for example, a nitride, such as SiN or SiBCN. The second gate sealing layer 142 can be, for example, an oxide, such as SiO2. The first gate sealing layer 140 is deposited over the fins, and the second gate sealing layer 142 is deposited between the fins.

[0036] In a particular embodiment, the second gate encapsulation layer 142 can be planarized. The planarization process can include a chemical mechanical polishing (CMP) followed by an etching process. Thus, the planarization process can be effected by CMP. Other planarization processes can include grinding and polishing.

[0037] Referring now to FIG. 9, which is a cross-sectional view of the semiconductor structure 100 of FIG. 8 at a next stage in the fabrication process, according to one embodiment, in which upper source / drain regions are formed in direct contact with the exposed upper portions of the fins. As shown in FIG. 9, in various embodiments, the first and second gate encapsulation layers 140, 142 are recessed until the upper portions 106', 108' of the fins are exposed, respectively. This removes the hard mask 110, with the remaining portions of the second gate encapsulation layer 142 remaining. The high-κ layer 124 in the nFET region 112 and the metal gate 125 of the nFET region remain intact. Additionally, the high-κ layer 124 in the pFET region 114 and the metal gate 126 of the pFET region also remain intact from the recesses in the first and second gate encapsulation layers 140, 142. The top of the high-κ layer 124 , the metal gate 125 of the nFET region in the nFET region 112 , and the metal gate 126 of the pFET region in the pFET region 114 are protected by the remaining portion of the first gate encapsulation layer 140 .

[0038] Recessing the first and second gate sealing layers 140, 142 can be done by a wet etching process. In one embodiment, a vertical wet etch can be used to define the channel length. Non-limiting examples of wet etching processes that can be used to form the recesses include hydrogen peroxide (H2O2), potassium hydroxide (KOH), ammonium hydroxide (ammonia), tetramethylammonium hydroxide (TMAH), hydrazine, ethylene diamine pyrocatechol (EDP), or any combination thereof.

[0039] Subsequently, upper source / drain regions 144 are formed on the exposed upper portions 106 ′ of the fins in the nFET region 112 , and upper source / drain regions 146 are formed on the exposed upper portions 108 ′ of the fins in the pFET region 114 .

[0040] The source / drain regions 144, 146 may be epitaxially grown. The source / drain regions 144, 146 may be, for example, Si:P for the nFET (in the nFET region 112) and SiGe:B for the pFET (in the pFET region 114). Thus, the upper source / drain region for the Si:C fin in the nFET region 112 is different compared to the upper source / drain region for the SiGe fin in the pFET region 114. It should be understood that the term "source / drain region" as used herein means that a given source / drain region may be either a source region or a drain region depending on the application.

[0041] 10, which is a cross-sectional view of the semiconductor structure 100 of FIG. 9 at a next stage in the fabrication process, where metallization of the upper source / drain regions 144, 146 has been performed, according to one embodiment. As shown in FIG. 10, in various embodiments, the upper spacer 147 is formed. The material of the upper spacer can be formed over the entire structure. The upper spacer 147 can be in direct contact with the lower regions of the upper source / drain regions 144, 146. Examples of the material of the upper spacer 147 include oxides and nitrides (e.g., SiN, SiBCN, SiOCN, etc.). The material of the upper spacer 147 can be a low-κ dielectric material. In one embodiment, the material of the upper spacer 147 can be formed using a technique similar to the formation of the material of the bottom spacer 122. The material of the bottom spacer 122 can be thicker than the material of the upper spacer 147.

[0042] In various exemplary embodiments, metallization of the upper source / drain regions 144, 146 is performed. The metallization includes forming a metal layer 150 (metal fill layer or fill layer). The metal layer 150 contacts and encapsulates or encases the upper source / drain region 144 in the nFET region 112 and the upper source / drain region 146 in the pFET region 114. Additionally, a contact 148 may be formed through the metal layer 150. The contact 148 may be a source, drain, or gate contact. The area 160 may be referred to as a drain and the area 162 may be referred to as a source. A graded threshold voltage may be realized in an area 166 close to the source area 162.

[0043] In one exemplary embodiment, the metal layer 150 can be, for example, a titanium / titanium nitride (Ti / TiN) layer or liner. In other exemplary embodiments, the metal layer 150 can be formed of, for example, Ti, TiN, Ni, etc. The metal layer 150 can be deposited, for example, by an ALD process. The metal layer 150 can be planarized. The planarization process can include chemical mechanical polishing (CMP) followed by an etching process. Thus, the planarization process can be effected by CMP. Other planarization processes can include grinding and polishing.

[0044] As a result, the exemplary embodiment has a graded threshold voltage in the VTFET, which improves device performance due to the electric field enhancement. In the exemplary embodiment, the graded threshold voltage of the VTFET can be achieved by a dual channel configuration. For Vt control of the nFET, low Ge content (LGC, Ge≦20%) SiGe is used near the source and Si is used for the main channel, while the Vt of the pFET is controlled by LGC·SiGe (Ge≦20%) near the source and high Ge content (HGC, Ge≧40%) SiGe as the main channel. The asymmetric threshold voltage profile can be seen in the steep potential distribution near the source side, which enhances the lateral channel electric field and increases the carrier mobility.

[0045] Further, the present embodiment describes a structure with a graded threshold voltage in a vertical transport FET (VTFET) that improves device performance by electric field enhancement, and a method for fabricating the structure. In particular, the present embodiment has a scheme of graded threshold voltage in VTFET that can be realized by a dual channel configuration. For Vt control of nFET, low Ge content (LGC, Ge≦20%) SiGe is used near the source and Si is used for the main channel, while Vt of pFET is controlled by LGC·SiGe (Ge≦20%) near the source and high Ge content (HGC, Ge≧40%) SiGe as the main channel. The structure according to the present embodiment can provide a high Vt of >100mV near the source that may be required for performance enhancement.

[0046] 1-10, deposition is any process that grows, coats, or otherwise transfers material onto a wafer. Available techniques include, but are not limited to, thermal oxidation, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and more recently, atomic layer deposition (ALD), among others. As used herein, "depositing" can include any known or later developed technique appropriate to the material being deposited, including, but not limited to, chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), subatmospheric pressure CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHCVD), limited reaction processing CVD (LRPCVD), metal organic CVD (MOCVD), sputtering deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporative drying.

[0047] The term "processing" as used herein includes depositing material or photoresist, patterning, exposing, developing, etching, cleaning, stripping, implanting, doping, compressing, layering, or removing material or photoresist as necessary to form the described structures, or combinations thereof.

[0048] Removal is any process that removes material from the wafer; examples include etching processes (wet or dry) and chemical mechanical planarization (CMP).

[0049] Patterning is the shaping or modification of deposited material, commonly referred to as lithography. For example, in traditional lithography, a wafer is coated with a chemical called photoresist, then a machine called a stepper focuses, aligns, and moves a mask to expose selected parts of the wafer to short wavelength light, and the exposed areas are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed. Patterning also includes electron beam lithography.

[0050] The adjustment of electrical properties involves doping, for example the doping of the source and drain of the transistor, typically by diffusion or ion implantation or both. These doping processes are followed by furnace annealing or rapid thermal annealing (RTA). The annealing serves to activate the implanted dopants.

[0051] Although the present embodiments are described with given example architectures, it should be understood that other architectures, structures, substrate materials, and process features and steps / blocks can be varied within the scope of the present embodiments.

[0052] Additionally, when an element, such as a layer, region, or substrate, is referred to as being "on" or "above" another element, it should be understood that it can be directly on the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements present. Additionally, when an element is referred to as being "connected" or "coupled" to another element, it should be understood that it can be directly connected or coupled to the other element, or that intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0053] The disclosure may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored on a computer storage medium (e.g., disk, tape, physical hard drive, or virtual hard drive, such as in a storage access network). If the designer does not manufacture the chip or the photolithographic mask used to manufacture the chip, the designer may send the resulting design to those entities directly or indirectly, by physical mechanism (e.g., by providing a copy of a storage medium that stores the design) or electronically (e.g., over the Internet). The stored design, including multiple copies of the chip design to be formed on a wafer, is then converted into a suitable format (e.g., GDSII) for the manufacture of a photolithographic mask. The photolithographic mask is used to define the areas of the wafer that are to be etched or otherwise processed.

[0054] The methods described herein can be used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form, such as bare die, or in packaged form. In the latter case, the chips are mounted in a single chip package (e.g., a plastic carrier with leads that are attached to a motherboard or other higher level carrier) or in a multi-chip package (e.g., a ceramic carrier with either surface interconnects or embedded interconnects, or both). In either case, the chips are then integrated with other chips, separate circuit elements, or other signal processing devices, or a combination of these, to become part of (a) an intermediate product, such as a motherboard, or (b) a final product. The final product can be any product that includes the integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processors.

[0055] It should be understood that material compounds are described by the elements listed, e.g., SiGe. These compounds can include various ratios of the elements in the compound, e.g., SiGe is Si where x is equal to or less than 1. x Ge 1-x and the like. Additionally, other elements may be included in the compound and still function according to the present embodiments. Compounds with additional elements will be referred to herein as alloys. Reference herein to "one embodiment" or "an embodiment" or other variations thereof means that the particular feature, structure, characteristic, etc. described in connection with that embodiment is included in at least one embodiment. Thus, appearances of the phrase "one embodiment" or "an embodiment" or any other variations appearing in various places throughout this specification are not necessarily all referring to the same embodiment.

[0056] For example, it should be recognized that the use of any of the following " / ", "and / or" and "at least one of" in the cases of "A / B", "A and / or B" and "at least one of A and B" is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of both alternatives (A and B). As yet another example, in the cases of "A, B, and / or C" and "A, B, and C", such language is intended to encompass the selection of only the first listed alternative (A), or the selection of only the second listed alternative (B), or the selection of only the third listed alternative (C), or the selection of only the first and second listed alternatives (A and B), or the selection of only the first and third listed alternatives (A and C), or the selection of only the second and third listed alternatives (B and C), or the selection of all three alternatives (A, B, and C). This can be extended to multiple listed items as would be readily apparent to one of ordinary skill in the art.

[0057] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural unless the context clearly indicates otherwise. Furthermore, it is to be understood that the terms "comprises", "comprising", "includes" or "including", or all of them, when used herein, specify the presence of stated features, integers, steps, operations, elements or components or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components or groups thereof or combinations thereof.

[0058] Spatial relationship terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the drawings. It should be understood that the spatial relationship terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, if a device in the drawings is turned over, an element described as "below" or "beneath" the other element or feature would then be oriented "above" the other element or feature. Thus, the term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial relationship descriptors used herein can be interpreted accordingly. Additionally, when a layer is referred to as being between two layers, it should be understood that it may be the only layer between the two layers or there may be one or more intervening layers.

[0059] It should be understood that terms such as first, second, etc. can be used in this specification to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below can be called a second element without departing from the scope of the present concept.

[0060] Having described a preferred embodiment of a method for forming an asymmetric threshold voltage vertical transport field effect transistor (VTFET) with inherent dual channel epitaxy (intended to be illustrative and not limiting), it is noted that modifications and variations can be made by those skilled in the art in view of the above teachings. It is therefore to be understood that changes can be made in the specific embodiments described that are within the scope of the invention as outlined by the appended claims. Thus, having described aspects of the invention with the detail and particularity required by the patent laws, it is desired to claim and protect by Letters Patent, as set forth in the appended claims.

[0061] The description of various embodiments has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements beyond the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A semiconductor structure for triggering an asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET), comprising: a first set of fins comprising a low germanium content layer and a first material layer formed on the low germanium content layer, the low germanium content layer comprising SiGe with a Ge content of at most 20%, and the first material layer comprising silicon (Si) or carbon-doped silicon (Si:C); a second set of fins adjacent to the first set of fins, the second set of fins including the low germanium content layer and a high germanium content layer formed on the low germanium content layer, the high germanium content layer including SiGe having a Ge content of at least 40%; a first high-κ metal gate disposed over the first set of fins; a second high-κ metal gate disposed over the second set of fins; and Equipped with an asymmetric threshold voltage exists along the channel of the VTFET in a region defined at a bottom of the first set of fins and the second set of fins; Semiconductor structure.

2. 2. The semiconductor structure of claim 1 wherein said low germanium content layer has a length in a vertical extension direction of said first set of fins that is 20-50% of a total channel length of said semiconductor structure in said vertical extension direction.

3. 10. The semiconductor structure of claim 1 , wherein said second high-κ metal gate is composed of a different material than said first high-κ metal gate.

4. 10. The semiconductor structure of claim 1, wherein a shallow trench isolation (STI) region separates the bottom source region from the bottom drain region.

5. 5. The semiconductor structure of claim 4 wherein upper source / drain regions are disposed over exposed upper portions of said first set of fins and said second set of fins.

6. 6. The semiconductor structure of claim 5 wherein a metal filling is disposed above said upper source / drain regions.

7. 7. The semiconductor structure of claim 6, wherein a bottom spacer is disposed between said first high-κ metal gate and said bottom source and drain regions.

8. 1. A method of fabricating a semiconductor structure for triggering an asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET), comprising: forming a first set of fins, the first set including a low germanium content layer and a first material layer on the low germanium content layer, the low germanium content layer including SiGe with a Ge content of at most 20%, the first material layer including silicon (Si) or carbon doped silicon (Si:C); forming a second set of fins adjacent to the first set of fins, the second set of fins including the low germanium content layer and a high germanium content layer over the low germanium content layer, the high germanium content layer including SiGe with a Ge content of at least 40%; forming a first high-κ metal gate over the first set of fins; forming a second high-κ metal gate over the second set of fins; Including, an asymmetric threshold voltage exists along the channel of the VTFET in a region defined at a bottom of the first set of fins and the second set of fins; method.

9. 9. The method of claim 8, wherein the low germanium content layer has a length in a vertical extension direction of the first set of fins that is between 20% and 50% of a total channel length of the semiconductor structure in the vertical extension direction.

10. The method of claim 8 , wherein the second high-κ metal gate is composed of a different material than the first high-κ metal gate.

11. 9. The method of claim 8, wherein a shallow trench isolation (STI) region separates the bottom source region from the bottom drain region.

12. 12. The method of claim 11, further comprising forming upper source / drain regions on exposed upper portions of the first set of fins and the second set of fins.

13. The method of claim 12 , further comprising forming a metal filling over the upper source / drain region.

14. 14. The method of claim 13, further comprising forming a bottom spacer between the first high-κ metal gate and the bottom source and drain regions.

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