Manufacturing and modification of hard bars for wafer clamps

Abstract

Systems, apparatus, and methods are provided for manufacturing a wafer clamp having hard burls. The method includes providing a first layer including a first surface. The method can further include forming a plurality of burls on the first surface of the first layer. Forming the plurality of burls can include forming a portion of the plurality of burls to a hardness of greater than about 6.0 gigapascals (GPa).

Description

[Technical field]

[0001] [CROSS REFERENCE TO RELATED APPLICATIONS] This application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 953,730, filed December 26, 2019, which is incorporated by reference in its entirety.

[0002] [Technical field] The present disclosure relates to a substrate table and to a method of forming burls and nanostructures on a substrate table surface. [Background technology]

[0003] A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. Lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In this case, a patterning device (alternatively referred to as a mask or reticle) can be used to generate a circuit pattern to be formed in an individual layer of the IC. This pattern can be transferred onto a target portion (e.g. comprising part of a die, one die or several dies) on the substrate (e.g. a silicon wafer). Transfer of the pattern is via imaging onto a layer of radiation-sensitive material (resist), typically provided on the substrate. In general, a single substrate will contain a network of adjacent target portions, which are successively patterned. Typical lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing the entire pattern onto the target portion at once, and so-called scanners, in which each target portion is irradiated by scanning the pattern through the radiation beam in a given direction (the "scan" direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.

[0004] Extreme ultraviolet (EUV) light, including electromagnetic radiation having wavelengths of about 50 nanometers (nm) or less (often also referred to as soft x-rays), and light having wavelengths of about 13 nm, can be used in lithography apparatus to generate extremely small features in a substrate, e.g., a silicon wafer. Methods of generating EUV light include, but are not necessarily limited to, converting elements having emission lines in the EUV region, such as, for example, xenon (Xe), lithium (Li), tin (Sn), etc., into a plasma state. For example, in one such method, called laser-produced plasma (LPP), plasma can be generated by irradiating a target material (also referred to synonymously as fuel in the context of LPP sources) with an amplified light beam (which can be referred to as a drive laser), for example, in the form of droplets, plates, tapes, streams, or clusters of material. For this process, plasma is typically generated in a closed vessel, e.g., a vacuum chamber, and monitored using various types of metrology instruments.

[0005] Another lithography system is an interference lithography system where there is no patterning device. Rather, an interference lithography system splits a light beam into two beams and, through the use of a reflection system, causes interference of the two beams at a target portion of a substrate. The interference causes a line to be formed at the target portion of the substrate.

[0006] During a lithography process, it may be necessary to sequentially form different layers on a substrate in different processing steps. It may therefore be necessary to position the substrate with high accuracy with respect to previous patterns formed on the substrate. Typically, alignment marks are placed on the substrate to be aligned and positioned with reference to a second object. The lithography apparatus may use an alignment device to detect the position of the alignment marks and align the substrate with the alignment marks to ensure accurate exposure from the mask. The misalignment between the alignment marks on two different layers is measured as an overlay error.

[0007] To monitor the lithography process, parameters of the patterned substrate are measured. The parameters may include, for example, the overlay error between successive layers formed in or on the patterned substrate and the critical linewidth of the developed photosensitive resist. The measurements may be performed on the product substrate, on a dedicated metrology target, or on both. There are various techniques for measuring the microstructures formed in the lithography process, including the use of scanning electron microscopes and various dedicated tools. A fast and non-invasive form of dedicated inspection tool is the scatterometer, in which a beam of radiation is directed at a target on the surface of the substrate and the properties of the scattered or reflected beam are measured. By comparing the properties of the beam before and after it is reflected or scattered by the substrate, the properties of the substrate can be determined. This may be done, for example, by comparing the reflected beam to data stored in a library of known measurements associated with known substrate properties. A spectroscopic scatterometer directs a broadband beam of radiation at the substrate and measures the spectrum (intensity as a function of wavelength) of the radiation scattered into a specific narrow angular range. In contrast, angle-resolved scatterometers use a monochromatic radiation beam and measure the intensity of the scattered radiation as a function of angle.

[0008] Such optical scatterometers can be used to measure parameters such as the critical dimensions of a developed photosensitive resist or the overlay error between two layers formed in or on a patterned substrate. The properties of the substrate can be determined by comparing the properties before and after the illumination beam is reflected or scattered by the substrate.

[0009] It is desirable to define and maintain tribological properties (e.g., friction, hardness, wear) on the surface of the substrate table. In an embodiment, a wafer clamp may be disposed on the surface of the substrate table. The substrate table, or the wafer clamp attached thereto, has surface level tolerances that may be difficult to meet due to the precision requirements of the lithography and metrology processes. A wafer (e.g., a semiconductor substrate) is particularly sensitive to unevenness on the substrate table because it is relatively thin (e.g., less than 1 millimeter (mm) thick) compared to the width of its surface area (e.g., greater than 100 mm wide). In addition, contacting ultra-smooth surfaces may stick to each other, which may be problematic when the substrate must be removed from the substrate table. To reduce the smoothness of the surface that interfaces with the wafer, the surface of the substrate table or the wafer clamp may include glass burrs formed by patterning or etching a glass substrate. However, these glass burrs have a hardness of only about 6.0 gigapascals (GPa) and as a result can crack during operation of the lithography apparatus and be crushed by particles forced into the glass burr by the clamped wafer. Summary of the Invention [Means for solving the problem]

[0010] This disclosure describes various aspects of systems, apparatus, and methods for substrate table and wafer clamping that include hard burls. The hard burls can be burls having a hardness greater than about 6.0 gigapascals (GPa), and in some aspects greater than about 20.0 GPa. These hard burls increase wear resistance and frictional properties, contributing to the latching and releasing of the substrate without cracking during operation of the lithographic apparatus.

[0011] In some embodiments, the present disclosure describes a method of manufacturing a device. The method can include providing a first layer including a first surface. The method can further include forming a plurality of burls on the first surface of the first layer. Forming the plurality of burls can include forming a portion of the plurality of burls to a hardness of greater than about 6.0 GPa.

[0012] In some embodiments, the present disclosure describes another method of manufacturing a device. The method can include receiving a wafer clamp. The wafer clamp can include a first layer including a first surface and a first plurality of burls disposed on the first surface of the first layer. The method can further include removing the first plurality of burls. The method can further include forming a second plurality of burls on the first surface of the first layer. Forming the second plurality of burls can include forming a portion of the second plurality of burls to a hardness of greater than about 6.0 GPa.

[0013] In some embodiments, the present disclosure describes an apparatus. The apparatus can include a first layer including a first surface. The apparatus can include a plurality of burls disposed on the first surface of the first layer, wherein a hardness of a portion of the plurality of burls is greater than about 6.0 GPa.

[0014] Further features, as well as the structure and operation of various embodiments, are described in detail below with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to the particular embodiments described herein. Such embodiments are presented herein for illustrative purposes only. Additional embodiments will be apparent to those skilled in the relevant art based on the teachings contained herein. [Brief description of the drawings]

[0015] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate the present disclosure and, together with the detailed description, further serve to explain the principles of aspects of the present disclosure and to enable those skilled in the relevant art to practice aspects of the present disclosure.

[0016] [Figure 1A] 1 illustrates a schematic diagram of an example of a reflective lithographic apparatus according to some aspects of the present disclosure;

[0017] [Figure 1B] 1 illustrates a schematic diagram of an example of a transmissive lithographic apparatus according to some aspects of the present disclosure;

[0018] [Diagram 2] 1B illustrates a schematic diagram of a more detailed view of the reflective lithographic apparatus shown in FIG. 1A according to some embodiments of the present disclosure;

[0019] [Diagram 3] FIG. 1 illustrates a schematic diagram of an exemplary lithographic cell according to some aspects of the present disclosure.

[0020] [Figure 4] 1 illustrates a schematic diagram of an exemplary substrate stage according to some aspects of the present disclosure.

[0021] [Diagram 5] 1 illustrates a cross-section of a region of an exemplary clamp according to some aspects of the present disclosure.

[0022] [Figure 6] 1 illustrates a cross-section of a region of another exemplary clamp according to some aspects of the present disclosure.

[0023] [Figure 7] 1 illustrates an exemplary method, or portion thereof, for manufacturing a device according to some aspects of the present disclosure.

[0024] [Figure 8] 1 illustrates another exemplary method, or portion thereof, for manufacturing a device according to some aspects of the present disclosure.

[0025] Features and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference numbers identify corresponding elements throughout. In the drawings, like reference numbers often indicate identical, functionally similar, and / or structurally similar elements. Moreover, in most cases, the leftmost digit(s) of a reference number will identify the drawing in which the reference number first appears. Unless otherwise specified, the drawings presented throughout this disclosure should not be construed as drawings to scale. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] This specification discloses one or more embodiments incorporating the features of the present disclosure. The disclosed embodiments are merely exemplary of the present disclosure. The scope of the present disclosure is not limited to the disclosed embodiments. The breadth and scope of the present disclosure are defined by the claims appended hereto and their equivalents.

[0027] References to the described embodiments, and to "one embodiment," "an embodiment," "an exemplary embodiment," and the like herein, are intended to indicate that the described embodiment may include a particular feature, structure, or characteristic, but not all embodiments may include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with one embodiment, it is understood that it is within the knowledge of one of ordinary skill in the art to affect such feature, structure, or characteristic in connection with other embodiments, whether or not explicitly described.

[0028] Spatially relative terms, such as "lower," "below," "lower side," "upper," "above," "upper," and the like, may be used herein for clarity of description to describe the relationship of one element or feature illustrated in the drawings to another element or feature. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted similarly, depending on the context.

[0029] As used herein, the term "about" refers to a value of a given amount that can vary based on the particular technique. Based on the particular technique, the term "about" can refer to a value of a given amount that can vary within a range of, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0030] overview

[0031] Conventional lithographic apparatus using EUV radiation sources typically require that the EUV radiation beam path, or at least a substantial portion thereof, be kept under vacuum during the lithographic process. In such a vacuum region of the lithographic apparatus, an electrostatic clamp can be used to clamp an object, such as a patterning device (e.g., a mask or reticle) or a substrate (e.g., a wafer), to a structure of the lithographic apparatus, such as a patterning device table or a substrate table, respectively. A conventional electrostatic clamp can include an electrode on one surface of the clamp and multiple burls can be disposed on the opposite surface of the clamp. When the clamp is energized (e.g., with a clamping voltage) and the reticle or wafer is pulled into contact with the burls, the tops of the conductive burls can be at a different potential than the backside of the reticle or wafer. At the moment of contact, this potential difference creates a discharge mechanism such that the two potentials become equal. This discharge mechanism can result in material transfer and particle generation, which can ultimately damage the reticle or wafer, the clamp, or a combination thereof. Furthermore, conventional wafer clamps typically include glass burrs formed by patterning and etching the glass substrate, which have a hardness of only about 6.0 GPa and, as a result, can crack during operation of the lithography apparatus and be crushed by particles forced into the glass burrs by the clamped wafer.

[0032] In contrast to these conventional systems, the present disclosure provides a method for fabricating a wafer clamp or electrostatic clamp that includes a hard burl. The hard burl can be fabricated from materials such as diamond-like carbon (DLC), aluminum nitride (AlN), silicon nitride (SiN), or chromium nitride (CrN). The hard burl can have a hardness greater than about 6.0 gigapascals (GPa), and in some embodiments, greater than about 20.0 GPa. Additionally, the present disclosure provides a method for reworking a wafer clamp or electrostatic clamp that has returned from the field with a broken glass burl. The method includes removing the glass burl and creating a layer of hard burl on the surface of the wafer clamp or electrostatic clamp.

[0033] In some aspects, the present disclosure provides a method of manufacturing a clamp, comprising, inter alia, the following three steps:

[0034] 1. First, the dielectric layer (e.g., glass substrate, borosilicate glass substrate, alkaline earth boroaluminosilicate) that the clamp has is thinned to a final thickness of about 100 micrometers (microns). In some embodiments where the clamp is returned from the field, this step can include grinding and polishing the glass burr. In some embodiments where the dielectric layer is thinned to a thickness of less than about 100 microns, this step can include depositing a layer of silicon dioxide (SiO2) (e.g., about 5.0 microns) via a vapor deposition method such as plasma enhanced chemical vapor deposition (PECVD).

[0035] 2. Deposit about 10.0 microns of a hard etchable material such as DLC, Cr, CrN, SiN or AlN, and pattern and etch the deposited layer to form the hard burls. For example, a dielectric layer is thinly coated (flashed) with Cr to form an adhesion layer, DLC is deposited on the Cr adhesion layer for 10.0 microns, the DLC layer is coated with Cr, a burl pattern for the hard burls (e.g., a burl-shaped pattern resist on the Cr) is created, and the Cr is patterned. A dry etch process is then used to pattern the DLC, and a final wet chemical etch is used to pattern the Cr adhesion layer and remove the Cr from the top of the hard burls. Alternatively, an isotropic oxygen etch (e.g., oxygen plasma ashing) is performed, and a Cr etch is performed to form the hard burls. In some embodiments, a similar process may be utilized when the hard burls are formed of CrN, AlN, or other suitable materials.

[0036] 3. Coating the hard burls with CrN and patterning and etching the coated hard burls to create conductive burr tips and, in some cases, to create electrical connections along the surface of the structure between the burr tips.

[0037] The clamps disclosed herein have many advantages and benefits. For example, the present disclosure provides wafer clamps and electrostatic clamps that include hard burls having a hardness of greater than about 6.0 gigapascals (GPa), and in some embodiments, greater than about 20.0 GPa. These hard burls provide increased wear resistance over conventional glass burls and provide frictional properties that contribute to locking and releasing a substrate or patterning device without cracking or breaking during operation of the lithography apparatus. Additionally, the present disclosure supports reworking of clamps with broken burls that are returned from the field. As a result of the techniques described in this disclosure, the associated lithography apparatus can be returned to service faster, cheaper, and more reliably than previous techniques. In some embodiments, the present disclosure supports returning to the field reworked clamps with much harder burls that would not easily break during the lithography process.

[0038] Before describing such aspects in greater detail, however, it is helpful to illustrate an exemplary environment in which aspects of the present disclosure can be implemented.

[0039] Exemplary Lithography System

[0040] 1A and 1B diagrammatically illustrate a lithographic apparatus 100 and a lithographic apparatus 100', respectively, in which aspects of the present disclosure can be implemented. Each of the lithographic apparatuses 100 and 100' includes an illumination system (illuminator) IL configured to condition a radiation beam B (e.g., deep ultraviolet (DUV) radiation or extreme ultraviolet (EUV) radiation); a support structure (e.g., a mask table) MT configured to support a patterning device (e.g., a mask, reticle or dynamic patterning device) MA and connected to a first positioning device PM configured to accurately position the patterning device MA; and a substrate holder, such as a substrate table (e.g., a wafer table) WT configured to hold a substrate (e.g., a resist-coated wafer) W and connected to a second positioning device PW configured to accurately position the substrate W. Lithographic apparatus 100 and 100' also comprise a projection system PS that is configured to project a pattern imparted to the radiation beam B by the patterning device MA onto a target portion C (e.g. comprising one or more dies) of the substrate W. In lithographic apparatus 100, the patterning device MA and the projection system PS are reflective. In lithographic apparatus 100', the patterning device MA and the projection system PS are transmissive.

[0041] The illumination system IL may include various types of optical elements, such as refractive, reflective, catadioptric, magnetic, electromagnetic, electrostatic or other types of optical elements, or any combination thereof, to direct, shape or control radiation.

[0042] The support structure MT holds the patterning device MA in a manner that depends on the orientation of the patterning device MA relative to a reference frame, the design of at least one of the lithographic apparatuses 100 and 100', and other conditions, such as for example whether the patterning device MA is held in a vacuum environment or not. The support structure MT can use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device MA. The support structure MT can be a frame or a table, for example which can be fixed or movable as required. By using sensors the support structure MT can ensure that the patterning device MA is at a desired position, for example with respect to the projection system PS.

[0043] The term "patterning device MA" should be interpreted broadly as referring to any device that can be used to impart a radiation beam B with a pattern in its cross-section, such as to create a pattern in a target portion C of a substrate W. The pattern imparted to the radiation beam B may correspond to a particular functional layer in a device being created in the target portion C to form an integrated circuit.

[0044] Patterning device MA can be transmissive (like lithographic apparatus 100' in FIG. 1B) or reflective (like lithographic apparatus 100 in FIG. 1A). Examples of patterning devices MA include masks, programmable mirror arrays, and programmable LCD panels. Masks include mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types. An example of a programmable mirror array employs a matrix of small mirrors, each of which can be individually tilted so as to reflect an incoming radiation beam in different directions. The tilted mirrors impart a pattern to a radiation beam B, which is reflected by the matrix of small mirrors.

[0045] The term "projection system PS" can encompass any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination of these, as appropriate for the exposure radiation used or other factors such as the use of an immersion liquid on the substrate W or the use of a vacuum. For EUV or electron beam radiation, a vacuum environment can be used as other gases would absorb too much radiation or electrons. Therefore, with the aid of a vacuum wall and vacuum pumps, a vacuum environment can be provided throughout the beam path.

[0046] Lithographic apparatus 100 and / or lithographic apparatus 100' may be of a type having two (dual stage) or more substrate tables WT (and / or two or more mask tables). In such a "multi-stage" machine, the additional substrate tables WT may be used in parallel, or preparatory steps may be performed on one or more tables while one or more other substrate tables WT may be used for exposure. In some circumstances the additional tables may not be substrate tables WT.

[0047] The lithographic apparatus may also be of a type in which at least a part of the substrate may be covered by a liquid having a relatively high refractive index, e.g. water, so as to fill a space between the projection system and the substrate. Immersion liquids may also be applied to other spaces in the lithographic apparatus, for example between the mask and the projection system. Immersion techniques result in an increase in the numerical aperture of the projection system. The term "immersion" as used herein does not imply that a structure such as the substrate must be submerged in liquid, but rather only that a liquid is located between the projection system and the substrate during exposure.

[0048] 1A and 1B, the illumination system IL receives the radiation beam B from the radiation source SO. The radiation source SO and the lithographic apparatus 100, 100' may be separate physical entities, for example if the radiation source SO is an excimer laser. In such a case, the radiation source SO is not considered to form part of the lithographic apparatus 100 or 100', and the radiation beam B passes from the radiation source SO to the illumination system IL with the aid of a beam delivery system BD (see FIG. 1B), for example including suitable directing mirrors and / or beam expanders. In other cases, the radiation source SO may be an integral part of the lithographic apparatus 100, 100', for example if the radiation source SO is a mercury lamp. The radiation source SO and the illuminator IL, together with the beam delivery system BD if necessary, may be referred to as a radiation system.

[0049] The illumination system IL may include an adjuster AD (see FIG. 1B) for adjusting the angular intensity distribution of the radiation beam. Typically, at least the outer and / or inner radial extent (commonly referred to as σ-outer and σ-inner, respectively) of the intensity distribution in a pupil plane of the illuminator may be adjusted. In addition, the illumination system IL may include various other components (see FIG. 1B), such as an integrator IN and a radiation collector (e.g. condenser) CO. The illumination system IL may be used to adjust the radiation beam B having a desired uniformity and intensity distribution in its cross-section.

[0050] Referring to FIG. 1A, a radiation beam B is incident on a patterning device (e.g., mask) MA, which is held on a support structure (e.g., mask table) MT, and is patterned by the patterning device MA. In the lithographic apparatus 100, the radiation beam B is reflected from the patterning device MA. After being reflected from the patterning device MA, the radiation beam B passes through a projection system PS, which focuses the radiation beam B onto a target portion C of a substrate W. With the aid of a second positioner PW and a position sensor IF2 (e.g., an interferometer device, a linear encoder, or a capacitive sensor), the substrate table WT can be moved precisely (e.g., so that different target portions C are positioned in the path of the radiation beam B). Similarly, the patterning device MA can be accurately positioned with respect to the path of the radiation beam B using the first positioner PM and another position sensor IF1. The patterning device MA and substrate W can be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2.

[0051] Referring to Figure 1B, a beam of radiation B is incident on a patterning device MA held on a support structure MT and is patterned by the patterning device MA. Having traversed the patterning device MA, the beam of radiation B passes through a projection system PS which focuses the beam onto a target portion C of a substrate W. The projection system has a pupil conjugate PPU to an illumination system pupil IPU. Each portion of radiation emanates from an intensity distribution at the illumination system pupil IPU, traverses the mask pattern without being affected by diffraction at the mask pattern and creates an image of the intensity distribution at the illumination system pupil IPU.

[0052] The projection system PS projects an image MP' of the mask pattern MP onto a resist layer coated on the substrate W. Here, the image MP' is formed by diffracted beams resulting from the mask pattern MP by radiation from the intensity distribution. For example, the mask pattern MP may include an array of lines and spaces. Diffraction of radiation at the array, which is different from the zeroth order diffraction, generates diffracted beams that are deflected with a change of direction in a direction perpendicular to the lines. Non-diffracted beams (for example so-called zeroth order diffracted beams) traverse the pattern without a change of propagation direction. The zeroth order diffracted beams traverse an upper lens or an upper lens group of the projection system PS, which is upstream of the pupil conjugate PPU of the projection system PS, to reach the pupil conjugate PPU. The part of the intensity distribution in the plane of the pupil conjugate PPU, which is related to the zeroth order diffracted beam, is an image of the intensity distribution in the illumination system pupil IPU of the illumination system IL. The aperture device PD is for example arranged in or approximately in a plane that includes the pupil conjugate PPU of the projection system PS.

[0053] The projection system PS is configured to capture not only the zeroth order diffracted beam but also the first order diffracted beam or the first and higher order diffracted beams (not shown) by a lens or lens group L. In some embodiments, dipole illumination for imaging a line pattern extending in a direction perpendicular to the line can be used to exploit the resolution enhancement effect of dipole illumination. For example, a first order diffracted beam can interfere with a corresponding zeroth order diffracted beam at the level of the substrate W to form an image of the mask pattern MP with the highest possible resolution and process window (e.g., usable depth of focus combined with an acceptable exposure dose deviation). In some embodiments, astigmatism can be reduced by providing a radiation pole (not shown) in the opposite quadrant of the illumination system pupil IPU. Furthermore, in some embodiments, astigmatism can be reduced by blocking the zeroth order beam of the projection system pupil conjugate PPU associated with the radiation pole in the opposite quadrant. This is described in more detail in U.S. Pat. No. 7,511,799, issued Mar. 31, 2009, which is incorporated herein by reference in its entirety.

[0054] With the aid of the second positioner PW and a position sensor IF (e.g. an interferometer device, a linear encoder or a capacitive sensor), the substrate table WT can be moved precisely (e.g. so that a different target portion C is placed in the path of the radiation beam B). Similarly, the first positioner PM and another position sensor (not shown in FIG. 1B) can be used to precisely position the patterning device MA with respect to the path of the radiation beam B (e.g. after machine retrieval from a mask library or during a scan).

[0055] In general, movement of the support structure MT can be realized with the aid of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of the first positioner PM. Similarly, movement of the substrate table WT can be realized by means of a long-stroke module and a short-stroke module, which form part of the second positioner PW. In the case of a stepper (as opposed to a scanner), the support structure MT can be connected to a short-stroke actuator only, or can be fixed. The patterning device MA and the substrate W can be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2. The substrate alignment marks occupy dedicated target portions (as shown) but may also be located in spaces between the target portions (e.g. scribe-line alignment marks). Similarly, in situations in which more than one die is provided on the patterning device MA, the mask alignment marks may be located between the dies.

[0056] The support structure MT and patterning device MA can be within a vacuum chamber V, and an in-vacuum robot IVR can be used to move a patterning device, such as a mask, in and out of the vacuum chamber. Alternatively, if the support structure MT and patterning device MA are outside the vacuum chamber, an ex-vacuum robot can be used for various transfer operations, similar to the in-vacuum robot IVR. In some cases, both the in-vacuum robot and the ex-vacuum robot need to be calibrated to smoothly transfer any payload (e.g., a mask) to the fixed kinematic mount of the transfer station.

[0057] The depicted apparatus can be used in at least one of the following modes:

[0058] 1. In step mode, while the support structure MT and substrate table WT are kept substantially stationary, the entire pattern imparted to the radiation beam B is projected onto the target portion C in one go (e.g. a single static exposure). The substrate table WT is subsequently shifted in the X and / or Y direction so that a different target portion C can be exposed.

[0059] 2. In scan mode, the support structure MT and the substrate table WT are scanned synchronously while a pattern imparted to the radiation beam B is projected onto a target portion C (i.e. a single dynamic exposure). The velocity and direction of the substrate table WT relative to the support structure (e.g. mask table) MT can be determined by the (de-)magnification and image reversal characteristics of the projection system PS.

[0060] 3. In another mode, the support structure MT holds the programmable patterning device and keeps it substantially stationary, while the substrate table WT is moved or scanned while a pattern imparted to the radiation beam B is projected onto a target portion C. A pulsed radiation source SO may be employed, with the programmable patterning device being updated as required after each movement of the substrate table WT or between successive pulses of radiation during a scan. This mode of operation is readily adaptable to maskless lithography employing a programmable patterning device MA, such as a programmable mirror array.

[0061] Combinations and variations on the described modes of use or entirely different modes of use may also be employed.

[0062] In another embodiment, the lithographic apparatus 100 includes an EUV source configured to generate an EUV radiation beam for EUV lithography. Typically, the EUV source is configured in a radiation system and a corresponding illumination system is configured to condition the EUV radiation beam of the EUV source.

[0063] FIG. 2 shows the lithographic apparatus 100 in more detail, including a radiation source (e.g., a source collector apparatus) SO, an illumination system IL, and a projection system PS. The radiation source SO is constructed and arranged to maintain a vacuum environment in an enclosure structure 220. The radiation source SO includes a source chamber 211 and a collector chamber 212, and is arranged to generate and transmit EUV radiation. The EUV radiation can be generated by a gas or vapor, such as xenon (Xe) gas, lithium (Li) vapor, or tin (Sn) vapor, in which an EUV radiation-emitting plasma 210 is generated that emits radiation in the EUV range of the electromagnetic spectrum. The at least partially ionized EUV radiation-emitting plasma 210 can be generated by, for example, an electric discharge or a laser beam. A partial pressure of, for example, 10 Pascals (Pa) of Xe gas, Li vapor, Sn vapor, or any other suitable gas or vapor can be used for efficient generation of radiation. In some embodiments, an excited tin plasma is provided to generate EUV radiation.

[0064] Radiation emitted by the EUV radiation emitting plasma 210 passes from the source chamber 211 towards the collector chamber 212 through an optional gas barrier or contaminant trap 230 (sometimes also referred to as a contaminant barrier or foil trap) located in or behind an opening in the source chamber 211. The contaminant trap 230 may include a channel structure. The contaminant trap 230 may also include a gas barrier or a combination of a gas barrier and a channel structure. The contaminant trap 230 as further described herein includes at least a channel structure.

[0065] The collector chamber 212 may include a radiation collector (e.g. collector optic) CO, which may be a so-called grazing incidence collector. The radiation collector CO has an upstream radiation collector side 251 and a downstream radiation collector side 252. Radiation traversing the radiation collector CO may be reflected off a grating spectral filter 240 and focused at a virtual source point IF. The virtual source point IF is commonly referred to as an intermediate focus, and the source collector arrangement is configured such that the virtual source point IF is located at or near an opening 219 in the enclosing structure 220. The virtual source point IF is an image of the EUV radiation emitting plasma 210. The grating spectral filter 240 is used to specifically suppress infrared (IR) radiation.

[0066] The radiation then traverses the illumination system IL, which may include a faceted field mirror device 222 and a faceted pupil mirror device 224, which are configured to provide a desired angular distribution of the radiation beam 221 at the patterning device MA, as well as a desired uniformity of the radiation intensity at the patterning device MA. Reflection of the radiation beam 221 off the patterning device MA, held by the support structure MT, forms a patterned beam 226 which is imaged by the projection system PS via reflective elements 228, 229 onto the substrate W, held by a wafer stage or substrate table WT.

[0067] In general, more elements than shown may be present in the illumination system IL and the projection system PS. Optionally, depending on the type of lithographic apparatus, a grating spectral filter 240 may be present. Additionally, more mirrors may be present than shown in Figure 2. For example, there may be 1-6 additional reflective elements in the projection system PS than shown in Figure 2.

[0068] Radiation collector CO is depicted as a nested collector with grazing incidence reflectors 253, 254, 255 as an example of a collector (or collector mirror), as shown in Figure 2. The grazing incidence reflectors 253, 254, 255 are arranged axisymmetrically about the optical axis O, and this type of radiation collector CO is preferably used in combination with a discharge produced plasma (DPP) source.

[0069] Exemplary Lithography Cell

[0070] FIG. 3 shows a lithography cell 300, also called a lithocell or cluster. The lithography apparatus 100 or 100′ may form part of the lithography cell 300. The lithography cell 300 may also include one or more apparatuses for performing pre-exposure and post-exposure processes on a substrate. For example, these apparatuses may include a spin coater SC for depositing a resist layer, a developer DE for developing the exposed resist, a chill plate CH, and a bake plate BK. A substrate handler (e.g. a robot) RO picks up substrates from input / output ports I / O1, I / O2, moves them between the different process apparatuses, and delivers them to a loading bay LB of the lithography apparatus 100 or 100′. These apparatuses are often collectively referred to as a track and are under the control of a track control unit TCU, which is itself controlled by a higher level control system SCS. The SCS also controls the lithography apparatuses via a lithography control unit LACU. In this way, the different apparatuses can be operated to maximize throughput or process efficiency.

[0071] Exemplary Substrate Stage

[0072] FIG. 4 illustrates a schematic diagram of an exemplary substrate stage 400 according to some embodiments of the present disclosure. In some embodiments, the exemplary substrate stage 400 may include a substrate table 402, a support block 404, one or more sensor structures 406, any other suitable components, or any combination thereof. In some embodiments, the substrate table 402 includes a clamp (e.g., a wafer clamp, a reticle clamp, an electrostatic clamp) for holding a substrate 408. In some embodiments, each of the one or more sensor structures 406 includes a transmission image sensor (TIS) plate. The TIS plate is a sensor unit that includes one or more sensors and / or markers for use in a TIS sensing system, and is used for accurate positioning of a wafer relative to the position of a projection system (e.g., the projection system PS described with reference to FIGS. 1A, 1B, and 2) and a mask (e.g., the patterning device described with reference to FIGS. 1A, 1B, and 2) of a lithographic apparatus (e.g., the lithographic apparatus 100 and the lithographic apparatus 100′ described with reference to FIGS. 1A, 1B, and 2). Here, a TIS plate is illustrated for purposes of explanation, and the embodiments herein are not limited to any particular sensor. The substrate table 402 is disposed on a support block 404. One or more sensor structures 406 are disposed on the support block 404.

[0073] In some embodiments, the substrate 408 can be disposed on the substrate table 402 as the exemplary substrate table stage 400 supports the substrate 408 .

[0074] Terms such as "flat," "planarity," and the like may be used herein to describe structures associated with a major plane of a surface. For example, curved or non-horizontal surfaces may not conform to a flat surface. Protrusions and depressions on a surface may also be characterized as deviations from a "flat" plane.

[0075] Terms such as "smooth" and "roughness" can be used to refer to local variations, microscopic deviations, graininess, or texture of a surface. For example, the term "surface roughness" can refer to the microscopic deviation of a surface profile from a mean line or plane. The deviation is commonly measured (in units of length) as an amplitude parameter such as the root mean square (RMS) or arithmetic mean deviation (Ra) (e.g., 1 nm RMS).

[0076] In some embodiments, the surface of the substrate table (e.g., substrate table WT in FIG. 1A and FIG. 1B, substrate table 402 in FIG. 4) can be flat or burled. If the surface of the substrate table is flat, any particles or contaminants that are deposited between the substrate table and the wafer will pass through the wafer and cause contaminant printing, resulting in lithography errors in its vicinity. As a result, the contaminants reduce device yields and increase manufacturing costs.

[0077] The placement of burls on the substrate table helps to reduce the undesirable effects of a flat substrate table. When a wafer is clamped to a burled substrate table, the free space is available where the wafer is not in contact with the substrate table. This free space acts as a pocket for contaminants, thus preventing print errors. Another advantage is that contaminants located on the burls are more likely to be crushed due to the increased load caused by the burls. Crushing the contaminants also helps to reduce print-through errors. In some embodiments, the total surface area of ​​the burls can be approximately 1 to 5 percent of the surface area of ​​the substrate table. Here, the surface area of ​​the burls refers to the surface that contacts the wafer (e.g., not including the side walls), and the surface area of ​​the substrate table refers to the full span of the surface of the substrate table where the burls are present (e.g., not including the sides or back of the substrate table). When a wafer is clamped to a burled substrate table, the load increases by 100 times compared to a flat substrate table, which is sufficient to crush most contaminants. Although a substrate table is used as an example here, this example is not intended to be limiting. For example, aspects of the present disclosure may be implemented in reticle tables, various clamping structures (eg, electrostatic clamps, clamping membranes), and various lithography systems (eg, EUV, DUV).

[0078] In some embodiments, the burl-wafer interface governs the functional performance of the substrate table. If the surface of the substrate table is smooth, adhesion forces can occur between the smooth surface of the substrate table and the smooth surface of the wafer. This phenomenon of two smooth surfaces coming into contact and sticking together is known as ringing. Ringing can cause problems in device manufacturing (e.g. overlay problems) due to high friction and in-plane stresses in the wafer (optimally the wafer slides easily during alignment).

[0079] Furthermore, it has been observed that the burled surface of the substrate table is prone to wear abnormally fast, especially at the edges away from the center of the substrate table (e.g., uneven wear). Uneven wear can cause bending of the wafer when clamped to the substrate table, resulting in poorer lithographic placement of device features and overlay drift over time. And global wear can re-occur ringing problems, leading to poorer imaging performance due to changes in the global shape of the clamping surface.

[0080] In order to increase the hardness of the burr top surface and prevent frictional wear of the surface, the present disclosure provides a hard burr. As referred to herein, the term "hard" can refer to a hardness of greater than about 6.0 GPa, and in some embodiments, greater than about 20.0 GPa. The term "hard burr" can refer to a burr having a hardness of greater than about 6.0 GPa, and in some embodiments, greater than about 20.0 GPa. For example, the hard burr can be a material selected from the group consisting of DLC, AlN, SiN, CrN, or any other suitable material or combination thereof.

[0081] Exemplary hard burled surfaces

[0082] 5 illustrates a cross-section of a region of an exemplary clamp 500 (e.g., a wafer clamp, a reticle clamp, an electrostatic clamp). The exemplary clamp 500 can include a first layer 502 (e.g., a glass substrate, a borosilicate glass substrate, an alkaline earth boroaluminosilicate substrate, a SiO2 layer) including a first surface 502a.

[0083] The exemplary clamp 500 may further include a second layer 504 (e.g., an adhesion layer such as a layer of Cr, Al, Si, or any suitable material) including a second surface 504a and a third surface 504b opposite the second surface 504a. The third surface 504b of the second layer 504 may be disposed on the first surface 502a of the first layer 502. In some embodiments, the second layer 504 may be patterned in a final or near-final step.

[0084] The exemplary clamp 500 may further include a plurality of burls 506 (e.g., DLC burls) disposed on the first surface 502a of the first layer 502. For example, the plurality of burls 506 may be disposed on the second surface 504a of the second layer 504. A hardness of a portion (subset) of the plurality of burls 506 may be greater than about 6.0 GPa, and in some embodiments, greater than about 10.0 GPa, about 15.0 GPa, or about 20.0 GPa. A thickness of the plurality of burls 506 may be greater than about 2.0 microns, and in some embodiments, greater than about 5.0 microns, about 7.5 microns, or about 10.0 microns. A radius of each of the plurality of burls 506 may be about 200.0 microns. In some embodiments, the plurality of burls 506 may include at least about 30,000 burls. In some embodiments, the plurality of burls 506 can be formed by patterning and etching a third layer (eg, a DLC layer) to form the plurality of burls 506.

[0085] The exemplary clamp 500 may further include a plurality of burl tops 507 (e.g., CrN burl tops) disposed on the plurality of burls 506. The plurality of burl tops 507 may be formed by patterning and etching a fourth layer (e.g., a CrN layer) to form the plurality of burl tops 507. In some embodiments, the plurality of burls 506, the plurality of burl tops 507, or both may be electrically conductive.

[0086] Each burl of the plurality of burls 506 can include a fourth surface 506a and a fifth surface 506b opposite the fourth surface 506a. The fifth surface 506b of the burl can be disposed on the second surface 504a of the second layer 504. Each burl apex of the plurality of burls 507 can include a sixth surface 507a and a seventh surface 507b opposite the sixth surface 507a. The seventh surface 507b of the burl apex can be disposed on the fourth surface 506a of the burl.

[0087] Optionally, an object 508 (e.g., a wafer W or a patterning device MA) can be positioned on the plurality of burl apexes 507. For example, an eighth surface 508a of the object 508 can be movably disposed (e.g., placed, positioned) on one or more sixth surfaces 507a of the plurality of burl apexes 507.

[0088] 6 illustrates a cross-section of a region of an exemplary clamp 600 (e.g., a wafer clamp, a reticle clamp, an electrostatic clamp). The exemplary clamp 600 can include a first layer 602 (e.g., a glass substrate, a borosilicate glass substrate, an alkaline earth borosilicate substrate, a SiO2 layer) that includes a first surface 602a.

[0089] The exemplary clamp 600 can further include a plurality of burls 606 (e.g., CrN, AlN, or SiN burls) disposed on the first surface 602a of the first layer 602. For example, the plurality of burls 606 can be disposed on the first surface 602a of the first layer 602. A hardness of a portion (subset) of the plurality of burls 606 can be greater than about 6.0 GPa, and in some embodiments, greater than about 10.0 GPa, about 15.0 GPa, or about 20.0 GPa. A thickness of the plurality of burls 606 can be greater than about 2.0 microns, and in some embodiments, greater than about 5.0 microns, about 7.5 microns, or about 10.0 microns. In some embodiments, the plurality of burls 606 can include at least about 30,000 burls. In some embodiments, the plurality of burls 606 can be formed by patterning and etching a second layer (e.g., a CrN, AlN, or SiN layer) to form the plurality of burls 606.

[0090] Each burl of the plurality of burls 606 may include a second surface 606a and a third surface 606b opposite the second surface 606a. The third surface 606b of the burl may be disposed on the first surface 602a of the first layer 602.

[0091] Optionally, an object 608 (e.g., a wafer W or a patterning device MA) can be positioned on the plurality of burls 606. For example, a fourth surface 608a of the object 608 can be movably disposed (e.g., placed, positioned) on one or more second surfaces 606a of the plurality of burls 606.

[0092] Exemplary Process for Producing a Surface with Hard Burls

[0093] 7 is an example method 700 or portion thereof for manufacturing a device according to some embodiments of the present disclosure. The steps described with reference to the example method 700 can be performed by any system, device, component, technique, or combination thereof described herein, such as those described with reference to FIGS. 1-6 above and FIG. 8 below.

[0094] At step 702, the method can include providing a first layer including a first surface. In some embodiments, providing the first layer can include providing a glass substrate, a borosilicate glass substrate, an alkaline earth boroaluminosilicate substrate, a SiO layer (e.g., deposited via PECVD or any other suitable technique), or any other suitable layer.

[0095] At step 704, the method may further include forming a plurality of burls on the first surface of the first layer. Forming the plurality of burls may include forming a subset of the plurality of burls to a hardness of greater than about 6.0 GPa. In some embodiments, forming the plurality of burls may include forming the plurality of burls of DLC. In some embodiments, forming the plurality of burls may include forming the plurality of burls to a thickness of greater than about 2.0 micrometers, greater than about 5.0 micrometers, or greater than about 10.0 micrometers. In some embodiments, forming the plurality of burls may include forming the plurality of burls of a material selected from the group consisting of AlN, SiN, or CrN. In some embodiments, forming the plurality of burls may include forming at least about 30,000 burls. In some embodiments, forming the portion of the plurality of burls may include forming the portion of the plurality of burls to a hardness of greater than about 10.0 GPa, greater than about 15.0 GPa, or greater than about 20.0 GPa.

[0096] In some embodiments, forming the plurality of burls comprises forming a second layer having a second surface and a third surface opposite the second surface, the third surface of the second layer being disposed on the first surface of the first layer; forming a third layer having a fourth surface and a fifth surface opposite the fourth surface, the fifth surface of the third layer being disposed on the second surface of the second layer; and forming the plurality of burls comprises patterning the third layer to form the plurality of burls. In some embodiments, forming the second layer can include forming an adhesion layer. In some embodiments, forming the adhesion layer can include forming the adhesion layer with at least one material selected from the group consisting of Cr or Al. In some embodiments, forming the third layer can include forming the third layer with DLC. Optionally, in some embodiments, the method can further include curing the first layer and the plurality of burls at a temperature greater than about 350°C.

[0097] 8 is an example method 800 or portion thereof for manufacturing a device according to some embodiments of the present disclosure. The steps described with reference to the example method 800 can be performed by any system, device, component, technique, or combination thereof described herein, such as those described with reference to FIGS. 1-7 above.

[0098] At step 802, the method may include receiving a wafer clamp, for example, the wafer clamp having a broken glass burl returned from a site. The wafer clamp may include a first layer including a first surface and a first plurality of burls disposed on the first surface of the first layer. The first layer may include a glass substrate, a borosilicate glass substrate, an alkaline earth boroaluminosilicate substrate, a SiO2 layer (e.g., deposited via PECVD or any other suitable technique), or any other suitable layer. The first plurality of burls may include a plurality of glass burls, some of which may be cracked or broken. In some embodiments, the first plurality of burls may have a hardness of about 6.0 GPa or less.

[0099] At step 804, the method may include removing the first plurality of burls. Removing the first plurality of burls may include grinding the first plurality of burls and grinding any intermediate layers between the first plurality of burls and the first layer. In some embodiments, removing the first plurality of burls may further include grinding a portion of the first layer to form a modified first surface of the first layer. Removing the first plurality of burls may further include polishing the first surface of the first layer (or, in some embodiments, the modified first surface of the first layer formed as a result of grinding the portion of the first layer). In some embodiments, after removing the first plurality of burls, the method may include performing a final polish to ensure that defects have been suitably removed from the surface of the first layer. Thereafter, the method may include depositing a thickness of SiO2 or another dielectric material (e.g., via a process such as PECVD) to return to the original thickness of the first layer (the borosilicate plate).

[0100] At step 806, the method may further include forming a second plurality of burls on the first surface of the first layer (or, in some embodiments, the modified first surface of the first layer). Forming the second plurality of burls may include forming a portion (subset) of the second plurality of burls to a hardness of greater than about 6.0 GPa. In some embodiments, forming the second plurality of burls includes forming the second plurality of burls from a material selected from the group consisting of DLC, AlN, SiN, or CrN. In some embodiments, forming the second plurality of burls includes forming the second plurality of burls to a thickness of greater than about 2.0 micrometers, greater than about 5.0 micrometers, or greater than about 10.0 micrometers. In some embodiments, forming the second plurality of burls includes forming at least about 30,000 burls. In some embodiments, forming the portion of the second plurality of burls includes forming the portion of the second plurality of burls to a hardness of greater than about 10.0 GPa, greater than about 15.0 GPa, or greater than about 20.0 GPa.

[0101] Other aspects of the invention are defined in the following numbered paragraphs: (Item 1) A method for manufacturing a device, comprising: providing a first layer having a first surface; forming a plurality of burls on the first surface of the first layer; The method, wherein forming the plurality of burls comprises forming a portion of the plurality of burls to a hardness of greater than about 6.0 gigapascals (GPa). (Item 2) The method of item 1, wherein providing the first layer comprises providing a glass substrate. (Item 3) The method of item 1, wherein forming the plurality of burls comprises forming the plurality of burls from diamond-like carbon (DLC). 4. The method of claim 3, wherein forming the plurality of burls comprises forming the plurality of burls to a thickness of greater than about 2.0 micrometers. Item 5. The method of item 3, wherein forming the plurality of burls comprises forming the plurality of burls to a thickness greater than about 5.0 micrometers. Item 6. The method of item 3, wherein forming the plurality of burls comprises forming the plurality of burls to a thickness greater than about 10.0 micrometers. (Item 7) The method of item 1, wherein forming the plurality of burls comprises forming the plurality of burls from a material selected from the group consisting of aluminum nitride (AlN), silicon nitride (SiN), or chromium nitride (CrN). (Item 8) The method of item 1, wherein forming the plurality of burls comprises forming at least about 30,000 burls. (Item 9) The method of item 1, wherein forming the portion of the plurality of burls comprises forming the portion of the plurality of burls to a hardness of greater than about 10.0 gigapascals (GPa). (Item 10) The method of item 1, wherein forming the portion of the plurality of burls comprises forming the portion of the plurality of burls to a hardness of greater than about 15.0 gigapascals (GPa). (Item 11) The method of item 1, wherein forming the portion of the plurality of burls comprises forming the portion of the plurality of burls to a hardness of greater than about 20.0 gigapascals (GPa). (Item 12) Forming the plurality of burls forming a second layer having a second surface and a third surface opposite the second surface, the third surface of the second layer being disposed on the first surface of the first layer; forming a third layer having a fourth surface and a fifth surface opposite the fourth surface, the fifth surface of the third layer being disposed on the second surface of the second layer; Item 14. The method of item 1, wherein forming the plurality of burls comprises patterning the third layer to form the plurality of burls. Item 13. The method of item 12, wherein forming the second layer comprises forming an adhesive layer. (Item 14) The method of item 13, wherein forming the adhesion layer comprises forming the adhesion layer from at least one material selected from the group consisting of chromium (Cr) or aluminum (Al). Item 15. The method of item 12, wherein forming the third layer comprises forming the third layer of diamond-like carbon (DLC). (Item 16) A method for manufacturing a device, comprising: receiving a wafer clamp comprising a first layer having a first surface and a first plurality of burls disposed on the first surface of the first layer; removing the first plurality of burls; forming a second plurality of burls on the first surface of the first layer; The method, wherein forming the second plurality of burls comprises forming a portion of the second plurality of burls to a hardness of greater than about 6.0 gigapascals (GPa). (Item 17) The method of item 16, wherein forming the second plurality of burls comprises forming the second plurality of burls from at least one material selected from the group consisting of diamond-like carbon (DLC), aluminum nitride (AlN), silicon nitride (SiN), or chromium nitride (CrN). Item 18. The method of item 16, wherein forming the second plurality of burls comprises forming the second plurality of burls to a thickness greater than about 2.0 micrometers. (Item 19) A first layer having a first surface; a first plurality of burls disposed on the first surface of the first layer; The apparatus, wherein a portion of the plurality of burrs have a hardness greater than about 6.0 gigapascals (GPa). (Item 20) The apparatus of claim 19, wherein the plurality of burrs comprises at least one material selected from the group consisting of diamond-like carbon (DLC), aluminum nitride (AlN), silicon nitride (SiN), or chromium nitride (CrN).

[0102] In some embodiments, forming the second plurality of burls includes forming a second layer including a second surface and a third surface opposite the second surface, the third surface of the second layer being disposed on the first surface of the first layer; forming a third layer including a fourth surface and a fifth surface opposite the fourth surface, the fifth surface of the third layer being disposed on the second surface of the second layer, and forming the second plurality of burls includes patterning the third layer to form the second plurality of burls. In some embodiments, forming the second layer includes forming an adhesion layer. In some embodiments, forming the adhesion layer includes forming the adhesion layer with at least one material selected from the group consisting of Cr or Al. In some embodiments, forming the third layer includes forming the third layer with DLC. Optionally, in some embodiments, the method can further include curing the first layer and the second plurality of burls at a temperature greater than about 350°C.

[0103] Although specific reference may be made in this text to the use of lithography apparatus in the manufacture of ICs, it is understood that the lithography apparatus described herein may have other applications. Other applications are integrated optical systems, guiding and detection patterns for magnetic domain memories, flat panel displays, LCDs, thin film magnetic heads, etc. Those skilled in the art will appreciate that in the context of such alternative applications, any use of the terms "wafer" or "die" herein may be considered synonymous with the more general terms "substrate" or "target portion", respectively. Substrates referred to herein may be processed before or after exposure, for example in a track unit (a tool that typically applies a layer of resist to a substrate and develops the exposed resist), a metrology unit, and / or an inspection unit. Where applicable, the disclosure herein may be applied to such and other substrate processing tools. Additionally, a substrate may be processed multiple times, for example to create a multi-layer IC, and the term substrate as used herein may refer to a substrate that already includes multiple processed layers.

[0104] It is to be understood that the phrases and terms used herein are for the purpose of description rather than of limitation, as the phrases and terms used herein would be interpreted by one of ordinary skill in the art in light of the teachings herein.

[0105] The term "substrate" as used herein describes a material onto which a layer of material is added. In some embodiments, the substrate itself can be patterned, and the material added onto it can also be patterned or can remain unpatterned.

[0106] The examples disclosed herein are intended to illustrate, but not to limit, embodiments of the present disclosure. Other suitable modifications and adaptations of the variety of conditions and parameters normally encountered in the art and obvious to those skilled in the relevant art are within the spirit and scope of the present disclosure.

[0107] Although specific reference may be made in this document to the use of the apparatus and / or system in the manufacture of ICs, it should be expressly understood that such apparatus and / or systems have many other possible applications. For example, they may be employed in the manufacture of integrated optical systems, guide and detection patterns for magnetic domain memories, LCD panels, thin film magnetic heads, etc. In the context of such alternative applications, it will be understood that any use of the terms "reticle," "wafer," or "die" in this document should be considered as replaced by the more general terms "mask," "substrate," and "target portion," respectively.

[0108] While certain aspects of the disclosure have been described above, it will be appreciated that the aspects may be practiced otherwise than as described. The description is not intended to limit the embodiments of the disclosure.

[0109] It is understood that the Detailed Description section, and not the Background, Overview, and Abstract sections, are intended to be used to interpret the claims. While the Overview and Abstract sections may define one or more exemplary embodiments contemplated by the inventors, they do not define all exemplary embodiments and are therefore not intended to limit the present embodiments and the appended claims in any manner.

[0110] Some aspects of the present disclosure have been described above with the help of functional blocks illustrating implementations of specified functions and relationships thereof. The boundaries of these functional blocks have been arbitrarily defined in this document for the convenience of description. Alternative boundaries may be defined as long as the specified functions and relationships thereof are appropriately performed.

[0111] The foregoing description of specific embodiments of the present disclosure is intended to sufficiently clarify the general nature of the embodiments so that others, by applying knowledge within the scope of those skilled in the art, may readily modify and / or adapt such specific embodiments for various applications without undue experimentation and without departing from the general concept of the present disclosure. Such adaptations and modifications are therefore intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teachings and suggestions presented herein.

[0112] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary aspects or embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. 1. A method of manufacturing a device, comprising: providing a first layer having a first surface; forming a plurality of burls on the first surface of the first layer; forming the plurality of burls disposing a plurality of conductive burl tops on the plurality of burls; forming electrical connections on the first surface between the plurality of conductive burr tips; forming a portion of the plurality of burls to a hardness of greater than about 6.0 Giga Pascals (GPa).

2. providing the first layer comprises providing a glass substrate; forming the plurality of burls comprises forming the plurality of burls of diamond-like carbon (DLC); The method of claim 1 , wherein forming the plurality of burls forms at least about 30,000 burls.

3. The method of claim 1 or 2, wherein forming the plurality of burls comprises forming the plurality of burls to a thickness of greater than about 2.0 micrometers.

4. The method of claim 1 or 2, wherein forming the plurality of burls comprises forming the plurality of burls to a thickness of greater than about 5.0 micrometers.

5. The method of claim 1 or 2, wherein forming the plurality of burls comprises forming the plurality of burls to a thickness of greater than about 10.0 micrometers.

6. 6. The method of claim 1, wherein forming the plurality of burls comprises forming the plurality of burls from a material selected from the group consisting of aluminum nitride (AlN), silicon nitride (SiN), or chromium nitride (CrN).

7. 7. The method of claim 1, wherein forming the portion of the plurality of burls comprises forming the portion of the plurality of burls to a hardness of greater than about 10.0 Giga Pascals (GPa).

8. 7. The method of claim 1, wherein forming the portion of the plurality of burls comprises forming the portion of the plurality of burls to a hardness of greater than about 15.0 Giga Pascals (GPa).

9. 7. The method of claim 1, wherein forming the portion of the plurality of burls comprises forming the portion of the plurality of burls to a hardness of greater than about 20.0 Giga Pascals (GPa).

10. forming the plurality of burls forming a second layer having a second surface and a third surface opposite the second surface, the third surface of the second layer being disposed on the first surface of the first layer; forming a third layer having a fourth surface and a fifth surface opposite the fourth surface, the fifth surface of the third layer being disposed on the second surface of the second layer; The method of claim 1 , wherein forming the plurality of burls comprises patterning the third layer to form the plurality of burls.

11. forming the second layer comprises forming an adhesive layer; forming the adhesion layer comprises forming the adhesion layer from at least one material selected from the group consisting of chromium (Cr) or aluminum (Al); The method of claim 10 , wherein forming the third layer comprises forming the third layer from diamond-like carbon (DLC).

12. 1. A method of manufacturing a device, comprising: receiving a wafer clamp comprising a first layer having a first surface and a first plurality of burls disposed on the first surface of the first layer; removing the first plurality of burls; forming a second plurality of burls on the first surface of the first layer; Forming the second plurality of burls includes: disposing a plurality of conductive burl tips on the second plurality of burl; forming electrical connections on the first surface between the plurality of conductive burr tips; forming a portion of the second plurality of burls to a hardness of greater than about 6.0 Giga Pascals (GPa).

13. forming the second plurality of burls comprises forming the second plurality of burls from at least one material selected from the group consisting of diamond-like carbon (DLC), aluminum nitride (AlN), silicon nitride (SiN), or chromium nitride (CrN); The method of claim 12 , wherein forming the second plurality of burls comprises forming the second plurality of burls to a thickness greater than about 2.0 micrometers.

14. a first layer having a first surface; a plurality of burls disposed on the first surface of the first layer; a plurality of conductive burl tops disposed on the plurality of burls; and forming electrical connections on the first surface between the plurality of conductive burr tips; The apparatus, wherein a portion of the plurality of burrs have a hardness greater than about 6.0 gigapascals (GPa).

15. 15. The apparatus of claim 14, wherein the plurality of burls comprises at least one material selected from the group consisting of diamond-like carbon (DLC), aluminum nitride (AlN), silicon nitride (SiN), or chromium nitride (CrN).

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