Semiconductor integrated circuit device

Abstract

A power supply wiring structure that supplies electrical power to a standard cell, wherein a region for laying signal wiring is ensured, and higher integration and smaller area of a semiconductor integrated circuit device are realized. Embedded power supply wiring (3) extending in a X direction is positioned with a prescribed gap in a Y direction. Local power supply wiring (5) extending in the Y direction is connected to the embedded power supply wiring (3). Metal power supply wiring (7) extending in the X direction is formed on an upper-layer metal wiring layer, the metal power supply wiring (7) being connected to the local power supply wiring (5). The Y-direction positioning interval of the metal power supply wiring (7) is greater than the positioning interval of the embedded power supply wiring (3).

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor integrated circuit device including standard cells. [Background technology]

[0002] The standard cell method is known as a method for forming semiconductor integrated circuits on a semiconductor substrate. The standard cell method is a method for designing an LSI chip by preparing basic units with specific logical functions (e.g. inverters, latches, flip-flops, full adders, etc.) as standard cells in advance, arranging multiple standard cells on a semiconductor substrate, and connecting these standard cells with wiring.

[0003] Also, in order to increase the integration density of semiconductor integrated circuit devices, it has been proposed to use buried power rails (BPRs), which are power supply wiring provided in a buried interconnect layer, for standard cells, rather than power supply wiring provided in a metal wiring layer formed above transistors as in the conventional method.

[0004] Patent Document 1 discloses a configuration in which, in a block composed of standard cells, power supply wiring is configured as embedded power supply wiring, the source of a transistor is connected to this embedded power supply wiring, and it is further connected to power supply wiring provided in an upper wiring layer. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Publication No. 2019 / 0080969 (FIG. 1E) Summary of the Invention [Problem to be solved by the invention]

[0006] In the configuration of Patent Document 1, although embedded power wiring is used as the power wiring of the standard cells, it is necessary to provide a power wiring in an upper wiring layer for each embedded power wiring, which reduces the area in the upper wiring layer for laying signal wiring, which hinders high integration of semiconductor integrated circuit devices.

[0007] An object of the present disclosure is to achieve high integration and a small area of ​​a semiconductor integrated circuit device by ensuring an area for laying signal wiring in a power wiring structure that supplies power to standard cells. [Means for solving the problem]

[0008] In a first aspect of the present disclosure, a semiconductor integrated circuit device includes a plurality of cell rows, each of which includes standard cells lined up in a first direction and arranged side by side in a second direction perpendicular to the first direction; a plurality of embedded power supply wirings formed in an embedded wiring layer, extending in the first direction and arranged at a first predetermined interval in the second direction, and supplying a first power supply voltage to the standard cells; a local power supply wiring formed in a local wiring layer in which local wiring contacting a source and a drain of a transistor included in the standard cell is formed, extending in the second direction, and connected to the plurality of embedded power supply wirings; and a plurality of metal power supply wirings formed in a metal wiring layer above the local wiring layer, extending in the first direction, arranged at a second predetermined interval in the second direction that is larger than the first predetermined interval, and connected to the local power supply wirings.

[0009] According to this aspect, a plurality of embedded power wirings extending in a first direction are arranged at a predetermined interval in a second direction. A local power wiring extending in the second direction is connected to the plurality of embedded power wirings. A plurality of metal power wirings extending in the first direction are formed in a metal wiring layer above the local wiring layer, and the plurality of metal power wirings are connected to the local power wirings. With this configuration, it is not necessary to provide metal wirings corresponding to the plurality of embedded power wirings, and the plurality of metal power wirings are arranged at intervals in the second direction that are greater than the intervals at which the plurality of embedded power wirings are arranged. This makes it possible to secure a larger area in the metal wiring layer for laying signal wiring. Therefore, it is possible to realize a reduction in the area of ​​the semiconductor integrated circuit device.

[0010] In a second aspect of the present disclosure, a semiconductor integrated circuit device includes a plurality of cell rows, each of which includes standard cells lined up in a first direction and arranged side by side in a second direction perpendicular to the first direction; a plurality of embedded power supply wirings formed in an embedded wiring layer, extending in the first direction and arranged at a first predetermined interval in the second direction, and supplying a first power supply voltage to the standard cells; a local power supply wiring formed in a local wiring layer in which local wiring contacting a source and a drain of a transistor included in the standard cell is formed, extending in the second direction and connected to the plurality of embedded power supply wirings; and a metal power supply wiring formed in a metal wiring layer above the local wiring layer, extending in the second direction, and overlapping with the local power supply wiring in a planar view, the local power supply wiring and the metal power supply wiring being connected to each other by a plurality of connection parts provided at a second predetermined interval in the second direction that is larger than the first predetermined interval.

[0011] According to this aspect, a plurality of embedded power wirings extending in a first direction are arranged at a predetermined interval in a second direction. A local power wiring extending in the second direction is connected to the plurality of embedded power wirings. A metal power wiring extending in the second direction is formed in a metal wiring layer above the local wiring layer, and this metal power wiring is connected to the local power wiring by a plurality of connection parts arranged at a predetermined interval in the second direction. With this configuration, it is not necessary to provide metal wiring corresponding to each of the plurality of embedded power wirings, and the metal power wiring is connected to the local wiring by a plurality of connection parts arranged at an interval larger than the arrangement interval of the plurality of embedded power wirings in the second direction. This makes it possible to secure a larger area in the metal wiring layer for laying signal wiring. Therefore, it is possible to realize a reduction in the area of ​​the semiconductor integrated circuit.

[0012] In a third aspect of the present disclosure, a semiconductor integrated circuit device includes a plurality of cell rows, each of which includes standard cells lined up in a first direction and arranged side by side in a second direction perpendicular to the first direction; a plurality of metal power supply wirings formed in a first metal wiring layer, extending in the first direction, and arranged at a first predetermined interval in the second direction, and supplying a first power supply voltage to the standard cells; a local power supply wiring formed in a local wiring layer in which local wiring contacting a source and a drain of a transistor included in the standard cell is formed, extending in the second direction, and connected to the plurality of metal power supply wirings; a buried power supply wiring formed in a buried wiring layer, extending in the second direction, overlapping with the local power supply wiring in a planar view, and connected to the local power supply wiring; and an upper layer metal power supply wiring formed in a second metal wiring layer above the first metal wiring layer, extending in the second direction, and overlapping with the local power supply wiring in a planar view, and the local power supply wiring and the upper layer metal power supply wiring are connected only in cell rows at both ends in the second direction among the plurality of cell rows.

[0013] According to this embodiment, a plurality of metal power wirings extending in a first direction are arranged at a predetermined interval in a second direction. A local power wiring extending in the second direction is connected to the plurality of metal power wirings. A buried power wiring extending in the second direction overlaps with the local power wiring in a plan view and is connected to the local power wiring. An upper layer metal power wiring extending in the second direction is formed in a metal wiring layer above the plurality of metal power wirings, and this upper layer metal power wiring is connected to the local power wiring only in the cell rows at both ends in the second direction. With this configuration, the power supply can be strengthened by the local power wiring and the buried power wiring connected to each other. In addition, since the upper layer metal power wiring is connected to the local power wiring only in the cell rows at both ends in the second direction, a larger area can be secured in the metal wiring layer for laying the signal wiring. Therefore, a reduction in the area of ​​the semiconductor integrated circuit can be realized. Effect of the Invention

[0014] According to the present disclosure, in a power supply wiring structure for supplying power to standard cells, an area for laying signal wiring can be secured, thereby achieving high integration and a small area of ​​a semiconductor integrated circuit device. [Brief description of the drawings]

[0015] [Figure 1] Layout example of circuit blocks included in the semiconductor integrated circuit device according to the first embodiment [Diagram 2] (a) and (b) are cross-sectional views of the circuit block in Fig. 1. [Diagram 3] FIG. 1 is a plan view showing an example of a layout structure of a power tap cell; [Figure 4] (a) and (b) are cross-sectional views of the power tap cell in Fig. 3. [Diagram 5] FIG. 1 is a plan view showing an example of a layout structure of an inverter cell; [Figure 6] (a) and (b) are cross-sectional views of the inverter cell in Fig. 5. [Figure 7]1A is a plan view showing a layout structure of a power tap cell according to a modified example, and FIG. 1B is a plan view showing a layout structure of a power tap cell according to a modified example. FIG. [Figure 8] Layout example of circuit block according to a modified example [Figure 9] Layout example of circuit block according to a modified example [Figure 10] (a) is a plan view showing the layout structure of a VDD-connected termination cell, and (b) is a plan view showing the layout structure of a VSS-connected termination cell. [Figure 11] Layout example of a circuit block included in a semiconductor integrated circuit device according to a second embodiment [Figure 12] (a) and (b) are cross-sectional views of the circuit block in Fig. 11. [Figure 13] Layout example of a circuit block included in a semiconductor integrated circuit device according to a third embodiment [Figure 14] (a) and (b) are cross-sectional views of the circuit block in Fig. 13. [Figure 15] 1A and 1B are diagrams showing an example of a layout structure of a power tap cell, in which (a) is a plan view and (b) is a cross-sectional view; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, the embodiments will be described with reference to the drawings. In the following embodiments, a semiconductor integrated circuit device includes a plurality of standard cells (in this specification, simply referred to as cells as appropriate), and at least some of the plurality of standard cells include, for example, nanosheet FETs (Field Effect Transistors). A nanosheet FET is a FET that uses a thin sheet (nanosheet) through which a current flows. The nanosheet is formed of, for example, silicon. In addition, in the present disclosure, the semiconductor layer portions that are formed on both ends of the nanosheet and that constitute the terminals that become the source or drain of the nanosheet FET are called "pads."

[0017] In this disclosure, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. In the following description, in plan views such as FIG. 1, the horizontal direction of the drawing is the X direction (corresponding to the first direction), the vertical direction of the drawing is the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface is the Z direction.

[0018] (First embodiment) FIG. 1 is an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the first embodiment, and FIG. 2(a) is a cross-sectional view taken along line A-A' in FIG. 1, and FIG. 2(b) is a cross-sectional view taken along line B-B' in FIG. 1. In the layout of FIG. 1, a plurality of cell rows CR each including standard cells C arranged in the X direction are arranged in the Y direction. The standard cells C include, for example, nanosheet FETs. The plurality of cell rows CR are arranged in a vertically inverted manner (flipped in the Y direction) every other row. Between the cell rows CR, a power supply wiring 3 for supplying a power supply voltage VDD and a power supply wiring 4 for supplying a power supply voltage VSS are alternately arranged. The power supply wirings 3 and 4 are so-called buried power supply wirings (BPR: Buried Power Rail) formed in a buried wiring layer. The cells C included in each cell row CR are supplied with power supply voltages VDD and VSS from the power supply wirings 3 and 4 arranged above and below the cell row CR in the drawing.

[0019] In the multiple cell rows CR, power tap cell groups 2a, 2b, and 2c, each including a multiple power tap cell 1, are arranged at equal intervals in the X direction. Each of the power tap cell groups 2a, 2b, and 2c includes a multiple power tap cell 1 at the same position in the X direction.

[0020] A local wiring extending in the Y direction is formed in the power tap cell 1. The local wiring is a wiring formed in a local wiring layer that contacts the source and drain of the transistor included in the standard cell C. In each of the power tap cell groups 2a, 2b, and 2c, the power tap cells 1 are arranged adjacent to each other in the Y direction, thereby forming local power supply wirings 5 ​​and 6 extending in the Y direction within the circuit block. The local power supply wiring 5 is connected to the power supply wiring 3 that supplies VDD within the power tap cell 1 through a via. The local power supply wiring 6 is connected to the power supply wiring 4 that supplies VSS within the power tap cell 1 through a via.

[0021] Metal power supply wires 7 and 8 extending in the X direction are formed in the M4 wiring layer (the fourth metal wiring layer from the bottom). The metal power supply wire 7 is connected to the local power supply wire 5 through the M1 to M3 wires and vias. The metal power supply wire 8 is connected to the local power supply wire 6 through the M1 to M3 wires and vias. That is, VDD is supplied from the metal power supply wire 7 to the power supply wire 3 through the local power supply wire 5. VSS is supplied from the metal power supply wire 8 to the power supply wire 4 through the local power supply wire 6.

[0022] FIG. 3 is a plan view showing an example of the layout structure of the power tap cell 1, and FIGS. 4(a) and (b) are cross-sectional views in the vertical direction in plan view. FIG. 4(a) is a cross-section along line A-A' in FIG. 3, and FIG. 4(b) is a cross-section along line B-B' in FIG. 3. FIG. 3 shows a cell frame CL of the power tap cell. This is the same for the subsequent plan views. FIG. 5 is a plan view showing an example of the layout structure of an inverter cell as an example of cell C, and FIGS. 6(a) and (b) are cross-sectional views in the vertical direction in plan view. FIG. 6(a) is a cross-section along line A-A' in FIG. 5, and FIG. 6(b) is a cross-section along line B-B' in FIG. 5.

[0023] First, the layout structure of the inverter cell will be described with reference to FIGS.

[0024] As shown in Fig. 5, power supply wiring 11, 12 extending in the X direction are provided at both ends of the inverter cell in the Y direction. Both power supply wiring 11, 12 are buried power supply wiring (BPR) formed in a buried wiring layer. The power supply wiring 11 supplies a power supply voltage VDD, and the power supply wiring 12 supplies a power supply voltage VSS. The power supply wiring 11 is shared with other cells C arranged in the same cell column CR as the inverter cell, forming the power supply wiring 3 in Fig. 1. The power supply wiring 12 is shared with other cells C arranged in the same cell column CR as the inverter cell, forming the power supply wiring 4 in Fig. 1.

[0025] A P-type transistor P1 is formed in a P-type region on an N-well, and an N-type transistor N1 is formed in an N-type region on a P-type substrate.

[0026] The transistor P1 has a nanosheet 21 consisting of two sheets as a channel part. That is, the transistor P1 is a nanosheet FET. Pads 22a and 22b consisting of an integral semiconductor layer connected to the two sheets are formed on both ends in the X direction of the nanosheet 21. The pads 22a and 22b become the source region and drain region of the transistor P1.

[0027] The transistor N1 has a nanosheet 26 consisting of two sheets as a channel part. In other words, the transistor N1 is a nanosheet FET. Pads 27a and 27b consisting of an integral semiconductor layer connected to the two sheets are formed on both ends in the X direction of the nanosheet 26. The pads 27a and 27b become the source region and drain region of the transistor N1.

[0028] The gate wiring 31 extends in the Y direction and surrounds the nanosheet 21 of the transistor P1 with a gate insulating film (not shown) therebetween, and also surrounds the nanosheet 26 of the transistor N1 with a gate insulating film (not shown) therebetween. The gate wiring 31 serves as the gates of the transistors P1 and N1.

[0029] Local wiring (denoted as LI in the figure) 41, 42, and 43 are formed extending in the Y direction. The local wiring 41 is connected to the pad 22a, and is also connected to the power supply wiring 11 through a via. The local wiring 42 is connected to the pad 27a, and is also connected to the power supply wiring 12 through a via. The local wiring 43 is connected to the pads 22b and 27b.

[0030] M1 wires 51 and 52 extending in the X direction are formed in the first metal wiring layer. The M1 wire 51 is connected to the gate wiring 31 through a via. An input terminal A is provided on the upper part of the M1 wire 51. The M1 wire 52 is connected to the local wiring 43 through a via. An output terminal Y is provided on the upper part of the M1 wire 52.

[0031] That is, the local wirings 41, 42, and 43 are formed in a local wiring layer that is above the buried power wiring and below the M1 wiring, and are in contact with the sources or drains of the transistors P1 and N1. The cell terminals are provided in the M1 wiring layer, and the inter-cell wiring is provided in a wiring layer above the M1 wiring layer.

[0032] Next, the layout structure of the power tap cell 1 will be described with reference to FIGS.

[0033] 3, like the inverter cell, power supply lines 11 and 12, which are embedded power supply lines extending in the X direction, are provided at both ends in the Y direction of the power tap cell 1. The power supply line 11 supplies a power supply voltage VDD, and the power supply line 12 supplies a power supply voltage VSS.

[0034] In the power tap cell 1, no nanosheets are formed and no transistors are formed.

[0035] The gate wiring 35 extends in the Y direction. Local wirings 46 and 47 extending in the Y direction are formed on both sides of the gate wiring 35 in the X direction. The local wirings 46 and 47 are formed in the same local wiring layer as the local wirings 41, 42, and 43 of the inverter cells. The local wirings 46 and 47 extend to the cell frame CL in the Y direction. The local wiring 46 is connected to the power supply wiring 11 through a via. The local wiring 47 is connected to the power supply wiring 12 through a via.

[0036] The power tap cells 1 shown in Figures 3 and 4 are arranged in a row in the Y direction as shown in Figure 1. As a result, local wirings 46, 47 are continuous across the multiple power tap cells 1 arranged in the Y direction, thereby forming the local power wirings 5, 6 in Figure 1. In each power tap cell 1, local wiring 46 is connected to power wiring 11 through a via, and local wiring 47 is connected to power wiring 12 through a via, so that local power wiring 5 is connected to power wiring 3, and local power wiring 6 is connected to power wiring 4.

[0037] 1, the interval in the Y direction between metal power wires 7 that supply VDD is greater than the interval in the Y direction between embedded power wires 3 that supply VDD. Also, the interval in the Y direction between metal power wires 8 that supply VSS is greater than the interval in the Y direction between embedded power wires 4 that supply VSS.

[0038] According to this embodiment, power can be supplied from the upper layer metal power supply wires 7 and 8 to the power supply wires 3 and 4, which are embedded power supply wires, via the local power supply wires 5 and 6 extending in the Y direction. Therefore, in the M1 wiring layer and higher metal wiring layers, it is not necessary to provide metal power supply wires corresponding to the embedded power supply wires 3 and 4. Therefore, in the M1 wiring layer and higher metal wiring layers, more metal wires can be used as signal wires. Therefore, the area of ​​the semiconductor integrated circuit device can be reduced.

[0039] Furthermore, since the power tap cell groups 2a, 2b, and 2c are arranged at equal intervals in the X direction, the power supply from the upper layer power wiring to the power wirings 3 and 4 can be made uniform within the circuit block, thereby making it possible to effectively suppress power supply voltage drops.

[0040] In the above-described configuration, the metal power supply wires 7 and 8 extending in the X-direction are formed in the M4 wiring layer, but the upper metal power supply wires extending in the X-direction may be formed in a wiring layer other than the M4 wiring layer. Also, the metal power supply wires 7 and 8 are connected to the local power supply wires 5 and 6 via the M1 to M3 wires and vias, but instead of this, for example, contacts (super vias) that directly connect the M4 wires and the local wires may be used.

[0041] In the above-mentioned configuration, a power supply wiring may be further provided in a wiring layer above the M4 wiring layer. By connecting this power supply wiring to the metal power supply wirings 7 and 8 formed in the M4 wiring layer, the power supply can be strengthened.

[0042] (Variation 1) The power tap cell shown in Figures 3 and 4 has a layout structure that supplies both VDD and VSS. However, the power tap cell may have a structure that supplies only one of VDD and VSS.

[0043] FIG. 7 is a plan view showing a layout structure of a power tap cell according to a modified example, where (a) is a power tap cell that supplies a power supply voltage VDD, and (b) is a power tap cell that supplies a power supply voltage VSS.

[0044] In Fig. 7(a), the local wirings 46a and 46b are both connected to the power supply wiring 11 through vias. In Fig. 7(b), the local wirings 47a and 47b are both connected to the power supply wiring 12 through vias.

[0045] Fig. 8 is an example of a layout of a circuit block according to a modified example. In the layout of Fig. 8, power tap cell groups 2d and 2f including a power tap cell 1A that supplies a power supply voltage VDD as shown in Fig. 7(a) and a power tap cell group 2e including a power tap cell 1B that supplies a power supply voltage VSS as shown in Fig. 7(b) are alternately arranged in the X direction.

[0046] In the power tap cell groups 2d and 2f, the local wirings 46a and 46b are continuous across multiple power tap cells 1A aligned in the Y direction, thereby forming the local wirings 5a and 5b in Fig. 8. In each power tap cell 1A, the local wirings 46a and 46b are connected to the power supply wiring 11 through vias, and therefore the local wirings 5a and 5b are connected to the power supply wiring 3.

[0047] In the power tap cell group 2e, the local wirings 47a, 47b are continuous across multiple power tap cells 1B aligned in the Y direction, thereby forming the local wirings 6a, 6b in Fig. 8. In each power tap cell 1B, the local wirings 47a, 47b are connected to the power wiring 12 through vias, and therefore the local wirings 6a, 6b are connected to the power wiring 4.

[0048] This modification also provides the same effects as those of the above embodiment. That is, power can be supplied from the upper metal power supply wiring 7 to the power supply wiring 3, which is an embedded power supply wiring, via the local power supply wirings 5a and 5b extending in the Y direction. Also, power can be supplied from the upper metal power supply wiring 8 to the power supply wiring 4, which is an embedded power supply wiring, via the local power supply wirings 6a and 6b extending in the Y direction. Therefore, in the M1 wiring layer and higher metal wiring layers, it is not necessary to provide metal power supply wirings corresponding to the embedded power supply wirings 3 and 4. Therefore, in the M1 wiring layer and higher metal wiring layers, more metal wirings can be used as signal wirings. Therefore, the area of ​​the semiconductor integrated circuit device can be reduced.

[0049] (Variation 2) Fig. 9 is an example of a layout of a circuit block according to a modified example. In the layout of Fig. 9, cells terminating the power supply wirings 3 and 4 are arranged at both ends in the X direction. That is, at the left end of the drawing, VDD connection termination cells 9A terminating the power supply wiring 3 are arranged in a row in the Y direction, and at the right end of the drawing, VSS connection termination cells 9B terminating the power supply wiring 4 are arranged in a row in the Y direction. The VDD connection termination cells 9A and the VSS connection termination cells 9B are arranged upside down in every other row, similar to the other standard cells C.

[0050] Fig. 10(a) is a plan view showing the layout structure of the VDD-connection termination cell 9A, and Fig. 10(b) is a plan view showing the layout structure of the VSS-connection termination cell 9B. In Fig. 10(a), a power supply wiring 11A that is an embedded power supply wiring extending in the X direction is provided, and further, an embedded power supply wiring 13 that is connected to the power supply wiring 11A and extends in the Y direction is provided. The power supply wiring 11A does not reach one end (the left end in Fig. 10(a)) of the VDD-connection termination cell 9A in the X direction.

[0051] 10(b), a power supply wiring 12A that is an embedded power supply wiring extending in the X direction is provided, and further, an embedded power supply wiring 14 that is connected to the power supply wiring 12A and extends in the Y direction is provided. The power supply wiring 12A does not reach one end in the X direction of the VSS connection termination cell 9B (the right end in FIG. 10(b)).

[0052] By arranging VDD connection termination cells 9A as shown in Fig. 10(a) in a row in the Y direction at the left end of the circuit block in Fig. 9, the power supply wires 3 that supply VDD are connected to each other via embedded power supply wires 13. By arranging VSS connection termination cells 9B as shown in Fig. 10(b) in a row in the Y direction at the right end of the circuit block in Fig. 9, the power supply wires 4 that supply VSS are connected to each other via embedded power supply wires 14.

[0053] Therefore, according to this modification, the power supply can be strengthened without using wiring in an upper wiring layer.

[0054] In this modification, the VDD-connected termination cell is placed at the left end of the circuit block and the VSS-connected termination cell is placed at the right end of the circuit block, but the placement of the cells terminating the power supply wirings 3 and 4 is not limited to this. For example, the VDD-connected termination cell may be placed at both ends of the circuit block, or the VSS-connected termination cell may be placed at both ends of the circuit block. Also, the cells terminating the power supply wirings 3 and 4 may be inserted in the middle of the cell row.

[0055] Second embodiment FIG. 11 is an example of the layout of a circuit block included in a semiconductor integrated circuit device according to the second embodiment. FIG. 12(a) is a cross-sectional view taken along line A-A' in FIG. 11, and FIG. 12(b) is a cross-sectional view taken along line B-B' in FIG. 11. In the layout of FIG. 11, a plurality of cell rows CR each including standard cells C arranged in the X direction are arranged in the Y direction. The standard cells C include, for example, nanosheet FETs. The plurality of cell rows CR are arranged in a vertically inverted manner (inverted in the Y direction) every other row. Between the cell rows CR, a power supply wiring 3 for supplying a power supply voltage VDD and a power supply wiring 4 for supplying a power supply voltage VSS are alternately arranged. The power supply wirings 3 and 4 are so-called buried power supply wirings (BPR) formed in a buried wiring layer. The cells C included in each cell row CR are supplied with VDD and VSS from the power supply wirings 3 and 4 arranged above and below the cell row CR.

[0056] In the multiple cell rows CR, power tap cell groups 2a, 2b, and 2c, each including a multiple power tap cell 1, are arranged at equal intervals in the X direction. Each of the power tap cell groups 2a, 2b, and 2c includes a multiple power tap cell 1 at the same position in the X direction.

[0057] Within the power tap cell 1, a local wiring extending in the Y direction is formed. In each of the power tap cell groups 2a, 2b, and 2c, the power tap cells 1 are arranged adjacent to each other in the Y direction, thereby forming local power wirings 5 ​​and 6 extending in the Y direction within the circuit block. Within the power tap cell 1, the local power wiring 5 is connected to the power wiring 3 that supplies VDD through a via. Within the power tap cell 1, the local power wiring 6 is connected to the power wiring 4 that supplies VSS through a via. The configuration up to this point is the same as the layout of FIG. 1 in the first embodiment.

[0058] In this embodiment, metal power supply wires 107 and 108 extending in the Y direction are formed in the M3 wiring layer (the third metal wiring layer from the bottom). The metal power supply wire 107 is connected to the local power supply wire 5 through the M1-M2 wires and vias. The metal power supply wire 108 is connected to the local power supply wire 6 through the M1-M2 wires and vias. That is, VDD is supplied from the metal power supply wire 107 to the power supply wire 3 through the local power supply wire 5. VSS is supplied from the metal power supply wire 108 to the power supply wire 4 through the local power supply wire 6.

[0059] Here, a configuration including the M1-M2 wirings and vias that connect the metal power wiring and the local power wiring is called a connection portion. In FIG. 11, the location where the connection portion is provided is indicated by a dashed line A1. Connection portions 111 and 112 that connect the metal power wiring 107 that supplies VDD and the local power wiring 5 are provided at a predetermined interval in the Y direction. The interval between the connection portions 111 and 112 is larger than the interval between the power wiring 3 that supplies VDD. Connection portions 121 and 122 that connect the metal power wiring 108 that supplies VSS and the local power wiring 6 are provided at a predetermined interval in the Y direction. The interval between the connection portions 121 and 122 is larger than the interval between the power wiring 4 that supplies VSS.

[0060] Furthermore, the connections 111 and 112 connecting the metal power supply wire 107 supplying VDD and the local power supply wire 5, and the connections 121 and 122 connecting the metal power supply wire 108 supplying VSS and the local power supply wire 6 are aligned in the Y direction.

[0061] According to this embodiment, power can be supplied from the upper layer metal power wirings 107, 108 to the power wirings 3, 4, which are embedded power wirings, via the local power wirings 5, 6 extending in the Y direction. Therefore, in the M1 wiring layer and higher metal wiring layers, it is not necessary to provide metal power wirings corresponding to the embedded power wirings 3, 4. Therefore, in the M1 wiring layer and higher metal wiring layers, more metal wirings can be used as signal wirings. Therefore, the area of ​​the semiconductor integrated circuit device can be reduced.

[0062] In addition, since the power tap cell groups 2a, 2b, and 2c are arranged at equal intervals in the X direction, the power supply from the upper layer power wiring to the power wirings 3 and 4 can be made uniform within the circuit block, thereby making it possible to effectively suppress the power supply voltage drop.

[0063] In addition, in the above-mentioned configuration, the connection parts 111, 112 relating to VDD and the connection parts 121, 122 relating to VSS are aligned in the Y direction. This reduces the area in the Y direction where signal wiring cannot be laid due to the presence of the connection parts, making it possible to secure a larger area for laying signal wiring. This allows the semiconductor integrated circuit device to have a smaller area.

[0064] The connection parts relating to VDD and the connection parts relating to VSS do not need to be aligned in the Y direction.

[0065] In the above-described configuration, the metal power supply wires 107, 108 extending in the Y direction are formed in the M3 wiring layer, but the upper metal power supply wires extending in the Y direction may be formed in a wiring layer other than the M3 wiring layer. Also, the metal power supply wires 107, 108 are connected to the local power supply wires 5, 6 via the M1-M2 wires and vias, but instead of this, for example, contacts (super vias) that directly connect the M3 wires and the local wires may be used.

[0066] In the above-mentioned configuration, a power supply wiring may be further provided in a wiring layer above the M3 wiring layer. By connecting this power supply wiring to the metal power supply wirings 107 and 108 formed in the M3 wiring layer, the power supply can be strengthened.

[0067] Third embodiment Fig. 13 is an example of the layout of a circuit block provided in a semiconductor integrated circuit device according to the third embodiment, Fig. 14(a) is a cross-sectional view taken along line A-A' in Fig. 13, and Fig. 14(b) is a cross-sectional view taken along line B-B' in Fig. 13. In the layout of Fig. 13, multiple cell rows CR each having standard cells C aligned in the X direction are arranged in the Y direction. The standard cells C include, for example, nanosheet FETs. The multiple cell rows CR are arranged in a vertically inverted manner (flipped in the Y direction) every other row.

[0068] In addition, at the upper end of the circuit block in the drawing, a termination cell row TCR1 in which termination cells TC1 are arranged side by side in the X direction is arranged, and at the lower end of the circuit block in the drawing, a termination cell row TCR2 in which termination cells TC2 are arranged side by side in the X direction is arranged. The termination cells TC1 and TC2 have the same size in the X direction, i.e., the cell width.

[0069] Between the multiple cell strings CR and the terminal cell strings TCR1 and TCR2, power supply wiring 203 that supplies a power supply voltage VDD and power supply wiring 204 that supplies a power supply voltage VSS are alternately arranged. Unlike the first and second embodiments described above, the power supply wiring 203 and 204 are formed in the M1 wiring layer. The cells C included in each cell string CR are supplied with VDD and VSS from the power supply wiring 203 and 204 arranged on both sides in the Y direction.

[0070] In the multiple cell columns CR and the terminal cell columns TCR1 and TCR2, power tap cell groups 202a, 202b, and 202c including multiple power tap cells 201 are arranged at equal intervals in the X direction. Each of the power tap cell groups 202a, 202b, and 202c includes multiple power tap cells 201 that are at the same position in the X direction.

[0071] In the power tap cell 201, embedded wiring and local wiring extending in the Y direction are formed. In each of the power tap cell groups 202a, 202b, and 202c, the power tap cells 201 are arranged adjacent to each other in the Y direction, thereby forming embedded power wirings 205 and 206 extending in the Y direction within the circuit block, and local power wirings 5 ​​and 6 extending in the Y direction within the circuit block. The embedded power wiring 205 and the local power wiring 5 are connected to the power wiring 203 that supplies VDD within the power tap cell 201 through a via. The embedded power wiring 206 and the local power wiring 6 are connected to the power wiring 204 that supplies VSS within the power tap cell 201 through a via.

[0072] Metal power supply wirings 107 and 108 extending in the Y direction are formed in the M3 wiring layer (the third metal wiring layer from the bottom). The metal power supply wiring 107 is connected to the local power supply wiring 5 and the embedded power supply wiring 205 in the power tap cells 201 arranged in the termination cell columns TCR1 and TCR2 through the M1-M2 wiring and vias. The metal power supply wiring 108 is connected to the local power supply wiring 6 and the embedded power supply wiring 206 in the power tap cells 201 arranged in the termination cell columns TCR1 and TCR2 through the M1-M2 wiring and vias. That is, VDD is supplied from the metal power supply wiring 107 to the power supply wiring 203 through the local power supply wiring 5 and the embedded power supply wiring 205. VSS is supplied from the metal power supply wiring 108 to the power supply wiring 204 through the local power supply wiring 6 and the embedded power supply wiring 206. In FIG. 13, the points where the metal power wiring 107 is connected to the local power wiring 5 and the embedded power wiring 205, and the points where the metal power wiring 108 is connected to the local power wiring 6 and the embedded power wiring 206 are indicated by dashed lines A2.

[0073] FIG. 15 is a diagram showing an example of the layout structure of the power tap cell 201, where (a) is a plan view and (b) is a cross section of line A-A'. M1 wiring 251, 252 extending in the X direction are provided at both ends in the Y direction of the power tap cell 201. The M1 wiring 251 supplies a power supply voltage VDD, and the M1 wiring 252 supplies a power supply voltage VSS. The M1 wiring 251 is shared with other cells C arranged in the same cell row CR as the power tap cell 201, or with the terminating cells TC1, TC2 arranged in the same terminating cell rows TCR1, TCR2 as the power tap cell 201, to form the power wiring 203 of FIG. 13. The M1 wiring 252 is shared with other cells C arranged in the same cell row CR as the power tap cell 201, or with the terminating cells TC1, TC2 arranged in the same terminating cell rows TCR1, TCR2 as the power tap cell 201, to form the power wiring 204 of FIG. 13.

[0074] The gate wiring 231 extends in the Y direction. Local wirings 241 and 242 extending in the Y direction are formed on both sides of the gate wiring 231 in the X direction. The local wirings 241 and 242 extend in the Y direction to the cell frame CL. In addition, in the buried wiring layer, buried power supply wirings 211 and 212 extending in the Y direction are formed so as to overlap the local wirings 241 and 242, respectively, in a planar view. The buried power supply wirings 211 and 212 extend in the Y direction to the cell frame CL. The local wiring 241 and the buried power supply wiring 211 are connected via a via. The local wiring 242 and the buried wiring 212 are connected via a via.

[0075] The local wiring 241 is connected to the M1 wiring 251 through a via. The local wiring 242 is connected to the M1 wiring 252 through a via.

[0076] The power tap cells 201 shown in Fig. 15 are arranged in a row in the Y direction as shown in Fig. 13. As a result, the embedded power wirings 211, 212 are continuous across the multiple power tap cells 201 aligned in the Y direction, forming the embedded power wirings 205, 206 in Fig. 13. Also, the local wirings 241, 242 are continuous across the multiple power tap cells 201 aligned in the Y direction, forming the local power wirings 5, 6 in Fig. 13. In each power tap cell 1, the local wiring 241 is connected to the M1 wiring 251 through a via, and the local wiring 242 is connected to the M1 wiring 252 through a via, so that the local power wiring 5 is connected to the power wiring 203, and the local power wiring 6 is connected to the power wiring 204.

[0077] According to this embodiment, the local power supply wirings 5 ​​and 6 extending in the Y direction are connected to the metal power supply wirings 203 and 204 extending in the X direction, respectively. The buried power supply wirings 205 and 206 extending in the Y direction overlap the local power supply wirings 5 ​​and 6 in a plan view, and are connected to the local power supply wirings 5 ​​and 6, respectively. The upper layer metal power supply wirings 107 and 108 extending in the Y direction are formed in a metal wiring layer above the metal power supply wirings 203 and 204, and the upper layer metal power supply wirings 107 and 108 are connected to the local power supply wirings 5 ​​and 6, respectively. With this configuration, the power supply can be strengthened by the mutually connected local power supply wirings 5 ​​and 6 and the buried power supply wirings 205 and 206. In addition, since the upper layer metal power supply wirings 107 and 108 are connected to the local power supply wirings 5 ​​and 6 only in the cell rows at both ends in the Y direction, a larger area for laying signal wiring can be secured in the metal wiring layer. Therefore, the area of ​​the semiconductor integrated circuit can be reduced.

[0078] Incidentally, logic cells may be arranged in the termination cell columns TCR1 and TCR2.

[0079] In the above-described configuration, the metal power supply wires 107, 108 extending in the Y direction are formed in the M3 wiring layer, but the upper metal power supply wires extending in the Y direction may be formed in a wiring layer other than the M3 wiring layer. Also, the metal power supply wires 107, 108 are connected to the local power supply wires 5, 6 via the M1-M2 wires and vias, but instead of this, for example, contacts (super vias) that directly connect the M3 wires and the local wires may be used.

[0080] In the above-mentioned configuration, a power supply wiring may be further provided in a wiring layer above the M3 wiring layer. By connecting this power supply wiring to the metal power supply wirings 107 and 108 formed in the M3 wiring layer, the power supply can be strengthened.

[0081] (Other embodiments) In each of the above-mentioned embodiments, the power tap cell groups do not have to be arranged at equal intervals in the X direction. For example, the power tap cell groups may be arranged at narrower intervals in an area where it is desired to further strengthen the power supply than in other areas. In other words, the power tap cell groups may be arranged at a predetermined interval in the X direction.

[0082] In each of the above-mentioned embodiments, the transistor in the cell C is a nanosheet FET, but is not limited thereto, and may be, for example, a fin transistor. Also, the nanosheet FET in the cell C has two nanosheets, but the number of nanosheets is not limited to two.

[0083] Moreover, the width (size in the X direction) of the power tap cell is not limited to that shown in each of the above-mentioned embodiments. For example, in the configuration of Fig. 3, the width of the power tap cell may be further increased and two local wirings for supplying VDD and two local wirings for supplying VSS may be arranged. Also, in the configuration of Fig. 7, the local wiring may be reduced to one and the width of the power tap cell may be reduced, or three or more local wirings may be arranged in parallel and the width of the power tap cell may be increased. [Industrial Applicability]

[0084] INDUSTRIAL APPLICABILITY The present disclosure makes it possible to ensure a larger area for laying out signal wiring in a power wiring structure, which is useful for, for example, miniaturizing semiconductor chips. [Explanation of symbols]

[0085] 1 Power Tap Cell 1A,1B Power Tap Cell 2a, 2b, 2c Power tap cell group 2d, 2e, 2f Power tap cell group 3,4 Embedded power wiring 5,6 Local power wiring 7,8 Metal power wiring 9A,9B Power Termination Cell 13,14 Buried power wiring 46,47 Local wiring 46a, 46b, 47a, 47b Local wiring 107,108 Metal power wiring 111,112 Connection 121,122 Connection 202a, 202b, 202c Power tap cell group 203,204 Metal power wiring 205,206 Buried power wiring 211,212 Buried power wiring 241,242 Local wiring C Standard Cell CR cell row TCR1,TCR2 Terminal cell string VDD, VSS power supply voltage

Claims

1. a plurality of cell rows each including standard cells aligned in a first direction and arranged in a second direction perpendicular to the first direction; a plurality of buried power supply lines formed in a buried wiring layer, extending in the first direction and arranged at first predetermined intervals in the second direction, for supplying a first power supply voltage to the standard cells; a local power supply wiring formed in a local wiring layer in which local wirings in contact with a source and a drain of a transistor included in the standard cell are formed, the local power supply wiring extending in the second direction and connected to the plurality of embedded power supply wirings; a plurality of metal power supply wirings formed in a metal wiring layer above the local wiring layer, extending in the first direction, arranged at second predetermined intervals in the second direction that are larger than the first predetermined intervals, and connected to the local power supply wirings; A semiconductor integrated circuit device comprising:

2. 2. The semiconductor integrated circuit device according to claim 1, a power tap cell group including a plurality of power tap cells arranged in the second direction and provided in each of the plurality of cell rows; The plurality of power tap cells include local wiring extending in the second direction; The local power supply wiring is formed by connecting the local wirings provided in the plurality of power supply tap cells. A semiconductor integrated circuit device comprising:

3. 3. The semiconductor integrated circuit device according to claim 2, The power tap cell groups are arranged in a plurality of groups, and are arranged at equal intervals in the first direction. A semiconductor integrated circuit device comprising:

4. 2. The semiconductor integrated circuit device according to claim 1, a plurality of second buried power supply lines formed in a buried wiring layer, extending in the first direction and arranged at third predetermined intervals in the second direction, for supplying a second power supply voltage to the standard cells; a second local power supply wiring formed in the local wiring layer, extending in the second direction, and connected to the plurality of second buried power supply wirings; a plurality of second metal power supply wires formed in the metal wiring layer, extending in the first direction, and arranged at fourth predetermined intervals in the second direction that are greater than the third predetermined intervals, and connected to the second local power supply wires; A semiconductor integrated circuit device comprising:

5. 5. The semiconductor integrated circuit device according to claim 4, a power tap cell group including a plurality of power tap cells arranged in the second direction and provided in each of the plurality of cell rows; the plurality of power tap cells include first and second local wirings extending in parallel in the second direction; The local power supply wiring is formed by continuing the first local wirings provided in the plurality of power tap cells, and the second local power supply wiring is formed by continuing the second local wirings provided in the plurality of power tap cells. A semiconductor integrated circuit device comprising:

6. 5. The semiconductor integrated circuit device according to claim 4, a first power tap cell group including a plurality of first power tap cells arranged in the second direction, the first power tap cells being provided in each of the plurality of cell rows; a second power tap cell group including a plurality of second power tap cells arranged in the second direction, the second power tap cells being provided in each of the plurality of cell rows; The plurality of first power tap cells include first local wiring extending in the second direction; the plurality of second power tap cells include second local wiring extending in the second direction; The local power supply wiring is formed by continuing the first local wirings provided in the plurality of first power tap cells, and the second local power supply wiring is formed by continuing the second local wirings provided in the plurality of second power tap cells. A semiconductor integrated circuit device comprising:

7. 2. The semiconductor integrated circuit device according to claim 1, a plurality of power supply termination cells arranged in the second direction at one end of the plurality of cell rows in the first direction; The plurality of power supply termination cells include buried wiring extending in the second direction for connecting the plurality of buried power supply wirings to each other. A semiconductor integrated circuit device comprising:

8. a plurality of cell rows each including standard cells aligned in a first direction and arranged in a second direction perpendicular to the first direction; a plurality of buried power supply lines formed in a buried wiring layer, extending in the first direction and arranged at first predetermined intervals in the second direction, for supplying a first power supply voltage to the standard cells; a local power supply wiring formed in a local wiring layer in which local wiring contacting a source and a drain of a transistor included in the standard cell is formed, the local power supply wiring extending in the second direction and connected to the plurality of embedded power supply wirings; a metal power supply wiring formed in a metal wiring layer above the local wiring layer, extending in the second direction, and overlapping the local power supply wiring in a plan view; The local power supply wiring and the metal power supply wiring are connected to each other by a plurality of connection parts provided at second predetermined intervals in the second direction, the second predetermined intervals being larger than the first predetermined intervals. A semiconductor integrated circuit device comprising:

9. 9. The semiconductor integrated circuit device according to claim 8, a plurality of second buried power supply lines formed in a buried wiring layer, extending in the first direction and arranged at a third predetermined interval in the second direction, for supplying a second power supply voltage to the standard cells; a second local power supply wiring formed in the local wiring layer, extending in the second direction, and connected to the plurality of second buried power supply wirings; a second metal power supply wiring formed in the metal wiring layer, extending in the second direction, and overlapping the second local power supply wiring in a plan view; The second local power supply wiring and the second metal power supply wiring are connected to each other by a plurality of second connection parts arranged at a fourth predetermined interval in the second direction, the fourth predetermined interval being larger than the third predetermined interval. A semiconductor integrated circuit device comprising:

10. 10. The semiconductor integrated circuit device according to claim 9, The plurality of connection portions and the plurality of second connection portions are disposed at the same positions in the second direction. A semiconductor integrated circuit device comprising:

11. a plurality of cell rows each including standard cells aligned in a first direction and arranged in a second direction perpendicular to the first direction; a plurality of metal power supply wirings formed in a first metal wiring layer, extending in the first direction and arranged at first predetermined intervals in the second direction, for supplying a first power supply voltage to the standard cells; a local power supply wiring formed in a local wiring layer in which local wirings connected to a source and a drain of a transistor included in the standard cell are formed, the local power supply wiring extending in the second direction and connected to the plurality of metal power supply wirings; a buried power supply wiring formed in a buried wiring layer, extending in the second direction, overlapping with the local power supply wiring in a plan view, and connected to the local power supply wiring; an upper layer metal power supply wiring that is formed in a second metal wiring layer that is above the first metal wiring layer, extends in the second direction, and overlaps the local power supply wiring in a plan view; The local power supply wiring and the upper metal power supply wiring are connected only in the cell rows at both ends in the second direction among the plurality of cell rows. A semiconductor integrated circuit device comprising:

12. 12. The semiconductor integrated circuit device according to claim 11, a power tap cell group including a plurality of power tap cells arranged in the second direction and provided in each of the plurality of cell rows; the plurality of power tap cells include local wiring extending in the second direction and embedded wiring overlapping the local wiring in a plan view; The local power wiring is formed by connecting the local wirings included in the plurality of power tap cells, and the buried power wiring is formed by connecting the buried wirings included in the plurality of power tap cells. A semiconductor integrated circuit device comprising:

13. 13. The semiconductor integrated circuit device according to claim 12, The power tap cell groups are arranged in a plurality of groups, and are arranged at equal intervals in the first direction. A semiconductor integrated circuit device comprising:

14. 12. The semiconductor integrated circuit device according to claim 11, a plurality of second metal power supply wirings formed in the first metal wiring layer, extending in the first direction and arranged at a third predetermined interval in the second direction, for supplying a second power supply voltage to the standard cells; a second local power supply wiring formed in the local wiring layer, extending in the second direction, and connected to the plurality of second metal power supply wirings; a second buried power supply wiring formed in a buried wiring layer, extending in the second direction, overlapping with the second local power supply wiring in a plan view, and connected to the second local power supply wiring; a second upper layer metal power supply wiring formed in the second metal wiring layer, extending in the second direction, and overlapping the second local power supply wiring in a plan view; The second local power supply wiring and the second upper metal power supply wiring are connected only in the cell rows at both ends in the second direction among the plurality of cell rows. A semiconductor integrated circuit device comprising:

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