Digit verification check control during instruction execution

Abstract

A digit validation check control for executing an instruction. The process obtains an instruction that performs an operation using input values. The instruction includes a no-validation indicator for controlling whether the digit validation check control is enabled for execution of the instruction. The process executes the instruction, where executing the instruction includes determining whether the digit validation check control is enabled for execution of the instruction based on the no-validation indicator, and performing processing based on the determining. The digit validation check control is enabled based on the no-validation indicator being set to a predetermined value, and the processing includes forcing a digit check error indicator output by the executing to indicate no digit check error for at least one input value.

Description

[Technical field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and in particular to facilitating processing of digit validation check controls in the execution of an instruction. [Background technology]

[0002] Binary-coded decimal (BCD) is a common encoding of decimal numbers used across different formats such as packed and zoned decimal formats in various computer systems. For example, the number +123 (positive 123) is represented in memory as 12 3C in packed decimal format, with spaces separating the different byte values. The number 12 3C consumes two bytes of data - four 4-bit fields, with the leftmost three, or most significant 4-bit fields, holding the binary representations of the digits 1, 2, and 3, and the least significant 4-bit field holding a "C" sign code indicating a positive sign. In zoned decimal format, +123 is represented in three bytes of memory as F1 F2 C3. Each of the three bytes contains (i) a 4-bit field that holds the binary representation of the digit, and (ii) a 4-bit field that holds the zone code for that digit. The first two digits, "1" and "2", have the zone code "F" and the last digit, "3", has the sign code "C" which means positive.

[0003] It is common in programming languages ​​such as COBOL to perform conversion and move operations, especially with binary-coded decimal numbers, when manipulating formats such as zoned decimal and packed decimal. COBOL and other languages ​​usually have clear rules about whether and which validations and sign corrections should be performed for various cases. In addition to changing digit locations and setting condition codes during these operations, digit and sign codes can also be checked for validity. Using packed decimal numbers as an example, the hardware checks that all digit locations contain digits in the range 0-9, and that the least significant 4-bit field contains a sign code in the range A-F. If the check fails, a data exception is raised. Additionally or alternatively, sign correction may occur as part of these operations.

[0004] The performance of such operations has been improved by various Instruction Set Architecture instructions, such as the well-known VECTOR PERFORM SIGN OPERATION DECIMAL (VPSOP) instruction of the z / Architecture® hardware architecture provided by International Business Machines Corporation, Armonk, N.Y. However, certain situations cannot yet be handled in a desired manner by existing instructions.

[0005] For example, converting a relatively large BCD number requires several instructions to perform the conversion in parts. It may be desirable to maintain the sign of zero throughout the multiple conversion steps involved. In this regard, it is well known that the zero value may have a sign, such as positive or negative.

[0006] An example of the conversion of a relatively large (31 digit) BCD number is presented and explained. To convert a source 31 digit packed decimal number to the target zoned format, the COBOL compiler generates three UNPK instructions, e.g., UNPK1(15,8),400(8,13), UNPK15(3,8),407(2,13), UNPK16(16,8),407(9,13). The last UNPK instruction converts the last 17 digits of the source. For example, as part of an optimization procedure to optimize COBOL code compiled using newer instructions, replacing the last UNPK instruction with a vector instruction would use a VPSOP instruction to truncate the original number to 17 digits, and then use the VECTOR UNPACK ZONED (VUPKZ) instruction, which is the vector equivalent of the UNPK instruction. If the last 17 digits are all zeros, the result of the VPSOP has a positive sign regardless of the original sign of the source. This leads to undesirable results if the original number is negative.

[0007] In another example, a COBOL compiler might use a combination of MVC and OI instructions to force the sign of a BCD number and then not check the digits. However, some instructions, e.g., VPSOP, contain such a check operation, which can cause problems. For example, assume it is desired to move data from a source location (A, containing the number 12 3C) to a target location (B). An example of an original instruction as input to this sequence would be an MVC and OI instruction that moves (MVC) data from source A to target B and sets the sign code (OI) as 0xF at target B. That is, MVC B,A [B contains 12 3C after it] OI B,0xF [B contains 12 3F after it. OI is an "or-immediate" which effectively changes the sign to F]

[0008] MVC and OI do not perform data or sign validation. In contrast, some instructions, for example the VPSOP instruction used to optimize this COBOL code sequence, are configured to validate decimal numbers and throw a data exception if they are invalid. Using a scenario where source A is A1 3C, note that the "A" in "A1" is not a digit in the range 0-9. The COBOL MVC+OI sequence will properly put A1 3F into target B. However, the source input A1 3C will cause a data exception at VPSOP execution based on A not being a valid digit in the range 0-9.

[0009] Testing for and correcting the above situations can require significant resources, especially when there is a large amount of code that contains several instances of the above incompatibilities. Summary of the Invention

[0010] The shortcomings of the prior art are overcome and further advantages are provided by providing a computer program product for facilitating processing within a computing environment. The computer program product includes a computer readable storage medium readable by a processing circuit and storing instructions for performing a method. The method includes obtaining instructions for performing one or more operations using at least one input value. The instruction is a single architected instruction, and the instruction includes a no-verification indicator for controlling whether a digit verification check control is enabled for execution of the instruction. The method also includes executing the instruction. The executing the instruction includes determining whether a digit verification check control is enabled for execution of the instruction based on the no-verification indicator. The executing the instruction also includes performing a process based on the determining. The digit verification check control is enabled based on the no-verification indicator being set to a predetermined value, and the process includes forcing a digit check error indicator output by the executing to indicate no digit check error for the at least one input value. This has the advantage of controlling on a per-instruction basis whether a digit verification check error is indicated by execution of the instruction. The indication of digit check errors can be selectively enabled or disabled on a per-instruction basis, providing the ability to communicate the absence of a digit check error when a validation check would normally result in a digit check error on a valid input based on the input digit not being in the expected range (e.g., 0-9). This is advantageous, for example, in situations where the input digits are not numeric (0-9) but are a non-numeric encoding of the remaining range of values, A-F.

[0011] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0012] In some embodiments, the performing further includes performing a digit validation check on the at least one input value, the digit validation check being to verify whether the at least one input value includes a digit in a specified position, and outputting a result indicative of whether a digit check error exists for the at least one input value based on the verification.

[0013] As one possibility, based on the no-verification indicator being set to a default value, the process can process the output result of the digit verification check to indicate that there is no digit check error, regardless of whether the output result of the digit verification check indicates that there is a digit check error. Thus, when the digit verification performed as part of the instruction execution indicates that there is a digit check error, i.e., even when some digits are indicated to be in error by the digit verification check, it is possible to control whether a digit check error is output by the entire execution of the instruction. This has the advantage of providing the ability to selectively override the result provided by the digit verification check when a digit is not within the range expected by the digit verification check.

[0014] As another possibility, based on the no verification indicator being set to a default value, the process may further include sending as an input to a digit verification check at least one selected predetermined value other than the at least one input value. The at least one predetermined input is selected based on the digit verification check being configured for an output result thereof to indicate that there is no digit check error. The digit check error indicator output by the execution may include an output result of the digit verification check indicating that there is no digit check error. This has the advantage of providing a way of controlling whether a digit check error is indicated without altering the output of the verification check or an operation performed as part of the execution of the instruction.

[0015] As yet another possibility, based on the no validation indicator being set to a default value, a digit validation check of at least one input value to validate whether the at least one input value contains a digit at a default position is omitted, which has the advantage that the validation check can be avoided altogether, which may increase the execution speed, reduce resource consumption, and bring efficiency to the execution of the code.

[0016] Additional features and advantages are realized by the techniques described herein.Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

[0017] The aspects described herein are particularly pointed out by way of example and distinctly claimed in the claims at the end of this specification. These and other objects, features and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0018] [Figure 1A] FIG. 1 illustrates an example of a computing environment that incorporates and uses one or more aspects of the present invention. [Figure 1B] FIG. 1B illustrates further details of the processor of FIG. 1A in accordance with one or more embodiments of the present invention. [Diagram 2] FIG. 1 illustrates another example of a computing environment incorporating and using one or more aspects of the present invention. [Diagram 3] FIG. 2 illustrates an example of execution of an instruction based on a negative zero control indicator and a no validation indicator of the instruction, according to aspects described herein. [Figure 4A] 4 illustrates an example of a process associated with using a negative zero control index of the instruction of FIG. 3 according to aspects described herein. [Figure 4B] 4 illustrates an example of a process associated with using a no-verification indicator of the instruction of FIG. 3 according to aspects described herein. [Figure 5A] 1 illustrates features of example instructions configured in accordance with aspects described herein. [Figure 5B] 1 illustrates features of example instructions configured in accordance with aspects described herein. [Figure 5C] 1 illustrates features of example instructions configured in accordance with aspects described herein. [Figure 5D] 1 illustrates features of example instructions configured in accordance with aspects described herein. [Figure 5E] 1 illustrates features of example instructions configured in accordance with aspects described herein. [Figure 6A] FIG. 1 illustrates an example that facilitates processing in a computing environment according to aspects described herein. [Figure 6B] FIG. 1 illustrates an example that facilitates processing in a computing environment according to aspects described herein. [Figure 7A] FIG. 1 illustrates another example of a computing environment incorporating and using aspects described herein. [Figure 7B] FIG. 7B shows further details of the memory of FIG. 7A. [Figure 8] FIG. 1 illustrates one embodiment of a cloud computing environment. [Figure 9] FIG. 2 illustrates an example of an abstraction model layer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0019] In various scenarios, it may be desirable to control data validation and / or zero sign coercion in the execution of various machine instructions. In the above example involving the VPSOP instruction to optimize some compiled COBOL code, check suppression may be desirable to suppress digit validation checks on input data.

[0020] Aspects described herein provide such data validation and zero sign control, which reduces the complexity of the resulting code by providing flexibility as to whether and when these activities are performed as part of instruction execution. Additionally, control over whether these activities are performed improves performance.

[0021] According to aspects described herein, functionality is provided that facilitates processing within a computing environment. In one example, the functionality includes zero sign control, e.g., negative zero control, on a per instruction basis as part of the operation of an instruction that generates a signed zero value. The operation may include, for example, a computer operation (e.g., arithmetic-decimal, binary-coded decimal, floating point), a conversion operation (e.g., binary to decimal, decimal to binary, etc.), or a move operation (e.g., moving a decimal value from one location (e.g., a register) to another), or combinations thereof, as examples. Control over the sign of the result, and in particular whether a negative zero result can be an output of instruction execution, allows for efficient operation and allows for obtaining the desired result in all scenarios, thereby avoiding the need to perform error or other checks and improving overall performance.

[0022] In a particular example, a modifier bit in the instruction code is provided to enable or disable negative zero control, e.g., to control whether the sign of a zero result is maintained or inverted, or more specifically, to force a zero magnitude result to be output as a positive zero regardless of how it was originally signed. The modifier bit may be a "negative zero control index" as used herein. In some examples, the negative zero control index is incorporated into a new architect instruction. In other examples, the negative zero control index is incorporated into an existing architect instruction, e.g., as an extension to the known VPSOP instruction. In a particular example of the VPSOP instruction, the negative zero control index may be utilized in the maintain and complement modes / variants of the VPSOP instruction, as described herein. Maintain and complement are two of several (e.g., four) modes / variants of the current VPSOP instruction. The modes relate to the sign operation indicated by the sign code of the instruction.

[0023] According to other aspects described herein, functionality is provided to facilitate processing within a computing environment, including per-instruction digit validation check control. In certain examples, modifier bits within an instruction code are provided to control digit check error indications. These modifier bits are referred to herein as "no validation indicators." In some examples, the no validation indicator is incorporated into a new architected instruction. In other examples, the no validation indicator is incorporated into an existing architected instruction, for example, as an extension to the known VPSOP instruction.

[0024] Thus, the negative zero control index and / or no validation index may be incorporated into new instructions or may be incorporated as a modification to existing instructions, such as the existing VPSOP instruction. For existing instructions, unused or otherwise available bits within the instruction text may instead be used as the negative zero control index and / or no validation index to provide the functionality described herein.

[0025] Aspects can eliminate the performance degradation normally incurred with COBOL described above. For example, without the improvements described herein, some existing instructions, such as the combination of MVC and OI, are not extended and therefore are propagated unoptimized to code that would normally be optimized, even though the surrounding COBOL operations could be converted to more efficient instructions. In addition, if one portion of the original COBOL code is unoptimized, it may be difficult or impossible to optimize other portions of the original COBOL code if they are closely related to portions that cannot be optimized.

[0026] As an example, an instruction is part of an instruction set architecture (ISA). For example, an instruction is a single architected hardware machine instruction at a hardware / software interface. An instruction may be one of several instructions that perform a computer operation, a transform operation, a move operation, a sign operation, or other operations, or a combination thereof. Instructions are used in many types of processing, including, by way of example and not limitation, computer processing, security processing, emulation, code optimization, and performing calculations for various technologies.

[0027] According to aspects, the digit validation check control and / or the negative zero control may be enabled and disabled on a per instruction basis, for example, a negative zero control indicator and a no validation indicator may be included in (or otherwise associated with) an instruction and set on the instruction to temporarily enable the negative zero control and the digit validation check control, respectively.

[0028] One embodiment of a computing environment incorporating and using one or more aspects of the present invention is described with reference to Figure 1A. The computing environment 100 includes a processor 102 (e.g., a central processing unit), memory 104 (e.g., also referred to as main memory, system memory, main storage, central storage, or storage), and one or more input / output (I / O) devices and / or interfaces 106 coupled together, for example, via one or more buses 108 or other connections or both.

[0029] In one example, the processor 102 is based on the z / Architecture® hardware architecture provided by International Business Machines Corporation, Armonk, NY, and is part of a server, such as an IBM Z® server, also provided by International Business Machines Corporation, implementing the z / Architecture® hardware architecture. One embodiment of the z / Architecture® hardware architecture is described in the publication entitled “z / Architecture Principles of Operation”, IBM Publication, No. SA22-7832-11, 12th Edition, September 2017, which is incorporated herein by reference in its entirety. However, the z / Architecture® hardware architecture is only one example architecture, and other architectures or other types of computing environments or both may include and / or use one or more aspects of the invention. In one example, the processor executes an operating system, such as the z / OS® operating system, also provided by International Business Machines Corporation.

[0030] The processor 102 may include multiple functional components used to execute instructions. As shown in FIG. 1B, these functional components may include, for example, an instruction fetch component 120 that fetches instructions to execute, an instruction decode unit 122 that decodes the fetched instructions and obtains operands for the decoded instructions, an instruction execution component 124 that executes the decoded instructions, a memory access component 126 that accesses memory for instruction execution, if necessary, and a write back component 130 that provides results of the executed instructions. In accordance with one or more aspects of the present invention, one or more of these components may include at least a portion of or have access to one or more other components used in validity check and / or negative zero processing, including the digit verification check control processing and / or negative zero control processing described herein. The one or more other components may include, for example, a validity check component 136 and a negative zero component 138.

[0031] Another example of a computing environment incorporating and using one or more aspects of the present invention is described with reference to Figure 2. In one example, the computing environment is based on the z / Architecture® hardware architecture, although the computing environment may be based on other architectures such as those offered by International Business Machines Corporation.

[0032] 2, in one example, a computing environment includes a central electronic processing unit (CEC) 200. The CEC 200 includes multiple components, such as, for example, memory 202 (also referred to as system memory, main memory, main storage, central storage, or storage) coupled to one or more processors (also referred to as central processing units (CPUs)) 204 and an I / O subsystem 206.

[0033] Memory 202 includes one or more logical partitions 208, a hypervisor 210 that manages the logical partitions, and processor firmware 212. One example of hypervisor 210 is the Processor Resource / Systems Manager (PR / SM®) hypervisor offered by International Business Machines Corporation, Armonk, NY. As used herein, firmware includes, for example, processor microcode. Firmware includes, for example, hardware level instructions and / or data structures used in implementing higher level machine code. In one embodiment, firmware includes, for example, trusted software or microcode specific to the underlying hardware and includes proprietary code provided as microcode that controls operating system access to system hardware.

[0034] Each logical partition 208 can function as a separate system, that is, each logical partition can be reset independently, run a guest operating system 220, such as the z / OS® operating system or another operating system, and operate with different programs 222. An operating system or application program running in a logical partition has the appearance of access to a full and complete system, when in fact it can only use a portion of it.

[0035] The memory 202 is coupled to a processor (e.g., CPU) 204, which is a physical processor resource that may be assigned to a logical partition. For example, a logical partition 208 includes one or more logical processors, each of which represents all or a share of the physical processor resource 204 that may be dynamically assigned to a logical partition. In one example, the processor 204 includes a validity check component 260 that performs digit validation check control and a negative zero control component 262 that performs zero sign control, also referred to as negative zero control, as described herein.

[0036] Additionally, memory 202 is coupled to an I / O subsystem 206, which may be part of or separate from a central electronic processing unit. I / O subsystem 206 directs the flow of information between main storage 202, an input / output control unit 230, and input / output (I / O) devices 240 coupled to the central electronic processing unit.

[0037] Many types of I / O devices can be used. One particular type is a data storage device 250. The data storage device 250 can store one or more programs 252, one or more computer readable program instructions 254, or data, or a combination thereof, etc. The computer readable program instructions can be configured to perform the functions of embodiments of aspects described herein.

[0038] Computer readable program instructions configured to carry out the functions of embodiments of the aspects described herein may also, or instead, be contained in the memory 202. Many variations are possible.

[0039] The central electronic processing unit 200 may include and / or be coupled to removable / non-removable volatile / non-volatile computer system storage media. For example, the central electronic processing unit 200 may include and / or be coupled to non-removable non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive that reads from and writes to a removable non-volatile magnetic disk (e.g., a "floppy disk"), and / or an optical disk drive that reads from and writes to a removable non-volatile optical disk, such as a CD-ROM, DVD-ROM, or other optical media. It is understood that other hardware and / or software components may be used in combination with the central electronic processing unit 200. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems.

[0040] Additionally, the central electronic processing unit 200 may be operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, that may be suitable for use with the central electronic processing unit 200 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics devices, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices.

[0041] Although various examples of computing environments are described herein, one or more aspects described herein may be used in conjunction with many types of environments. The computing environments presented herein are merely examples.

[0042] According to aspects described herein, instructions executing on a processor, such as processor 102 or 204, include or have access to a per-instruction negative zero control indicator that indicates whether the negative zero control described herein is enabled for execution of the instruction. Enabling the negative zero control may cause the sign of a zero result output by executing the instruction to be negative. In a similar situation where the negative zero control is not enabled, as indicated by the negative zero control indicator, a negative-signed zero magnitude result is forced to a positive-signed zero magnitude result. In some examples, execution of the instruction performs an operation that sets the sign of the zero magnitude result to negative. Further processing of the instruction dependent on the negative zero control indicator according to aspects described herein forces a positive sign on the zero value or allows the zero result to be output with a negative sign. Thus, the negative zero control indicator may control whether negative zero is an acceptable output data result.

[0043] According to another aspect described herein, instructions executing on a processor, such as processor 102 or 204, include or have access to a per-instruction no-verification indicator that controls whether a digit verification check control is enabled for execution of the instruction. By controlling whether the digit verification check control is enabled, such digit verification checks can be disabled or enabled as desired. The digit verification check control being enabled refers to forcing execution of the instruction to indicate no digit check errors, regardless of whether digit verification performed as part of execution of the instruction indicates a digit check error.

[0044] Further details regarding the negative zero control indicator, the no validation indicator, and the processing associated therewith are described with reference to Figures 3, 4A, and 4B.

[0045] FIG. 3 illustrates an example of execution of an instruction based on a negative zero control index and a no-validation index of the instruction according to aspects described herein.

[0046] Referring initially to FIG. 3, in one embodiment, an instruction 300 includes a number of fields including a field 304 having a negative zero control indicator (NZ), a field 306 having a no validation indicator (NV), and one or more other fields included as part of the instruction text (I-text) 302. The instruction text includes, for example, operands used to perform an operation specified by the instruction text. The instruction may perform many types of operations on input data 316, including, for example, but not limited to, arithmetic operations such as decimal operations, binary coded decimal operations, floating point operations, conversion operations such as binary to decimal, decimal to binary, or move operations (e.g., move decimal), or combinations thereof. Thus, the input data 316 may be or include, for example, one or more operands from a register file, a cache, or a memory hierarchy. The one or more operands may be or include, for example, binary coded decimal data.

[0047] In another embodiment, the NZ index and the NV index are not explicit fields of the instruction, but are instead included in implicit fields or registers of the instruction. Additionally, in another embodiment, the NZ index and the NV index are not part of the instruction itself, but are in a location that is accessible to the instruction (e.g., a register or memory location) or are part of another instruction (e.g., a prefix instruction) that is used to modify the instruction to execute. Regardless of the embodiment, the NZ index and the NV index are per-instruction indexes that are specifically provided with respect to the instruction that performs one or more operations.

[0048] Note also that the instructions in the example of Figure 3 include both an NZ indicator and an NV indicator for the negative zero control and the no validation control. In other embodiments, the instructions include only one of the indicators to perform only the negative zero control or only the no validation control, as the case may be.

[0049] 3, an instruction is dispatched to an issue queue 308 of the processor's instruction sequencing unit 310 where it waits, for example, until its operands are available. Once ready, the instruction is issued to an appropriate functional execution unit 314 of the processor's execution units 312. By way of example, if the instruction is a decimal instruction, it is issued to a functional unit that performs decimal arithmetic, if the instruction is a floating point instruction, it is issued to a floating point functional unit, etc. Other examples are possible.

[0050] The execution unit 314 receives an instruction to execute, as well as an NZ control index 304 and an NV index 306. The instruction is executed to perform one or more operations, a digit check error 322 is indicated, and output data 332 is generated as a result of executing the instruction.

[0051] According to aspects described herein, the NZ control indicator is input to a zero sign control component 326 and the NV indicator is input to a logical operator, i.e., AND gate 320, used to indicate whether a digit check error is reported at 322. With respect to the NV indicator, if the digit validation check control is enabled, e.g., NV=1, to control the digit validation check and force reporting of no digit check error at 322, then the digit check error 322 will indicate no digit check error regardless of whether the digit validation check 318 indicates that there is a digit validation error. If the negative zero control is enabled, e.g., NZ=1, to indicate that negative zero is an acceptable output data result, then a positive or negative signed zero result may be the output of execution of the instruction. When the negative zero control is disabled, e.g., NZ=0, the embodiments described herein cause the sign 328 of the zero result of calculation 324 to undergo a potential reversal, e.g., from negative to positive, such that the number 330 of output data 332 has, e.g., a positive sign 328, even though the result of calculation 324 was negative zero.

[0052] The negative zero control (NZ) indicator has the effect of controlling the sign of the output zero value of the calculation 324 by enabling or disabling the negative zero control. The negative zero control being enabled refers to controlling the execution of an instruction that allows a negative zero result to be the output of the execution. When the negative zero control is disabled with the NZ indicator, this allows a specific, e.g., positive sign, to be forced into a zero magnitude result. Note that this forcing does not necessarily mean that an operation on the sign of the result output by the calculation 324 is performed, and if the result already has a positive sign, the sign will not be changed even if it receives a forced positive output. Whether or not to change the sign of the result of the calculation 324 may depend, for example, on the specific sign operation for a given instruction. For example, an instruction may be executed in different modes corresponding to a specific sign operation. One such sign operation may indicate that any result of the processing has a positive sign. In this case, a sign reversal of a zero magnitude value may occur regardless of whether NZ is enabled or not.

[0053] Thus, whether or not a sign change is made to the result computed by calculation 324 varies depending on the input data of the instruction, the calculation itself, the NZ control index, and the sign operation. In some examples, a lookup table such as that shown in Figure 5B is used to indicate whether the zero sign control 326 should invert or maintain the sign provided by calculation 324. The zero sign control 326 controls whether to maintain the sign of the zero result output by calculation 324 or to invert the sign instead.

[0054] To illustrate, take an example of a VPSOP instruction with sign operations corresponding to four modes: preserve, complement, force positive, and force negative. With force positive, the output is always positively signed. An output zero magnitude result is positively signed (e.g., 00 0C or 00 0F) regardless of whether NZ=0 or NZ=1. Thus, any zero magnitude result with a negative sign (e.g., 00 0D) is forced to positive (e.g., 00 0C or 00 0F) regardless of the value of the NZ index.

[0055] In the preserve case, the sign of the value is preserved. Conventional VPSOP processing of a negative zero, e.g., 00 0D, produces a positive zero regardless of the sign operation indicating to preserve the sign of the result. This is because conventional VPSOPs do not output zero with a negative sign. However, with the negative zero feature described herein, the result is different when negative zero control is enabled. For example, when negative zero control is not enabled (NZ=0), execution forces the positive sign to a negative zero result. The instruction outputs a positive zero in the preserve case. Instead, when NZ=1 and negative zero control is enabled, the negative zero input is preserved and output as a negative zero in accordance with the embodiments described herein. That is, when NZ=0, the negative zero result is not subject to the forced positive implementation of conventional VPSOPs or the processing described herein.

[0056] In the negative forced case, the output for a zero magnitude value is positive zero because conventional VPSOP processing does not allow a zero output to have a negative sign. Thus, an example of conventional VPSOP processing would output positive zero for an input 00 0x (x is any input sign). If NZ=0, the negative zero control is not enabled and the output is similar to conventional functionality, i.e., positive zero. However, if NZ=1 instead, the embodiments described herein allow the output of negative zero. The zero sign control 326, which is accepting the result of a zero value with a negative sign, outputs negative zero. Thus, an input 00 0x (x is any input sign) would result in an output of negative zero.

[0057] In the case of complementation, conventional VPSOP processing does not complement output negative zeros with positive zeros. However, with negative zero control enabled (e.g., NZ=1), negative zeros can be generated and output. Zero sign control 326 allows for the complementation of positive zero inputs by passing a result of zero magnitude of either sign as the output of the instruction. Thus, input positive zeros are changed to negative zeros and output as such.

[0058] Further details regarding the process associated with the negative zero control index are described with reference to Figure 4A. In one example, the process is performed by a processor, such as processor 102 or processor 204.

[0059] Referring to FIG. 4A, initially, at step 400, an instruction is issued to an execution unit of the processor (e.g., execution unit 312). At step 402, the instruction is executed by the execution unit of the processor to perform a calculation. At query 404, it is determined whether the result has a magnitude of zero (i.e., the numerical value zero). If the result does not have a magnitude of zero (404,N), then at step 410, the process outputs data, including, for example, a signed result. If instead, at 404, the result has a magnitude of zero (404,Y), then at query 406, the process determines whether NZ is equal to 0. If NZ is not equal to zero (406,N), for example, NZ=1, then the negative zero control is enabled, and thus a negative zero magnitude result along with a positive zero result is enabled and output. The process proceeds to step 410, where it outputs data, including a positive or negative signed result. Otherwise, if NZ is equal to 0 (406, Y), the negative zero control is disabled and the process proceeds to force a positive sign result in step 408 and output data including the result with the forced positive sign in step 410. Note that forcing a positive sign does not in itself imply that a change has been made to the sign of the result, and if the result was given a positive sign, no change is necessary. Even in this scenario, the positive zero result may be subject to the forced positive sign aspect of the process described (step 408) and is output therefrom as part of the output data (step 410).

[0060] In some examples, negative zero control is said to be enabled when the negative zero index is set. The negative zero control index is said to be set when it is set to a predetermined value, e.g., 1, as shown, for example, in FIG. 4A. If the negative zero control index is set to another predetermined value, e.g., zero ("0"), then negative zero control is not enabled. The particular predetermined values ​​for enabling and disabling negative zero control can vary, e.g., "0" can enable negative zero control and "1" can disable negative zero control.

[0061] 3, the validation checks 318 include a digit validation check on the input data 316 of the instruction, e.g., the input operands. A digit validation check is checking that the input operands contain valid digits, e.g., in the range 0 to 9. However, this can be problematic when valid numbers are formed by a combination of letters and numbers as digits, e.g., A represents a non-numeric encoding in the remaining range of values ​​(A to F).

[0062] According to the embodiment of FIG. 3, a verification check 318 is performed and the output is sent to an AND gate 320 to be ANDed with another input, in this case the NV indicator (or a modified version thereof, e.g., inverted). The output of the AND gate is a digit check error indicator 322. The AND gate controls whether the result of the verification check 318 sent to the AND gate is used as the digit check error 322. ANDing that result with a false value, e.g., "0", will always produce a false (e.g., "0") result for the digit check error 322. This is interpreted to mean that there is no digit check error. ANDing with a value "1" or another true value effectively produces the output of 318, i.e., a true or false digit check error depending on whether a digit check error was indicated by 318. In this manner, the result of the verification check 318 may be selectively used or not used as the digit check error 322, and this selective control is referred to herein as the "verification check control." When enabled, the control serves to control the digit check error indicator 322. If disabled, such control does not function and the digit check error indicator 322 is that indicated by, for example, the validation check 318.

[0063] In some examples, the digit validation check control is said to be enabled when the no validation control indicator is set. The no validation control indicator is said to be set, for example, when it is set to a default value, such as 1. If the no validation control indicator is set to another default value (e.g., zero), the no validation control is not enabled. The particular default values ​​for enabling and disabling the no validation control can vary, for example, "0" can enable the no validation control and "1" can disable the no validation control.

[0064] In some examples, the NV indicator is used in setting the digit check error indicator 322. In one particular example, NV is a single bit that, when set to 1, indicates that the result of the verification check 318 is suppressed, i.e., the no verification control is enabled. In cases such as FIG. 3, where an AND gate is used, the NV bit can be inverted before inputting to the AND gate 320. By inverting the 1 to a "false" value of 0, the AND gate 320 will receive at least one false value and the AND gate will output "false" as the digit check error 322, indicating that there is no digit check error. This is regardless of whether a digit check error was indicated by the verification check 318.

[0065] The use of an AND gate in FIG. 3 is just one example of controlling whether a digit check error is indicated by 322. As another example, an AND gate or other hardware circuit precedes the verification check 318 and utilizes at least the value of the NV indicator as an input. This circuit preceding the verification check may be configured to output some valid input to the verification check 318 that causes the verification check to indicate that there is no digit check error. For example, a zero value input to the verification check may indicate that there is no digit check error. In the particular example where NV=1 and the no verification control is enabled, the NV indicator is inverted to zero and input to the AND gate, and the output of the AND gate is sent as an input to the verification check 318, thereby causing the input to the verification check 318 to be zero, resulting in an output of 0 from the verification check, thereby indicating that there is no digit check error 322.

[0066] 4B, a process associated with using the no validation control is described. In one example, the process is performed by a processor, such as processor 102 or processor 204.

[0067] Referring to FIG. 4B, initially, at step 420, an instruction is issued to an execution unit of the processor (e.g., execution unit 312). At step 422, the instruction is executed by the execution unit of the processor to perform a validation check, e.g., a digit validation check. At query 424, it is determined whether a digit validation check control is enabled. The digit validation check control refers to whether or not control is applied to the digit check error indicator (322) that is output. An enabled validation check control means that no control is applied to the digit check error indicator (e.g., indicating that there is no digit check error). A disabled control means that no such control is applied to the digit check error indicator, and the digit check error indicator is, for example, that indicated by the validation check 422. In one example, this determination is made by checking a no validation (NV) indicator. If the digit validation check control is enabled (424, Y), then at step 426, the digit check error indicator is forced to indicate that there is no digit check error. In a particular example, this is accomplished by feeding the output of the digit verification check into a circuit, such as an AND gate, such that the output of the circuit is a digit check error indicator 322 indicating that there is no digit check error.

[0068] If instead it is determined that the validation check control is not enabled (424, N), then in step 428 the process uses the result of the digit validation check as the output of the digit check error indicator.

[0069] Thus, the embodiments described herein encode in the instruction word the suppression of BCD digit checking and the preservation or inversion of the BCD sign of zero magnitude results.

[0070] In the examples of Figures 3 and 4B, the digit verification check is performed unconditionally and its output can be either (i) selectively manipulated to indicate no error or (ii) passed through as an output digit check error indicator. If the no verification control is enabled, the result is suppression of the check error. However, in some embodiments, if the digit verification check control is enabled, the verification check is omitted altogether. In other words, in some scenarios, for example when the subject instruction is architecturally emulated using selected software code, the verification check 318 itself can be prevented or omitted altogether. In that case, the NV indicator can be checked and if the NV is set to a default value indicating that the digit check verification control is enabled, the software digit check process can be omitted.

[0071] As previously discussed, the negative zero control indicator and / or no validation indicator may be incorporated into new instructions or as modifications or extensions to existing instructions. One example of an instruction is a variation of the known VPSOP instruction. Figures 5A-5E illustrate features of example instructions configured in accordance with aspects described herein.

[0072] 5A illustrates an exemplary instruction format, including opcode fields 502a, 502b, a first operand field 504 for a first operand, a second operand field 506 for a second operand, intermediate data fields 508, 510, a mask field 512, and an extension field 514.

[0073] This instruction places the modified sign and a specified number of rightmost digits of the second operand into place of the first operand and sets other digits to zero. The operands and the result are in signed packed decimal format.

[0074] If the operand 2 no verify (NV) control is not 1, then all digit codes of the second operand are checked for validity. The sign code of the second operand is checked for validity based on the sign operation (SO) control, the operand 2 sign verify (SV) control, and the operand 2 no verify (NV) control, as shown in FIG. 5B, which is a table illustrating the operation of an example instruction. The table includes the following columns: sign operation (SO) 520, result magnitude (after RDC applied) 522, V2 sign 524, positive sign code (PC) 526, negative zero (NZ) 528, V2 sign code validity check 530, V2 digit code validity check to perform if 532, result sign code (hex) 534, and condition code 536.

[0075] As shown in FIG. 5B, the result sign code varies depending on the SO control, the second operand sign, the second operand digit, the result digit count (RDC) control, the positive sign code (PC) control, and the negative zero (NZ) control.

[0076] In FIG. 5B, "-" indicates that the result does not depend on this value, "a" indicates that the magnitude of the result is considered non-zero if any bit of the result is non-zero, "b" indicates that sign codes from 0 to 9 are considered invalid, "c" indicates that this will generate a suppress data exception, and "d" indicates that the table shows the condition code for non-overflow; in the case of overflow, a condition code of 3 (CC3) is given.

[0077] If the RDC control does not specify enough digits to include all of the leftmost nonzero digits of the second operand, a decimal overflow occurs. The operation is completed. The result is obtained by ignoring the overflow digit, and if the condition code set (CS) flag is 1, condition code 3 is set. If the decimal overflow mask in the PSW is 1 and the instruction overflow mask (IOM) is zero, a program interrupt occurs because of decimal overflow.

[0078] If the RDC controls specify fewer than 31 digits, the remaining leftmost digits of the first operand are filled with zeros.

[0079] The I3 field 510 of Figure 5A has an exemplary format shown in Figure 5C, which includes an instruction overflow mask (IOM) 538 and a result digit count (RDC) 540. In the particular example, the I3 field is 8 bits long, with the IOM being the first bit, bit 0, and the RDC being the last 5 bits (i.e., bits 3 through 7).

[0080] For IOM538, if the Vector-Packed-Decimal-Enhancement Facility is not installed or if bit 0 is zero, program interrupts for decimal overflow are presented according to the PSW decimal overflow mask. If the Vector-Packed-Decimal-Enhancement Facility is installed and bit 0 is one, program interrupts for decimal overflow are not recognized regardless of the value of the PSW decimal overflow mask.

[0081] Regarding RDC 540, bits 3 through 7, these contain an unsigned binary number that specifies the number of rightmost digits of the second operand that are placed into the first operand. If the magnitude of the second operand is greater than the maximum decimal number that can be represented by the specified number of digits, a decimal overflow occurs, and if the decimal overflow mask is 1, a program interrupt for decimal overflow occurs. If the RDC field is zero, a specification exception is recognized.

[0082] In this example, bits 1-2 of I3 are reserved and optional. In some cases, they contain zero. If the Vector-Packed-Decimal-Enhancement Facility is not installed, bit 0 of I3 may also be reserved and contain zero. Otherwise, a specification exception is recognized.

[0083] The I4 field 508 of FIG. 5A has an exemplary format shown in FIG. 5D.

[0084] No Validation (NV) 542 is a 1-bit field in bit 0 of the I4 field. If bit 0 is zero or the Vector-Packed-Decimal-Enhancement Facility is not installed, the digits of the second operand are checked for validity. If the SO control specifies sign preservation, the sign code of the second operand is also checked for validity. The validity of the sign code is always checked if the SO control specifies sign complement, and depends on the SV control if the SO control specifies forced positive or forced negative. If the validity check fails, a data exception is recognized. If instead bit 0 is set to "1" to indicate that the digit validation check control is enabled, the digits of the second operand are not checked for validity, or the results of any such checks are suppressed, as described herein, and the sign code of the second operand is not checked if the SO control specifies sign preservation.

[0085] Negative Zero (NZ) 544 is a 1-bit field in bit 1 of the I4 field. If bit 1 is zero or the Vector-Packed-Decimal-Enhancement Facility is not installed, then the sign of the zero result after application of the RDC will be positive. If bit 1 is instead 1, indicating that the negative zero control is enabled, e.g., NZ=1, then the sign of the zero result after application of the RDC will depend on the sign of the second operand, unless the SO control specifies forced positive or forced negative.

[0086] The sign operation (SO) 546 is a 2-bit field consisting of bits 4-5 of the I4 field. The SO bit specifies the sign operation used in determining the sign code of the result. As shown in the table of FIG. 5B, the sign code of the result varies depending on the SO control, the sign of the second operand, the digit of the second operand, the RDC control, and the PC bit.

[0087] Positive sign code (PC) 548 is a 1-bit field in bit 6 of the I4 field. If bit 6 is 1, sign code 1111 is used when the result is positive. If bit 6 is zero, sign code 1100 is used when the result is positive.

[0088] Operand 2 sign verify (SV) 550 is a 1-bit field in bit 7 of the I4 field. If bit 7 is 1 and the SO control specifies forced positive or forced negative, the sign code of the second operand is checked for validity. If bit 7 is zero and the SO control specifies forced positive or forced negative, the sign code of the second operand is not checked for validity. When the SO control specifies preserve or complement sign, the sign code of the second operand is checked for validity based on the NV bit value. If the validity check fails, a data exception is recognized.

[0089] In some cases, bits 2-3 of the I4 field are ignored, but contain zeros, otherwise the program may not behave in a future compatible manner.

[0090] The M5 field 512 of FIG. 5A has an exemplary format shown in FIG. 5E, which has a condition code set (CS) field 552. In some examples, M5 is 4 bits long, and CS 552 is a 1-bit field in bit 3, the last bit of the M5 field. When bit 3 is zero, the condition code is not set and remains unchanged. When bit 3 is one, the condition code is set as specified in the resulting condition code portion below. Bits 0-2 of the M5 field can be ignored, but may contain zeros, otherwise the program may not operate in a future compatible manner.

[0091] When the CS bit is 1, the condition code is set as follows: 0 - result is zero, no overflow, 1 - result is less than zero, no overflow, 2 - result is greater than or nonzero, invalid sign code, no overflow, 3 - overflow.

[0092] When the CS bit is zero, the condition code remains unchanged.

[0093] Examples of program exceptions include: data with DXC FE; vector instruction; data with DXC 00; general operand; decimal overflow; arithmetic (unless the Vector-Packed-Decimal Facility of the z / Architecture(R) is installed); specification; and transaction limits.

[0094] As a programming note, if the CS bit is 1, a zero result after applying RDC can always be CC0, regardless of the positive or negative sign of the zero.

[0095] As described herein, in accordance with aspects, a per-instruction negative zero control indicator is used to determine whether negative zero control is enabled. This indicator can be used to selectively enable negative zero output for instructions that would otherwise be configured to force any output zero values ​​to be positively signed. This can save additional processing cycles, reduce code length, and reduce complexity by avoiding subsequent processing corrections when output positive zeros are appropriately negatively signed.

[0096] According to another aspect, a no-validation indicator is used to determine whether the digit validation check control is enabled. The indicator can be used to selectively enable digit check suppression for instructions that would otherwise indicate a digit check error, thereby avoiding situations where digit checks would otherwise indicate a digit check error that could result in an unnecessary data exception. Avoiding such situations saves additional processing cycles and reduces code length and complexity.

[0097] In addition, by providing per-instruction indicators, user code can specify whether negative zero control and / or digit validation check control are performed for different parts of the code.

[0098] One or more aspects of the present invention are closely related to computer technology and facilitate processing in a computer to improve its performance. Providing per-instruction negative zero control improves performance, for example, by enabling updated instructions to generate the desired negative zero output, allowing the output to be used in code optimization to save additional processing cycles, reduce code length, and reduce complexity. Providing per-instruction digit validation check control improves performance, for example, by reducing the number of data exceptions received and providing flexibility to user code.

[0099] Instructions using per-instruction negative zero control and / or no-validation indicators may be included in many types of processes that perform different types of tasks. For example, the instructions may be included in internal computer processes that perform calculations, transformations, or movements, or combinations thereof, security processes that check authentication information, code emulation, code optimization, and any process that uses arithmetic operations in performing a task. There are many possibilities.

[0100] 6A and 6B illustrate an example process for facilitating processing in a computing environment according to aspects described herein. In some examples, the process is performed by one or more computer systems as described herein.

[0101] Referring to FIG. 6A, which illustrates an example process related to a negative zero control index, the process obtains an instruction to perform one or more operations using an input value (602). The one or more operations may include a particular calculation performed by the instruction, such as a data conversion, a data movement, or a sign operation on the input value, as examples. The instruction is a single architected instruction, and the instruction includes a negative zero control index that indicates whether negative zero control is enabled for execution of the instruction. In a particular example, the negative zero control index (NZ) is a bit included in the instruction text. The process then executes the instruction, for example, by first performing one or more operations using the input value to obtain a result including a sign (604). Performing the one or more operations may include setting the sign of the result. The result may be, for example, an output of a computation component (324 of FIG. 3) that is subject to zero sign control.

[0102] The process determines (606) whether the result has a magnitude of zero. If the result does not have a magnitude of zero, the process outputs (612) the signed result as part of the execution of the instruction. If not (606, Y), the process determines (608) whether to control the sign of the result, e.g., to force positive. The determination is based at least in part on whether negative zero control is enabled or disabled, and thus whether a negative zero control index (NZ) is set to a default value. If negative zero control is enabled, e.g., NZ is set to "1" to indicate that negative zero control is enabled, this allows a zero result with a negative sign to be output. As a result, the sign of the zero magnitude result (per 604) is not controlled to be forced positive. The process proceeds to output (612) the zero magnitude result with a negative or positive sign. The negative zero control index NZ may be located, for example, in a field of the instruction. In some examples, determining whether to control the sign of the zero result is further based on a selected mode for execution of the instruction, e.g., a selected sign operation of the instruction, where the selected sign operation is selected by a field of the instruction. This has the advantage of providing flexibility and selectivity as to when to force a sign change by allowing the sign of the result to be forced or independent of the selected sign operation performed by the instruction.

[0103] Thereafter, based on the determination (i.e., 608), the process performs further processing as part of the execution of the instruction. As previously described, if it is determined at 608 that the sign control forcing positive zero is not necessary, for example because negative zero control is enabled (NZ=1) and both negative and positive results are enabled for output from the execution of the instruction, then the process outputs a result having a sign set by the operation (612). Thus, the negative zero control indicator (NZ) being set to a prescribed value (e.g., "1") indicates that negative zero control is enabled for the execution of the instruction. The determination (608) may determine that the sign of the numeric zero result is not to be controlled based on negative zero control being enabled for the execution of the instruction, and thus further processing may generate an output of the execution of the instruction, the output including a numeric zero having a sign. This has the advantage that the sign provided as part of the zero result may be passed as the output of the execution without forcing any particular (e.g., positive) sign. This provides the ability to selectively override the otherwise forced positive zero and enable the output of negative zero instead. Otherwise, if it is determined at 608 that sign control is required (608, Y), for example because negative zero control is not enabled (NZ=0) and thus output of negative zero is not permitted, the process forces the sign of the zero result to be positive (610) (e.g., by unconditionally setting the sign to be positive regardless of whether it is initially positive or negative) and outputs a result having a forced positive sign (612). Thus, the negative zero control indicator (NZ) being set to another value (e.g., "0") different from the specified value "1" indicates that negative zero control is not enabled for execution of the instruction. The determination (608) may determine that the sign is controlled by forcing the sign of the numeric zero to be positive based on negative zero control not being enabled (NZ=0), and thus further processing may generate an output of execution of the instruction by forcing the sign of the numeric zero to be positive, the output including the numeric zero with a forced positive sign. This has the advantage that the forcing of the positive sign can be selectively enabled when desired.

[0104] It should be noted that by first determining (606) whether the result has a magnitude of zero, the determination (608) and further processing (610 / 612) may be selectively performed or not (i.e., omitted) depending on the result of the query 606. This has the advantage that unnecessary processing may be avoided. By omitting some processing (e.g., emulation processing that emulates a portion of the behavior of an instruction according to aspects described herein), it is possible to speed up execution time and efficiency and possibly conserve computing resources.

[0105] In a particular example, setting the sign of the zero result (i.e., as part of 604) sets the sign of the zero result to negative, and forcing (610) inverts the sign of the zero result to positive. Alternatively, performing the operation (604) sets the sign of the result to positive instead, and performing a process including forcing (610) when controlling the sign (608, Y) leaves the positive sign unchanged and outputs a result including a positive sign.

[0106] In some embodiments, the input values ​​are binary coded decimal numbers and the output of further processing and execution is a negative zero value in binary coded decimal format.

[0107] The process of Figure 6A has the advantage of controlling the sign of values ​​output by execution on a per-instruction basis: negative zero control can be selectively enabled or disabled on a per-instruction basis, providing the ability to avoid situations where instruction processing might otherwise force a particular sign (e.g., positive) onto a result even though that sign is inappropriate or undesirable.

[0108] In another exemplary embodiment, the zero sign control described herein is an extension to instructions that result in a result that already has a forced sign (e.g., positive) from a negative sign. The NZ indicator can indicate whether to make a possible "correction" back to a negative sign in this situation. This embodiment can be useful in situations where a conventional instruction is configured to impose a positive sign on a negative zero value, and an NZ function is implemented for that instruction to not modify that conventional processing, but rather the zero sign control utilizes as input a result that has already undergone a sign reversal (e.g., to a positive) by the conventional processing, and applies a correction (back to a negative sign) when appropriate. In this embodiment, the NZ indicator indicates whether the resulting zero result (with a positive sign) may have its sign reversed to negative, even if the zero is properly negatively signed (e.g., in a complementary sign operation on a positive zero), based on the instruction calculation forcing a positive sign to its zero value. For example, when NZ=1, a query on whether to reverse the sign of a negative zero result may be triggered to consider a specific sign operation for that instruction.

[0109] Referring now to FIG. 6B, which illustrates an example process related to using the no-verification control, the process obtains (620) an instruction to perform one or more operations using at least one input value. The one or more operations may include a particular calculation performed by the instruction, such as a data conversion, a data movement, or a sign operation on the input value. The instruction is a single architected instruction, and the instruction includes a no-verification indicator that can control whether the digit verification check control is enabled for execution of the instruction. In a particular example, the no-verification indicator (NV) is a bit included in the instruction text. The digit verification check control refers to controlling what is indicated based on execution of the instruction as far as digit verification check is concerned. The no-verification indicator may be located in a field of the instruction, for example. The input value may include at least one binary coded decimal number for which digit verification check is controlled according to aspects described herein.

[0110] The process then executes the instruction by determining 622 whether the digit validation check control is enabled for execution of the instruction, e.g., based on the no validation indicator. In a particular example, this determination checks whether the validation indicator is set to 1, indicating that the digit validation check control is enabled.

[0111] The process continues by executing an operation based on the determination. Thus, based on a determination that the digit validation check control is enabled (622, Y), for example, by determining that a no validation indicator (NV) is set to a predetermined value, such as 1, the process forces (624) a digit check error indicator output by execution to indicate that there are no digit check errors for at least one input value. The digit check error indicator is, for example, 322 in FIG. 3.

[0112] In certain examples, execution of the instruction further includes performing a digit verification check on the at least one input value. The digit verification check is to verify whether the at least one input value includes a digit (e.g., 0-9) in a specified position and output a result indicating whether a digit check error exists for the at least one input value based on the verification as part of the digit verification check. In certain examples, this is the output of verification check 318 in FIG. 3, a result that can be cancelled / suppressed if the digit verification check control is enabled for execution of the instruction. The output result of the digit verification check indicates whether a digit check error exists. However, based on the no verification indicator being set to a specified value, processing can process the output result of the digit verification check to indicate that there is no digit check error, regardless of whether the output result of the digit verification check indicates that there is a digit check error. In this regard, this forces the digit check error indicator to indicate that there is no digit check error. In some examples, such as that shown in FIG. 3, an AND gate unconditionally cancels the result output by the digit verification check, regardless of whether the digit check indicates a 0 or a 1 as a result. The output result of the digit verification check can be processed, for example, by reference to sending the result to an AND gate that also receives a false ("0") input to generate a false ("0") output indicating that there is no digit check error. In some examples, a value of "1" of the NV bit indicates that the digit verification check control is enabled, and thus when execution indicates that there is no digit check error, the NV value of 1 is negated to 0 and sent as a false input to the AND gate to force its output to be false. Thus, the digit check error indication output by the execution (e.g., 322) can include a processed output result of the digit verification check, which processed output result indicates that there is no digit check error. Thus, it is possible to control whether a digit check error is output by the entire execution of the instruction even when a digit verification performed as part of the instruction execution indicates that a digit check error exists, i.e., when some digits are indicated to be in error by the digit verification check.This has the advantage of providing the ability to selectively override the results produced by the digit validation check when a digit is not within the range expected by the digit validation check.

[0113] In some examples, the output of a digit verification check performed as part of the execution of the instruction is controlled by providing an input to the digit verification check that ensures that no digit check error is reported by the digit verification check. Thus, based on the no verification indicator being set to a default value indicating that the digit verification check control is enabled, the process may include sending as an input to the digit verification check at least one selected predefined value other than the at least one input value. The at least one predefined input may be selected based on a configuration of the digit verification check, i.e., based on the digit verification check being configured for its output result to indicate no digit check error based on the predefined input value. Thus, the digit check error indicator output by the execution (e.g., 322) may include an output result of the digit verification check indicating no digit check error based on the preselected input value. This has the advantage of providing a way to control whether a digit check error is indicated without altering the output or operation of the verification check performed as part of the execution of the instruction.

[0114] In some examples, the execution of the instruction proceeds in an emulated environment where the emulation of the execution of the instruction proceeds by executing specific code. Some of that code may emulate the digit validation checks (318 in FIG. 3) of the general processing of the instruction. In these circumstances, when the digit validation check control is enabled, the execution of the specific code that emulates the digit validation checks may be avoided or omitted altogether. Thus, based on the no validation indicator being set to a specified value, a digit validation check of at least one input value to verify whether the at least one input value contains a digit at a specified position is omitted. This has the advantage that the validation checks may be avoided altogether, which may increase the execution speed, reduce resource consumption, and bring efficiency to the execution of the code.

[0115] Also, as previously mentioned, the process may use the no verification indicator (NV) as an input to hardware (e.g., an AND gate) that sets the digit check error indicator (322) to indicate the absence of a digit check error. Such use may include, for example, converting the NV value "1" to a "0" which is then input to an AND gate to force a false ("0") output.

[0116] Referring back to decision 622 of FIG. 6B, the default value for enabling the digit validation check control may be a first value, and the digit validation check control is disabled and so determined based on the no validation indicator being set to a second value different from the first value (622, N). In this case, the process may perform a digit validation check on the at least one input value to verify whether the at least one input value includes a digit (0-9) in the default position, and output a result indicating whether a digit check error exists for the at least one input value based on the verification (626). Note that the digit validation check may be performed before or after decision 622.

[0117] In either case, based on the digit validation control not being enabled (622, N), the process proceeds from 626 to use the result of the digit validation check as the digit check error indicator output by execution (i.e., 322 in FIG. 3) (628). For example, if the digit validation check control is disabled, then whatever digit check error result results from the digit validation check is used as the digit check error indicator output by execution of the instruction (e.g., 322).

[0118] The process of Figure 6B has the advantage of controlling on a per-instruction basis whether a digit validation check error is indicated by execution of an instruction. The ability to selectively enable or disable the indication of a digit check error on a per-instruction basis provides the ability to communicate the absence of a digit check error when a validation check would normally result in a digit check error based on an input digit not being in an expected range (e.g., 0-9), but the digit is nevertheless valid. This is advantageous in situations where, for example, the input digit is not numeric (0-9), but is a non-numeric encoding of the remaining range of values ​​A-F.

[0119] Other variations and embodiments are possible.

[0120] Although various examples have been presented, variations are possible without departing from the spirit of the claimed aspects.

[0121] The processes described herein may be performed by one or more computer systems, individually or collectively, as described herein, and the aspects described herein may be used by many types of computing environments. Referring to FIG. 7A, another embodiment of a computing environment incorporating and using one or more aspects of the present invention is described. In this example, the computing environment 10 includes, for example, a native central processing unit (CPU) 12, memory 14, and one or more input / output devices or interfaces 16 coupled to each other, for example, via one or more buses 18 or other connection mechanisms or both. By way of example, the computing environment 10 may include a PowerPC® processor provided by International Business Machines Corporation, Armonk, NY, an HP Superdome with an Intel® Itanium II processor provided by Hewlett-Packard, Palo Alto, CA, or other machines based on architectures provided by International Business Machines Corporation, Hewlett-Packard, Intel, Oracle, etc., or combinations thereof. IBM, z / Architecture, IBM Z, z / OS, PR / SM and PowerPC are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction. Intel and Itanium are trademarks or registered trademarks of Intel or its subsidiaries in the United States and / or other countries.

[0122] The native central processing unit 12 includes one or more native registers 20, such as one or more general purpose registers and / or one or more special purpose registers, that are used during processing within the environment. These registers contain information that represents the state of the environment at any particular time.

[0123] Additionally, the native central processing unit 12 executes instructions and code stored in memory 14. In one particular example, the central processing unit executes emulator code 22 stored in memory 14. This code allows a computing environment configured in one architecture to emulate another architecture. For example, the emulator code 22 allows machines based on architectures other than the z / Architecture® hardware architecture, such as PowerPC processors, HP Superdome servers, etc., to emulate the z / Architecture® hardware architecture and execute software and instructions developed based on the z / Architecture® hardware architecture.

[0124] Further details regarding emulator code 22 are described with reference to FIG. 7B. Guest instructions 30 stored in memory 14 include software instructions (e.g., interrelated with machine instructions) developed to execute on an architecture other than that of native CPU 12. For example, guest instructions 30 may be designed to execute on a processor based on the z / Architecture® hardware architecture, but are instead emulated on native CPU 12, which may be, for example, an Intel® Itanium II processor. In one example, emulator code 22 includes an instruction fetch routine 32 for retrieving one or more guest instructions 30 from memory 14, and possibly providing local buffering for the retrieved instructions. It also includes an instruction conversion routine 34 for determining the type of the retrieved guest instruction and converting the guest instruction into one or more corresponding native instructions 36. This conversion includes, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform the function.

[0125] Additionally, emulator code 22 includes an emulation control routine 40 for causing native instructions to be executed. Emulation control routine 40 may cause native CPU 12 to execute a routine of native instructions that emulates one or more previously fetched guest instructions, and at the end of such execution, return control to an instruction fetch routine for emulating the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 36 may include loading data from memory 14 into a register, storing data from a register back to memory, or performing some type of arithmetic or logical operation, as determined by the translation routine.

[0126] Each routine may be implemented, for example, in software stored in memory and executed by native central processing unit 12. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or some combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 20 or using locations in memory 14. In an embodiment, guest instructions 30, native instructions 36, and emulator code 22 may be in the same memory or may be distributed across different memory devices.

[0127] The above computing environments are only examples of computing environments that may be used: other environments may be used, including, but not limited to, non-partitioned, partitioned, or emulated environments, or combinations thereof, and embodiments are not limited to any one environment.

[0128] Each computing environment may be configured to include one or more aspects of the present invention. For example, in accordance with one or more aspects of the present invention, each computing environment may be configured to perform overflow processing.

[0129] Although this disclosure includes a detailed description of cloud computing, it should be understood that implementation of the teachings described herein is not limited to a cloud computing environment. Rather, embodiments of the invention may be implemented in conjunction with any other type of computing environment now known or later developed.

[0130] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computational resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) and the ability to rapidly provision and release these resources with minimal administrative effort or interaction with a service provider. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0131] Its features are as follows:

[0132] On-Demand Self-Service: Cloud consumers can unilaterally and automatically provision computing capacity, such as server time and network storage, on an as-needed basis, without the need for human interaction with the service provider.

[0133] Broad network access: Functionality is available over the network and can be accessed through standard mechanisms, facilitating use by heterogeneous thin-client or thick-client platforms (e.g., cell phones, laptops, and PDAs).

[0134] Resource Pooling: Provider computing resources are pooled and offered to multiple consumers using a multi-tenant model. Different physical and virtual resources are dynamically allocated and reallocated according to demand. Consumers typically have no control or knowledge of the exact location of the resources offered to them, although there is a sense of location independence in that they may be able to specify location at a higher level of abstraction (e.g. country, state, data center).

[0135] Rapid Elasticity: Capabilities can be provisioned quickly and elastically, in some cases automatically, scaled out quickly, and released quickly to scale in quickly. To the consumer, the capabilities available for provisioning often appear unlimited, and any amount can be purchased at any time.

[0136] Metered Services: Cloud systems automatically control and optimize resource usage by leveraging metering capabilities at an abstraction level appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). Resource usage can be monitored, controlled, and reported, providing transparency to both providers and consumers of utilized services.

[0137] The service model is as follows:

[0138] Software as a Service (SaaS): The functionality provided to the consumer is the use of the provider's applications running on a cloud infrastructure. The applications are accessible from a variety of client devices through thin-client interfaces such as web browsers (e.g., web-based email). The consumer has no management or control over the underlying cloud infrastructure, including networks, servers, operating systems, storage, or individual application features, except for limited user-specific application configuration settings.

[0139] Platform as a Service (PaaS): The functionality offered to the consumer is the deployment onto a cloud infrastructure of applications that the consumer creates or acquires, written using programming languages ​​and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does control the deployed applications and, in some cases, the configuration of the application hosting environment.

[0140] Infrastructure as a Service (IaaS): The functionality provided to the consumer is the provisioning of processing, storage, network, and other basic computing resources over which the consumer can deploy and run any software, which may include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but does control the operating systems, storage, and deployed applications, and possibly has limited control over selected network components (e.g., host firewalls).

[0141] The deployment models are as follows:

[0142] Private Cloud: The cloud infrastructure is operated exclusively for the organization. It can be managed by the organization or a third party and can reside on-premise or off-premise.

[0143] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with common concerns (e.g., mission, security requirements, policies, and compliance concerns). This cloud infrastructure can be managed by these organizations or by a third party and can exist on-premise or off-premise.

[0144] Public Cloud: This cloud infrastructure is available for use by the general public or large industry entities and is owned by an organization that sells cloud services.

[0145] Hybrid Cloud: This cloud infrastructure is a composite of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that allow data and application portability (e.g., cloud bursting for load balancing between clouds).

[0146] Cloud computing environments are service-oriented with a focus on statelessness, loose coupling, modularity, and semantic interoperability. At the heart of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0147] Referring now to FIG. 8, an exemplary cloud computing environment 50 is shown. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10 with which a local computing device used by a cloud consumer, such as, for example, a personal digital assistant (PDA) or cell phone 54A, a desktop computer 54B, a laptop computer 54C, or an automobile computer system 54N, or combinations thereof, can communicate. The nodes 10 can communicate with each other. These nodes 10 may be physically or virtually grouped (not shown) in one or more networks, such as a private, community, public, or hybrid cloud, or combinations thereof, as described above. This enables the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service for which the cloud consumer does not need to maintain resources on the local computing device. It will be understood that the types of computing devices 54A-54N shown in FIG. 8 are intended to be illustrative only, and that the computing node 10 and cloud computing environment 50 may communicate with any type of computerized device over any type of network and / or network-addressable connections (e.g., using a web browser).

[0148] Referring now to Figure 9, a set of functional abstraction layers provided by cloud computing environment 50 (Figure 8) is shown. It should be understood in advance that the components, layers, and functions shown in Figure 9 are intended to be illustrative only and that embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0149] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframes 61, reduced instruction set computing (RISC) architecture based servers 62, servers 63, blade servers 64, storage devices 65, and networks and network components 66. In some embodiments, the software components include network application server software 67 and database software 68.

[0150] The virtualization layer 70 provides an abstraction layer that can provide examples of the following virtual entities: virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75.

[0151] In one example, the management layer 80 may provide the following functions: Resource provisioning 81 provides dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 provides cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. In one example, these resources may include application software licenses. Security provides identity verification for cloud consumers and tasks and protection of data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management to ensure required service levels are met. Service level agreement (SLA) planning and fulfillment 85 provides advance arrangement and procurement for cloud computing resources for anticipated future demand according to SLAs.

[0152] The workload layer 90 provides examples of functionality for which a cloud computing environment can be utilized. Examples of workloads and functions that may be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instructional delivery 93, data analytics processing 94, transaction processing 95, and negative zero / no validation processing 96.

[0153] The present invention may be a system, method, or computer program product, or a combination thereof, at any possible level of integration of technical details. The computer program product may include a computer-readable storage medium having computer-readable program instructions stored thereon for causing a processor to perform aspects of the present invention.

[0154] A computer readable storage medium may be a tangible device capable of holding and storing instructions for use by an instruction execution device. A computer readable storage medium may be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. A non-exhaustive list of more specific examples of computer readable storage media includes the following: portable computer diskettes, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), static random access memories (SRAM), portable compact disk read-only memories (CD-ROM), digital versatile disks (DVD), memory sticks, floppy disks, mechanically encoded devices such as punch cards or ridge structures in grooves in which instructions are recorded, and any suitable combination thereof. As used herein, a computer-readable storage medium should not be construed as a transitory signal per se, such as electric waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or electrical signals transmitted over electrical wires.

[0155] The computer readable program instructions described herein may be downloaded from a computer readable storage medium into each computing / processing device or may be downloaded to an external computer or storage device over a network, such as the Internet, a local area network, a wide area network, or a wireless network, or a combination thereof. The network may include copper transmission cables, optical transmission fiber, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface in each computing / processing device receives the computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0156] The computer readable program instructions for carrying out the operations of the present invention may be source or object code written in any combination of one or more programming languages, including assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, configuration data for an integrated circuit, or object oriented programming languages ​​such as Smalltalk®, C++, and procedural programming languages ​​such as the “C” programming language or similar programming languages. The computer readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or remote server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry to carry out aspects of the invention.

[0157] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0158] These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, executed by the processor of the computer or other programmable data processing apparatus, produce means for performing the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams. These computer readable program instructions may be stored on a computer readable medium, such that the computer readable storage medium on which the instructions are stored includes an article of manufacture containing instructions for performing aspects of the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams, directing a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner.

[0159] The computer readable program instructions may be loaded into a computer, other programmable data processing apparatus, or other device to cause the computer, other programmable apparatus, or other device to perform a series of operational steps to produce a computer-implemented process such that the instructions, which execute on the computer, other programmable apparatus, or other device, perform the functions / operations specified in one or more blocks of the flowcharts and / or block diagrams.

[0160] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, including one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions shown in the blocks may be performed out of the order shown in the figures. For example, two blocks shown in succession may in fact be executed substantially simultaneously, or the blocks may sometimes be executed in the reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams and / or flowchart illustrations, as well as combinations of blocks in the block diagrams and / or flowchart illustrations, may be implemented by a dedicated hardware-based system that performs the specified functions or operations, or executes a combination of dedicated hardware instructions and computer instructions.

[0161] In addition to the above, one or more aspects may be provided, offered, deployed, managed, maintained, etc., by a service provider that provides management of a customer environment. For example, a service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from the customer, for example based on a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0162] In one aspect, an application may be deployed to execute one or more embodiments. As an example, deploying an application includes providing a computer infrastructure operable to execute one or more embodiments.

[0163] As a further aspect, a computing infrastructure may be deployed that includes computer readable code embedded in a computing system that in combination with the computing system is capable of executing one or more embodiments.

[0164] In yet another aspect, a process can be provided for implementing a computing infrastructure, the process comprising incorporating computer readable code into a computer system, the computer system including a computer readable medium, the computer medium including one or more embodiments, the code being capable of performing one or more embodiments in combination with the computer system.

[0165] Although various embodiments have been described above, these are merely examples, and other architectures of computing environments can be used to incorporate and use one or more embodiments.

[0166] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," as used herein, specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof, or combinations thereof.

[0167] Corresponding structures, materials, operations, and equivalents of all means or step-plus-function elements within the scope of the following claims are intended to include any structure, material, or operation for performing a function in combination with other claimed elements, when present, as specifically claimed. The description of one or more embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Many modifications and variations will be apparent to those skilled in the art. The embodiments have been selected and described in order to best explain the various aspects and practical applications, and to enable others skilled in the art to understand the various embodiments with various modifications as suitable for the particular use under consideration.

Claims

1. A computer readable storage medium having recorded thereon a computer program for facilitating processing within a computing environment, the computer readable storage medium being readable by a processing circuit and storing instructions for performing a method, the method comprising: obtaining an instruction for performing one or more operations using at least one input value, the instruction being a single architected instruction, the instruction including a no-verification indicator for controlling whether a digit verification check control is enabled for execution of the instruction, separate from a sign verification indicator for controlling a sign verification check in which the validity of a sign of an operation result is verified; Executing the instructions, determining whether a digit validation check control is enabled for execution of the instruction based on the no validation indicator; performing an operation based on said determining, said operation including: based on said no validation indicator being set to a default value, a digit validation check control is enabled, said operation forcing a digit check error indicator output by said executing to indicate no digit check error for said at least one input value. wherein, unless the no verification indicator is set to the predetermined value, the sign verification check is performed if a sign arithmetic control specifies a maintain or complement sign, and is performed depending on a setting of the sign verification indicator if the sign arithmetic control specifies a force positive or force negative sign.

23. A computer-readable storage medium comprising:

2. 2. The computer-readable storage medium of claim 1, wherein said executing further comprises performing a digit verification check on the at least one input value, the digit verification check verifying whether the at least one input value includes a digit in a specified position, and outputting a result indicative of whether a digit check error exists for the at least one input value based on the verification.

3. 3. The computer-readable storage medium of claim 2, wherein based on the no validation indicator being set to the specified value, the process processes an output result of the digit validation check to indicate that there is no digit check error regardless of whether the output result of the digit validation check indicates that a digit check error exists.

4. 4. The computer-readable storage medium of claim 3, wherein the digit check error indication output from the executing comprises the processed output result of the digit verification check indicating no digit check error.

5. 3. The computer-readable storage medium of claim 2, wherein the processing further comprises sending as an input to the digit verification check at least one selected predetermined value other than the at least one input value based on the no verification indicator being set to the specified value, the at least one predetermined input being selected based on the digit verification check being configured with an output result indicating no digit check error, and the digit check error indicator output by the executing comprises the output result of the digit verification check indicating no digit check error.

6. 2. The computer-readable storage medium of claim 1, wherein a digit verification check of the at least one input value to verify whether the at least one input value contains a digit at a specified position is omitted based on the no validation indicator being set to the specified value.

7. 2. The computer-readable storage medium of claim 1, wherein the at least one input value comprises at least one binary coded decimal number.

8. The computer-readable storage medium of claim 1 , wherein the no-validation indicator is located in a field of the instruction.

9. 2. The computer-readable storage medium of claim 1, wherein performing the process uses the no validation control indicator as an input to hardware that sets the digit check error indicator to indicate the absence of a digit check error.

10. the digit validation check control is disabled based on the specified value being a first value and the no validation indicator being set to a second value different from the first value; The process, performing a digit verification check on the at least one input value, the digit verification check comprising verifying whether the at least one input value includes a digit at a specified position, and outputting a result indicative of whether a digit check error exists for the at least one input value based on the verification; using the result of the digit verification check as the digit check error indicator output by the executing. The computer-readable storage medium of claim 1 , comprising:

11. 1. A computer system for facilitating processing within a computing environment, comprising: Memory, a processor coupled to the memory; wherein the computer system comprises: obtaining an instruction for performing one or more operations using at least one input value, the instruction being a single architected instruction, the instruction including a no-verification indicator for controlling whether a digit verification check control is enabled for execution of the instruction, separate from a sign verification indicator for controlling a sign verification check in which the validity of a sign of an operation result is verified; Executing the instructions, determining whether a digit validation check control is enabled for execution of the instruction based on the no validation indicator; performing an operation based on said determining, said operation including: based on said no validation indicator being set to a default value, a digit validation check control is enabled, said operation forcing a digit check error indicator output by said executing to indicate no digit check error for said at least one input value. wherein, unless the no verification indicator is set to the predetermined value, the sign verification check is performed if a sign arithmetic control specifies a maintain or complement sign, and is performed depending on a setting of the sign verification indicator if the sign arithmetic control specifies a force positive or force negative sign.

23. A computer system configured to perform a method comprising:

12. 12. The computer system of claim 11, wherein said executing further comprises performing a digit verification check on said at least one input value, said digit verification check verifying whether said at least one input value includes a digit in a specified position, and outputting a result indicative of whether a digit check error exists for said at least one input value based on said verification.

13. 13. The computer system of claim 12, wherein based on the no validation indicator being set to the specified value, the processing processes an output result of the digit validation check to indicate that there is no digit check error regardless of whether the output result of the digit validation check indicates that a digit check error exists, and the digit check error indicator output by the executing comprises the processed output result of the digit validation check indicating that there is no digit check error.

14. 13. The computer system of claim 12, wherein the processing further comprises sending as an input to the digit verification check at least one selected predetermined value other than the at least one input value based on the no verification indicator being set to the specified value, the at least one predetermined input being selected based on the digit verification check being configured with an output result indicating no digit check error, and the digit check error indicator output by the executing comprises the output result of the digit verification check indicating no digit check error.

15. 12. The computer system of claim 11, wherein the at least one input value comprises at least one binary coded decimal number.

16. 12. The computer system of claim 11, wherein performing the process uses the no validation control indicator as an input to hardware that sets the digit check error indicator to indicate the absence of a digit check error.

17. 1. A computer-implemented method for facilitating processing within a computing environment, comprising: obtaining an instruction for performing one or more operations using at least one input value, the instruction being a single architected instruction, the instruction including a no-verification indicator for controlling whether a digit verification check control is enabled for execution of the instruction, separate from a sign verification indicator for controlling a sign verification check in which the validity of a sign of an operation result is verified; Executing the instructions, determining whether a digit validation check control is enabled for execution of the instruction based on the no validation indicator; performing an operation based on said determining, said operation including: based on said no validation indicator being set to a default value, a digit validation check control is enabled, said operation forcing a digit check error indicator output by said executing to indicate no digit check error for said at least one input value. wherein, unless the no verification indicator is set to the predetermined value, the sign verification check is performed if a sign arithmetic control specifies a maintain or complement sign, and is performed depending on a setting of the sign verification indicator if the sign arithmetic control specifies a force positive or force negative sign. A method comprising:

18. 18. The method of claim 17, wherein said performing further comprises performing a digit verification check on said at least one input value, said digit verification check verifying whether said at least one input value includes a digit in a specified position, and outputting a result indicative of whether a digit check error exists for said at least one input value based on said verification.

19. 20. The method of claim 18, wherein based on the no validation indicator being set to the specified value, the processing processes an output result of the digit validation check to indicate that there is no digit check error regardless of whether the output result of the digit validation check indicates that a digit check error exists, and the digit check error indicator output by the executing comprises the processed output result of the digit validation check indicating that there is no digit check error.

20. 20. The method of claim 18, wherein the processing further comprises sending as an input to the digit verification check at least one selected predetermined value other than the at least one input value based on the no verification indicator being set to the specified value, the at least one predetermined input being selected based on the digit verification check being configured with an output result indicating no digit check error, and the digit check error indicator output by the executing comprises the output result of the digit verification check indicating no digit check error.

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