Circuit device and oscillator

Abstract

To provide a circuit device and the like capable of improving linearity of a capacitance value of a variable capacitance circuit for controlling an oscillation frequency.SOLUTION: A circuit device 20 includes a processing circuit 60 that generates capacitance control data CTD, and an oscillation circuit 30. The oscillation circuit 30 has a variable capacitance circuit 31 whose capacitance value is variably controlled on the basis of the capacitance control data CTD, an oscillation frequency of the oscillation circuit 30 being controlled by the capacitance value of the variable capacitance circuit 31. The variable capacitance circuit 31 has a capacitor array. The capacitor array has: a plurality of capacitors with binary weighted capacitance value for each capacitor; and a plurality of switches on / off-controlled on the basis of the capacitance control data CTD. The processing circuit 60 outputs the capacitance control data CTD that is subjected to a dithering process so as to switch the capacitance value of the variable capacitance circuit 31 between a first capacitance value and a second capacitance value in a time-division manner.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a circuit device, an oscillator, and the like. [Background technology]

[0002] A temperature-compensated oscillator is known in which a capacitor array is connected to an oscillation node of an oscillation circuit, and the capacitance value of the capacitor array is controlled according to temperature to temperature-compensate the oscillation frequency. The digital temperature-compensated oscillator disclosed in Patent Document 1 includes a plurality of first capacitance elements having the same capacitance value and a second capacitance element having a capacitance value of 1 / (n+1) of the capacitance value of the first capacitance element in order to perform precise control using a small number of capacitance elements. A capacitor array is formed by the plurality of first capacitance elements and the second capacitance element, and the digital temperature-compensated oscillator temperature-compensates the oscillation frequency by controlling the capacitance value of the capacitor array according to temperature. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 5-218738 Summary of the Invention [Problem to be solved by the invention]

[0004] In temperature compensation using a capacitor array, the linearity of the capacitance value of the capacitor array affects the compensation accuracy of temperature compensation. It is possible to use a configuration in which the capacitance value of each capacitor is weighted in binary as the capacitor array. For example, assume that the capacitance value corresponding to the LSB is C, and the capacitor array has capacitors of C, 2C, 4C, and 8C. In this case, for example, when switching between a state in which C+2C+4C=7C is selected and a state in which 8C is selected, or when switching between a state in which C+2C=3C is selected and a state in which 4C is selected, there is a problem that the linearity of the capacitance value is likely to decrease due to the influence of parasitic capacitance or manufacturing variation. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a circuit device that includes a processing circuit that generates capacitance control data, and an oscillation circuit having a variable capacitance circuit whose capacitance value is variably controlled based on the capacitance control data and whose oscillation frequency is controlled by the capacitance value of the variable capacitance circuit, wherein the variable capacitance circuit has a capacitor array, and the capacitor array has a plurality of capacitors, each of which has a capacitance value weighted binary, and a plurality of switches that are arranged in series with the plurality of capacitors between an oscillation node and a ground node of the oscillation circuit and are controlled to be turned on and off based on the capacitance control data, and the processing circuit outputs the capacitance control data that has been dithered so as to switch the capacitance value of the variable capacitance circuit between a first capacitance value and a second capacitance value in a time-division manner.

[0006] Another aspect of the present disclosure relates to an oscillator including the circuit device described above and an oscillator that oscillates when driven by the oscillation circuit. [Brief description of the drawings]

[0007] [Figure 1] 1 shows configuration examples of a circuit device and an oscillator. [Diagram 2] 3 shows a detailed configuration example of an oscillator circuit and a variable capacitance circuit. [Diagram 3]1 shows a first detailed configuration example of a capacitor array. [Figure 4] A detailed example of a capacitor configuration. [Diagram 5] A detailed example of a capacitor configuration. [Figure 6] A detailed example of a capacitor configuration. [Figure 7] 1 shows an example of a configuration of an elementary capacitor that constitutes a capacitor and an elementary switch that constitutes a switch. [Figure 8] The capacitance value of the variable capacitance circuit with respect to the capacitance control data when dither processing is not performed by the dither processing unit. [Figure 9] 4 is a timing chart illustrating the operation of the processing circuit. [Figure 10] 6 shows the capacitance value of the variable capacitance circuit relative to capacitance control data when the dither processing of the present embodiment is applied. [Figure 11] A first detailed configuration example of the processing circuit and memory. [Figure 12] 2 shows a second detailed configuration example of a capacitor array. [Figure 13] 2. A second detailed configuration example of the processing circuitry and memory. [Figure 14] 6 is an example of a second table stored in a time division pattern storage section. [Figure 15] 10 is a timing chart illustrating the operation of a processing circuit in the second detailed configuration example. [Figure 16] The capacitance value of the variable capacitance circuit with respect to the capacitance control data when dither processing is not performed by the dither processing unit. [Figure 17] 13 shows the capacitance value of the variable capacitance circuit relative to the capacitance control data when dither processing of the second detailed configuration example is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A preferred embodiment of the present disclosure will be described in detail below. Note that the embodiment described below does not unduly limit the contents described in the claims, and all of the configurations described in the embodiment are not necessarily essential configurations.

[0009] 1.Circuit device 1 shows an example of the configuration of a circuit device 20 and an oscillator 4. The oscillator 4 includes a circuit device 20 and a resonator 10.

[0010] The circuit device 20 is an integrated circuit device called an IC (Integrated Circuit). For example, the circuit device 20 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which circuit elements are formed on a semiconductor substrate. The circuit device 20 includes an oscillation circuit 30, a temperature sensor circuit 45, a processing circuit 60, and a memory 70. The temperature sensor circuit may be provided outside the circuit device 20. In this case, temperature detection data is input to the circuit device 20 from the outside.

[0011] The temperature sensor circuit 45 detects the temperature and outputs temperature detection data DTD indicating the result. The temperature detection data DTD is data that monotonically increases or decreases with respect to the temperature. The temperature sensor circuit 45 includes, for example, a temperature sensor and an A / D conversion circuit. The temperature sensor outputs a temperature detection voltage whose voltage value changes according to the temperature by using the temperature dependency of the forward voltage of the PN junction. The A / D conversion circuit A / D converts the temperature detection voltage and outputs the result as the temperature detection data DTD. Alternatively, the temperature sensor circuit 45 includes a ring oscillator and a counter. The oscillation frequency of the ring oscillator has temperature dependency. The counter counts the output pulse signal, which is the oscillation signal of the ring oscillator, during a count period defined by a clock signal based on the oscillation signal of the oscillation circuit 30, and outputs the count value as the temperature detection data DTD.

[0012] The oscillation circuit 30 has a variable capacitance circuit 31 formed of a capacitor array, and oscillates at an oscillation frequency corresponding to the capacitance value of the variable capacitance circuit 31. The capacitance value of the variable capacitance circuit 31 is controlled so that the oscillation frequency is constant against temperature fluctuations, thereby temperature compensating the oscillation frequency. The oscillation circuit 30 oscillates the vibrator 10 electrically connected to the oscillation circuit 30. Specifically, the circuit device 20 includes a first terminal and a second terminal, and one end of the vibrator 10 is connected to the oscillation circuit 30 via the first terminal, and the other end of the vibrator 10 is connected to the oscillation circuit 30 via the second terminal. As the oscillation circuit 30, various types of oscillation circuits can be used, such as a Pierce type, a Colpitts type, an inverter type, or a Hartley type.

[0013] The vibrator 10 is an element that generates mechanical vibration by an electrical signal. The vibrator 10 can be realized by a vibrating piece such as a quartz crystal vibrating piece. For example, the vibrator 10 is a tuning fork type quartz crystal vibrating piece. Alternatively, the vibrator 10 can be realized by a quartz crystal vibrating piece that has a cut angle of AT cut or SC cut, etc., that vibrates in a thickness shear manner. The vibrator 10 of this embodiment can be realized by various vibrating pieces such as a vibrating piece other than a tuning fork type or a thickness shear vibration type, or a piezoelectric vibrating piece formed of a material other than quartz. For example, the vibrator 10 may be a SAW resonator or a MEMS vibrator as a silicon vibrator formed using a silicon substrate. SAW is an abbreviation for Surface Acoustic Wave, and MEMS is an abbreviation for Micro Electro Mechanical Systems.

[0014] The processing circuit 60 performs capacitance control for the variable capacitance circuit 31 based on the temperature detection data DTD. The processing circuit 60 includes a temperature compensation section 63 and a dither processing section 65. The temperature compensation section 63 performs temperature compensation processing based on the temperature detection data DTD and information stored in the memory 70, and outputs the result as temperature-compensated capacitance control data. The temperature-compensated capacitance control data is input to the dither processing section 65 as input capacitance control data. The dither processing section 65 performs dither processing on the input capacitance control data, and outputs the result as dither processed capacitance control data. The processing circuit 60 may output the dither processed capacitance control data as capacitance control data CTD, or may further process the dither processed capacitance control data and then output it as capacitance control data CTD. The capacitance value of the variable capacitance circuit 31 is set to a capacitance value indicated by the capacitance control data CTD.

[0015] The processing circuit 60 is a logic circuit configured with logic elements such as an AND circuit, an OR circuit, an inverter, and a latch circuit. The temperature compensation unit 63, the dither processing unit 65, etc. may each be configured with an individual logic circuit. Alternatively, the processing of the temperature compensation unit 63, the dither processing unit 65, etc. may be executed by a DSP. DSP is an abbreviation for Digital Signal Processor. In this case, the functions of the temperature compensation unit 63, the dither processing unit 65, etc. are realized by the DSP executing a program describing the functions of the temperature compensation unit 63, the dither processing unit 65, etc.

[0016] The memory 70 stores information used when the processing circuit 60 generates the capacity control data CTD based on the temperature detection data DTD. The information stored in the memory 70 includes a lookup table that associates the temperature detection data DTD with a capacity adjustment value. The processing circuit 60 obtains a capacity adjustment value corresponding to the temperature detection data DTD from the lookup table, and outputs the temperature-compensated capacity control data by performing a process such as linear interpolation on the capacity adjustment value. The memory 70 is, for example, a nonvolatile memory. In this case, the above information is written to the nonvolatile memory during the manufacture of the oscillator 4. The nonvolatile memory may be, for example, an EEPROM (Electrically Erasable Programmable Read Only Memory), a flash memory, or a fuse memory. Alternatively, the memory 70 may be a RAM (Random Access Memory) or a register. In this case, the above information is written to the RAM or the register from an external host device or the like.

[0017] In this embodiment, the connection is an electrical connection. An electrical connection is a connection that allows an electrical signal to be transmitted, and is a connection that allows information to be transmitted by an electrical signal. The electrical connection may be a connection via a passive element or an active element.

[0018] 2 is a detailed configuration example of the oscillator circuit 30 and the variable capacitance circuit 31. The oscillator circuit 30 includes a variable capacitance circuit 31 and a drive circuit 32. Here, the number of bits of the capacitance control data CTD is 11, but the number of bits of the capacitance control data CTD may be, for example, 3 or more.

[0019] The driving circuit 32 drives the oscillator 10 to oscillate the oscillator 10, and outputs a clock signal CLK obtained by the oscillation to a node NQ. The node NQ is an output node of the oscillation circuit 30. An input node N1 of the driving circuit 32 is connected to one end of the oscillator 10, and an output node N2 of the driving circuit 32 is connected to the other end of the oscillator 10.

[0020] The drive circuit 32 includes an inverter INV and resistors R1 and R2. An input node of the inverter INV and one end of the resistor R1 are connected to an input node N1 of the drive circuit 32. An output node of the inverter INV and the other end of the resistor R1 are connected to a node NQ. One end of the resistor R2 is connected to the node NQ, and the other end of the resistor R2 is connected to an output node N2 of the drive circuit 32.

[0021] The variable capacitance circuit 31 is connected to an input node N1 and an output node N2 of the drive circuit 32. The capacitance value of the variable capacitance circuit 31 changes based on the capacitance control data CTD[10:0], thereby changing the load of the drive circuit 32 and changing the oscillation frequency of the oscillation circuit 30. This realizes temperature compensation of the oscillation frequency. The variable capacitance circuit 31 includes a capacitor array CPA1 connected to the input node N1 of the drive circuit 32 and a capacitor array CPA2 connected to the output node N2 of the drive circuit 32. The capacitor arrays CPA1 and CPA2 are set to the same capacitance value by the capacitance control data CTD[10:0]. It is to be noted that only one of the capacitor arrays CPA1 and CPA2 may be provided.

[0022] A node in the oscillation loop of the oscillation circuit 30 to which the capacitor array is connected is also called an oscillation node. In Fig. 2, the input node N1 or the output node N2 is the oscillation node.

[0023] 3 shows a first detailed configuration example of the capacitor array CPA1. The capacitor array CPA2 has a similar configuration, so the capacitor array CPA1 will be taken as an example for explanation.

[0024] The capacitor array CPA1 includes capacitors CC1 to CC11 and switches SW1 to SW11. The number of capacitors and switches is not limited to this, and the capacitor array CPA1 only needs to include first to n-th capacitors and first to n-th switches. n is an integer of 2 or more, and is, for example, the number of bits of the capacitance control data CTD.

[0025] One end of the capacitor CC1 is connected to an input node N1 of the drive circuit 32, the other end of the capacitor CC1 is connected to one end of the switch SW1, and the other end of the switch SW1 is connected to a ground node NGN. Similarly, one ends of the capacitors CC2 to CC11 are connected to the input node N1, the other ends of the capacitors CC2 to CC11 are connected to one ends of the switches SW2 to SW11, respectively, and the other ends of the switches SW2 to SW11 are connected to the ground node NGN.

[0026] The switches SW1 to SW11 are, for example, transistors. The switch SW1 is controlled to be on or off by the first bit CTD[0] of the capacitance control data CTD[10:0]. Similarly, the switches SW2 to SW11 are controlled to be on or off by the second to eleventh bits CTD[1] to CTD

[11] of the capacitance control data CTD[10:0], respectively.

[0027] The capacitance values ​​of the capacitors CC1 to CC11 are weighted by a binary. That is, when s is an integer between 1 and 11, the capacitance value of the capacitor CCs is twice the capacitance value of the capacitor CC1. s-1 Hereinafter, an example in which the capacitors CC1 to CC11 are configured by combining series and parallel connections of unit capacitors will be described. However, the present invention is not limited to this example. The capacitor CC1 is configured by one unit capacitor, and the capacitor CCs is configured by two s-1 It may be composed of unit capacitors.

[0028] As shown in FIG. 3, the capacitors CC4 to CC11 are a first capacitor group LCG corresponding to the upper bits CTD[10:3] of the capacitance control data CTD[10:0]. The capacitors CC1 to CC3 are a second capacitor group SCG corresponding to the lower bits CTD[2:0] of the capacitance control data CTD[10:0]. Each capacitor of the first capacitor group LCG is composed of a plurality of unit capacitors connected in parallel, and each capacitor of the second capacitor group SCG is composed of a plurality of unit capacitors connected in series. Each unit capacitor is, for example, an MIM capacitor. MIM is an abbreviation for Metal Insulator Metal. Note that the first capacitor group LCG may include one or more capacitors, and the second capacitor group SCG may include one or more capacitors.

[0029] 4 shows a detailed configuration example of the capacitor CC1. The capacitor CC1 includes unit capacitors UC1a to UC1d connected in series between the input node N1 and one end of the switch SW1. When the capacitance of the unit capacitors is 4C, the capacitance of the capacitor CC1 is 4C / 4=C. For example, the unit capacitors UC1a and UC1b are two MIM capacitors stacked in the thickness direction of a semiconductor substrate, and the unit capacitors UC1c and UC1d are two MIM capacitors stacked in the thickness direction of a semiconductor substrate.

[0030] 5 shows a detailed configuration example of the capacitor CC2. The capacitor CC2 includes unit capacitors UC2a and UC2b connected in series between the input node N1 and one end of the switch SW1. The capacitance value of the capacitor CC2 is 4C / 2=2C. For example, the unit capacitors UC2a and UC2b are two MIM capacitors stacked in the thickness direction of a semiconductor substrate.

[0031] 6 is a detailed configuration example of the capacitor CC3. The capacitor CC3 includes unit capacitors UC3a and UC3b connected in series between the input node N1 and one end of the switch SW1, and unit capacitors UC3c and UC3d connected in series between the input node N1 and one end of the switch SW1. The capacitance value of the capacitor CC3 is (4C / 2)×2=4C. For example, the unit capacitors UC3a and UC3b are two MIM capacitors stacked in the thickness direction of a semiconductor substrate, and the unit capacitors UC3c and UC3d are two MIM capacitors stacked in the thickness direction of a semiconductor substrate.

[0032] FIG. 7 shows a configuration example of basic capacitors UC constituting capacitors CC4 to CC11 and basic switches USW constituting switches SW4 to SW11. The basic capacitor UC includes unit capacitors UCa and UCb connected in parallel between an input node N1 and one end of the basic switch USW. The other end of the basic switch USW is connected to a ground node NGN. The capacitance value of the basic capacitor UC is 4C×2=8C. For example, the unit capacitors UCa and UCb are two MIM capacitors stacked in the thickness direction of a semiconductor substrate. The basic switch USW is a transistor.

[0033] The basic capacitor UC and basic switch USW shown in FIG. 7 are collectively called a basic unit. Capacitor CC4 and switch SW4 are composed of one basic unit. Capacitor CC5 and switch SW5 are composed of two basic units connected in parallel. Capacitor CC6 and switch SW6 are composed of four basic units connected in parallel. Thereafter, the number of basic units connected in parallel increases by a power of 2. Note that, although an example in which each of switches SW4 to SW11 is composed of one or more basic switches has been described here, each of switches SW4 to SW11 may be composed of one transistor.

[0034] 8 shows the capacitance value of the variable capacitance circuit 31 versus capacitance control data CTD when dither processing is not performed by the dither processing unit 65. The capacitance value of the capacitor CC1 is set to 1C, and the vertical axis shows the capacitance value in units of 1C. The horizontal axis shows CTD in decimal notation.

[0035] A1 indicates an ideal value when there is no error in the capacitance value, and the capacitance value=CTD. A2 is the capacitance value for the capacitance control data CTD when the error in the capacitance value is taken into consideration. When CTD=7, the capacitors CC1 to CC3 in which the unit capacitors are connected in series are used, and when CTD=8, the capacitor CC4 in which the unit capacitors are connected in parallel is used. Since the way in which the parasitic capacitance is attached changes when the unit capacitors are connected in series and when they are connected in parallel, the error in the capacitance value also differs greatly. Therefore, when CTD=7 and CTD=8 are switched, the linearity of the capacitance value is greatly reduced. Since the linearity of the capacitance value of the variable capacitance circuit 31 affects the compensation accuracy of the temperature compensation of the oscillation frequency, the deviation of the oscillation frequency may increase if the linearity is reduced.

[0036] The dither processing of this embodiment, which can improve such linearity degradation, will be described below. Note that although the description has been given here with an example of linearity degradation when switching between series connection and parallel connection, the dither processing of this embodiment can also be applied to other linearity degradations. For example, when CTD is expressed in binary, there is a tendency for the linearity of the capacitance value to decrease when the bit digit is carried up or down, such as CTD=0111 and 1000. The dither processing of this embodiment is also effective against such linearity degradation.

[0037] 9 is a timing chart for explaining the operation of the processing circuit 60. Here, an example is explained in which the output of the dither processing unit 65 becomes the capacitance control data CTD, but the output of the dither processing unit 65 may be further processed and then output as the capacitance control data CTD, for example, as in a second detailed configuration example of the processing circuit 60 described later.

[0038] The temperature compensation unit 63 outputs temperature-compensated capacity control data ICL at a predetermined interval, and the temperature-compensated capacity control data ICL is input to the dither processing unit 65 as input capacity control data. Here, ICL and CTD are assumed to be 4 bits. TA1 to TA4 indicate periods of predetermined intervals, and in the example of Fig. 9, the temperature compensation unit 63 outputs ICL=0111, 1000, 1001, 1010 at TA1, TA2, TA3, and TA4.

[0039] The dither processing unit 65 performs dither processing on the input ICL, and alternately outputs CTD=ICL and CTD=ICL+1. Specifically, when CTD=ICL and CTD=ICL+1 are one set, the dither processing unit 65 repeats one or more sets in each of the periods TA1 to TA4. FIG. 9 shows an example in which two sets are repeated in each period. For example, in the period TA1, the dither processing unit 65 outputs CTD=0111, 1000, 0111, and 1000 in a time-division manner. The time average of CTD in the period TA1 is (7+8) / 2=7.5. Similarly, the dither processing unit 65 performs dither processing on the input ICL=8, 9, and 10 in the periods TA2, TA3, and TA4, and outputs CTD with time averages of CTD=8.5, 9.5, and 10.5.

[0040] In addition, FIG. 9 illustrates an example in which the temperature-compensated capacity control data ICL is different in each of the periods TA1 to TA4, but the interval between TA1 to TA4 means the data sampling period, and in reality, the temperature-compensated capacity control data ICL may be different or the same in adjacent periods.

[0041] A3 in FIG. 10 is the capacitance value of the variable capacitance circuit 31 with respect to the capacitance control data CTD when the dither processing of this embodiment is applied to A2 in FIG.

[0042] When ICL=7, the dither processing unit 65 outputs CTD=7 and 8 in a time-division manner, so that the capacitance value of the variable capacitance circuit 31 is the time average of the capacitance value corresponding to CTD=7 and the capacitance value corresponding to CTD=8. In FIG. 10, this is shown by a triangular mark corresponding to CTD=7.5. Similarly, when ICL=8, the capacitance value of the variable capacitance circuit 31 is the time average of the capacitance value corresponding to CTD=8 and the capacitance value corresponding to CTD=9. Although there is a large error in the capacitance value when CTD=7 and 8 are switched, the error is dispersed by the dither processing, and the linearity of the capacitance value with respect to the CTD is improved. By improving the linearity, the compensation accuracy of the temperature compensation of the oscillation frequency is improved, and the deviation of the oscillation frequency can be reduced.

[0043] In the above embodiment, the circuit device 20 includes a processing circuit 60 that generates capacitance control data CTD, and an oscillation circuit 30. The oscillation circuit 30 has a variable capacitance circuit 31 whose capacitance value is variably controlled based on the capacitance control data CTD, and the oscillation frequency is controlled by the capacitance value of the variable capacitance circuit 31. The variable capacitance circuit 31 has a capacitor array CPA1. The capacitor array CPA1 has a plurality of capacitors CC1 to CC11 whose capacitance values ​​are binary weighted, and a plurality of switches SW1 to SW11. The plurality of switches SW1 to SW11 are provided in series with the plurality of capacitors CC1 to CC11 between an oscillation node of the oscillation circuit 30 and a ground node NGN, and are on / off controlled based on the capacitance control data CTD. The processing circuit 60 outputs capacitance control data CTD that has been dithered so as to switch the capacitance value of the variable capacitance circuit 31 between a first capacitance value and a second capacitance value in a time-division manner.

[0044] In the period TA1 in FIG. 9, the capacitance value corresponding to CTD=0111 is the first capacitance value, and the capacitance value corresponding to CTD=1000 is the second capacitance value. Alternatively, in a second detailed configuration example described later in FIG. 15, a time-division process is further performed after the dither process, and the capacitance value realized as the time average of the time-division process becomes the first capacitance value or the second capacitance value. In the period TB1 in FIG. 15, the capacitance control data ICL'[13:0] after the dither process includes an integer part ICL'[13:3]=CLQ and a fractional part ICL'[2:0], and the fractional part ICL'[2:0] is time-division-divided into 010 and 011 by the dither process. The capacitor array is time-division-controlled for this ICL'[2:0]=010, 011, thereby realizing the first capacitance value CLQ+2 / 8 and the second capacitance value CLQ+3 / 8 as the time average.

[0045] According to this embodiment, the capacitance value of the variable capacitance circuit 31 is dithered so as to be switched between the first capacitance value and the second capacitance value in a time-division manner, so that the capacitance value of the variable capacitance circuit 31 becomes the average value of the first capacitance value and the second capacitance value in the time average. This improves the linearity of the capacitance value of the variable capacitance circuit 31 with respect to the capacitance control data CTD. The first capacitance value and the second capacitance value differ according to the temperature detection data DTD input to the processing circuit 60, but it is assumed that the capacitance values ​​are ones at which the linearity decreases, such as the switching between CTD=7 and 8 in FIG. 8. At this time, the error in the capacitance value is dispersed by the dithering process, so that the linearity of the capacitance value is improved.

[0046] In this embodiment, the processing circuit 60 samples the input capacitance control data ICL at a predetermined interval in the dither process. In a first period TA1 having a predetermined interval, the processing circuit 60 switches between the input capacitance control data ICL=0111 of the first period TA1 and data 1000 obtained by adding 1 LSB to the input capacitance control data ICL=0111 of the first period TA1 in a time-division manner. In a second period TA2 following the first period TA1, the processing circuit 60 switches between the input capacitance control data ICL=1000 of the second period TA2 and data 1001 obtained by adding 1 LSB to the input capacitance control data ICL=1000 of the second period TA2 in a time-division manner.

[0047] In this embodiment, the temperature-compensated capacitance control data ICL output by the temperature compensation unit 63 corresponds to the input capacitance control data for the dither process. In Fig. 9, the input capacitance control data ICL in the first period TA1 and the input capacitance control data ICL in the second period TA2 are different, but the input capacitance control data ICL in the first period TA1 and the input capacitance control data ICL in the second period TA2 may be the same.

[0048] According to this embodiment, since the input capacitance control data ICL is sampled at a predetermined interval, the input capacitance control data ICL does not change in the first period TA1, and the input capacitance control data ICL and data obtained by adding 1LSB to the input capacitance control data ICL are output in a time-division manner. The same is true in the second period TA2. By performing such dither processing, even if the linearity between the capacitance value corresponding to ICL and the capacitance value corresponding to ICL+1 is reduced, the capacitance value error that reduces the linearity is dispersed by the dither processing, improving the linearity.

[0049] In this embodiment, the capacitors CC1 to CC11 of the capacitor array CPA1 include a first capacitor group LCG and a second capacitor group SCG. The first capacitor group LCG is made up of a plurality of MIM capacitors connected in parallel and corresponds to the most significant bits CTD[10:3] of the capacitance control data CTD[10:0]. The second capacitor group SCG is made up of a plurality of MIM capacitors connected in series and corresponds to the least significant bits CTD[2:0] of the capacitance control data CTD[10:0].

[0050] If capacitor CC1 is assumed to be composed of one unit capacitor, capacitor CC11 is composed of 1024 unit capacitors. The size of the unit capacitor is restricted by design rules, so the layout area of ​​the capacitor array becomes large. In this regard, by using a second capacitor group SCG in which multiple MIM capacitors are connected in series, it is possible to generate a capacitance value smaller than the capacitance value of the unit capacitor. This makes it possible to reduce the layout area of ​​the capacitor array.

[0051] However, parasitic capacitance occurs between the node between the unit capacitors and the ground, and the first capacitor group LCG and the second capacitor group SCG have different parasitic capacitances, which results in different capacitance value errors. Therefore, there is a risk that the linearity of the capacitance value of the variable capacitance circuit 31 will be significantly reduced at the boundary between the range of capacitance control data CTD in which the first capacitor group LCG is used and the range of capacitance control data CTD in which the second capacitor group SCG is used. In this regard, the capacitance value error is dispersed by dither processing, improving the linearity at the above-mentioned boundary.

[0052] In this embodiment, the processing circuit 60 includes a temperature compensation unit 63 and a dither processing unit 65. The temperature compensation unit 63 performs temperature compensation processing based on the temperature detection data DTD, and outputs the result of the temperature compensation processing as input capacitance control data ICL. The dither processing unit 65 performs dither processing on the input capacitance control data ICL, and outputs dither processed capacitance control data.

[0053] For example, in Fig. 9, the dithered capacitance control data is the capacitance control data CTD. Alternatively, as in a second detailed configuration example described later in Fig. 15, the dithered capacitance control data ICL' may be further processed to generate the capacitance control data CTD.

[0054] In temperature compensation, if the linearity of the capacitor array is degraded, there is a risk that the deviation of the oscillation frequency after temperature compensation will become large. According to this embodiment, the linearity of the capacitor array is improved by dither processing, so that the deviation of the oscillation frequency after temperature compensation can be reduced.

[0055] 2. First detailed configuration example Fig. 11 shows a first detailed configuration example of the processing circuit 60 and the memory 70. The processing circuit 60 includes a digital filter 61, a temperature compensation section 63, and a dither processing section 65. The temperature compensation section 63 is also called a linear interpolation section. The memory 70 includes a capacity adjustment value storage section 71. The number of bits of each piece of data shown in Fig. 11 is an example, and these numbers of bits may be arbitrary.

[0056] The digital filter 61 performs digital filtering on the temperature detection data DTD[9:0] input from the temperature sensor circuit 45, and outputs the result as output data FLQ[11:0]. The digital filter 61 is, for example, an IIR filter, and the digital filtering is, for example, low-pass filtering. IIR stands for Infinite Impulse Response.

[0057] The capacity adjustment value storage unit 71 is a storage area specified by a predetermined address range in the address space of the memory 70, and stores a first table in which the upper 8 bits FLQ[11:4] of the output data FLQ[11:0] correspond to the capacity adjustment value CL[10:0]. The temperature compensation unit 63 reads out the capacity adjustment value CL[10:0] corresponding to the upper bits FLQ[11:4] of the output data FLQ[11:0] input from the digital filter 61 from the capacity adjustment value storage unit 71. The temperature compensation unit 63 linearly interpolates the read capacity adjustment value CL[10:0], and outputs the result as temperature-compensated capacity control data ICL[10:0].

[0058] Specifically, when i is an integer between 0 and 255, it is assumed that FLQ[11:4]=i is input to the capacity adjustment value storage unit 71. The capacity adjustment value storage unit 71 outputs the capacity adjustment values ​​CL[10:0]=CLi, CLi+1 corresponding to FLQ[11:4]=i, i+1 in the first table to the temperature compensation unit 63. CLi is called the first capacity adjustment value, and CLi+1 is called the second capacity adjustment value. The temperature compensation unit 63 performs an interpolation process between the first capacity adjustment value CLi and the second capacity adjustment value CLi+1 based on the lower 4 bits FLQ[3:0] of the output data FLQ[11:0]. The interpolation process is, for example, linear interpolation, and the temperature compensation unit 63 selects a value corresponding to FLQ[3:0] from among values ​​obtained by dividing the range between CLi and CLi+1 by 16.

[0059] The dither processing unit 65 receives the temperature compensated capacitance control data ICL[10:0] as input capacitance control data. The dither processing unit 65 performs dither processing on the input capacitance control data ICL[10:0], and outputs the resultant dither processed capacitance control data as capacitance control data CTD[10:0] to the variable capacitance circuit 31. The operation of the dither processing unit 65 is as described in FIG. 9. That is, the dither processing unit 65 outputs CTD[10:0]=ICL[10:0] and ICL[10:0]+1 in a time-division manner. "+1" indicates that the LSB of ICL[10:0] is incremented by +1.

[0060] In the above-described embodiment, the processing circuit 60 outputs the dither processed capacitance control data to the variable capacitance circuit 31 as capacitance control data CTD.

[0061] According to this embodiment, the input capacitance control data and data obtained by adding 1 LSB to the input capacitance control data are output as capacitance control data CTD to the variable capacitance circuit 31. As a result, the capacitance value of the variable capacitance circuit 31 is switched in a time-division manner between a first capacitance value corresponding to the input capacitance control data and a second capacitance value corresponding to data obtained by adding 1 LSB to the input capacitance control data. As a result, the error in the capacitance value is dispersed as described above, improving the linearity of the capacitance value.

[0062] 3. Second detailed configuration example 12 is a second detailed configuration example of the capacitor array CPA1. The capacitor array CPA2 has a similar configuration. The capacitor array CPA1 includes capacitors CC1 to CC11, switches SW1 to SW11, a switching capacitor CDV, and a switching switch SWDV. The description of the same parts as in FIG. 3 will be omitted.

[0063] One end of the switching capacitor CDV is connected to an input node N1 of the drive circuit 32, the other end of the switching capacitor CDV is connected to one end of the switching switch SWDV, and the other end of the switching switch SWDV is connected to a ground node NGN. The configuration of the switching capacitor CDV is the same as the configuration of the capacitor CC1 described in FIG. 4. The capacitance value of the switching capacitor CDV is the same as the capacitance value of the capacitor CC1. The switching switch SWDV is, for example, a transistor. The switching switch SWDV is controlled to be on or off by a switching control signal CTDV.

[0064] Fig. 13 is a second detailed configuration example of the processing circuit 60 and the memory 70. The processing circuit 60 includes a digital filter 61, a temperature compensation section 63, a dither processing section 65, and a time division processing section 64. The memory 70 includes a capacity adjustment value storage section 71 and a time division pattern storage section 72. Note that the number of bits of each data shown in Fig. 13 is an example, and these number of bits may be arbitrary. Descriptions of components that are the same as the components explained in Fig. 11 will be omitted as appropriate.

[0065] The capacity adjustment value storage unit 71 stores a first table in which the upper 8 bits FLQ[11:4] of the output data FLQ[11:0] correspond to the capacity adjustment value CL[13:0]. The temperature compensation unit 63 reads out the capacity adjustment value CL[13:0] corresponding to the upper bits FLQ[11:4] of the output data FLQ[11:0] input from the digital filter 61 from the capacity adjustment value storage unit 71. The temperature compensation unit 63 linearly interpolates the read capacity adjustment value CL[13:0] and outputs the result as temperature-compensated capacity control data ICL[13:0].

[0066] The dither processing unit 65 performs dither processing on the temperature-compensated capacity control data ICL[13:0] input from the temperature compensation unit 63, and outputs the result as dither-processed capacity control data ICL'[13:0]. The dither processing unit 65 outputs ICL'[13:0]=ICL[13:0] and ICL[13:0]+1 in a time-division manner. "+1" indicates that the LSB of ICL[13:0] is incremented by +1.

[0067] The time division pattern storage unit 72 is a storage area specified by a predetermined address range in the address space in the memory 70, and stores a second table in which the lower 3 bits ICL'[2:0] of the dithered capacity control data ICL'[13:0] correspond to the time division pattern information TDP[31:0]. When j is an integer between 0 and 7, it is assumed that ICL'[2:0]=j is input to the time division pattern storage unit 72. The time division pattern storage unit 72 outputs TDP[k]=TDPj corresponding to ICL'[2:0]=j in the second table to the time division processing unit 64. The time division pattern information TDP[31:0] is information instructing in what time series the first capacity control data and the second capacity control data are to be output.

[0068] When the capacitance of capacitor CC1, which is the smallest capacitance of the capacitor array, is the integer "1", ICL'[13:3] indicates the integer part of the capacitance value, and ICL'[2:0] indicates the decimal part of the capacitance value. The decimal part is realized by time-division processing by time-division processing unit 64.

[0069] The time division processing unit 64 outputs the capacitance control data CTD[10:0]=CLQ and the switching control signal CTDV=TDP[k] based on the most significant 11 bits ICL'[13:3]=CLQ of the dithered capacitance control data ICL'[13:0] and the time division pattern information TDPj. k is an integer between 0 and 31. The time division processing unit 64 outputs CTDV=TDP[0], TDP[1], . . . , TDP

[31] in a time division manner without changing CTD[10:0]=CLQ, thereby controlling the capacitance value of the variable capacitance circuit 31 in a time division manner. CTD[10:0]=CLQ and CTDV=0 are called the first capacitance control data, and CTD[10:0]=CLQ and CTDV=1 are called the second capacitance control data. The time division processing unit 64 outputs the first capacitance control data and the second capacitance control data in a time division manner based on the time division pattern information TDPj, thereby realizing the decimal part of the capacitance value as a time average.

[0070] Fig. 14 is an example of the second table stored in the time division pattern storage unit 72. In Fig. 14, ICL'[2:0] is expressed in binary notation. Also, the logical level of each bit in the time division pattern information TDP[31:0] is expressed as 0 or 1.

[0071] When ICL'[2:0]=000h, the percentage of bits in TDP[31:0] that are logic level 1 is 0 / 8, so the corresponding decimal is 0.000. When ICL'[2:0]=001h, the percentage of bits in TDP[31:0] that are logic level 1 is 1 / 8, so the corresponding decimal is 0.125. Similarly, when ICL'[2:0]=010h, 011h, 100h, 101h, 110h, 111h, the percentage of bits in TDP[31:0] that are logic level 1 is 2 / 8, 3 / 8, 4 / 8, 5 / 8, 6 / 8, 7 / 8, so the corresponding decimal is 0.250, 0.375, 0.500, 0.625, 0.750, 0.875.

[0072] By performing time division control using such time division pattern information TDP[31:0], capacity control data that substantially includes decimal parts such as CLQ+0, CLQ+0.125, CLQ+0.250, . . . , CLQ+0.875 is realized.

[0073] Fig. 15 is a timing chart for explaining the operation of the processing circuit 60 in the second detailed configuration example. Fig. 15 shows one period TB1 among a plurality of periods repeated at a predetermined interval.

[0074] Assume that the temperature compensation unit 63 outputs ICL[13:3]=CLQ and ICL[2:0]=010 during period TB1. The dither processing unit 65 outputs ICL'[13:3]=CLQ and also outputs ICL'[2:0]=010 and 011 alternately in a time-division manner. The time-division processing unit 64 outputs capacitance control data CTD[10:0]=ICL'[13:3]=CLQ. Furthermore, when ICL'[2:0]=010, the time-division processing unit 64 outputs CTDV=TDP[k]=1, 0, 0, 0, 1, . . . , 0 in a time-division manner based on the time-division pattern information TDP[31:0] corresponding to ICL'[2:0]=010. When ICL'[2:0]=011, the time division processing unit 64 outputs CTDV=TDP[k]=1, 0, 1, 0, 1, ..., 0 in a time division manner based on the time division pattern information TDP[31:0] corresponding to ICL'[2:0]=011.

[0075] When ICL'[2:0]=010, the time average of TDP[k] is 2 / 8, so the time average capacitance value of the variable capacitance circuit 31 is CLQ+2 / 8. When ICL'[2:0]=011, the time average of TDP[k] is 3 / 8, so the time average capacitance value of the variable capacitance circuit 31 is CLQ+3 / 8. These are alternately repeated by the dither process, so the time average capacitance value in period TB1 is CLQ+2.5 / 8.

[0076] 16 shows the capacitance value of the variable capacitance circuit 31 relative to the capacitance control data CTD=CLQ when dither processing is not performed by the dither processing unit 65. The black circles indicate the capacitance values ​​actually present in the capacitor array, i.e., the integer part indicated by CLQ. The white circles indicate the decimal part realized by the time-division processing by the time-division processing unit 64.

[0077] Considering the integer part of the capacitance value, the linearity of the capacitance value corresponding to CLQ=7 and the capacitance value corresponding to CLQ=8 decreases when CLQ=7 and 8 switch because the unit capacitors switch between series and parallel connections. If the decimal part of the capacitance value is included, the linearity of the capacitance value decreases when CLQ=7+7 / 8 and CLQ=8+0 / 8 switch. Note that 7 / 8 and 0 / 8 indicate the decimal part realized by CTDV=TDP[k].

[0078] Fig. 17 shows the capacitance value of the variable capacitance circuit 31 with respect to the capacitance control data CTD=CLQ when the dither processing of the second detailed configuration example is applied. Fig. 17 shows an enlarged view of only the vicinity of CLQ=8. The black and white circles are the same as those in Fig. 16, and the triangles indicate the capacitance value when the dither processing of the second detailed configuration example is applied.

[0079] When CLQ=7+7 / 8, CLQ=7+7 / 8 and CLQ=8+0 / 8 are output alternately by dither processing, so the capacitance value of the variable capacitance circuit 31 is the time average of the capacitance value when CLQ=7+7 / 8 and the capacitance value when CLQ=8+0 / 8. In FIG. 17, this is shown by a triangular mark corresponding to CLQ=7+7.5 / 8. Although there is a large error in the capacitance value when CLQ=7+7 / 8 and CLQ=8+0 / 8 switch, the error is dispersed by the dither processing, improving the linearity of the capacitance value with respect to CLQ. Improving the linearity improves the compensation accuracy of the temperature compensation of the oscillation frequency, and the deviation of the oscillation frequency can be reduced.

[0080] In the above embodiment, the processing circuit 60 has a time division processing unit 64 that performs time division processing on the dithered capacitance control data ICL'[13:0]. The dither processing unit 65 outputs the first dithered capacitance control data ICL'[13:3]=CLQ, ICL'[2:0]=010 corresponding to the first capacitance value CLQ+2 / 8 and the second dithered capacitance control data ICL'[13:3]=CLQ, ICL'[2:0]=010 corresponding to the second capacitance value CLQ+3 / 8 in a time division manner. The time division processing unit 64 performs time division processing based on the first dithered capacitance control data so that the capacitance value of the variable capacitance circuit 31 becomes the first capacitance value CLQ+2 / 8 as a time average, and outputs the capacitance control data CTD[10:0]=CLQ, CTDV=TDP[k]. The time-division processing unit 64 performs time-division processing based on the capacitance control data after the second dither processing so that the capacitance value of the variable capacitance circuit 31 becomes the second capacitance value CLQ+3 / 8 as a time average, and outputs capacitance control data CTD[10:0]=CLQ, CTDV=TDP[k].

[0081] According to this embodiment, by further performing time division processing after dither processing, it is possible to realize a capacitance value smaller than the minimum capacitance value of the capacitor array as a time average of the time division processing. The minimum capacitance value of the capacitor array is the capacitance value of the capacitor CC1, and if this is the integer "1", CLQ corresponds to the integer part, and 2 / 8 and 3 / 8 correspond to the decimal part. This makes it possible to improve the compensation accuracy of the temperature compensation without increasing the number of capacitors in the capacitor array or the layout area of ​​the capacitor array. By improving the compensation accuracy of the temperature compensation, the deviation of the oscillation frequency after temperature compensation becomes smaller.

[0082] Furthermore, in this embodiment, when the first dither processed capacitance control data ICL'[13:3]=CLQ, ICL'[2:0]=010 is input, the time-division processing unit 64 outputs capacitance control data corresponding to the third capacitance value and capacitance control data corresponding to the fourth capacitance value in a time-division manner to the variable capacitance circuit 31 so that the capacitance value of the variable capacitance circuit 31 becomes the first capacitance value CLQ+2 / 8 on time average. The third capacitance value is equal to or smaller than the first capacitance value CLQ+2 / 8, and the fourth capacitance value is greater than the first capacitance value CLQ+2 / 8.

[0083] 15, the capacitance control data corresponding to the third capacitance value is CTD[10:0]=CLQ, CTDV=0, and the third capacitance value is the capacitance value corresponding to CLQ. The capacitance control data corresponding to the fourth capacitance value is CTD[10:0]=CLQ, CTDV=1, and the fourth capacitance value is the capacitance value corresponding to CLQ+1. Time division is performed based on CTDV=TDP[k]=1, 0, 0, 0, 1, . . . , 0, and the first capacitance value CLQ+2 / 8 is realized as the time average.

[0084] Furthermore, when second dither processed capacitance control data ICL'[13:3]=CLQ, ICL'[2:0]=011 is input, the time division processing unit 64 outputs capacitance control data corresponding to the fifth capacitance value and capacitance control data corresponding to the sixth capacitance value in a time division manner to the variable capacitance circuit 31 so that the capacitance value of the variable capacitance circuit 31 becomes the second capacitance value CLQ+3 / 8 on time average. The fifth capacitance value is equal to or smaller than the second capacitance value CLQ+3 / 8, and the sixth capacitance value is greater than the second capacitance value CLQ+3 / 8.

[0085] 15, the capacitance control data corresponding to the fifth capacitance value is CTD[10:0]=CLQ, CTDV=0, and the fifth capacitance value is the capacitance value corresponding to CLQ. The capacitance control data corresponding to the sixth capacitance value is CTD[10:0]=CLQ, CTDV=1, and the sixth capacitance value is the capacitance value corresponding to CLQ+1. Time division is performed based on CTDV=TDP[k]=1, 0, 1, 0, 1, . . . , 0, and the second capacitance value CLQ+3 / 8 is realized as the time average.

[0086] According to this embodiment, the capacitance value of the variable capacitance circuit 31 is switched between a first capacitance value CLQ+2 / 8 and a second capacitance value CLQ+3 / 8 by dither processing. At this time, the decimal parts of the capacitance value, 2 / 8 and 3 / 8, are each realized by time-division processing. This makes it possible to use a capacitance value smaller than the minimum capacitance value of the capacitor array and to improve the linearity of the capacitance value by dither processing.

[0087] In this embodiment, the capacitor array CPA1 has a switching capacitor CDV and a switching switch SWDV. The switching capacitor CDV has the same capacitance as the capacitor CC1, which has the smallest capacitance among the binary-weighted capacitors CC1 to CC11. The switching switch SWDV is provided in series with the switching capacitor CDV between the oscillation node and the ground node NGN. The switching switch SWDV is turned off when capacitance control data corresponding to a third capacitance value is input, and turned on when capacitance control data corresponding to a fourth capacitance value is input. The switching switch SWDV is turned off when capacitance control data corresponding to a fifth capacitance value is input, and turned on when capacitance control data corresponding to a sixth capacitance value is input.

[0088] According to this embodiment, the changeover switch SWDV is turned on or off in a time-division manner, so that the capacitance value of the variable capacitance circuit 31 changes in a time-division manner by the capacitance value of the switching capacitor CDV. Since the capacitance value of the switching capacitor CDV is the same as that of the capacitor CC1, which has the smallest capacitance value in the capacitor array, a capacitance value smaller than the minimum capacitance value is realized as the time-division average.

[0089] The circuit device of the present embodiment described above includes a processing circuit that generates capacitance control data and an oscillation circuit. The oscillation circuit has a variable capacitance circuit whose capacitance value is variably controlled based on the capacitance control data, and the oscillation frequency is controlled by the capacitance value of the variable capacitance circuit. The variable capacitance circuit has a capacitor array. The capacitor array has a plurality of capacitors whose capacitance values ​​are binary weighted, and a plurality of switches that are provided in series with the plurality of capacitors between an oscillation node of the oscillation circuit and a ground node, and that are controlled to be turned on and off based on the capacitance control data. The processing circuit outputs capacitance control data that has been dithered so as to switch the capacitance value of the variable capacitance circuit between a first capacitance value and a second capacitance value in a time-division manner.

[0090] According to this embodiment, the capacitance value of the variable capacitance circuit is dithered to switch between the first capacitance value and the second capacitance value in a time-division manner, so that the capacitance value of the variable capacitance circuit becomes the average value of the first capacitance value and the second capacitance value on a time average basis. This improves the linearity of the capacitance value of the variable capacitance circuit with respect to the capacitance control data. In other words, the error in the first capacitance value and the error in the second capacitance value are dispersed over time by the dithering process, so that the linearity of the capacitance value is improved when viewed as the capacitance value on a time average basis.

[0091] In the present embodiment, the processing circuit may sample the input capacitance control data at a predetermined interval in the dither process. In a first period of the predetermined interval, the processing circuit may switch between the input capacitance control data of the first period and data obtained by adding 1 LSB to the input capacitance control data of the first period in a time-division manner. In a second period following the first period, the processing circuit may switch between the input capacitance control data of the second period and data obtained by adding 1 LSB to the input capacitance control data of the second period in a time-division manner.

[0092] According to this embodiment, since the input capacitance control data is sampled at a predetermined interval, the input capacitance control data does not change in the first period, and the input capacitance control data and data obtained by adding 1 LSB to the input capacitance control data are output in a time-division manner. The same is true in the second period. Even if the linearity between the capacitance value corresponding to the input capacitance control data and the capacitance value corresponding to the data obtained by adding 1 LSB to the input capacitance control data is reduced, the linearity is improved by performing the dither processing as described above.

[0093] In this embodiment, the capacitors of the capacitor array may include a first capacitor group and a second capacitor group. The first capacitor group may include a plurality of MIM capacitors connected in parallel and correspond to the most significant bits of the capacitance control data. The second capacitor group may include a plurality of MIM capacitors connected in series and correspond to the least significant bits of the capacitance control data.

[0094] The first capacitor group and the second capacitor group have different parasitic capacitances, and therefore have different capacitance error. Therefore, there is a risk that the linearity of the capacitance of the variable capacitance circuit will be significantly reduced at the boundary between the range of capacitance control data in which the first capacitor group is used and the range of capacitance control data in which the second capacitor group is used. In this embodiment, the capacitance error is dispersed by dither processing, improving the linearity at the boundary.

[0095] In this embodiment, the processing circuit may have a temperature compensation unit and a dither processing unit. The temperature compensation unit may perform temperature compensation processing based on the temperature detection data and output a result of the temperature compensation processing as input capacitance control data. The dither processing unit may perform dither processing on the input capacitance control data and output the dither processed capacitance control data.

[0096] In temperature compensation, if the linearity of the capacitor array is degraded, there is a risk that the deviation of the oscillation frequency after temperature compensation will become large. According to this embodiment, the linearity of the capacitor array is improved by dither processing, so that the deviation of the oscillation frequency after temperature compensation can be reduced.

[0097] In this embodiment, the processing circuit may output the dither processed capacitance control data to the variable capacitance circuit as capacitance control data.

[0098] According to this embodiment, the input capacitance control data and data obtained by adding 1LSB to the input capacitance control data are output to the variable capacitance circuit as capacitance control data. As a result, the capacitance value of the variable capacitance circuit is switched in a time-division manner between a first capacitance value corresponding to the input capacitance control data and a second capacitance value corresponding to the data obtained by adding 1LSB to the input capacitance control data. As a result, the error in the capacitance value is dispersed as described above, improving the linearity of the capacitance value.

[0099] In this embodiment, the processing circuit may have a time-division processing unit that performs time-division processing on the dithered capacitance control data. The dither processing unit may output first dithered capacitance control data corresponding to a first capacitance value and second dithered capacitance control data corresponding to a second capacitance value in a time-division manner. The time-division processing unit may perform time-division processing based on the first dithered capacitance control data so that the capacitance value of the variable capacitance circuit becomes the first capacitance value as a time average, and output the capacitance control data. The time-division processing unit may perform time-division processing based on the second dithered capacitance control data so that the capacitance value of the variable capacitance circuit becomes the second capacitance value as a time average, and output the capacitance control data.

[0100] According to this embodiment, by further performing time-division processing after dither processing, a capacitance value smaller than the minimum capacitance value of the capacitor array is realized as a time average of the time-division processing. This makes it possible to improve the compensation accuracy of temperature compensation without increasing the number of capacitors in the capacitor array or the layout area of ​​the capacitor array. By improving the compensation accuracy of temperature compensation, the deviation of the oscillation frequency after temperature compensation becomes smaller.

[0101] In this embodiment, when the first post-dither processing capacitance control data is input, the time-division processing unit may output, in a time-division manner, to the variable capacitance circuit, capacitance control data corresponding to a third capacitance value equal to or less than the first capacitance value and capacitance control data corresponding to a fourth capacitance value greater than the first capacitance value, so that the capacitance value of the variable capacitance circuit becomes the first capacitance value on a time average. When the second post-dither processing capacitance control data is input, the time-division processing unit may output, in a time-division manner, to the variable capacitance circuit, capacitance control data corresponding to a fifth capacitance value equal to or less than the second capacitance value and capacitance control data corresponding to a sixth capacitance value greater than the second capacitance value, so that the capacitance value of the variable capacitance circuit becomes the second capacitance value on a time average.

[0102] According to this embodiment, the capacitance value of the variable capacitance circuit is switched between a first capacitance value and a second capacitance value by dither processing. At this time, the fractional part of the first capacitance value and the fractional part of the second capacitance value are each realized by time division processing. As a result, a capacitance value smaller than the minimum capacitance value of the capacitor array is realized, and the linearity of the capacitance value is improved by dither processing.

[0103] In this embodiment, the capacitor array may have a switching capacitor having the same capacitance value as a capacitor having a minimum capacitance value among the plurality of binary-weighted capacitors, and a switching switch provided in series with the switching capacitor between the oscillation node and the ground node. The switching switch may be turned off when capacitance control data corresponding to a third capacitance value is input, and turned on when capacitance control data corresponding to a fourth capacitance value is input. The switching switch may be turned off when capacitance control data corresponding to a fifth capacitance value is input, and turned on when capacitance control data corresponding to a sixth capacitance value is input.

[0104] According to this embodiment, the changeover switch is turned on or off in a time-division manner, so that the capacitance of the variable capacitance circuit changes in a time-division manner by the capacitance of the changeover capacitor. Since the capacitance of the changeover capacitor is the same as that of the capacitor with the smallest capacitance in the capacitor array, a capacitance smaller than the minimum capacitance is realized as the time-division average.

[0105] Moreover, an oscillator of the present embodiment includes any of the circuit devices described above, and a resonator that oscillates when driven by the oscillation circuit.

[0106] Although the present embodiment has been described in detail as above, it will be readily understood by those skilled in the art that many modifications are possible that do not substantially deviate from the novel matters and effects of the present disclosure. Therefore, all such modifications are intended to be included in the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader meaning or synonymy can be replaced with that different term anywhere in the specification or drawings. All combinations of the present embodiment and modifications are also included in the scope of the present disclosure. The configurations and operations of the circuit devices, resonators, oscillators, etc. are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0107] 4...oscillator, 10...vibrator, 20...circuit device, 30...oscillating circuit, 31...variable capacitance circuit, 32...driving circuit, 45...temperature sensor circuit, 60...processing circuit, 61...digital filter, 63...temperature compensation section, 64...time division processing section, 65...dither processing section, 70...memory, 71...capacitance adjustment value storage section, 72...time division pattern storage section, CC1 to CC11...capacitor, CDV...switching capacitor, CPA1, CPA2...capacitor array, CTD...capacitor amount control data, CTDV...switching control signal, DTD...temperature detection data, ICL...input capacitance control data, ICL'...capacitance control data after dither processing, LCG...first capacitor group, SCG...second capacitor group, SW1~SW11...switch, SWDV...switching switch, TA1~TA4, TB1...period, TDP...time division pattern information, UC1a~UC1d, UC2a, UC2b, UC3a~UC3d, UCa, UCb...unit capacitor

Claims

1. a processing circuit for generating capacitance control data; an oscillation circuit having a variable capacitance circuit whose capacitance value is variably controlled based on the capacitance control data, and whose oscillation frequency is controlled by the capacitance value of the variable capacitance circuit; Including, the variable capacitance circuit includes a capacitor array; The capacitor array comprises: A plurality of capacitors, each of which has a capacitance value weighted by a binary; a plurality of switches that are connected in series with the plurality of capacitors between an oscillation node of the oscillation circuit and a ground node, and that are controlled to be turned on and off based on the capacitance control data; having the processing circuit outputs the capacitance control data that has been dithered so as to switch the capacitance value of the variable capacitance circuit between a first capacitance value and a second capacitance value in a time division manner; The processing circuitry includes: a temperature compensation unit that performs a temperature compensation process based on the temperature detection data and outputs a result of the temperature compensation process as input capacitance control data; a dither processing unit that performs the dither processing on the input capacitance control data and outputs dither-processed capacitance control data; a time division processing unit that performs time division processing on the dithered capacity control data; having The dither processing unit, in the dither processing, Sampling the input capacitance control data at predetermined intervals; during a first period of the predetermined interval, the input capacitance control data during the first period is switched in a time division manner as first post-dither processing capacitance control data corresponding to the first capacitance value, and data obtained by adding 1 LSB to the input capacitance control data during the first period is switched as second post-dither processing capacitance control data corresponding to the second capacitance value; in a second period following the first period, the input capacitance control data of the second period is switched in a time division manner as the first post-dither processing capacitance control data and data obtained by adding 1 LSB to the input capacitance control data of the second period is switched as the second post-dither processing capacitance control data; The time division processing unit is performing the time division processing based on the first dither processed capacitance control data so that the capacitance value of the variable capacitance circuit becomes the first capacitance value as a time average, and outputting the capacitance control data; A circuit device characterized in that, based on the second dither processed capacitance control data, the time division processing is performed so that the capacitance value of the variable capacitance circuit becomes the second capacitance value as a time average, and the capacitance control data is output.

2. 2. The circuit device according to claim 1, The plurality of capacitors of the capacitor array include a first capacitor group including a plurality of MIM capacitors connected in parallel and corresponding to the most significant bits of the capacitance control data; a second capacitor group including a plurality of MIM capacitors connected in series and corresponding to the lower bits of the capacitance control data; A circuit device comprising:

3. 2. The circuit device according to claim 1, The time division processing unit is when the first dither processed capacitance control data is input, the capacitance control data corresponding to a third capacitance value equal to or smaller than the first capacitance value and the capacitance control data corresponding to a fourth capacitance value larger than the first capacitance value are output in a time-division manner to the variable capacitance circuit so that a capacitance value of the variable capacitance circuit becomes the first capacitance value on a time average; a circuit device characterized in that, when the second dither processed capacitance control data is input, the capacitance control data corresponding to a fifth capacitance value equal to or less than the second capacitance value and the capacitance control data corresponding to a sixth capacitance value greater than the second capacitance value are output in a time-division manner to the variable capacitance circuit so that the capacitance value of the variable capacitance circuit becomes the second capacitance value on a time average.

4. 4. The circuit device according to claim 3, The capacitor array comprises: a switching capacitor having the same capacitance as a capacitor having a minimum capacitance among the plurality of binary-weighted capacitors; a changeover switch provided in series with the changeover capacitor between the oscillation node and the ground node; having The changeover switch is When the capacitance control data corresponding to the third capacitance value is input, the capacitance control circuit is turned off, and when the capacitance control data corresponding to the fourth capacitance value is input, the capacitance control circuit is turned on. a circuit device which is turned off when the capacitance control data corresponding to the fifth capacitance value is input, and which is turned on when the capacitance control data corresponding to the sixth capacitance value is input.

5. a processing circuit for generating capacitance control data; an oscillation circuit having a variable capacitance circuit whose capacitance value is variably controlled based on the capacitance control data, and whose oscillation frequency is controlled by the capacitance value of the variable capacitance circuit; Including, the variable capacitance circuit includes a capacitor array; The capacitor array comprises: A plurality of capacitors, each of which has a capacitance value weighted by a binary; a plurality of switches that are connected in series with the plurality of capacitors between an oscillation node of the oscillation circuit and a ground node, and that are controlled to be turned on and off based on the capacitance control data; having the processing circuit outputs the capacitance control data that has been dithered so as to switch the capacitance value of the variable capacitance circuit between a first capacitance value and a second capacitance value in a time division manner; The processing circuit, in the dither processing, Sampling the input capacitance control data at predetermined intervals; A circuit device characterized in that, in each period divided by the predetermined interval, the input capacitance control data sampled corresponding to each period and data obtained by adding 1 LSB to the input capacitance control data sampled corresponding to each period are switched in a time-division manner at a cycle shorter than the predetermined interval.

6. 6. The circuit device according to claim 5, The processing circuitry includes: a temperature compensation unit that performs a temperature compensation process based on the temperature detection data and outputs a result of the temperature compensation process as the input capacitance control data; a dither processing unit that performs the dither processing on the input capacitance control data and outputs dither-processed capacitance control data; A circuit device comprising:

7. 7. A circuit device according to claim 6, The circuit device according to claim 1, wherein the processing circuit outputs the dither-processed capacitance control data to the variable capacitance circuit as the capacitance control data.

8. 7. A circuit device according to claim 6, the processing circuit has a time division processing unit that performs time division processing on the dithered capacity control data, the dither processing unit outputs, in a time division manner, first dither processed capacitance control data corresponding to the first capacitance value and second dither processed capacitance control data corresponding to the second capacitance value; The time division processing unit is performing the time division processing based on the first dither processed capacitance control data so that the capacitance value of the variable capacitance circuit becomes the first capacitance value as a time average, and outputting the capacitance control data; A circuit device characterized in that, based on the second dither processed capacitance control data, the time division processing is performed so that the capacitance value of the variable capacitance circuit becomes the second capacitance value as a time average, and the capacitance control data is output.

9. A circuit arrangement according to any one of claims 1 to 8; a vibrator that oscillates when driven by the oscillation circuit; 13. An oscillator comprising:

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