Multilayer capacitor, mounting substrate thereof, and manufacturing method thereof

Abstract

A multilayer capacitor is provided that can increase the overlapping area of ​​internal electrodes having different polarities, thereby reducing the size of the product and increasing the capacitance of the product. [Solution] The present invention provides a multilayer capacitor including a capacitor body including a dielectric layer, first and second internal electrodes arranged alternately with the dielectric layer sandwiched therebetween, and first and second groove portions provided on opposing first and second surfaces along a first direction in which the dielectric layers are stacked and in contact with the first and second internal electrodes, respectively, and first and second via electrodes formed in the first groove portion and the second groove portion, respectively, and connected to the first internal electrode and the second internal electrode, as well as a mounting substrate for the multilayer capacitor and a manufacturing method thereof.

Description

[Technical field]

[0001] The present invention relates to a multilayer capacitor, a mounting board therefor, and a manufacturing method thereof. [Background technology]

[0002] Stacked capacitors, which are one type of stacked chip electronic components, are mounted on the substrates of various electronic products such as visual equipment such as liquid crystal displays (LCDs) and plasma display panels (PDPs), computers, personal digital assistants (PDAs), and mobile phones, and play a role in charging and discharging electricity.

[0003] Such stacked capacitors have the advantages of being small, having a guaranteed capacitance, and being easy to mount, and can therefore be used as components in a variety of electronic devices. Recently, however, development has been underway to achieve higher capacitance and higher reliability.

[0004] In order to realize a multilayer capacitor with a high capacitance, there are methods of increasing the dielectric constant of the material constituting the capacitor body, or of decreasing the thickness of the dielectric layers and internal electrodes to increase the number of layers.

[0005] However, it is not easy to develop a composition for a high dielectric constant material, and there is a limit to how thin the dielectric layer can be made using current manufacturing methods, so there is also a limit to how much the capacity of the product can be increased using such methods.

[0006] Therefore, in order to meet the trend toward miniaturization of capacitors while still increasing the capacity of the product, research is being conducted into methods for increasing the overlapping area of ​​internal electrodes having different polarities.

[0007] Recently, as the packaging density of substrates increases, attempts have been made to reduce the mounting area and mounting height of multilayer capacitors. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Korean Patent Publication No. 10-2016-0000753 [Patent Document 2] JP 2012-023752 A Summary of the Invention [Problem to be solved by the invention]

[0009] SUMMARY OF THE PRESENT EMBODIMENT An object of the present invention is to provide a multilayer capacitor capable of increasing the capacitance of a product while reducing the size of the product by increasing the overlapping area of ​​internal electrodes having different polarities.

[0010] Another object of the present invention is to provide a multilayer capacitor capable of reducing a mounting area. [Means for solving the problem]

[0011] One aspect of the present invention provides a multilayer capacitor including a plurality of dielectric layers stacked in a first direction as a stacking direction, first and second internal electrodes arranged alternately in the first direction, each sandwiching the dielectric layers, and a capacitor body having a first face and a second face as both end faces opposing each other in the first direction, in which a first groove portion and a second groove portion extending along the first direction are formed on a side face connecting the first face and the second face, and first and second via electrodes formed in the first groove portion and the second groove portion, respectively, and connected to the first internal electrode and the second internal electrode, respectively.

[0012] Another aspect of the present invention provides a multilayer capacitor including a dielectric layer, first and second body portions arranged alternately with the dielectric layer in between and overlapping each other, first and second internal electrodes extending from the first and second body portions and including first and second lead portions, respectively, whose tip portions are exposed on a mounting surface of the capacitor body, and a capacitor body including first and second groove portions extending along a first direction in which the dielectric layer is stacked on the mounting surface on which the first and second lead portions are exposed and in contact with the first and second lead portions, respectively; and first and second via electrodes formed in the first groove portion and the second groove portion, respectively, and connected to the first lead portion and the second lead portion, respectively. Effect of the Invention

[0013] According to one embodiment of the present invention, the first and second internal electrodes are electrically connected to each other through the first and second via electrodes formed along the lamination direction of the dielectric layers, respectively, thereby increasing the overlapping area of ​​the internal electrodes having different polarities, thereby reducing the thickness of the dielectric layers and the internal electrodes, thereby increasing the number of laminated dielectric layers, or increasing the capacity of the product at the same size without increasing the dielectric constant.

[0014] Furthermore, since the external terminals are disposed only on the mounting surface of the capacitor body, the contact area of ​​the solder when mounted on a board is small, making it possible to reduce the mounting area. [Brief description of the drawings]

[0015] [Figure 1] 1 is an exploded perspective view showing a stacked capacitor according to a first embodiment of the present invention, turned upside down; [Diagram 2] 2(a) and 2(b) are plan views showing the first and second internal electrodes, respectively, in FIG. [Diagram 3] FIG. 2 is a side view of the capacitor body in FIG. [Figure 4] 1. FIG. 4 is an exploded perspective view showing another embodiment of the groove portion and the via electrode in the multilayer capacitor of FIG. [Diagram 5]1. (a) and (b) are plan views showing other examples of the first and second internal electrodes, respectively, in the multilayer capacitor of FIG. [Figure 6] 6 is a side view showing one side of a capacitor body to which the internal electrode of FIG. 5 is applied. [Figure 7] 1. (a) and (b) are plan views showing still other embodiments of the first and second internal electrodes in the multilayer capacitor of FIG. [Figure 8] 8 is a side view showing one side of a capacitor body to which the internal electrode of FIG. 7 is applied. [Figure 9] FIG. 11 is a perspective view illustrating a multilayer capacitor according to a second embodiment of the present invention. [Figure 10] 10(a) and 10(b) are plan views showing the first and second internal electrodes, respectively, of the multilayer capacitor of FIG. 9 before the first and second grooves are provided. [Figure 11] 10 is a perspective view showing a capacitor body in FIG. 9 excluding first and second via electrodes. [Figure 12] 10 is a perspective view showing a part of a process for manufacturing the multilayer capacitor of FIG. 9. FIG. [Figure 13] 10A to 10C are cross-sectional views showing some of the steps for manufacturing the multilayer capacitor of FIG. [Figure 14] 10A to 10C are cross-sectional views showing some of the steps for manufacturing the multilayer capacitor of FIG. [Figure 15] 13 is a perspective view showing another embodiment of the first and second via electrodes in the multilayer capacitor according to the second embodiment of the present invention. FIG. [Figure 16] 16 is a perspective view showing a capacitor body in FIG. 15 excluding first and second via electrodes. [Figure 17] 16 is a perspective view showing a part of a process for manufacturing the multilayer capacitor of FIG. 15. FIG. [Figure 18] 2 is a cross-sectional view showing a state in which the multilayer capacitor of FIG. 1 is mounted on a substrate. [Figure 19] FIG. 1 is a cross-sectional view showing a state in which a conventional two-terminal capacitor is mounted on a substrate. [Figure 20]1 is a graph showing a comparison of acoustic noise between a conventional two-terminal capacitor and a capacitor having a bottom mounting structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention is not limited to the embodiments described below. Furthermore, the embodiments of the present invention are provided to more completely explain the present invention to those having average knowledge in the art. Therefore, the shapes and sizes of elements in the drawings may be enlarged or reduced (or highlighted or simplified) for a clearer description.

[0017] In addition, components having the same function within the same concept shown in the drawings of each embodiment will be described using the same reference numerals.

[0018] In order to clearly explain the embodiments of the present invention, the directions of the capacitor body are defined as X, Y and Z in the drawings, which respectively indicate the length direction, width direction and thickness direction, where the thickness direction may be used in the same concept as the lamination direction of the dielectric layers and the internal electrodes.

[0019] In addition, in this embodiment, for convenience of explanation, both sides of the capacitor body 110 facing in the Z direction are set as the first and second sides S1, S2, both sides facing in the X direction and connecting the ends of the first and second sides S1, S2 are set as the third and fourth sides S3, S4, and both sides facing in the Y direction and connecting the ends of the first and second sides S1, S2 and the third and fourth sides S3, S4 are set as the fifth and sixth sides S5, S6. Here, the first side S1 can be used in the same concept as the mounting surface.

[0020] <First Example> Multilayer Capacitor FIG. 1 is an exploded perspective view showing a schematic upside-down stacked capacitor according to a first embodiment of the present invention, FIGS. 2(a) and (b) are plan views showing first and second internal electrodes in FIG. 1, respectively, and FIG. 3 is a side view of the capacitor body in FIG. 1.

[0021] 1 to 3, a multilayer capacitor 100 according to a first embodiment of the present invention includes a capacitor body 110 including a dielectric layer 111, first and second internal electrodes 121, 122, and first and second groove portions 121a, 122a, and first and second via electrodes 141, 142.

[0022] The capacitor body 110 is formed by stacking a plurality of dielectric layers 111, and may have a substantially hexahedral shape as shown in the figure, although there is no particular limitation thereto.

[0023] At this time, the shape and size of the capacitor body 110 and the number of laminated dielectric layers 111 are not limited to those shown in the drawings.

[0024] Furthermore, the dielectric layers 111 are in a sintered state, and the boundaries between adjacent dielectric layers 111 can be integrated to such an extent that they are difficult to confirm without using a scanning electron microscope (SEM).

[0025] The capacitor body 110 is a portion that contributes to forming the capacitance of the capacitor, and includes an active area including first and second internal electrodes 121 and 122, and upper and lower cover areas 112 and 113 disposed above and below the active area as marginal areas.

[0026] The active region may be formed by repeatedly stacking a plurality of first and second internal electrodes 121, 122 with a dielectric layer 111 sandwiched therebetween. At this time, the thickness of the dielectric layer 111 may be changed as desired according to the capacitance design of the multilayer capacitor 100. The dielectric layer 111 may contain ceramic powder having a high dielectric constant, for example, barium titanate (BaTiO3)-based or strontium titanate (SrTiO3)-based powder, but the present invention is not limited thereto. Furthermore, the dielectric layer 111 may further contain at least one of a ceramic additive, an organic solvent, a plasticizer, a binder, and a dispersant, etc., in addition to the ceramic powder, as necessary.

[0027] The upper and lower cover regions 112 and 113 are located at the upper and lower portions of the capacitor body 110 in the Z direction, respectively, and may have the same material and structure as the dielectric layer 111, except that they do not include internal electrodes.

[0028] The upper and lower cover regions 112, 113 may be formed by stacking a single dielectric layer or two or more dielectric layers 111 on the upper and lower outer edges of the active region in the Z direction, respectively, and may essentially serve to prevent damage to the first and second internal electrodes 121, 122 due to physical or chemical stress.

[0029] The first and second internal electrodes 121, 122 are electrodes having different polarities and are alternately arranged in the Z direction with the dielectric layer 111 sandwiched between them in the capacitor body 110. They can be formed by printing a conductive paste containing a conductive metal on the dielectric layer 111 to a predetermined thickness, and can be electrically insulated from each other by the dielectric layer 111 arranged therebetween.

[0030] The conductive metal contained in the conductive paste may be, for example, nickel (Ni), copper (Cu), palladium (Pd), or an alloy thereof, but the present invention is not limited thereto.

[0031] The conductive paste may be printed by screen printing, gravure printing, or the like, but the present invention is not limited thereto.

[0032] In this embodiment, the first and second internal electrodes 121, 122 are formed to be exposed to the third and fourth surfaces S3, S4 of the capacitor body 110. The area of ​​the first and second internal electrodes 121, 122 overlapping each other in the Z direction is related to the capacitance of the capacitor.

[0033] In this embodiment, the first and second internal electrodes 121 and 122 are exposed to the third and fourth surfaces S3 and S4 of the capacitor body 110, so that the overlap area between the first and second internal electrodes 121 and 122 can be maximized.

[0034] This makes it possible to increase the capacitance of the capacitor without adopting a method such as reducing the thickness of the existing dielectric layers 111 and internal electrodes and increasing the number of laminated layers of the internal electrodes.

[0035] The first groove 121a is provided to extend long along the Z direction on the third surface S3 of the capacitor body 110. At this time, the first groove 121a is provided such that one end is exposed to the first surface S1 of the capacitor body 110, and a part of an edge on one side in the X direction of the first internal electrode 121 (the left side in the drawing) is also removed.

[0036] The second groove portion 122a is provided to extend long along the Z direction on the fourth surface S4 of the capacitor body 110. At this time, the second groove portion 122a is provided such that one end is exposed to the first surface S1 of the capacitor body 110, and a part of an edge on one side in the X direction of the second internal electrode 122 (the right side in the drawing) is also removed.

[0037] In this embodiment, the shapes of the first and second groove portions 121a, 122a are illustrated and described as semicircular, but the present invention is not limited to this, and the shapes of the first and second groove portions 121a, 122a may be variously changed to a circle, a rectangle, a triangle, etc. as necessary.

[0038] The first via electrode 141 is formed by filling the first groove 121a with a conductive material or by castellation, and contacts an edge of the first internal electrode 121 corresponding to the first groove 121a to electrically connect the plurality of first internal electrodes 121 stacked in the Z direction. At this time, one end of the first via electrode 141 in the Z direction is exposed to the first surface S1 of the capacitor body 110.

[0039] The second via electrode 142 is formed by filling the second groove 122a with a conductive material or by castellation, and contacts the edge of the second internal electrode 122 corresponding to the second groove 122a to electrically connect the plurality of second internal electrodes 122 stacked in the Z direction. At this time, one end of the second via electrode 142 in the Z direction is exposed to the first surface S1 of the capacitor body 110.

[0040] Such first and second via electrodes 141, 142 can be formed from a conductive paste containing a conductive metal.

[0041] The conductive metal may be, for example, nickel (Ni), copper (Cu), palladium (Pd), gold (Au) or an alloy thereof, but the present invention is not limited thereto.

[0042] A third groove 121b is provided in an edge of the first internal electrode 121 in contact with the fourth surface S4 of the capacitor body 110. The third groove 121b is provided at a position corresponding to the second groove 122a and is larger than the second groove 122a. A fourth groove 122b is provided in an edge of the second internal electrode 122 in contact with the third surface S3 of the capacitor body 110. The fourth groove 122b is provided at a position corresponding to the first groove 121a and is larger than the first groove 121a.

[0043] Therefore, the first via electrode 141 is connected to the first internal electrode 121 by the first groove portion 121a, but is separated from the second internal electrode 122 by the fourth groove portion 121b, and is therefore electrically connected only to the multiple first internal electrodes 121 and not connected to the second internal electrode 122.

[0044] The second via electrode 142 is connected to the second internal electrode 122 by the second groove portion 122a, but is separated from the first internal electrode 121 by the third groove portion 122b, and is therefore electrically connected only to the multiple second internal electrodes 122 and not to the first internal electrode 121.

[0045] First and second external electrodes 131, 132 may be disposed on the first surface S1 of the capacitor body 110, spaced apart in the X-direction. The first external electrode 131 is electrically connected to the first via electrode 141 in a state of contact with a portion exposed on the first surface S1 of the capacitor body 110. The second external electrode 132 is electrically connected to the second via electrode 142 in a state of contact with a portion exposed on the first surface S1 of the capacitor body 110.

[0046] In this embodiment, the first and second external electrodes 131, 132 are formed in a substantially flat shape on the first surface S1 of the capacitor body 110, which makes it easy to make the thickness uniform, thereby reducing the variation (dispersion) of the chip size.

[0047] The first and second external electrodes 131 and 132 may be formed by plating a conductive metal.

[0048] On the third and fourth surfaces S3 and S4 of the capacitor body 110, first and second insulating layers 151 and 152 are formed.

[0049] The first and second insulating layers 151 and 152 may be formed by molding the third and fourth surfaces S3 and S4 of the capacitor body 110 with a non-conductive material or by attaching a required number of separate ceramic sheets, but the present invention is not limited thereto.

[0050] In this case, the first and second insulating layers 151 and 152 may be made of at least one material selected from the group consisting of insulating resin, insulating ceramic, and insulating resin and filler, but the present invention is not limited thereto.

[0051] Such first and second insulating layers 151, 152 serve to cover the portions of the first and second internal electrodes 121, 122 exposed to the third and fourth surfaces S3, S4 of the capacitor body 110 and the portions of the first and second via electrodes 141, 142 exposed to the third and fourth surfaces S3, S4 of the capacitor body.

[0052] In addition, the first and second insulating layers 151 and 152 may play a role in increasing the durability of the capacitor body 110 and further securing a margin of a predetermined thickness, thereby improving the reliability of the capacitor.

[0053] Furthermore, since the first and second insulating layers 151 and 152 are formed after the capacitor body 110 is formed, the size of the product can be minimized by minimizing their thickness within the limits where the insulation properties, durability of the capacitor body, and reliability of the capacitor are maintained at a certain level.

[0054] In the multilayer capacitor 100 configured as described above, the volume of the external terminals and the height of the entire capacitor are minimized, so that the volume and height of the internal electrodes can be relatively increased, thereby further improving the capacitance of the capacitor.

[0055] Furthermore, since the thickness of the capacitor is very thin, it is possible to manufacture a thin-film multilayer capacitor having a thickness of 100 μm or less.

[0056] <Modified Example> FIG. 4 is an exploded perspective view showing another embodiment of the groove and the via electrode in the multilayer capacitor of FIG.

[0057] Here, the structures of the dielectric layer 111, the first and second external electrodes 131, 132, and the first and second insulating layers 151, 152 are similar to those in the above-described embodiment, and therefore detailed descriptions thereof will be omitted to avoid duplication.

[0058] Referring to FIG. 4, a capacitor body 110 ′ of a multilayer capacitor 100 ′ may include a plurality of first and second grooves 121 a ′ and 122 a ′ and a plurality of first and second via electrodes 141 and 142 .

[0059] Two first grooves 121a' are provided spaced apart from each other in the Y direction on the third surface S3 of the capacitor body 110', and a first via electrode 141 may be formed in each of the first grooves 121a'.

[0060] In addition, two second grooves 122a' are provided spaced apart from each other in the Y direction on the fourth surface S4 of the capacitor body 110', and a second via electrode 142 may be formed in each of the second grooves 122a'.

[0061] Meanwhile, although FIG. 4 illustrates and explains that there are two first and two second grooves, three or more first and second grooves may be provided as necessary.

[0062] 5(a) and (b) are plan views showing other embodiments of the first and second internal electrodes in the multilayer capacitor of FIG. 1, and FIG. 6 is a side view showing one side of a capacitor body to which the internal electrode of FIG. 5 is applied.

[0063] Here, the structures of the dielectric layer 111, the first and second via electrodes 141, 142, the first and second external electrodes 131, 132, and the first and second insulating layers 151, 152 are similar to those of the above-mentioned embodiments, so detailed descriptions will be omitted to avoid duplication.

[0064] Referring to Figures 5(a) and 6, the first internal electrode 123 is exposed to the third surface S3 of the capacitor body 110 and is spaced apart from the fourth surface S4, and the second internal electrode 124 is exposed to the fourth surface S4 of the capacitor body 110 and is spaced apart from the third surface S3.

[0065] The first groove portion 123a is provided such that a portion of the edge on one side in the X direction of the first internal electrode 123 (the left side in the drawing) is removed, and the second groove portion 124a is provided such that a portion of the edge on the other side in the X direction of the second internal electrode 124 (the right side in the drawing) is removed.

[0066] In this case, the distance between the edge of the first internal electrode 123 and the fourth surface S4 of the capacitor body 110 must be such that it does not overlap with the second groove portion 124a, and the distance between the edge of the second internal electrode 124 and the third surface S3 of the capacitor body 110 must be such that it does not overlap with the first groove portion 123a.

[0067] Then, the first and second via electrodes 141, 142 are formed in the first and second groove portions 123a, 124a, so that the first via electrode 141 is connected to the first internal electrode 123 by the first groove portion 123a but is not connected to and separated from the second internal electrode 124. Similarly, the second via electrode 142 is connected to the second internal electrode 124 by the second groove portion 124a but is not connected to and separated from the first internal electrode 123.

[0068] 7(a) and (b) are plan views respectively showing still another embodiment of the first and second internal electrodes in the multilayer capacitor of FIG. 1, and FIG. 8 is a side view showing one side of a capacitor body to which the internal electrode of FIG. 7 is applied.

[0069] Here, the structures of the dielectric layer 111, the first and second via electrodes 141, 142, the first and second external electrodes 131, 132, and the first and second insulating layers 151, 152 are similar to those of the above-mentioned embodiments, so detailed descriptions will be omitted to avoid duplication.

[0070] 7(a) and 8, the first and second internal electrodes 125, 126 are all spaced apart from the third and fourth faces S3, S4 of the capacitor body 110. In particular, the first internal electrode 125 has a separation distance m3 between the surface facing the fourth face S4 of the capacitor body 110 in the X direction that is greater than the separation distance m1 between the surface facing the third face S3 of the capacitor body 110. Similarly, the second internal electrode 126 has a separation distance m4 between the surface facing the third face S3 of the capacitor body 110 in the X direction that is greater than the separation distance m2 between the surface facing the fourth face S4 of the capacitor body 110.

[0071] The first groove portion 125a is provided such that a portion of the edge on one side in the X direction of the first internal electrode 125 (the left side in the drawing) is removed, and the second groove portion 126a is provided such that a portion of the edge on the other side in the X direction of the second internal electrode 126 (the right side in the drawing) is removed.

[0072] In this case, the distance m3 between the edge of the first internal electrode 125 and the fourth surface S4 of the capacitor body 110 must be such that it does not overlap with the second groove portion 126a, and the distance m4 between the edge of the second internal electrode 126 and the third surface S3 of the capacitor body 110 must be such that it does not overlap with the first groove portion 125a.

[0073] Then, since the first and second via electrodes 141, 142 are formed in the first and second groove portions 125a, 126a, the first via electrode 141 is connected to the first internal electrode 125 by the first groove portion 125a, but is not connected to the second internal electrode 126 in a separated state. Similarly, the second via electrode 142 is connected to the second internal electrode 126 by the second groove portion 126a, but is not connected to the first internal electrode 125 in a separated state.

[0074] In this embodiment, the internal electrodes are disposed at separate positions inside the capacitor body, thereby improving the effect of preventing cracks and delamination that mainly occur at the four corners of the capacitor body.

[0075] <Second Example> Multilayer Capacitor FIG. 9 is a schematic perspective view of a multilayer capacitor according to a second embodiment of the present invention, FIGS. 10(a) and (b) are plan views showing first and second internal electrodes, respectively, in the multilayer capacitor of FIG. 9 before the first and second groove portions are provided, and FIG. 11 is a perspective view showing the capacitor body in FIG. 9 excluding the first and second via electrodes.

[0076] Hereinafter, detailed explanations of parts similar to those in the first embodiment will be omitted to avoid duplication.

[0077] In addition, in this embodiment, for convenience of explanation, one surface (MS, the front surface in the drawing) of the capacitor body 210 in the Y direction is set as the mounting surface.

[0078] 9 to 11, a multilayer capacitor 200 according to a second embodiment of the present invention includes a capacitor body 210 including a dielectric layer 211, first and second internal electrodes 221, 222, and first and second groove portions 231, 232, and first and second via electrodes 241, 242.

[0079] The first internal electrode 221 includes a first body portion 221a and a first lead portion 221b extending from the first body portion 221a and exposed to the mounting surface MS of the capacitor body 210. The second internal electrode 222 includes a second body portion 222a overlapping the first body portion 221a and a second lead portion 222b extending from the second body portion 222a and exposed to the mounting surface MS of the capacitor body 210. At this time, the first and second lead portions 221b, 222b are spaced apart in the X direction.

[0080] The first groove 231 is provided long along the Z direction on the mounting surface MS of the capacitor body 210. At this time, the first groove 231 is provided such that a part of the first lead portion 221b is removed together.

[0081] The second groove portion 232 is provided long in the Z direction at a position spaced apart from the first groove portion 241 in the X direction on the mounting surface MS of the capacitor body 210. At this time, the second groove portion 232 is provided such that a portion of the second lead portion 222b is removed together with the second groove portion 232.

[0082] In this embodiment, the cross sections of the first and second groove portions 231, 232 are shown and described as semicircular, but the present invention is not limited to this, and the shapes of the first and second groove portions 231, 232 can be changed to various shapes such as a circular cross section, a rectangular cross section, and a triangular cross section as necessary.

[0083] The first via electrode 241 is formed by filling or castellating a conductive material in the first groove 231. Also, the first via electrode 241 contacts the cut portion of the first lead portion 221b corresponding to the first groove 231, and electrically connects the plurality of first internal electrodes 221 stacked in the Z direction.

[0084] The second via electrode 242 is formed by filling or castellating a conductive material in the second groove 232. Also, the second via electrode 242 contacts the cut portion of the second lead portion 222b corresponding to the second groove 232, and electrically connects the plurality of second internal electrodes 222 stacked in the Z direction.

[0085] In this embodiment, the first and second lead portions 221b, 222b are all exposed to the mounting surface MS of the capacitor body 210, and the first and second via electrodes 241, 242 exposed to the mounting surface MS of the capacitor body 210 serve as external terminals to be mounted on a substrate.

[0086] That is, this embodiment has a bottom mounting structure, and when a voltage is applied, a current path is shortened, thereby reducing the inductance of the multilayer capacitor 200.

[0087] 12 to 14 are perspective and cross-sectional views showing some of the steps for manufacturing the multilayer capacitor of FIG.

[0088] A method for manufacturing the multilayer capacitor of this embodiment will be described below with reference to the above drawings.

[0089] First, a plurality of first and second ceramic sheets are provided.

[0090] Next, a conductive paste is printed to a predetermined thickness on one surface of the first and second ceramic sheets to form first and second internal electrodes, each of which has a first and second body portion and a first and second lead portion extending perpendicularly in the same direction from the first and second body portions.

[0091] Next, the first and second ceramic sheets on which the first and second internal electrodes are formed are alternately stacked in the Z direction and compressed to provide a bar-shaped laminate. At this time, the first and second ceramic sheets are stacked such that the first and second lead portions are not positioned to overlap each other in the Z direction.

[0092] Next, the laminate is punched at regular intervals at positions that correspond to the positions from which the first and second leads will be drawn when the laminate is cut into individual chips.

[0093] As a result, as shown in FIG. 12, a laminate 2100 is provided having a plurality of holes 250 through which parts of the first and second lead portions are alternately exposed.

[0094] Next, as shown in Figures 13 and 14, the holes 250 of the laminate 2100 are filled with a film 400 cast with a conductive material using pressure to provide a laminate 2100 having a plurality of vias 240 formed therein.

[0095] At this time, the vias 240 are processed so that there are no protruding portions on the upper and lower surfaces of the laminate 2100, so that after the capacitor is manufactured, the size of the capacitor body can be prevented from increasing due to the volume of the protruding vias.

[0096] Next, the laminate 2100 is cut into chips for each region corresponding to each multilayer capacitor, and then fired to complete a multilayer capacitor having first and second via electrodes.

[0097] <Modified Example> FIG. 15 is a perspective view showing yet another embodiment of the first and second via electrodes in the multilayer capacitor according to the second embodiment of the present invention, and FIG. 16 is a perspective view showing the capacitor body in FIG. 15 excluding the first and second via electrodes.

[0098] Here, the structures of the dielectric layer 111 and the first and second internal electrodes 221 and 222 are similar to those in the above-described embodiment, and therefore detailed description thereof will be omitted to avoid duplication.

[0099] 15 and 16, the first groove 233 of the multilayer capacitor 200′ is provided such that one corner in the X direction of the capacitor body 210′ ​​(the left side in the drawings) is removed, and the second groove 234 is provided such that the other corner in the X direction of the capacitor body 210′ ​​(the right side in the drawings) is removed. Then, the first and second grooves 233 and 234 are filled with a conductive material or castellated to form first and second via electrodes 243 and 244.

[0100] Meanwhile, Fig. 17 is a perspective view showing a part of a process for manufacturing the multilayer capacitor of Fig. 15. Referring to Fig. 17, in this embodiment, the position where the hole 250' is formed in the multilayer body 2100' during the punching operation is a point that becomes a corner part of the capacitor body adjacent to the position where the first and second lead parts are pulled out when cut into individual chips.

[0101] <Mounting board for multilayer capacitors> 18, the mounting board for the multilayer capacitor according to this embodiment includes a substrate 311 on which the multilayer capacitor 100 is mounted, and first and second electrode pads 321 and 322 disposed on an upper surface of the substrate 311 at a distance from each other.

[0102] The multilayer capacitor 100 may be fixed by solders 331 and 332 in a state where the first and second external electrodes 131 and 132 are in contact with and positioned on the first and second electrode pads 321 and 322, respectively, and may be electrically connected to the substrate 311.

[0103] In the mounting board for the multilayer capacitor configured as described above, the first and second external electrodes 131, 132 of the multilayer capacitor 100 are exposed only on the mounting surface of the capacitor body 110, so that the area a on which the solder 331, 332 is formed when mounted on the substrate 211 can be minimized.

[0104] In this way, by reducing the formation area a of the solders 331 and 332, it is possible to reduce acoustic noise. Furthermore, assuming that the mounting area is the same, the capacitance of the capacitor can be relatively increased by increasing the chip size by further securing a size of about b compared to conventional capacitors.

[0105] 19, in a conventional two-terminal multilayer capacitor 10, first and second external electrodes 31, 32 surround both ends of a capacitor body 11, and the area c on which solder 333, 334 is formed when mounted on a substrate 311 is relatively larger than that of the capacitor in FIG.

[0106] In this way, if the formation area c of the solders 333 and 334 is increased, the acoustic noise increases. Furthermore, assuming that the mounting area is the same, a larger solder formation area is required than in the capacitor of FIG. 18, and as the chip size becomes smaller, the capacitance of the capacitor becomes smaller relatively.

[0107] Moreover, the multilayer capacitor 200 of this embodiment has a bottom mounting structure, which can reduce acoustic noise.

[0108] 20, the comparative example shows acoustic noise of the two-terminal structure capacitor shown in FIG. 19, and the working example shows the stacked capacitor with the bottom mounting structure shown in FIG.

[0109] Referring to FIG. 20, it can be seen that in the embodiment, the acoustic noise is reduced across all frequencies compared to the comparative example.

[0110] Meanwhile, FIG. 18 illustrates and describes a form in which the stacked capacitor of FIG. 1 is mounted, but the present invention is not limited thereto, and the stacked capacitor of FIG. 9 or FIG. 15 may also be mounted on a substrate in a similar structure to form a mounting substrate.

[0111] Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that the scope of the present invention is not limited thereto, and that various modifications and variations are possible within the scope of the technical idea of ​​the present invention described in the claims. [Explanation of symbols]

[0112] 100, 200 Stacked capacitor 110, 210 Capacitor body 111, 211 Dielectric layer 112, 113 Upper and lower cover areas 121, 122 First and second internal electrodes 121a, 122a First and second groove portions 121b, 122b Third and fourth groove portions 131, 132 First and second external electrodes 141, 142 First and second via electrodes 151, 152 First and second insulating layers 221, 222 First and second internal electrodes 221a, 222a First and second body parts 221b, 222b First and second lead portions 231, 232 First and second grooves 241, 242 First and second via electrodes 311 Substrate 321, 322 First and second electrode pads 331, 332 Solder

Claims

1. a capacitor body including first and second surfaces facing each other along a first direction, third and fourth surfaces facing each other in a second direction perpendicular to the first direction, and fifth and sixth surfaces facing each other in a third direction perpendicular to the first and second directions, the capacitor body including a dielectric layer and first and second internal electrodes alternately disposed with the dielectric layer therebetween; first and second via electrodes that are partially embedded in the capacitor body and electrically connected to the first and second internal electrodes, respectively; a first insulating layer disposed on a third surface of the capacitor body; a second insulating layer disposed on a fourth surface of the capacitor body; a first external electrode disposed on a first surface of the capacitor body and spaced apart from each other, the first external electrode electrically connected to the first via electrode and the second via electrode, respectively; an outer surface of the first via electrode exposed by the capacitor body and an outer surface of the second via electrode exposed by the capacitor body are located on the same plane as third and fourth surfaces of the capacitor body, respectively; the first and second internal electrodes are spaced apart from third to sixth surfaces of the capacitor body; the first via electrode is disposed on a third surface of the capacitor body such that a first-1 end of the first internal electrode has a recess; the second via electrode is disposed on a fourth surface of the capacitor body such that a second-1 end of the second internal electrode has a recess; a linear 1-2 end portion of the first internal electrode facing the 1-1 end portion in the second direction is spaced apart from a second via electrode, and a distance from the 1-2 end portion of the first internal electrode to a fourth surface of the capacitor body is greater than a distance from the 1-1 end portion of the first internal electrode to a third surface of the capacitor body; a linear second-2 end portion of the second internal electrode facing the second-1 end portion in the second direction is spaced apart from a first via electrode, and a distance from the second-2 end portion of the second internal electrode to a third surface of the capacitor body is greater than a distance from the second-1 end portion of the second internal electrode to a fourth surface of the capacitor body; The first and second external electrodes are disposed only on a first surface of the capacitor body and are formed to both ends of the first surface in the third direction. Stacked capacitor.

2. the first insulating layer covers an outer surface of the first via electrode exposed by the capacitor body; The multilayer capacitor according to claim 1 , wherein the second insulating layer covers an outer surface of the second via electrode exposed by the capacitor body.

3. The multilayer capacitor according to claim 1 , further comprising two or more first and second via electrodes.

4. a substrate having first and second electrode pads on an upper surface thereof; A multilayer capacitor mounting substrate comprising: the multilayer capacitor according to claim 1 mounted on the substrate.

5. forming a laminated body including one or more dielectric layers, a plurality of first and second internal electrodes alternately laminated with the dielectric layers interposed therebetween; forming a plurality of holes penetrating the laminated body such that the first and second internal electrodes are exposed to the holes; filling the plurality of holes with a first conductive material; cutting the laminated body along paths passing through the holes filled with the first conductive material to form a plurality of capacitor bodies, each of the plurality of capacitor bodies including first and second surfaces facing each other along a first direction, third and fourth surfaces facing each other in a second direction perpendicular to the first direction, and fifth and sixth surfaces facing each other in a third direction perpendicular to the first and second directions; each of the capacitor bodies after the cutting includes a first via electrode and a second via electrode electrically connected to the first and second internal electrodes, the first conductive material being partially embedded in the respective capacitor bodies; the first and second internal electrodes are spaced apart from third and fourth surfaces of the capacitor body, the first via electrode is disposed on a third surface of the capacitor body such that a first-1 end of the first internal electrode has a recess; the second via electrode is disposed on a fourth surface of the capacitor body such that a second-1 end of the second internal electrode has a recess; a linear 1-2 end portion of the first internal electrode facing the 1-1 end portion in the second direction is spaced apart from a second via electrode, and a distance from the 1-2 end portion of the first internal electrode to a fourth surface of the capacitor body is greater than a distance from the 1-1 end portion of the first internal electrode to a third surface of the capacitor body; a linear second-2 end portion of the second internal electrode facing the second-1 end portion in the second direction is spaced apart from a first via electrode, and a distance from the second-2 end portion of the second internal electrode to a third surface of the capacitor body is greater than a distance from the second-1 end portion of the second internal electrode to a fourth surface of the capacitor body; After forming the plurality of capacitor bodies, forming first and second external electrodes from a second conductive material only on a first surface of the capacitor body to both ends of the first surface in the third direction, the first and second external electrodes being electrically connected to the first and second internal electrodes via the first conductive material; A method for manufacturing a multilayer capacitor.

6. In each of the capacitor bodies, The method for manufacturing a multilayer capacitor according to claim 5 , wherein the first via electrode and the second via electrode are exposed on different surfaces of the capacitor body formed by cutting.

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