Semiconductor Device

Abstract

The present invention improves the radiation resistance of a solid-state imaging element.　A semiconductor device (100) is provided with a semiconductor substrate (1), and a pixel circuit (10) formed on the semiconductor substrate. The pixel circuit comprises: a first semiconductor region (2) of a first conductivity type, said region being formed on the semiconductor substrate; a second semiconductor region (3) of a second conductivity type, said region being formed over the first semiconductor region and constituting, together with the first semiconductor region, a photodiode (PPD); third semiconductor regions (6, 7) of the second conductivity type, said regions being formed on the semiconductor substrate so as to be spaced apart from the second semiconductor region and so as to surround the photodiode in the plan view; and a gate region (5) that is formed between the second semiconductor region and the third semiconductor region as seen from a direction perpendicular to the plane of the semiconductor substrate and that, together with the second semiconductor region and the third semiconductor region, constitutes an overflow transistor (Mpdr) for draining a charge that has accumulated in the photodiode.

Description

[Technical field]

[0001] The present invention relates to a semiconductor device, for example, a semiconductor device having a solid-state image sensor formed on a semiconductor substrate. [Background technology]

[0002] In decommissioning work at nuclear facilities, an imaging device is attached to the tip of a robot arm or the like in order to perform work while grasping the situation inside the facility in a high radiation environment. In recent years, as an imaging device to be used in a high radiation environment, there has been a demand for a radiation-resistant camera that is small, lightweight, and equipped with a solid-state imaging element with high image quality, rather than the large, low-image-quality imaging tubes used in conventional radiation-resistant cameras.

[0003] However, it is known that the characteristics of solid-state imaging elements formed on semiconductor substrates are deteriorated by the total dose effect of radiation such as gamma rays. For example, in the case of solid-state imaging elements such as CMOS (Complementary Metal Oxide Semiconductor) image sensors, the dark current of the photodiode serving as the light sensor increases due to the ionization effect of the total dose effect of gamma rays, causing operational malfunction due to whiteout. The whiteout due to the total dose effect also shortens the life of the solid-state imaging element and, in turn, the camera. For example, the cumulative radiation dose, which is an index of the radiation resistance of an imaging tube, is several megaGy, but the cumulative radiation dose of a solid-state imaging element is several kiloGy to 100 kiloGy. In addition, secondary electrons generated by the ionization effect of radiation in the semiconductor constituting the photodiode enter the photodiode, causing false signals in the captured image, lowering the S / N ratio of the image, which looks like a sandstorm. Thus, conventional solid-state imaging devices cannot be said to have high radiation resistance.

[0004] Meanwhile, a technology for improving the radiation resistance of a solid-state imaging element is disclosed in Patent Document 1. Specifically, Patent Document 1 discloses a solid-state imaging element with improved radiation resistance by employing a pinned photodiode (PPD) in which an N-well is formed on a P-well and a P-region of a pinning layer is formed on a surface portion in contact with an interlayer insulating oxide film (Pre-Metal Dielectric: PMD). Here, the PPD has a structure surrounded by an element isolation oxide film layer made of STI (Shallow Trench Isolation). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2019-201164 A [Patent Document 2] Japanese Patent Application Publication No. 58-210662 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the technique disclosed in Patent Document 1 alone is not sufficient for suppressing the dark current of the photodiode, which causes whiteout.

[0007] For example, when radiation hits the device isolation oxide layer (STI) around the photodiode, a fixed positive charge is generated due to the total dose effect, and due to the influence of this fixed positive charge, the P-well region near the device isolation oxide layer is inverted to N-type, forming an N-type inversion region. Dark current flows from this N-type inversion region into the N-type diffusion region of the photodiode, which may cause a whiteout in the image.

[0008] One method for solving this problem is to surround the periphery of the photodiode not with an element isolation oxide film layer, but with the gate of a charge discharging transistor for resetting the photodiode and the drain of the charge discharging transistor (see Patent Document 2). With this method, the drain of the charge discharging transistor functions as a guard ring around the photodiode, and the photodiode and the element isolation oxide film layer are not in direct contact with each other, so that it is possible to suppress dark current.

[0009] However, even when the above-described structure is adopted, an element isolation oxide film layer is inevitably formed around the charge discharging transistor, and therefore, there is a risk that dark current generated by the total dose effect of radiation will flow through the semiconductor substrate into the photodiode, causing a whiteout in the image.

[0010] The present invention has been made in consideration of the above-mentioned problems, and has an object to improve the radiation resistance of a solid-state imaging device. [Means for solving the problem]

[0011] A semiconductor device according to a representative embodiment of the present invention comprises a semiconductor substrate and a pixel circuit formed on the semiconductor substrate, the pixel circuit comprising: a first semiconductor region of a first conductivity type formed on the semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region; a third semiconductor region of a second conductivity type formed on the semiconductor substrate and spaced apart from the second semiconductor region so as to surround the photodiode in a planar view; and a gate region formed between the second semiconductor region and the third semiconductor region when viewed from a direction perpendicular to the plane of the semiconductor substrate, and constituting an overflow transistor together with the second semiconductor region and the third semiconductor region that discharges charge accumulated in the photodiode. Effect of the Invention

[0012] According to the semiconductor device of the present invention, it is possible to improve the radiation resistance of the solid-state imaging element. [Brief description of the drawings]

[0013] [Figure 1] 1 is a diagram showing a configuration of one pixel circuit that constitutes a solid-state imaging device as a semiconductor device according to a first embodiment. [Figure 2A] 1 is a plan view showing a layout configuration of a pixel circuit of a semiconductor device according to a first embodiment. [Figure 2B] 2B is a diagram showing a schematic cross-sectional structure of the pixel circuit shown in FIG. 2A taken along the line BB'. FIG. [Figure 3A] 1 is a plan view showing a layout configuration of a semiconductor device in which a plurality of pixel circuits according to a first embodiment are arranged. [Figure 3B] 3B is a diagram showing a schematic cross-sectional structure of the semiconductor device shown in FIG. 3A taken along the line CC'. FIG. [Figure 4] FIG. 11 is a plan view showing a layout configuration of a semiconductor device according to a second embodiment. [Diagram 5] FIG. 11 is a plan view showing a layout configuration of a pixel circuit of a semiconductor device according to a third embodiment. [Figure 6] FIG. 11 is a plan view showing a layout configuration of a semiconductor device according to a third embodiment. [Figure 7] FIG. 11 is a plan view showing a layout configuration of a pixel circuit of a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 13 is a plan view showing a layout configuration of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] 1. Overview of the embodiment First, a typical embodiment of the invention disclosed in this application will be outlined. In the following description, as an example, reference numerals in the drawings corresponding to components of the invention are given in parentheses.

[0015] [1] A semiconductor device (100, 100A, 100B) according to a representative embodiment of the present invention comprises a semiconductor substrate (1) and a pixel circuit (10, 10B) formed on the semiconductor substrate, the pixel circuit being characterized in having: a first semiconductor region (2) of a first conductivity type (P type) formed on the semiconductor substrate; a second semiconductor region (3) of a second conductivity type (N type) formed on the first semiconductor region and constituting a photodiode (PPD) together with the first semiconductor region; a third semiconductor region (6, 7) of a second conductivity type formed on the semiconductor substrate and spaced apart from the second semiconductor region so as to surround the photodiode in a planar view; and a gate region (5) formed between the second semiconductor region and the third semiconductor region when viewed from a direction perpendicular to the plane of the semiconductor substrate, and constituting an overflow transistor (Mpdr) together with the second semiconductor region and the third semiconductor region that discharges charge accumulated in the photodiode.

[0016] [2] In the semiconductor device (100, 100A, 100B) described in [1] above, the photodiode may be formed in a polygonal shape in a planar view, the third semiconductor region may be formed in a form surrounding at least one side of the polygonal photodiode in a planar view, and the gate region may be formed between the second semiconductor region and the third semiconductor region in a form surrounding at least the other side of the photodiode in a planar view.

[0017] [3] In the semiconductor device (100, 100A, 100B) described in [2] above, the pixel circuit further includes a transfer transistor (Mtg) that transfers the charge of the photodiode, a charge storage section (FD) that stores the charge transferred by the transfer transistor, a reset transistor (Mfdr) that resets the voltage of the charge storage section, an amplification transistor (Mdrv) that amplifies a signal corresponding to the charge stored in the charge storage section, and a selection transistor (Msel) that switches whether or not to output the signal amplified by the amplification transistor to a signal line (OUT), and the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor may be formed in a region on one side of the photodiode when viewed in a planar view.

[0018] [4] The semiconductor device (100, 100A, 100B) described in [3] above may have a plurality of the pixel circuits, and the plurality of pixel circuits may be formed, in a planar view, side by side in a column direction (Y-axis direction) which is a predetermined direction in the plane of the semiconductor substrate, and a row direction (X-axis direction) which is a direction perpendicular to the column direction, and the pixel circuits adjacent to each other in the row direction may have the third semiconductor region in common with each other in the row direction.

[0019] [5] In the semiconductor device (100, 100B) described in [4] above, the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor of the pixel circuit in an odd row are arranged on one side in the column direction, and the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor of the pixel circuit in an even row are arranged on the other side in the column direction, and two pixel circuits in which the overflow transistors are adjacent to each other in the column direction may have the third semiconductor region in common with each other in the column direction.

[0020] [6] In the semiconductor device (100A) described in [4] above, the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor of each of the pixel circuits may be arranged on one side of the column direction, and adjacent pixel circuits in the row direction and the column direction may be arranged so that the distance between the photodiodes of each pixel circuit is equal (L12=L13).

[0021] [7] In the semiconductor device (100B) described in [4] above, the third semiconductor region of each of the pixel circuits may be formed in contact with the second pixel boundary line, such that a distance (Lp1) from a first pixel boundary line (A) in the row direction on the side on which the transfer transistor, the reset transistor, the amplifying transistor, and the selection transistor are formed to an end of the photodiode is equal to a distance (Lp2) from a second pixel boundary line (A') in the row direction on the opposite side of the photodiode to the first pixel boundary line.

[0022] [8] A semiconductor device (100C) according to another representative embodiment of the present invention comprises a semiconductor substrate (1) and a pixel circuit (10C) formed on the semiconductor substrate, the pixel circuit comprising: a first semiconductor region (2) of a first conductivity type formed on the semiconductor substrate; a second semiconductor region (3) of a second conductivity type formed on the first semiconductor region and constituting a polygonal photodiode (PPD) together with the first semiconductor region; a gate region (5) formed to surround at least the other sides of the polygonal photodiode except for one side in a planar view; and a third semiconductor region (6C, 7C) of a second conductivity type formed along one of the other sides of the photodiode surrounded by the gate region in a planar view, spaced apart from the second semiconductor region across the gate region, and constituting an overflow transistor (Mpdr) together with the second semiconductor region and the gate region that discharges charge accumulated in the photodiode.

[0023] [9] In the semiconductor device described in [8] above, the semiconductor device may include a plurality of the pixel circuits (10C), and the plurality of pixel circuits may be formed, in a plan view, side-by-side in a column direction (Y-axis direction) that is a predetermined direction in the plane of the semiconductor substrate and a row direction (X-axis direction) that is a direction perpendicular to the column direction, and the pixel circuits adjacent to each other in the row direction may have the gate region in common with each other in the row direction.

[0024] 2. Specific examples of embodiments Hereinafter, specific examples of the embodiments of the present invention will be described with reference to the drawings. In the following description, components common to each embodiment will be given the same reference numerals, and repeated description will be omitted. It should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from the actual situation. The drawings may also include parts with different dimensional relationships and ratios. In addition, in this specification, the first conductivity type is described as P type and the second conductivity type is described as N type as an example, but the present invention is not limited to this.

[0025] First Embodiment FIG. 1 is a diagram showing the configuration of one pixel circuit constituting a solid-state imaging device as a semiconductor device according to the first embodiment.

[0026] The semiconductor device 100 according to the first embodiment is, for example, a CMOS image sensor serving as a solid-state imaging element, and is formed on a single semiconductor substrate such as silicon using, for example, a known CMOSLSI manufacturing technique.

[0027] The semiconductor device 100 has a plurality of pixel circuits 10 formed on a semiconductor substrate. The pixel circuit 10 is, for example, a five-transistor type pixel circuit in which an overflow transistor Mpdr is further added to a four-transistor type pixel circuit having four transistors, also called an APS (Active Pixel Sensor). Specifically, the pixel circuit 10 has a photodiode PPD, a transfer transistor Mtg, a charge storage unit FD, a reset transistor Mfdr, an amplification transistor Mdrv, a selection transistor Msel, and an overflow transistor Mpdr.

[0028] The photodiode PPD is, for example, a pinned photodiode, as described later. In the photodiode PPD, an anode electrode is connected to the ground potential GND, and a cathode electrode is connected to the transfer transistor Mtg.

[0029] The transfer transistor Mtg is an element for transferring the charge of the photodiode PPD, and is, for example, a MOS transistor of a second conductivity type (N-type).

[0030] In the transfer transistor Mtg, the source electrode is connected to the cathode electrode of the photodiode PPD, and the drain electrode is connected to the gate electrode of the amplification transistor Mdrv and the source electrode of the reset transistor Mfdr. A binary signal φTG is input to the gate electrode of the transfer transistor Mtg. The transfer transistor Mtg is switched on and off by the signal φTG.

[0031] The charge storage unit (Floating Diffusion) FD stores the charge transferred by the transfer transistor Mtg. The charge storage unit FD is formed at a node where the drain electrode of the transfer transistor Mtg, the gate electrode of the amplification transistor Mdrv, and the source electrode of the reset transistor Mfdr are commonly connected. The charge storage unit FD is realized by, for example, parasitic capacitance and floating capacitance present at the node.

[0032] The reset transistor Mfdr is a charge discharging element that resets the voltage of the charge storage unit FD. The reset transistor (charge discharging transistor) Mfdr is, for example, a second conductivity type (N-channel type) MOS transistor. The source electrode of the reset transistor Mfdr is connected to the charge storage unit FD, and the drain electrode of the reset transistor Mfdr is connected to a power supply voltage VRR. A binary signal φFDR is input to the gate electrode of the reset transistor Mfdr. The reset transistor Mfdr is switched on / off by the signal φFDR.

[0033] The amplification transistor Mdrv is an element that amplifies a signal corresponding to the charge stored in the charge storage unit FD. The amplification transistor Mdrv is, for example, a MOS transistor of a second conductivity type (N-channel type), and configures a source follower circuit.

[0034] The drain electrode of the amplifier transistor Mdrv is connected to a power supply voltage VDD, and the gate electrode of the amplifier transistor is connected to the charge storage unit FD. The source electrode of the amplifier transistor Mdrv is connected to the output signal line OUT via the selection transistor Msel.

[0035] The selection transistor Msel is an element that switches whether or not the signal amplified by the amplification transistor Mdrv is output to the output signal line OUT. The selection transistor Msel is, for example, a MOS transistor of a second conductivity type (N-channel type).

[0036] The drain electrode of the selection transistor Msel is connected to the source electrode of the amplification transistor Mdrv, and the source electrode of the selection transistor Msel is connected to the output signal line OUT. A signal φSEL is input to the gate electrode of the selection transistor Msel. The selection transistor Msel is switched on and off by the signal φSEL.

[0037] The overflow transistor Mpdr is an element that discharges the charge accumulated in the photodiode PPD. The overflow transistor Mpdr is, for example, a MOS transistor of the second conductivity type (N-channel type).

[0038] The overflow transistor Mpdr is connected between a power supply voltage VRR and the cathode electrode of the photodiode PPD. Specifically, the drain electrode of the overflow transistor Mpdr is connected to the power supply voltage VRR, and the source electrode of the overflow transistor Mpdr is connected to the cathode electrode of the photodiode PPD. A binary signal φPDR is input to the gate electrode of the overflow transistor Mpdr. The on / off of the overflow transistor Mpdr is switched by the signal φPDR.

[0039] Here, the power supply voltage VDD is the power supply of the source follower circuit (amplification transistor Mdrv), and the power supply voltage VRR is the power supply for resetting the charge storage unit FD and the photodiode PPD. By separating the power supply voltage VDD and the power supply voltage VRR, it becomes possible to optimize the operating conditions of the pixel. The power supply voltage for resetting the charge storage unit FD and the power supply voltage for resetting the photodiode PPD may be separated. In addition, in the present embodiment, the case where the power supply voltage VDD and the power supply voltage VRR are separated is illustrated as an example, but the present invention is not limited to this, and the power supply voltage VDD and the power supply voltage VRR may be common.

[0040] The photodiode PPD accumulates charge according to the received optical signal. The transfer transistor Mtg turns on when the signal φTG is enabled, and transfers the charge accumulated by the photodiode PPD to the charge accumulation unit FD. The amplification transistor Mdrv amplifies a signal according to the charge accumulated in the charge accumulation unit FD and outputs it to the node N1. The selection transistor Msel turns on when the signal φSEL is enabled, and outputs the signal of the node N1 to the output signal line OUT. The reset transistor Mfdr turns on when the signal φFDR is enabled, and connects the power supply voltage VRR to the charge accumulation unit FD. As a result, the electrons accumulated in the charge accumulation unit FD are discharged to the power supply voltage VRR, and the charge accumulation unit FD is reset.

[0041] The overflow transistor Mpdr turns on when the signal φPDR is enabled, and connects the power supply voltage VRR, which is higher than the depletion voltage of the photodiode, to the cathode electrode of the photodiode PPD in which charge is accumulated. This causes the electrons accumulated in the photodiode PPD to be discharged to the power supply voltage VRR, and the photodiode PPD is reset. In this way, the overflow transistor Mpdr can function as an electronic shutter for the photodiode PPD.

[0042] FIG. 2A is a plan view showing a layout configuration of pixel circuit 10 of semiconductor device 100 according to embodiment 1. FIG.

[0043] FIG. 2B is a diagram illustrating a schematic cross-sectional structure of the pixel circuit 10 shown in FIG. 2A taken along line BB'.

[0044] 2A and 2B, the semiconductor substrate 1 is disposed in a three-dimensional space consisting of an X-axis, a Y-axis, and a Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Also, the line segment connecting points B and B' is parallel to the X-axis. FIG. 2A shows the layout configuration of the pixel circuit 10 viewed from a direction perpendicular to the plane (XY plane) of the semiconductor substrate 1 constituting the semiconductor device 100. Note that in FIGS. 2A and 2B, the uppermost wiring layer among the wiring layers connecting circuit elements is omitted.

[0045] For example, a P-well 2 as a first semiconductor region of a first conductivity type (P-type) is formed in a semiconductor substrate 1, which is a P-type substrate in which silicon is doped with B (boron). The P-well 2 is formed by doping the P-type substrate 1 with a low concentration of P-type impurities.

[0046] An N well 3 as a second semiconductor region of a second conductivity type (N type) is formed on the P well 2. The P well 2 and the N well 3 form a PN junction type photodiode.

[0047] In this embodiment, a pinning layer 4 is further formed on the N well 3 as a P-type semiconductor layer (P+ region) having a higher P-type impurity concentration than the P well 2. The pinning layer 4 is formed, for example, by doping a P-type impurity into the surface of the P-type substrate 1. By forming the pinning layer 4, the photodiode becomes a buried type photodiode PPD. In this embodiment, the buried photodiode PPD is also simply referred to as a "photodiode PPD."

[0048] As shown in FIG. 2A, in a plan view seen from a direction perpendicular to the plane of the semiconductor substrate 1 (the positive side of the Z axis), an N well 6 and an N diffusion region 7 as a third semiconductor region of a second conductivity type (N type) are formed at a distance from the N well 3 so as to surround the photodiode PPD.

[0049] More specifically, the photodiode PPD is formed, for example, in a polygonal shape in a plan view. Here, the polygonal shape refers to a shape having three or more corners, and examples thereof include a triangular shape, a rectangular shape (quadrangle shape), a pentagonal shape, and a hexagonal shape. In the present embodiment, the photodiode PPD is described as being formed in a rectangular shape as an example, but is not limited thereto.

[0050] The N well 6 is formed in a shape that surrounds at least all but one side of the polygonal photodiode PPD in a plan view. For example, in the case where the photodiode PPD is rectangular as in the present embodiment, the N well 6 is formed in a shape that surrounds at least three of the four sides of the photodiode PPD.

[0051] An N-type diffusion region (N++ region) 7 having a higher N-type impurity concentration than the N-well 6 is formed on the N-well 6 so as to overlap the N-well 6 in a planar view. Here, the N-well 6 and the N-type diffusion region 7 extend so as to be in contact with a pixel boundary line A that defines the region of one pixel circuit 10, for example.

[0052] In the present embodiment, the case where the N well 6 and the N diffusion region 7 are formed as the third semiconductor region is illustrated, but this is not limited thereto, and it is sufficient that at least the N diffusion region 7 is formed as the third semiconductor region.

[0053] Furthermore, in plan view, a gate region 5 is formed on the P well 2 between the N well 3 as the second semiconductor region and the N well 6 and N-type diffusion region 7 as the third semiconductor region. The gate region 5 is, for example, a gate portion of a Metal-Oxide-Semiconductor (MOS) structure formed from a gate oxide film (e.g., SiO2) and an electrode (e.g., polysilicon, etc.) formed on the gate oxide film. Specifically, the gate region 5 is formed between the N well 3 and the N well 6 in a form surrounding at least three sides of the N well 3 of the photodiode PPD in plan view.

[0054] Here, an overflow transistor Mpdr is configured with the N well 3 as a source electrode, the N well 6 and the N-type diffusion region 7 as a drain electrode, and the gate region 5 as a gate electrode.

[0055] 2A, in a plan view, in an area on the one side (an edge other than the three sides) of the rectangular photodiode PPD, circuit elements constituting the pixel circuit 10 other than the overflow transistor Mpdr are formed. That is, in an area on the one side on the negative side of the Y axis of the photodiode PPD, a transfer transistor Mtg, a charge storage unit FD, a reset transistor Mfdr, an amplifier transistor Mdrv, and a selection transistor Msel are formed.

[0056] Furthermore, as shown in FIG. 2B, a PMD (Pre Metal Dielectric) 8, which is a transparent insulating film such as SiO 2 , is formed on the surface of the semiconductor substrate 1 by, for example, a CVD (Chemical Vapor Deposition) method.

[0057] As described above, the pixel circuit 10 in the semiconductor device 100 according to the first embodiment has a structure in which the overflow transistor Mpdr surrounds the periphery of the photodiode PPD, excluding the transfer transistor Mtg connected to the photodiode PPD and the contact portion (P++) for connecting the pinning layer 4 to a ground potential. As a result, no element isolation oxide layer (STI) is formed in the X-axis direction of the pixel boundary line A and in the positive Y-axis direction of the pixel boundary line A.

[0058] Next, an example of an arrangement in which a plurality of pixel circuits 10 shown in FIG. 2A and FIG. 2B are arranged on semiconductor substrate 1 will be described.

[0059] FIG. 3A is a plan view showing a layout configuration of a semiconductor device 100 in which a plurality of pixel circuits 10 according to the first embodiment are arranged.

[0060] FIG. 3B is a diagram that illustrates a cross-sectional structure of the semiconductor device 100 shown in FIG. 3A taken along the line CC'.

[0061] In Fig. 3A and Fig. 3B, similarly to Fig. 2A and Fig. 2B, the semiconductor substrate 1 is arranged in a three-dimensional space consisting of an X-axis, a Y-axis, and a Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Note that in Fig. 3A and Fig. 3B, the uppermost wiring layer among the wiring layers connecting the circuit elements is omitted. In the plane of the semiconductor substrate 1 shown in Fig. 3A, the Y-axis direction, which is a predetermined direction, is the column direction, and the X-axis direction is the row direction.

[0062] As shown in Fig. 3A, in the semiconductor device 100, a plurality of pixel circuits 10 are formed side by side in the row direction and the column direction on a semiconductor substrate. Specifically, for example, assuming that the top row on the positive side of the Y axis in Fig. 3A is the first row, in the pixel circuits 10 in odd-numbered rows, the transfer transistor Mtg, the reset transistor Mfdr, the amplification transistor Mdrv, and the selection transistor Msel are arranged on one side in the column direction (the positive side in the Y axis direction). In addition, in the pixel circuits 10 in even-numbered rows, the transfer transistor Mtg, the reset transistor Mfdr, the amplification transistor Mdrv, and the selection transistor Msel are arranged on the other side in the column direction (the negative side in the Y axis direction).

[0063] The overflow transistors Mpdr of the pixel circuits 10 adjacent in the row direction (X-axis direction) have a drain electrode (the N-well 6 and the N-type diffusion region 7 as the third semiconductor region) that is common to each other in the row direction.

[0064] 3A, it is preferable to adjust the range of the N-well 6 and the N-type diffusion region 7 in the row direction so that the distance between adjacent photodiodes PPD in the row direction (X-axis direction) is equal. This makes it possible to make the pixel resolution in the horizontal direction uniform.

[0065] 3B, in two pixel circuits 10 in which the overflow transistor Mpdr is adjacent to each other in the column direction (Y-axis direction), the overflow transistor Mpdr has a third semiconductor region (N-well 6 and N-type diffusion region 7) that is common to both in the column direction. For example, the pixel circuit 10 in the first row and the pixel circuit in the second row share a drain electrode of the overflow transistor Mpdr in the Y-axis direction, and the pixel circuit 10 in the third row and the pixel circuit in the fourth row share a drain electrode of the overflow transistor Mpdr in the Y-axis direction.

[0066] 3A, by arranging a plurality of pixel circuits 10, the N-well 6 and N-type diffusion region 7 serving as the drain electrode of the overflow transistor Mpdr of each pixel circuit 10 are shared in the regions surrounding three sides other than the side on which the transfer transistor Mtg, reset transistor Mfdr, amplifier transistor Mdrv, and selection transistor Msel are formed of the rectangular photodiode PPD of each pixel circuit 10. In other words, an element isolation oxide film layer such as STI is not formed in the regions on the three sides of the photodiode PPD.

[0067] As described above, according to the semiconductor device 100 of embodiment 1, the N-well 6 and the N-type diffusion region 7 serving as the drain electrode of the overflow transistor Mpdr are formed so as to surround the photodiode PPD, so that the element isolation oxide film layer formed in the area surrounding the photodiode PPD can be significantly reduced compared to conventional solid-state imaging elements.

[0068] Specifically, as shown in FIG. 3A, when multiple pixel circuits 10 are arranged in the row and column directions on a semiconductor substrate 1, the overflow transistors Mpdr of adjacent pixel circuits 10 in the row direction (X-axis direction) have a drain electrode (N-well 6 and N-type diffusion region 7) that is common to each other in the row direction. This eliminates the need to form an element isolation oxide layer between adjacent pixel circuits 10 in the row direction, making it possible to reduce the element isolation oxide layer formed in the region around the photodiode PPD. It also makes it possible to reduce the chip area of ​​the semiconductor substrate 1 required for forming the solid-state imaging element, thereby enabling the cost of the semiconductor device 100 to be reduced.

[0069] As described above, in two pixel circuits 10 adjacent to each other in the column direction (Y-axis direction), the overflow transistor Mpdr has the N well 6 and the N-type diffusion region 7 that are common to each other in the column direction. This makes it possible to reduce the number of element isolation oxide film layers formed between the pixel circuits 10 in the column direction. It also makes it possible to reduce the chip area of ​​the semiconductor substrate 1 required for forming the solid-state imaging element, thereby enabling further cost reduction of the semiconductor device 100.

[0070] As described above, according to the semiconductor device 1 of the present embodiment, the element isolation oxide film layer formed in the region surrounding the photodiode PPD can be significantly reduced, and the dark current flowing through the photodiode can be significantly reduced. This makes it possible to more effectively suppress whiteout caused by the total dose effect of radiation compared to conventional solid-state imaging devices, thereby improving radiation resistance.

[0071] Second Embodiment FIG. 4 is a plan view showing a layout configuration of a semiconductor device 100A according to the second embodiment.

[0072] In Fig. 4, similarly to the first embodiment, the semiconductor substrate 1 is arranged in a three-dimensional space consisting of an X-axis, a Y-axis, and a Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Note that the top wiring layer among the wiring layers connecting the circuit elements is omitted in Fig. 4. In Fig. 4, the Y-axis direction is the column direction, and the X-axis direction is the row direction.

[0073] As shown in FIG. 4, the semiconductor device 100A of embodiment 2 differs from the semiconductor device 100 of embodiment 1 in that each pixel circuit 10 is arranged on the semiconductor substrate 1 so as to face in the same direction, but is otherwise similar to the semiconductor device 100 of embodiment 1.

[0074] Specifically, in the semiconductor device 100A, the transfer transistor Mtg, reset transistor Mfdr, amplification transistor Mdrv, and selection transistor Msel of each pixel circuit 10 are arranged on one side in the column direction (the positive side in the Y-axis direction).

[0075] The overflow transistors Mpdr of the pixel circuits 10 adjacent in the row direction (X-axis direction) have a drain electrode (the N-well 6 and the N-type diffusion region 7 as the third semiconductor region) that is common to each other in the row direction.

[0076] In addition, the pixel circuits 10 adjacent in the row direction (X-axis direction) and column direction (Y-axis direction) are arranged so that the distance between the photodiodes PPD of each pixel circuit 10 is equal. For example, as shown in Fig. 4, the distance L12 from the center P1 of the pixel circuit 10_1 to the center P2 of the pixel circuit 10_2 adjacent to the pixel circuit 10_1 in the row direction (X-axis direction) is equal to the distance L13 from the center P1 of the pixel circuit 10_1 to the center P3 of the pixel circuit 10_3 adjacent to the pixel circuit 10_1 in the column direction (Y-axis direction) (L12 = L13).

[0077] As described above, according to the semiconductor device 100A of embodiment 2, the pixel circuits 10 can be evenly arranged not only in the row direction (X-axis direction) but also in the column direction (Y-axis direction), so that the horizontal resolution and vertical resolution of the captured image can be made uniform.

[0078] Also, similarly to the semiconductor device 100 according to the first embodiment, the overflow transistors Mpdr of the pixel circuits 10 adjacent in the row direction (X-axis direction) have a common drain electrode (N-well 6 and N-type diffusion region 7) in the row direction, so that the element isolation oxide film layer can be reduced by two of the four sides of the rectangular photodiode PPD. This makes it possible to reduce the cost of the semiconductor device 100A while suppressing whiteout due to the total dose effect of radiation.

[0079] Third Embodiment FIG. 5 is a plan view showing a layout configuration of a pixel circuit 10B of a semiconductor device 100B according to the third embodiment.

[0080] FIG. 6 is a plan view showing a layout configuration of a semiconductor device 100B according to the third embodiment.

[0081] 5 and 6, similarly to the first embodiment, the semiconductor substrate 1 is arranged in a three-dimensional space consisting of an X-axis, a Y-axis, and a Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Note that the uppermost wiring layer among the wiring layers connecting the circuit elements is omitted in Fig. 5 and 6. In Fig. 6, the Y-axis direction is the column direction, and the X-axis direction is the row direction.

[0082] As shown in FIG. 5, the semiconductor device 100B of the third embodiment differs from the semiconductor device 100 of the first embodiment in that, in the plane of the semiconductor substrate 1, the N-well 6 and the N-type diffusion region 7 of each pixel circuit 10B are extended in the X-axis direction and the Y-axis direction, but is otherwise similar to the semiconductor device 100 of the first embodiment.

[0083] Specifically, as shown in Figures 5 and 6, among the pixel boundaries that define each pixel circuit 10B in the plane of the semiconductor substrate 1, the third semiconductor region (N well 6 and N-type diffusion region 7) of each pixel circuit 10 is formed adjacent to the second pixel boundary line A' so that the distance Lp1 from the first pixel boundary line A in the row direction on the side on which the transfer transistor Mtg, the reset transistor Mfdr, the amplification transistor Mdrv, and the selection transistor Msel are formed to the end of the photodiode PPD is equal to the distance Lp2 from the second pixel boundary line A' in the row direction on the opposite side of the photodiode PPD to the first pixel boundary line A. According to this, the pixel circuits 10B can be arranged evenly in the column direction (Y-axis direction), so that the vertical resolution of the captured image can be made uniform.

[0084] As shown in FIG. 6, the N well 6 and the N type diffusion region 7 of each pixel circuit 10B are extended in the row direction (X-axis direction) so that the distance between the photodiodes PPD of each pixel circuit 10B is equal in the row direction as well. This allows the pixel circuits 10B to be evenly arranged in the row direction (X-axis direction), making the horizontal resolution of the captured image uniform. Furthermore, by making the distances between the photodiodes PPD in the column direction and the row direction equal, the resolution in the horizontal and vertical directions can be made uniform.

[0085] As described above, according to the semiconductor device 100B of embodiment 3, it is possible to improve radiation resistance in the same way as the semiconductor device 100 of embodiment 1, and also to make the image resolution uniform.

[0086] Fourth Embodiment FIG. 7 is a plan view showing a layout configuration of a pixel circuit 10C of a semiconductor device 100C according to the fourth embodiment.

[0087] 7, similarly to the first embodiment, the semiconductor substrate 1 is placed in a three-dimensional space consisting of an X-axis, a Y-axis, and a Z-axis, and the plane of the semiconductor substrate 1 is parallel to the XY plane. Note that in FIG. 7, the topmost wiring layer among the wiring layers connecting the circuit elements is omitted.

[0088] The semiconductor device 100C of embodiment 4 differs from the semiconductor device 100 of embodiment 1 in that, in the plane of the semiconductor substrate 1, the N-well 6 and the N-type diffusion region 7 as the third semiconductor region of each pixel circuit 10 are formed only on one of the four sides of the rectangular photodiode PPD, but is otherwise similar to the semiconductor device 100 of embodiment 1.

[0089] In the pixel circuit 10C according to the fourth embodiment, the gate region 5C serving as the gate electrode of the overflow transistor Mpdr is formed so as to surround at least all but one side of the polygonal photodiode. For example, as shown in Fig. 7, the gate region 5C is formed so as to surround at least three of the four sides of the photodiode PPD which is rectangular in plan view.

[0090] In addition, in a plan view, a third semiconductor region (N well 6C and N-type diffusion region 7C) which becomes the drain electrode of the overflow transistor Mpdr is formed along one of the other sides (three sides) of the photodiode PPD surrounded by the gate region 5C, separated from the N well 3 with the gate region 5C in between. For example, the N well 6C and the N-type diffusion region 7C are formed along one side of the photodiode PPD on the positive side in the Y-axis direction, separated from the N well 3 with the gate region 5C in between.

[0091] Fig. 8 is a plan view showing a layout configuration of a semiconductor device 100C according to embodiment 4. In Fig. 8, the Y-axis direction is the column direction, and the X-axis direction is the row direction.

[0092] 8, the pixel circuits 10C are formed, in a plan view, side by side in the column direction (Y direction) and row direction (X direction) of the semiconductor substrate 1. The pixel circuits 10C adjacent to each other in the row direction have a gate region 5C common to each other in the row direction.

[0093] 8, the top row in the positive Y-axis direction is the first row, in the pixel circuits 10 in odd-numbered rows, the transfer transistor Mtg, reset transistor Mfdr, amplifier transistor Mdrv, and selection transistor Msel are arranged on one side in the column direction (positive side in the Y-axis direction). In the pixel circuits 10 in even-numbered rows, the transfer transistor Mtg, reset transistor Mfdr, amplifier transistor Mdrv, and selection transistor Msel are arranged on the other side in the column direction (negative side in the Y-axis direction).

[0094] As shown in FIG. 8, pixel circuits 10C in which the drain electrodes of the overflow transistors Mpdr are adjacent to each other in the column direction (Y-axis direction) have a third semiconductor region (N well 6 and N-type diffusion region 7) common to each other in the row and column directions.

[0095] As described above, according to the semiconductor device 100C of the fourth embodiment, the pixel circuits 10C adjacent to each other in the row direction have the gate region 5C common to each other in the row direction, so that the element isolation oxide film layer can be reduced by two of the four sides of the photodiode. This makes it possible to suppress whiteout due to the total dose effect of radiation, compared to conventional solid-state imaging devices.

[0096] In addition, since the N-well 6 and N-type diffusion region 7 constituting the drain electrode of the overflow transistor Mpdr are not formed in the row direction, the area of ​​the photodiode PPD can be increased. This allows the aperture of each pixel to be enlarged, which is expected to increase the charge storage capacity of the photodiode and improve its light sensitivity.

[0097] In the semiconductor device 100C according to the fourth embodiment, in order to uniformize the pixel resolution in the vertical direction (Y direction) and the horizontal direction (X direction), each pixel circuit 10 may be expanded as in the semiconductor device 100B according to the third embodiment. For example, the photodiode PPD may be expanded in the horizontal direction, or the gate region 5C serving as the gate electrode of the overflow transistor Mpdr may be expanded in the horizontal direction. Also, as in the semiconductor device 100A according to the second embodiment, the orientation of each pixel circuit 10C may be unified to uniformize the distance between the photodiodes PPD of each pixel circuit 10.

[0098] <<Extension of the embodiment>> The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the invention is not limited thereto and can be modified in various ways without departing from the spirit of the invention.

[0099] For example, each transistor may be formed with the first conductivity type being N-type and the second conductivity type being P-type. [Explanation of symbols]

[0100] 1...semiconductor substrate, 2...first semiconductor region (P well), 3...second semiconductor region (N well), 4...pinning layer, 5,5C...gate region, 6,6C...third semiconductor region (N well), 7,7C...third semiconductor region (N-type diffusion region), 10,10_1 to 10_3,10B,10C...pixel circuit, 100,100A,100B,100C...semiconductor device, A...first pixel boundary line, A'...second pixel boundary line, FD...charge storage section, GND...ground potential, L12...distance, L13...distance, Lp... Distance, Lp1...distance, Lp2...distance, Mdrv...amplification transistor, Mfdr...reset transistor, Mpdr...overflow transistor, Msel...selection transistor, Mtg...transfer transistor, N1...node, OUT...output signal line, P1~P3...photodiode center of PPD, PPD...embedded photodiode (photodiode), VDD...power supply voltage, VRR...power supply voltage, φFDR...signal, φPDR...signal, φSEL...signal, φTG...signal.

Claims

1. A semiconductor substrate, a pixel circuit formed on the semiconductor substrate; The pixel circuit includes: a first semiconductor region of a first conductivity type formed in the semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region; a third semiconductor region of a second conductivity type formed in the semiconductor substrate and spaced apart from the second semiconductor region so as to surround the photodiode in a plan view; a gate region that is formed between the second semiconductor region and the third semiconductor region when viewed in a direction perpendicular to a plane of the semiconductor substrate, and that constitutes an overflow transistor that discharges charges accumulated in the photodiode together with the second semiconductor region and the third semiconductor region; The photodiode is formed in a polygonal shape in a plan view, the third semiconductor region is formed in a shape surrounding at least one side of the polygonal photodiode in a plan view, the gate region is formed between the second semiconductor region and the third semiconductor region so as to surround at least the other side of the photodiode in a plan view; the pixel circuit further includes a transfer transistor that transfers charge of the photodiode, a charge storage unit that stores the charge transferred by the transfer transistor, a reset transistor that resets a voltage of the charge storage unit, an amplification transistor that amplifies a signal corresponding to the charge stored in the charge storage unit, and a selection transistor that switches whether or not to output the signal amplified by the amplification transistor to a signal line, the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor are formed in a region on the one side of the photodiode in a plan view, A pixel circuit includes a plurality of the pixel circuits, the pixel circuits are formed, in a plan view, side by side in a column direction that is a predetermined direction in a plane of the semiconductor substrate and in a row direction that is a direction perpendicular to the column direction, the pixel circuits adjacent to each other in the row direction have the third semiconductor region common to each other in the row direction, the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor of the pixel circuits in odd-numbered rows are disposed on one side in the column direction, the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor of the pixel circuit in an even-numbered row are disposed on the other side in the column direction, The two pixel circuits in which the overflow transistors are adjacent to each other in the column direction have the third semiconductor region common to each other in the column direction. A semiconductor device comprising:

2. A semiconductor substrate; a pixel circuit formed on the semiconductor substrate; The pixel circuit includes: a first semiconductor region of a first conductivity type formed in the semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a photodiode together with the first semiconductor region; a third semiconductor region of a second conductivity type formed in the semiconductor substrate and spaced apart from the second semiconductor region so as to surround the photodiode in a plan view; a gate region that is formed between the second semiconductor region and the third semiconductor region when viewed in a direction perpendicular to a plane of the semiconductor substrate, and that constitutes an overflow transistor that discharges charges accumulated in the photodiode together with the second semiconductor region and the third semiconductor region; The photodiode is formed in a polygonal shape in a plan view, the third semiconductor region is formed in a shape surrounding at least one side of the polygonal photodiode in a plan view, the gate region is formed between the second semiconductor region and the third semiconductor region so as to surround at least the other side of the photodiode in a plan view; the pixel circuit further includes a transfer transistor that transfers charge of the photodiode, a charge storage unit that stores the charge transferred by the transfer transistor, a reset transistor that resets a voltage of the charge storage unit, an amplification transistor that amplifies a signal corresponding to the charge stored in the charge storage unit, and a selection transistor that switches whether or not to output the signal amplified by the amplification transistor to a signal line, the transfer transistor, the reset transistor, the amplification transistor, and the selection transistor are formed in a region on the one side of the photodiode in a plan view, A pixel circuit includes a plurality of the pixel circuits, the pixel circuits are formed, in a plan view, side by side in a column direction that is a predetermined direction in a plane of the semiconductor substrate and in a row direction that is a direction perpendicular to the column direction, the pixel circuits adjacent to each other in the row direction have the third semiconductor region common to each other in the row direction, The third semiconductor region of each of the pixel circuits is formed in contact with the second pixel boundary line such that, among pixel boundary lines defining each of the pixel circuits in the plane of the semiconductor substrate, a distance from a first pixel boundary line in the row direction on a side on which the transfer transistor, the reset transistor, the amplifying transistor, and the selection transistor are formed to an end of the photodiode is equal to a distance from a second pixel boundary line in the row direction on an opposite side to the first pixel boundary line across the photodiode to an end of the photodiode. A semiconductor device comprising:

3. A semiconductor substrate; a pixel circuit formed on the semiconductor substrate; The pixel circuit includes: a first semiconductor region of a first conductivity type formed in the semiconductor substrate; a second semiconductor region of a second conductivity type formed on the first semiconductor region and constituting a polygonal photodiode together with the first semiconductor region; a gate region formed so as to surround at least one side of the polygonal photodiode in a plan view; a third semiconductor region of a second conductivity type that is formed along one of the other sides of the photodiode surrounded by the gate region and spaced apart from the second semiconductor region with the gate region in between in a plan view, and that constitutes an overflow transistor that discharges charges accumulated in the photodiode together with the second semiconductor region and the gate region; A pixel circuit includes a plurality of the pixel circuits, the pixel circuits are formed, in a plan view, side by side in a column direction that is a predetermined direction in a plane of the semiconductor substrate and in a row direction that is a direction perpendicular to the column direction, The pixel circuits adjacent to each other in the row direction have the gate region common to each other in the row direction. A semiconductor device comprising:

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