Clock signal generating circuit, driving method and electronic device

Abstract

The present invention provides a clock signal generation circuit, a driving method, and an electronic device, which belong to the technical field of digital circuits, in which the phase of the generated clock signal can be dynamically adjusted and switched, and glitches do not occur when the phase is dynamically adjusted and switched. The clock signal generation circuit includes: a counter for generating a phase setting value from a count value in response to a clock phase adjustment request; a decoding and synchronization module for loading an initial phase value, receiving the phase setting value from the counter during the phase adjustment process, decoding the initial phase value or the phase setting value into an enable control signal, and synchronizing and outputting the enable control signal; and a clock selector for receiving the synchronized enable control signal, selecting, synthesizing, and outputting an input clock signal corresponding to the phase of the initial phase value or the phase setting value from multi-channel input clock signals in accordance with the enable control signal.

Description

[Technical field]

[0001] The present invention relates to the technical field of digital circuits, and in particular to a clock signal generating circuit, a driving method and an electronic device. [Background technology]

[0002] Clock signals are essential signals in digital circuit systems, and different designs have different requirements for the clock frequency, duty ratio and phase of the clock signal. As digital circuits become more integrated and complex, the clock signal generation of synchronous circuit systems is also becoming more and more complex. For VLSI (Very Large Scale Integration) systems such as FPGA (Field Programmable Gate Array), multiple clock signals with different phases are required, and at the same time, some system applications require that the data signal and the clock signal maintain a certain phase relationship, so it is generally necessary to dynamically adjust the phase of the clock signal to ensure the accuracy of the circuit sequence and function.

[0003] A commonly used clock signal phase selection method is to select the input clock CLKIN <n:0>The clocks have a specific phase relationship between them, i.e., the phases between the clocks are continuous and can cover one clock period. In this method, a MUX (multiplexer) selects the target phase clock as the output. In this method, the selection signal SELx <m:0>Since is an asynchronous signal, when clocks of different phases are switched by changing the selection signal, a glitch may occur in the output clock, which may cause the subsequent functioning of the logic circuit to be abnormal. Summary of the Invention

[0004] The embodiments of the present invention provide a clock signal generating circuit, a driving method and an electronic device, in which the phase of the clock signal generated by the present invention can be dynamically adjusted and switched, and no glitch phenomenon occurs when the phase is dynamically adjusted and switched.

[0005] According to a first aspect, an embodiment of the present invention provides a clock signal generation circuit, comprising: a counter for generating a phase setting value from a count value in response to a clock phase adjustment request; a decoding and synchronizing module, which loads a phase initial value during an initial phase realization process, receives the phase setting value from a counter during a phase adjustment process, decodes the phase initial value or the phase setting value into an enable control signal, synchronizes and outputs the enable control signal, and synchronizes the enable control signal with a clock domain that needs to be adjusted through the synchronization process; a clock selector that receives a synchronized enable control signal, and selects as an output an input clock signal that corresponds to the phase of the phase initial value or the phase setting value from among the multi-channel input clock signals in response to the enable control signal, so that the phases of the multi-channel input clock signals are continuous and can cover one clock period.

[0006] Selectably, the clock selector comprises one or more Clock Selection Unit the decoding and synchronization module outputs one or more enable control signals, the enable control signals being Clock Selection Unit corresponds to one-to-one, Clock Selection Unit is used to receive a corresponding synchronized enable control signal from the decoding and synchronization module, and select an input clock signal corresponding to the phase of the phase initial value or the phase setting value as an output from the multi-channel input clock signals according to the corresponding synchronized enable control signal.

[0007] Optionally, the decoding and synchronization module Phase Initial Value or a decoder that decodes the phase setting value into a plurality of enable control signals, only one of which is at a high level and the rest are at a low level, and a synchronization circuit that synchronizes and outputs the enable control signal, and the synchronized enable control signal is triggered by the falling edge of the input clock.

[0008] Optionally, the decoder is a 3-8 decoding circuit, and the synchronization circuit includes a first flip-flop, a second flip-flop, and eight output flip-flops; A first input clock signal among the input clock signals is input to a trigger end of the first flip-flop, an input end of the first flip-flop is connected to an output end of the 3-8 decoding circuit, and first to fourth signals from a low level to a high level among the first flip-flop output signals are output to input ends of first to fourth output flip-flops among the eight output flip-flops, and the first flip-flop is used to be triggered by a rising edge of the first input clock signal to sample an output signal of the 3-8 decoding circuit; The first input clock signal is input to a trigger end of the second flip-flop, an input end of the first flip-flop receives fourth to eighth signals from a low level to a high level among the output signals of the first flip-flop, and an output end of the second flip-flop is connected to input ends of fifth to eighth output flip-flops among the eight output flip-flops, and the second flip-flop is used to sample the fourth to eighth output signals from a low level to a high level among the output signals of the first flip-flop, and outputs the samples at a falling edge of the first input clock signal; Each of the eight output flip-flops receives one of the input clock signals at its trigger end, and each of the eight output flip-flops outputs after being sampled at the falling clock edge of the corresponding input clock signal.

[0009] Optionally, Clock Selection Unit includes a first AND gate receiving an enable control signal corresponding to a switched clock signal from an input end, a second AND gate receiving an enable control signal corresponding to a target switching clock signal from an input end, and an OR gate having two input ends respectively connected to the output end of the first AND gate and the output end of the second AND gate, and an output end being the output end of the clock selector, wherein the clock selection unit corresponds one-to-one to the output channels, the switched clock signal refers to an input clock having a phase similar to that of an output clock corresponding to an output channel before phase adjustment, and the target switching clock signal refers to an input clock having a phase similar to that of an output clock corresponding to an output channel after phase adjustment.

[0010] According to a second aspect, an embodiment of the present invention provides a method for driving the clock signal generation circuit, in which the counter receives a dynamic phase adjustment trigger signal STEP_N, a dynamic phase adjustment direction DIRECTION, a dynamic phase adjustment channel selection signal SEL <m:0>, a load signal LOAD of the dynamic phase adjustment selected channel phase selection signal, and a current phase selection signal PHASENOW of the dynamic phase adjustment selected channel <m:0>The decoding and synchronization module receives a new phase selection signal PHASENEW after dynamic phase adjustment from the output end of the counter. <m:0>The decoding and synchronization module receives an input clock signal CLKIN <n:0>, dynamic phase adjustment trigger signal STEP_N, dynamic phase adjustment channel selection signal SEL <m:0>and each channel clock phase initial setting value PHASEINIT0 / 1 / ··· / x <m:0>The clock selector further receives an enable control signal CLKEN0 / 1 / ··· / x of each channel clock selector from the output end of the decoding and synchronization module. <n:0>and the clock selector receives the input clock signal CLKIN <n:0>Further receiving The driving method includes setting each channel clock phase initial value PHASEINIT0 / 1 / ··· / x by the decoding and synchronization module. <m:0>, and then decode the phase initial value into a corresponding enable control signal. Then, each enable control signal is synchronized, and each synchronized enable control signal CLKEN0 / 1 / ··· / x is generated. <n:0>The corresponding Clock Selection Unit and Clock Selection Unit The input clock signal CLKIN is generated according to the phase initial value. <n:0>the input clock signal of the corresponding phase from the input clock signal as an output.

[0011] The driving method further includes a dynamic phase adjustment step, A new phase selection signal PHASENEW after dynamic phase adjustment of the counter output <m:0>Receive the selected channel enable signal (EN0 / 1 / 2··· / x <n:0>), among which only one channel of the enable signals of n+1 channels is at a high level and the remaining n channels are at a low level, and then the enable signal (EN0 / 1 / 2... / x <n:0>) are synchronized, and after the synchronization process, the enable control signal CLKEN0 / 1...x <n:0>The synchronization process outputs the input clock CLKIN <n:0>Triggered by the falling edge of the enable control signal CLKEN0 / 1...x <n:0>are sent to the corresponding clock selection units as synchronous input controls.

[0012] When the output channel is not changed during phase adjustment, the dynamic phase adjustment step is performed by a counter that obtains the direction of dynamic phase adjustment from the dynamic phase adjustment direction DIRECTION. At this time, the dynamic phase adjustment channel selection signal SEL <m:0>does not change, the load signal LOAD that triggers the dynamic phase adjustment selected channel phase selection signal remains at low level, and then the current channel phase selection value PHASENOW <m:0>After loading the counter with PHASE_N, the STEP_N signal is triggered and depending on the dynamic phase adjustment direction, the counter counts up or down on the STEP_N rising edge and outputs a new phase selection value PHASENEW from the counter. <m:0>and transmits the enable control signal to the decoding and synchronization module, which decodes the enable control signal and synchronizes it to the clock domain of the input clock, and outputs a new enable control signal. Clock Selection Unit and Clock Selection Unit further includes switching to a new phase clock in response to the enable control signal.

[0013] If the output channel is not changed during phase adjustment, dynamic The phase adjustment step includes: when the counter selects a dynamic phase adjustment direction according to the dynamic phase adjustment direction DIRECTION, a dynamic phase adjustment channel selection signal SEL <m:0>and a current phase selection signal PHASENOW of the dynamic phase adjustment selection channel of the counter is selected. <m:0>After sending to the counter, the LOAD signal is triggered and held at a high level for a certain period of time, and the current channel phase selection value PHASENOW <m:0>After loading the counter with the STEP_N signal, the counter will count up or down on the rising edge of STEP_N depending on the adjustment direction, and the counter will load the new phase selection value PHASENEW <m:0>to the decoding and synchronization module, where it is decoded and synchronized to the clock domain of the input clock CLKIN, and outputs a new enable control signal, and the enable control signal is converted to the corresponding Clock Selection Unit and Clock Selection Unit further includes the step of switching to a new phase clock.

[0014] According to a third aspect, an embodiment of the present invention further provides an electronic device including a clock signal generation circuit according to any one of the above claims.

[0015] According to a fourth aspect, an embodiment of the present invention further provides a computer readable storage medium having stored thereon computer instructions which, when executed by a processor, perform the driving method according to any one of the above claims. Effect of the Invention

[0016] In the clock signal generating circuit, driving method and electronic device provided by the embodiments of the present invention, a counter generates a phase setting value according to a clock phase adjustment request, and sends it to a clock selector through a decoding and synchronization module, and the clock selector selects an input clock signal corresponding to the phase of the phase setting value from the multi-channel input clock signals according to the phase setting value as an output, among which the phases of the multi-channel input clock signals are continuous and can cover one clock period. The control signal of the input clock selector is controlled by the signal output from the decoding and synchronization module, so that no glitch occurs when dynamically adjusting and switching the phase. [Brief description of the drawings]

[0017] [Figure 1] FIG. 1 is a schematic diagram of a commonly used clock signal phase selection method. [Diagram 2] 2 is a schematic diagram of a clock signal generating circuit provided by an embodiment of the present invention; [Diagram 3] FIG. 2 is a schematic diagram of an exemplary 3-8 decoding circuit constituting a decoding and synchronization module provided by an embodiment of the present invention. [Figure 4] 2 is a schematic diagram of an exemplary synchronization circuit constituting a decoding and synchronization module provided by an embodiment of the present invention; FIG. [Diagram 5] 3 is a simplified logic schematic diagram of an exemplary clock selector applied in the clock signal generation circuit shown in FIG. 2 provided by an embodiment of the present invention. [Figure 6] 4 is a schematic diagram of a clock initial phase sequence applied to the clock signal generating circuit of the present embodiment. FIG. [Figure 7] 4 is a schematic diagram of a clock phase adjustment sequence applied to the clock signal generating circuit of the present embodiment. [Figure 8] 4 is a schematic diagram of a clock phase adjustment internal signal sequence applied to the clock signal generating circuit of the present embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] In order to make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be described clearly and completely below with reference to the drawings of the embodiments of the present invention, but it goes without saying that the described embodiments are only some of the embodiments of the present invention, and do not include all the embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative labor are all included in the protection scope of the present invention.

[0019] Currently, in the clock signal phase selection method shown in Figure 1, the selection signal SELx <m:0>Since is an asynchronous signal, when switching different phase clocks by changing the selection signal, glitches may occur in the output clock, and the logic circuit may function abnormally after that, so the method shown in Fig. 1 usually realizes a static selection clock. In the process of realizing the present invention, the inventor found that there are currently technical problems that (1) the phase of the clock cannot be dynamically adjusted, and (2) even if the phase of the clock is dynamically adjusted and switched, a glitch may occur in the clock when switching.

[0020] In order to solve the above main problems, the present inventor puts forward a new design proposal for a circuit that dynamically adjusts the clock phase, and the clock signal generation circuit only requires one counter and a clock selector circuit, which can be combined with other logic circuits to adjust the clock signal phase, realizing dynamic forward and reverse cycle adjustment (which can accumulate delays or advances of one or more clock cycles), and no glitches occur in the output clock. The solution of this application will be described below with reference to the drawings.

[0021] As shown in FIG. 2, the clock signal generating circuit provided by the embodiment of the present invention includes a counter (COUNT) 11, a decoding and synchronization module (DECODE&SYNC) 12 and a clock selector (PHASESEL0 / 1.. / x) 13.

[0022] The counter 11 is used to generate a phase setting value from the count value in response to a clock phase adjustment request.

[0023] The decoding and synchronization module 12 is used to load a phase initial value during an initial phase realization process, receive the phase setting value from the counter 11 during a phase adjustment process, decode the phase initial value or the phase setting value into an enable control signal, and output the enable control signal after synchronization processing, where the synchronization processing is to synchronize the enable control signal with the clock domain that needs to be adjusted.

[0024] The clock selector 13 receives a synchronized enable control signal, and selects as an output an input clock signal from the multi-channel input clock signal that corresponds to the phase of the phase initial value or the phase setting value according to the enable control signal, so that the phases of the multi-channel input clock signal are continuous and can cover one clock period.

[0025] In this embodiment, the counter 11 is used to count up or down by one cycle or count in other steps. According to the clock phase adjustment request, the interface signal is adjusted and the counter value is converted into the counter count value in a certain sequence, so that the phase adjustment information can be converted into a digital phase setting value. For example, the larger the phase after adjustment, the longer the counting time is, and the larger the output number representing the phase setting value is.

[0026] As shown in FIGS. 2 and 6, in some embodiments, the counter 11 receives a dynamic phase adjustment trigger signal STEP_N, a dynamic phase adjustment direction DIRECTION, a dynamic phase adjustment channel selection signal SEL <m:0>, a load signal LOAD of the dynamic phase adjustment selected channel phase selection signal, and a current phase selection signal PHASENOW of the dynamic phase adjustment selected channel <m:0>and receiving a new phase selection signal PHASENEW after dynamic phase adjustment from the decoding and synchronization module. <m:0>The implementation process of the counter is as follows: the counter 11 counts up or down with DIRECTION (containing dynamic phase adjustment direction information), then triggers the LOAD signal (holds it at a high level for a certain period of time), and outputs the selected channel phase selection value PHASENOW <m:0>The counter is loaded with PHASENOW on the rising edge of the clock signal STEP_N. <m:0>Count up or down based on the phase to select the new phase. <m:0>Output.

[0027] The decoding and synchronization module 12 of this embodiment is Phase Initial Value The phase initial value is stored in the memory, and the output of the counter 11 is received to determine which channel's output clock needs phase adjustment, and then the phase setting value is updated, and the enable control signal is generated based on the phase initial value or the phase setting value.

[0028] As shown in FIGS. 2 and 6, in an alternative embodiment, the decoding and synchronization module 12 performs the following steps during the initial phase: Phase Initial Value PHASEINIT0 / 1...x <m:0>Load the control signals EN0 / 1...x corresponding to each channel. <n:0>After decoding, these control signals EN0 / 1...x <n:0>to the clock domain that needs to be adjusted, and the synchronized enable control signals CLKEN0 / 1...x <n:0>In the process of dynamically adjusting the phase, the PHASENEW output from the counter 11 is used to input a control signal from the clock selector module (later module) in the initial phase process. <m:0>After receiving, select channel EN0 / 1...x <n:0>Decode into enable control signal, then control signal EN0 / 1...x <n:0>to the clock domain that needs to be adjusted, and the synchronized enable control signals CLKEN0 / 1...x <n:0>and inputs a control signal from the clock selector module during the process of dynamically adjusting the phase to achieve synchronization.

[0029] In an alternative embodiment, the clock selector 13 selects one or more Clock Selection Unit (PHASESEL0 / 1.. / x), and the decoding and synchronization module 12 outputs one or more enable control signals, and the enable control signals are Clock Selection Unit corresponds to one-to-one, Clock Selection Unit receives a corresponding synchronized enable control signal from the decoding and synchronization module 12, and generates the multi-channel input clock signal CLKIN in response to the corresponding synchronized enable control signal. <n:0>from which an input clock signal corresponding to the phase of the initial phase value or the phase setting value is selected as an output.

[0030] In an alternative embodiment, the decoding and synchronization module 12 comprises: Phase Initial Value Alternatively, the phase setting value is combined into a plurality of enable control signals, and a decoder in which only one channel of the plurality of enable control signals is at a high level and the rest are at a low level is used to synchronize and output the enable control signals, and the synchronized enable control signals are outputted based on an input clock CLKIN. <n:0>and a synchronization circuit triggered by the falling edge of

[0031] As shown in FIG. 3, the decoder may be a 3-8 decoding circuit.

[0032] As shown in FIG. 4, the synchronous circuit includes a first flip-flop, a second flip-flop and eight output flip-flops, and the input clock signal CLKIN is input to the trigger edge of the first flip-flop. <n:0>The first input clock signal CLCK <0> is input, the input terminal of the first flip-flop is connected to the output terminal of the 3-8 decoding circuit, the first to fourth bits <3:0> of the first flip-flop output signal from a low level to a high level are output to the input terminals of the first to fourth output flip-flops among the eight output flip-flops, and the first flip-flop is connected to the first input clock signal CLCK <0> The first input clock signal CLCK is used to sample the output signal of the 3-8 decoding circuit by being triggered by a rising edge, and the trigger edge of the second flip-flop is connected to the first input clock signal CLCK <0> is input to the first flip-flop, an input terminal of the first flip-flop receives the fourth to eighth signals <7:4> from a low level to a high level among the output signals of the first flip-flop, an output terminal of the second flip-flop is connected to input terminals of the fifth to eighth output flip-flops among the eight output flip-flops, the second flip-flop is used to sample the fourth to eighth output signals <7:4> from a low level to a high level of the first flip-flop output signals, and the first input clock signal CLCK <0> The eight output flip-flops are sampled at the falling edge of the input clock signal CLKIN <n:0>The eight output flip-flops each receive the corresponding input clock signal CLKIN <n:0>The signal is sampled and output on the falling edge of the clock.

[0033] The clock selector of this embodiment is a clock selector that receives enable control signals CLKEN0 / 1...x output from the decoding and synchronization module. <n:0>Receives the input enable control signal CLKEN0 / 1...x <n:0>(clock synchronized), and the clock selector module switches to a new phase clock and outputs it according to the appropriate logic design. The new phase is the enable control signal CLKEN0 / 1...x <n:0>or the phase setting value included in the

[0034] The clock selector includes one or more clock selection units, each of which corresponds to an output channel (or output clock) in a one-to-one correspondence with the output channel (or output clock). The clock selection unit obtains a phase setting value of the corresponding output channel from the decoding and synchronization module, and then selects an input clock signal corresponding to the phase of the phase setting value from the multi-channel input clock signals as an output.

[0035] As shown in FIG. 5, in an alternative embodiment, Clock Selection Unit includes a first AND gate whose input end receives a switched clock signal and a corresponding enable control signal, a second AND gate whose input end receives a target switched clock signal and a corresponding enable control signal, and an OR gate whose two input ends are connected to the output end of the first AND gate and the output end of the second AND gate and whose output end is the output end of the clock selector, where the switched clock signal refers to the input clock having a phase similar to that of the output clock of this channel before phase adjustment, and the target switched clock signal refers to the input clock having a phase similar to that of the output clock of this channel after phase adjustment.

[0036] The embodiment of the present invention further provides a driving method for the above clock signal generating circuit, in which, during the process of realizing the initial phase adjustment, the driving method includes: <m:0>, and then decodes the phase initial value into a corresponding enable control signal, and synchronizes each enable control signal, and outputs the synchronized enable control signal CLKEN0 / 1 / ··· / x <n:0>The corresponding Clock Selection Unit and Clock Selection Unit The input clock signal CLKIN is generated according to the phase initial value. <n:0>the input clock signal of the corresponding phase from the input clock signal as an output.

[0037] The driving method further includes a dynamic phase adjustment step, and the dynamic phase adjustment step is a step of adjusting a new phase selection signal PHASENEW output from the counter 11 after the dynamic phase adjustment. <m:0>Receive the selected channel enable signal (EN0 / 1 / 2··· / x <n:0>), among which only one channel of the n+1 channel enable signals is at a high level and the remaining n channels are at a low level, and then the enable signal (EN0 / 1 / 2... / x <n:0>) are synchronized, and after the synchronization process, the enable control signal CLKEN0 / 1...x <n:0>The synchronization process outputs the input clock CLKIN <n:0>Triggered by the falling edge of the enable control signal CLKEN0 / 1...x <n:0>to the corresponding clock selection units as synchronous input controls.

[0038] The clock signal generating circuit and the driving method thereof provided by the present invention will be further described below with reference to the drawings.

[0039] As shown in FIG. 2, in some embodiments, counter 11 receives a dynamic phase adjustment trigger signal STEP_N, a dynamic phase adjustment direction DIRECTION, a dynamic phase adjustment channel selection signal SEL <m:0>, a load signal LOAD of the dynamic phase adjustment selected channel phase selection signal, and a current phase selection signal PHASENOW of the dynamic phase adjustment selected channel <m:0>The decoding and synchronization module 12 receives the new phase selection signal PHASENEW after dynamic phase adjustment. <m:0>Output.

[0040] The decoding and synchronization module 12 outputs a new phase selection signal PHASENEW after dynamic phase adjustment from the output end of the counter 11. <m:0>The decoding and synchronization module receives an input clock signal CLKIN <n:0>, dynamic phase adjustment trigger signal STEP_N, dynamic phase adjustment channel selection signal SEL <m:0>and each channel clock phase initial setting value PHASEINIT0 / 1 / ··· / x <m:0>The clock selector 13 further receives enable control signals CLKEN0 / 1 / ··· / x for the channel clock selectors. <m:0>Output.

[0041] The clock selector 13 includes a plurality of Clock Selection Unit (PHASESEL0 / 1.. / x) Clock Selection Unit (PHASESEL0 / 1.. / x) are enable control signals CLKEN0 / 1 / ··· / x for the corresponding channels output from the output terminal of the decoding and synchronization module 12. <m:0>and the clock selector receives an input clock signal CLKIN <n:0>and the output signal is the output clock CLKOUT0 / 1 / ··· / x.

[0042] The implementation process of the counter is as follows: the dynamic phase adjustment direction DIRECTION controls the counter to count up or count down, then triggers the LOAD signal (holds it at a high level for a certain period of time), and the selected channel phase selection value PHASENOW <m:0>The counter is loaded with PHASENOW on the rising edge of the clock signal STEP_N. <m:0>Count up or down based on the phase to select the new phase. <m:0>Output.

[0043] The realization process of the decoding and synchronization module is as follows: In the realization process of the initial phase, first, the initial phase value (PHASEINIT0 / 1 / 2··· / x <m:0>) and load each enable signal (EN0 / 1 / 2... / x <n:0>), among which only one of the n+1 channel enable signals is at high level and the remaining n channels are at low level, and then the enable signal (EN0 / 1 / 2··· / x <n:0>) and then synchronize the enable control signals CLKEN0 / 1...x <n:0>This output signal is the input clock CLKIN <n:0>Triggered by the falling edge of CLKEN0 / 1...x <n:0>are sent to each clock selection unit as synchronous input controls.

[0044] As shown in FIG. 3, for example, in the case of m=2, when the PHASE<2:0> setting value is determined by the 3-8 decoding circuit, only one channel of the output enable signal EN<7:0> is at high level, and the remaining seven channels are all at low level. After that, the enable signal (EN0 / 1 / 2··· / x <n:0>) and then synchronize the enable control signals CLKEN0 / 1...x <n:0>As shown in Figure 4, for example, in the case of n=7, the decoder outputs EN<7:0> and then first CLKIN <0> According to the phase relationship of the input clock CLKIN<7:0> and the control relationship between the clock and the enable control signal, the enable signal<7:0> after sampling is divided into two sets, among which the low bit<3:0> is sent directly to the corresponding DFF, and sampled and output at the corresponding clock falling edge, and the high bit<7:4> is sent to the corresponding DFF by the CLKIN <0> The falling edge triggers DFF1 and samples it again, then sends it to the corresponding DFF, which samples it at the falling edge of the corresponding clock and outputs it. Finally, the enable signal CLKEN0 / 1...x <n:0>are sent to each clock selector as synchronous input controls.

[0045] During the process of implementing dynamic phase adjustment, the PHASENEW output from counter 11 <m:0>Receive the selected channel enable signal (EN0 / 1 / 2··· / x <n:0>), among which only one of the n+1 channel enable signals is at high level and the remaining n channels are at low level, and then the enable signal (EN0 / 1 / 2··· / x <n:0>) and then synchronize the enable control signals CLKEN0 / 1...x <n:0>This output signal is synchronized to the input clock CLKIN <n:0>CLKEN0 / 1...x <n:0>are sent to each clock selector as synchronous input controls.

[0046] As shown in Figure 6, for example, in the case of the process of realizing the initial phase of the output clock CLKOUT0 / 1 / 2, the initial phase value PHASEINIT0 / 1 / 2 <m:0>are (m+1)'b0···000 / 0···001 / 0···010, respectively, and the difference between the initial values ​​of two adjacent clocks is (m+1)'b0···001. In other words, the phase difference between two adjacent output clocks CLKOUT0 / 1 / 2 is T / (n+1). The enable control signals CLKEN0 / 1 / 2 generated by decoding and synchronizing are <n:0>are (n+1)'b0···000 / 0···010 / 0···100, respectively. Among them, only one channel of each enable signal is 1, and the remaining n channels are all 0. The enable control signals are sent to each clock selector to select the corresponding phase clock as the output.

[0047] The realization process of the clock selector is as follows: the switched clock signal and the corresponding enable control signal are ANDed (AND logic processing) to obtain signal A, the target switched clock signal and the corresponding enable control signal are ANDed (AND logic processing) to obtain signal B, and then signals A+B are ORed (OR logic processing) to realize a glitch-free clock switching process, and the simple logic is shown in Figure 5.

[0048] The process of dynamically adjusting the clock phase is realized in a certain sequence through the digital interface. Figure 7 shows a schematic diagram of the clock phase adjustment sequence.

[0049] The process of dynamic adjustment without changing the channel is as follows: First, select the dynamic phase adjustment direction through DIRECTION, and then press SEL <m:0>does not change, then triggers the LOAD signal and holds it at a high level for a certain period of time, and the current channel phase selection value PHASENOW <m:0>After loading the counter, the STEP_N signal is triggered and depending on the adjustment direction, the counter counts up or down on the STEP_N rising edge and the counter loads the new phase selection value PHASENEW <m:0>and sends it to the decoding and synchronization module, where it is decoded and synchronized to the CLKIN clock domain, outputs a new enable control signal, and finally sends the enable control signal to the corresponding clock selector module to switch to the new phase clock.

[0050] As shown in Figure 8, for example, in the case of the output clock CLKOUT0 / 1, its phase initial value PHASEINIT0 / 1 <m:0>are (m+1)'b0···000 / 0···001 respectively, and the difference between the initial values ​​of the two clocks is (m+1)'b0···001, that is, the initial phase difference of the output clock CLKOUT0 / 1 is T / (n+1). CLKOUT0 is selected to dynamically adjust backward. At this time, PHASENOW is PHASEINIT0. <m:0>, that is, it corresponds to (m+1)'b0···000, triggers the STEP_N signal to generate a new phase selection value, and the counter counts up based on PHASENOW and updates it to PHASENEW. At this time, PHASENEW changes from (m+1)'b0···000 to (m+1)'b0···001, and the new phase selection value is decoded and synchronized by the decoding and synchronization module before being switched to the input clock CLKIN<7:0> clock domain. At this time, CLKEN0 <0> is switched from high to low, and CLKEN0 <0> is switched from low to high, sending an enable control signal to the clock selector PHASESEL0 and CLKIN <1> is selected as the output clock, and after dynamic adjustment, the output clock CLKOUT0 / 1 phase difference changes from the initial T / (n+1) to the same clock.

[0051] The process of changing the channel by dynamic adjustment is as follows. When you select the dynamic phase adjustment direction from DIRECTION, you also need to select SEL <m:0>Change the target channel current phase selection value to PHASENOW <m:0>Then, trigger the LOAD signal and hold it at a high level for a certain period of time, and the current channel phase selection value PHASENOW <m:0>After loading the counter, the STEP_N signal is triggered and depending on the adjustment direction, the counter counts up or down on the STEP_N rising edge and the counter counts up to the new phase selection value, PHASENEW. <m:0>and sends it to the decoding and synchronization module, where it is decoded and synchronized to the CLKIN clock domain, outputs a new enable control signal, and finally sends the enable control signal to the corresponding clock selector module to switch to the new phase clock.

[0052] As shown in FIG. 7, each signal must satisfy the corresponding sequence relationship to effectively perform the current dynamic adjustment.

[0053] The clock signal generating circuit and driving method provided by the embodiment of the present invention adopts the design concept of a timer, realizes positive and negative cycle adjustment of the clock phase, does not generate glitches in the output clock, and can dynamically switch between multi-channel clocks to adjust the phase.

[0054] The clock signal generating circuit provided by the embodiment of the present invention is particularly suitable for the field of multi-clocks where the output clock signal phase of a channel needs to be continuously adjusted, and according to application requirements, the clock signal generating circuit provided by the embodiment can continuously adjust the clock phase in a certain sequence through a specific digital interface.

[0055] An embodiment of the present invention further provides an electronic device, the electronic device including the clock signal generating circuit according to any one of the above claims.

[0056] An embodiment of the present invention further provides a computer-readable storage medium, in which computer instructions are stored in the computer-readable storage medium, and which, when executed by a processor, performs the driving method described in any one of the above.

[0057] The present invention relates to a circuit for dynamically adjusting the clock phase of a digital circuit system, which is particularly suitable for the field of multi-clocks where the clock phase of a channel needs to be adjusted continuously, and the clock phase can be adjusted continuously in a certain sequence through a specific digital interface according to application requirements. According to the proposed design sequence and concept, the clock phase can be adjusted in a forward and reverse cycle, no glitch occurs in the output clock, and the phase can be adjusted by switching between multi-channel clocks.

[0058] Those skilled in the art should understand that all or part of the steps of implementing the above method embodiments can be implemented by instructing relevant hardware through a computer program, and the program is stored in a computer-readable storage medium, and when the program is executed, it includes the steps of each of the above method embodiments. In which, the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM), etc.

[0059] Although the specific embodiments of the present invention have been described above, the scope of protection of the present invention is not limited thereto, and any modifications or replacements that are easily conceived by those skilled in the art within the technical scope disclosed in the present invention are all included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. a counter for generating a phase setting value from a count value in response to a clock phase adjustment request; a decoding and synchronizing module, which loads a phase initial value during an initial phase realization process, receives the phase setting value from the counter during a phase adjustment process, decodes the phase initial value or the phase setting value into an enable control signal, synchronizes and outputs the enable control signal, and synchronizes the enable control signal with a clock domain that needs to be adjusted through the synchronization process; a clock selector for receiving a synchronized enable control signal, and selecting, as an output, an input clock signal corresponding to the phase of the phase initial value or the phase setting value from among the multi-channel input clock signals in response to the enable control signal, such that the phases of the multi-channel input clock signals are continuous and can cover one clock period; The clock signal generation circuit is characterized in that the clock selector includes one or more clock selection units, the decoding and synchronization module outputs one or more enable control signals, the enable control signals having a one-to-one correspondence with the clock selection units, and the clock selection units receive corresponding synchronized enable control signals from the decoding and synchronization module, and are used to select as output an input clock signal corresponding to the phase of the phase initial value or the phase setting value from the multi-channel input clock signals according to the corresponding synchronized enable control signal.

2. The decoding and synchronization module includes: a decoder that decodes the phase initial value or the phase setting value into a plurality of enable control signals, only one of the plurality of enable control signals being at a high level and the rest being at a low level; a synchronization circuit that synchronizes and outputs the enable control signal, the synchronized enable control signal being triggered by a falling edge of an input clock.

2. The clock signal generating circuit according to claim 1 .

3. the decoder is a 3-8 decoding circuit, the synchronization circuit includes a first flip-flop, a second flip-flop and eight output flip-flops; a first input clock signal among the input clock signals is input to a trigger end of the first flip-flop, an input end of the first flip-flop is connected to an output end of the 3-8 decoding circuit, first to fourth signals among the first flip-flop output signals, ranging from a low level to a high level, are output to input ends of first to fourth output flip-flops among the eight output flip-flops, and the first flip-flop is used to be triggered by a rising edge of the first input clock signal to sample an output signal of the 3-8 decoding circuit; the first input clock signal is input to a trigger end of the second flip-flop, an input end of the first flip-flop receives fourth to eighth signals from a low level to a high level of the output signal of the first flip-flop, an output end of the second flip-flop is connected to input ends of fifth to eighth output flip-flops among the eight output flip-flops, the second flip-flop is used to sample fourth to eighth output signals from a low level to a high level of the output signal of the first flip-flop, and outputs the fourth to eighth output signals after sampling at a falling edge of the first input clock signal; 3. The clock signal generating circuit according to claim 2, wherein one of the input clock signals is input to a trigger end of each of the eight output flip-flops, and each of the eight output flip-flops outputs after being sampled at a clock falling edge of a corresponding input clock signal.

4. The clock selection unit includes: a first AND gate receiving an enable control signal corresponding to the switched clock signal from an input terminal; a second AND gate for receiving an enable control signal corresponding to the target switching clock signal from an input end; an OR gate having two input terminals connected to the output terminal of the first AND gate and the output terminal of the second AND gate, respectively, and an output terminal which is the output terminal of the clock selector; 2. The clock signal generating circuit of claim 1, wherein the clock selection unit corresponds to the output channel one-to-one, the switched clock signal refers to an input clock having a phase similar to that of an output clock corresponding to the output channel before phase adjustment, and the target switched clock signal refers to an input clock having a phase similar to that of an output clock corresponding to the output channel after phase adjustment.

5. A method for driving the clock signal generating circuit according to any one of claims 1 to 4, comprising: The counter receives a dynamic phase adjustment trigger signal STEP_N, a dynamic phase adjustment direction DIRECTION, a dynamic phase adjustment channel selection signal SEL<m:0>, a dynamic phase adjustment selected channel phase selection signal load signal LOAD, and a dynamic phase adjustment selected channel current phase selection signal PHASENOW<m:0>. The decoding and synchronization module receives a new phase selection signal PHASENEW<m:0> after dynamic phase adjustment from the output end of the counter. The decoding and synchronization module receives an input clock The clock selector further receives a signal CLKIN<n:0>, a dynamic phase adjustment trigger signal STEP_N, a dynamic phase adjustment channel selection signal SEL<m:0> and each channel clock phase initial setting value PHASEINIT0 / 1 / ... / x<m:0>, and the clock selector receives an enable control signal CLKEN0 / 1 / ... / x<n:0> of each channel clock selector from the output end of the decoding and synchronization module, and the clock selector further receives the input clock signal CLKIN<n:0>; The driving method includes the steps of loading and saving a phase initial value through each channel clock phase initial setting value PHASEINIT0 / 1 / ... / x<m:0> by the decoding and synchronization module, decoding the phase initial value into a corresponding enable control signal, then synchronizing each enable control signal, and sending each synchronized enable control signal CLKEN0 / 1 / ... / x<n:0> to a corresponding clock selection unit, and the clock selection unit selects an input clock signal of a corresponding phase from an input clock signal CLKIN<n:0> as an output according to the phase initial value.

6. The driving method further includes a dynamic phase adjustment step, Receive a new phase selection signal PHASENEW<m:0> after dynamic phase adjustment of the counter output, decode it into a selection channel enable signal (EN0 / 1 / 2... / x<n:0>), among which only one channel of the enable signals of n+1 channels is at a high level and the remaining n channels are at a low level, and then synchronize the enable signals (EN0 / 1 / 2... / x<n:0>); 6. The driving method according to claim 5, further comprising: outputting enable control signals CLKEN0 / 1...x<n:0> after a synchronization process, the synchronization process being triggered by a falling edge of the input clock CLKIN<n:0>, and sending the enable control signals CLKEN0 / 1...x<n:0> to corresponding clock selection units as synchronization input control, respectively.

7. In the case where the output channel is not changed during the phase adjustment, the dynamic phase adjustment step includes:

7. The driving method of claim 6, further comprising the steps of: the counter obtains a direction of dynamic phase adjustment from a dynamic phase adjustment direction DIRECTION; at this time, the dynamic phase adjustment channel selection signal SEL<m:0> is not changed; a load signal LOAD for triggering a dynamic phase adjustment selection channel phase selection signal remains at a low level; then, after a current channel phase selection value PHASENOW<m:0> is loaded into the counter, a STEP_N signal is triggered; according to the dynamic phase adjustment direction, the counter counts up or counts down at a rising edge of STEP_N; outputting a new phase selection value PHASENEW<m:0> from the counter and sending it to the decoding and synchronization module; being decoded in the decoding and synchronization module and synchronized with the clock domain of an input clock; outputting a new enable control signal; and sending the enable control signal to a corresponding clock selection unit; and the clock selection unit switches to a new phase clock according to the enable control signal.

8. In the case where the output channel is changed during the phase adjustment, the dynamic phase adjustment step includes:

7. The driving method of claim 6, further comprising the steps of: when the counter selects a dynamic phase adjustment direction according to a dynamic phase adjustment direction DIRECTION, selecting a channel for phase adjustment from a dynamic phase adjustment channel selection signal SEL<m:0>; sending a current phase selection signal PHASENOW<m:0> of the dynamic phase adjustment selection channel of the counter to the counter; triggering a LOAD signal to be held at a high level for a certain period of time; loading a current channel phase selection value PHASENOW<m:0> to the counter; triggering a STEP_N signal; according to the adjustment direction, the counter counts up or counts down at a rising edge of STEP_N; the counter outputs a new phase selection value PHASENEW<m:0> to a decoding and synchronization module, which is decoded and synchronized to the clock domain of the input clock CLKIN in the decoding and synchronization module; outputting a new enable control signal; and sending the enable control signal to the corresponding clock selection unit, which switches to a new phase clock.

9. An electronic device comprising the clock signal generating circuit according to any one of claims 1 to 4.

10. A computer-readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the method according to any one of claims 5 to 8.

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