A new clock control method and system based on FPGA

Abstract

The invention provides a novel clock control method and system based on FPGA, and relates to the technical field of signal processing. The system provided by the invention comprises: a VCXO voltage-controlled crystal oscillator, a digital-to-analog converter, a PLL phase-locked loop module, a DDMTD measurement module and an adaptive clock control module. The phase-locked loop is implemented, a phase detection algorithm and a clock control algorithm are executed based on a single FPGA chip, and the hardware design complexity is low. The invention uses a digital dual-mixing time difference method (DDMTD) to measure and obtain a clock phase detection result, and cooperates with a dynamic PID clock control algorithm to quickly adjust the local clock frequency, so as to realize the fast tracking and locking of the frequency and phase between the local clock and the clock source. The dynamic PID clock control algorithm of the invention dynamically adjusts the parameter P of the PID algorithm in real time according to the state, the clock frequency deviation and the clock phase difference, so that the algorithm has the advantages of stronger locking ability, shorter convergence time and faster response.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, and in particular to a novel clock control method and system based on FPGA. Background Art

[0002] Precision time and frequency play a very important role in aerospace, modern industry, mobile communications, military and other fields. With the advancement of technology, the requirements for the accuracy of time and frequency references in various application fields are getting higher and higher. At the same time, the frequency accuracy of the clock is very important for the stable and reliable operation of the equipment. Usually, clock devices are configured in various application devices. The purpose of clock control is to synchronize the local controlled clock with the reference clock with high-precision frequency and phase, and then provide the synchronized high-precision clock signal to the local equipment to improve the frequency accuracy of the local equipment clock.

[0003] There are generally two existing clock control methods: one is to use a dedicated chip to complete the clock phase difference measurement, and its measurement accuracy is about tens of picoseconds. The clock phase measurement data is then handed over to the microcontroller or CPU to complete the clock control according to the software clock control algorithm. This results in a long clock control convergence time, slow clock tracking response, and high dedicated chip hardware cost; the other is an analog control method, which completes the clock control through a hardware phase-locked loop circuit. This method requires the design of related hardware circuits, has high hardware design complexity, high hardware cost, and weak tight coupling and anti-interference ability.

[0004] Therefore, there is an urgent need for a new clock control method and system based on FPGA to solve the above technical problems. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a new clock control method and system based on FPGA, aiming to reduce the complexity of hardware design and solve the problems of long clock control convergence time, slow clock tracking response, poor versatility, etc.

[0006] The purpose of the present invention is achieved through the following technical solutions:

[0007] On the one hand, the present invention provides a novel clock control system based on FPGA, characterized by a VCXO voltage-controlled crystal oscillator, a digital-to-analog converter, a PLL phase-locked loop module, a DDMTD measurement module and an adaptive clock control module;

[0008] The DDMTD measurement module is electrically connected to the PLL phase-locked loop module, the VCXO voltage-controlled crystal oscillator and the adaptive clock control module respectively; the PLL phase-locked loop module is electrically connected to the VCXO voltage-controlled crystal oscillator; and the adaptive clock control module is electrically connected to the VCXO voltage-controlled crystal oscillator through a digital-to-analog converter;

[0009] The DDMTD measurement module receives the clock source signal clk input from the outside A And voltage-controlled crystal oscillator clock signal clk B and by measuring the clock source signal clk A And voltage-controlled crystal oscillator clock signal clk B The phase difference is used to obtain the clock phase difference measurement data; the PLL phase-locked loop module is generated by the FPGA IP core, and the FPGA PLL phase-locked loop IP core is based on the voltage-controlled crystal oscillator clock signal clk B Generate DDMTD mixing clock signal clk ddmtd , and input to the DDMTD measurement module;

[0010] The adaptive clock control module receives and adaptively adjusts the voltage control word according to the clock phase difference measurement data, the digital-to-analog converter adjusts the DAC output voltage according to the voltage control word, and the VCXO voltage-controlled crystal oscillator generates a voltage-controlled crystal oscillator clock signal clk according to the DAC output voltage. B ; Wherein, the voltage-controlled control word controls the voltage-controlled crystal oscillator clock signal clk B Tracking clock source signal clk A , and keep the same frequency and phase locked within the setting range.

[0011] As a further solution, the DDMTD mixing clock signal clk ddmtd And the voltage-controlled crystal oscillator clock signal clk B The signal frequency satisfies the following equation:

[0012]

[0013] Where N is a positive integer, Indicates the DDMTD mixing clock signal clk ddmtd The signal frequency, Represents the voltage-controlled crystal oscillator clock signal clk B The phase difference between the DDMTD mixer output and the measured clock input

[0014] As a further solution, the phase difference between the DDMTD mixing clock signal and the measured clock input is:

[0015]

[0016] Among them, n cycles Indicates the use of clk ddmtd The clock measures the phase difference between two periodically amplified clock signals. [ns] indicates that all calculations are performed in nanoseconds.

[0017] As a further solution, the clock phase difference measurement data measured by the DDMTD measurement module is: the clock source signal clk A The phase of the voltage-controlled crystal oscillator clock signal clk is subtracted B The phase of the voltage-controlled crystal oscillator clock signal clk is taken first B Phase data, and then take the clock source signal clk A phase data and ensure that the measured clock phase difference measurement data is always positive.

[0018] As a further solution, the adaptive clock control module is used to execute a clock control algorithm, and the clock control algorithm is implemented by a state machine; wherein the control state of the state machine includes:

[0019] s_IDLE state: used to execute the power-on reset initial parameter configuration function;

[0020] s_FREQ_ROUGH_ADJ state: used to perform frequency coarse adjustment function;

[0021] s_CLK_STATE_CONTROL state: used to perform clock state control functions;

[0022] s_FREQ_FINE_ADJ state: used to perform frequency fine adjustment function;

[0023] s_PHASE_ADJ state: used to perform phase adjustment function;

[0024] s_HOLD state: used to execute the clock hold function;

[0025] s_LOCK state: used to perform frequency phase locking function.

[0026] On the other hand, the present invention provides a novel clock control method based on FPGA, which is applied to a novel clock control system based on FPGA as described in any one of the above items, wherein the adaptive clock control module completes the local voltage-controlled clock control through the following steps:

[0027] Step 1: Enter the s_IDLE state after power-on reset; in the s_IDLE state: the voltage-controlled crystal oscillator clock signal clk B Initialization, setting the voltage control word to the voltage control word stored before the last power failure or the preset theoretical center value;

[0028] Step 2: Wait for the voltage-controlled crystal oscillator clock signal clk B After stabilization, it enters the s_FREQ_ROUGH_ADJ state; in the s_FREQ_ROUGH_ADJ state: collect clock phase difference measurement data, and control and adjust the voltage-controlled crystal oscillator clock signal clk through the PID algorithmB , reduce the clock source signal clk A The frequency difference is less than or equal to f rough ;

[0029] Step 3: Enter the s_CLK_STATE_CONTROL state; obtain the voltage-controlled crystal oscillator clock signal clk B With the clock source signal clk A The clock phase difference measurement data is used to calculate the clock frequency difference according to the clock phase difference change rate, and the current control state is switched according to the execution conditions; wherein,

[0030] Condition 1: Voltage-controlled crystal oscillator clock signal clk B With the clock source signal clk A The frequency difference is greater than f fine , and the clock phase difference measurement data is greater than P lock and less than T clkA -P lock ; If condition 1 is met, switch to s_FREQ_FINE_ADJ state;

[0031] Condition 2: The frequency difference between the local clock and the clock source is less than or equal to f fine , and the clock phase difference measurement data is greater than P lock and less than T clkA -P lock ; If condition 2 is met, switch to s_PHASE_ADJ state;

[0032] Condition 3: The clock phase difference measurement data cannot be obtained; if condition 3 is met, the state switches to s_HOLD;

[0033] Condition 4: The clock phase difference measurement data is less than or equal to P lock Or greater than or equal to T clkA -P lock ; If condition 4 is met, switch to s_LOCK state;

[0034] Among them, f fine The frequency difference threshold for completing the s_FREQ_FINE_ADJ state, f rough The frequency difference threshold for completing the s_FREQ_ROUGH_ADJ state, and there is f fine Less than or equal to f rough ;P lock is the clock phase difference threshold for entering the s_LOCK state, and P lock Less than or equal to T clkA Half of T clkA is the clock source signal clk A cycle.

[0035] As a further solution, in the s_PHASE_ADJ state,

[0036] If the clock phase difference measurement data is less than T clkA / 2 and it is expanding, then the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data. B With the clock source signal clk A The frequency difference is then controlled by the PID algorithm to change the expansion trend of the clock phase difference measurement data according to the frequency difference;

[0037] If the clock phase difference measurement data is less than T clkA / 2 and it shows a decreasing trend, the voltage-controlled control word is not changed, and the voltage-controlled crystal oscillator clock signal clk is maintained. B The unchanged trend makes the decreasing trend continue;

[0038] If the clock phase difference measurement data is greater than or equal to T clkA / 2 and it is expanding, the voltage-controlled control word is not changed, and the voltage-controlled crystal oscillator clock signal clk is maintained. B The unchanged trend makes the expansion trend continue;

[0039] If the clock phase difference measurement data is greater than or equal to T clkA / 2 and it is decreasing, then the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data. B With the clock source signal clk A The frequency difference is then determined by the PID algorithm to change the decreasing trend of the clock phase difference measurement data.

[0040] As a further solution, in the s_HOLD state, if the acquisition of the clock phase difference measurement data is not resumed, the voltage control word is kept unchanged and the s_HOLD state is continued; if the acquisition of the clock phase difference measurement data is resumed, the s_CLK_STATE_CONTROL state is entered.

[0041] As a further solution, in the s_LOCK state,

[0042] If the clock phase difference measurement data is less than P lock And it is expanding, then the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data B With the clock source signal clk A The frequency difference is then controlled by the PID algorithm to change the expansion trend of the clock phase difference measurement data according to the frequency difference;

[0043] If the clock phase difference measurement data is less than P lock If the voltage-controlled control word is not changed and the voltage-controlled crystal oscillator clock signal clk is maintained,B The unchanged trend makes the decreasing trend continue;

[0044] If the clock phase difference measurement data is greater than or equal to T clkA -P lock If the voltage-controlled control word is not changed, the voltage-controlled crystal oscillator clock signal clk is maintained. B The unchanged trend makes the expansion trend continue;

[0045] If the clock phase difference measurement data is greater than or equal to T clkA -P lock And it shows a decreasing trend, the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data B With the clock source signal clk A The frequency difference is then determined by the PID algorithm to change the decreasing trend of the clock phase difference measurement data.

[0046] As a further solution, in the s_FREQ_FINE_ADJ state, s_PHASE_ADJ state and s_LOCK state, the voltage-controlled crystal oscillator clock signal clk is controlled and adjusted by the PID algorithm. B , reduce the clock source signal clk A The frequency difference and clock phase difference measurement data of the clock are obtained; wherein, the size of the PID algorithm parameter P is dynamically determined by the state of the clock control algorithm, the size of the clock frequency deviation and the size of the clock phase difference.

[0047] Compared with the related art, the novel clock control method and system based on FPGA provided by the present invention has the following advantages:

[0048] 1. The present invention adopts full digital dual-mixing phase-detection technology based on FPGA for automatic and rapid clock control, and has the advantages of high phase-detection accuracy, short clock control convergence time, and rapid clock tracking response.

[0049] 2. The clock control strength (i.e., PID algorithm parameter P) of the clock control algorithm of the present invention is adjusted dynamically in real time according to the state of the clock control algorithm, clock frequency deviation, and clock phase difference, so that the clock control algorithm has the advantages of stronger locking ability, shorter convergence time, and faster response.

[0050] 3. The novel clock control system structure of the present invention is based on a single FPGA chip to execute phase detection and clock control algorithms, has strong portability and small integration capabilities, and has low hardware cost and design complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A schematic diagram of the structure of a novel clock control system based on FPGA provided by the present invention;

[0052] Figure 2 A schematic diagram of the functional structure of the adaptive clock control module provided by the present invention;

[0053] Figure 3 A schematic diagram of the steps of a novel clock control method based on FPGA provided by the present invention;

[0054] Figure 4 A schematic diagram of the architecture of the all-digital dual-mixing phase-detection technology provided by the present invention;

[0055] Figure 5 Schematic diagram for explaining the principle of DDMTD provided by the present invention. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0057] Example 1

[0058] See also Figure 1 , the present invention provides a novel clock control system based on FPGA, characterized by a VCXO voltage-controlled crystal oscillator, a digital-to-analog converter, a PLL phase-locked loop module, a DDMTD measurement module and an adaptive clock control module;

[0059] The DDMTD measurement module is electrically connected to the PLL phase-locked loop module, the VCXO voltage-controlled crystal oscillator and the adaptive clock control module respectively; the PLL phase-locked loop module is electrically connected to the VCXO voltage-controlled crystal oscillator; and the adaptive clock control module is electrically connected to the VCXO voltage-controlled crystal oscillator through a digital-to-analog converter;

[0060] The DDMTD measurement module receives the clock source signal clk input from the outside A And voltage-controlled crystal oscillator clock signal clk B and by measuring the clock source signal clk A And voltage-controlled crystal oscillator clock signal clk B The phase difference is used to obtain the clock phase difference measurement data; the PLL phase-locked loop module is generated by the FPGA IP core, and the FPGA PLL phase-locked loop IP core is based on the voltage-controlled crystal oscillator clock signal clk B Generate DDMTD mixing clock signal clk ddmtd , and input to the DDMTD measurement module;

[0061] The adaptive clock control module receives and adaptively adjusts the voltage control word according to the clock phase difference measurement data, the digital-to-analog converter adjusts the DAC output voltage according to the voltage control word, and the VCXO voltage-controlled crystal oscillator generates a voltage-controlled crystal oscillator clock signal clk according to the DAC output voltage. B ; Wherein, the voltage-controlled control word controls the voltage-controlled crystal oscillator clock signal clk B Tracking clock source signal clk A , and keep the same frequency and phase locked within the setting range.

[0062] The novel clock control system provided in this embodiment utilizes the high-precision phase detection capability of DDMTD (whose theoretical measurement accuracy can reach femtosecond level) to complete high-performance locking of the clock source according to the clock control algorithm; the advantages of this novel clock control system are: high phase detection accuracy, short clock control convergence time, rapid clock tracking response, and real-time dynamic control of clock control intensity; low hardware design complexity and low hardware cost; this embodiment executes phase detection and clock control algorithms based on a single FPGA chip, and has strong portability and small integration capabilities.

[0063] like Figure 1 As shown, in this embodiment, the clock clk is measured by the DDMTD measurement module A and clk B The phase difference data, the adaptive clock control module adjusts the voltage control word through the clock control algorithm to control the voltage controlled crystal oscillator clock clk B Tracking clock source clock clk A , so that clk B Keep locked clk A , reaching clk B and clk A Keep the same frequency and phase within a certain range; among them, clk A It is the clock source signal input from the outside, clk B It is the clock signal output by the voltage-controlled crystal oscillator clock VCXO.

[0064] The DDMTD measurement module used in this embodiment completes the high-precision phase difference measurement of two clock signals with the same period through the full digital dual-mixing phase-detection technology (DDMTD); in the full digital dual-mixing phase-detection technology, the period of the input clock signal is amplified by using a D flip-flop, and then the phase difference of the period-amplified clock signal is measured, and the original clock phase difference is calculated based on the measurement data to complete the high-precision measurement of the clock signal phase difference.

[0065] The full digital dual mixer phase detection technology architecture is as follows Figure 4 As shown, the input signal under test (clk A and clk B ) is the clock square wave signal, clk A and clkB The frequency is close, DDMTD mixing clock (clk ddmtd ) is determined by the input clock (clk A ) is generated by the PLL phase-locked loop. The DDMTD mixing clock frequency has a certain frequency deviation from the input clock frequency. The mixer uses a simple D-type flip-flop. The mixer clock uses the DDMTD mixing clock (clk ddmtd ), using DDMTD technology to measure clock clk A and clk B The phase difference between them.

[0066] The principle of DDMTD can be explained in a more intuitive way, such as Figure 5 (a) shows a vernier caliper with two scales, a main scale in millimeters and a small vernier scale with units slightly smaller than the main scale. For a typical caliper, the vernier caliper is divided into 10 intervals. If the length of the object being measured has a fractional part, one scale bar on the vernier caliper will align with one scale bar on the main scale to complete a higher precision measurement. In DDMTD, the main scale is the input clock under test, where each interval represents one cycle, and the vernier scale is the DDMTD mixing clock (clk ddmtd ), when the main scale is aligned with the vernier scale, it means that the rising edge of the DDMTD mixing clock is aligned with the rising edge of the measured clock, and the measurement of the measured clock phase in the DDMTD mixing clock domain is completed.

[0067] like Figure 5 As shown in (b), input A is clk A , input B is clk B , offset clock is clk ddmtd , outputA is clk A After the output of the D flip-flop, output B is clk B After the output of the D flip-flop, when the DDMTD mixing clock (clk ddmtd ) An example of DDMTD clock phase detection when parameter N = 8. The DDMTD mixer output phase difference is N+1 times the measured clock input phase difference (φ). The measured clock input phase difference (φ) and the DDMTD mixer clock frequency The general relationship can be expressed as formula 1:

[0068]

[0069] Among them, n cycles Indicates the use of clk ddmtd The clock counts the measured value of the phase difference of the two periodically amplified clock signals; N is a positive integer, and the above formula represents the mixing clock signal clk ddmtdAnd voltage-controlled crystal oscillator clock signal clk B The larger the N value, the closer their frequencies are, the higher the DDMD measurement accuracy is, and the fewer DDMTD measurement results are obtained per unit time.

[0070] The clock phase difference data measured by the DDMTD measurement module is the clock source signal clk A Phase minus voltage-controlled crystal oscillator clock signal clk B Phase, and first take the voltage-controlled crystal oscillator clock signal clk B Phase data, and then take the clock source signal clk A phase data and ensure that the measured clock phase difference measurement data is always positive.

[0071] The adaptive clock control module uses the clock control algorithm to complete the local voltage-controlled clock control according to the DDMTD phase difference measurement data. The clock control algorithm can be functionally divided into power-on reset, frequency coarse adjustment, clock control state judgment, frequency fine adjustment, phase adjustment, clock hold and frequency phase lock. Its functions are divided as follows: Figure 2 shown.

[0072] Example 2

[0073] See also Figure 3 The present invention provides a novel clock control method based on FPGA, which is applied to a novel clock control system based on FPGA as described in any one of the above items, wherein the adaptive clock control module completes the local voltage-controlled clock control through the following steps:

[0074] Step 1: Enter the s_IDLE state after power-on reset; in the s_IDLE state: the voltage-controlled crystal oscillator clock signal clk B Initialization, setting the voltage control word to the voltage control word stored before the last power failure or the preset theoretical center value;

[0075] Step 2: Wait for the voltage-controlled crystal oscillator clock signal clk B After stabilization, it enters the s_FREQ_ROUGH_ADJ state; in the s_FREQ_ROUGH_ADJ state: collect clock phase difference measurement data, and control and adjust the voltage-controlled crystal oscillator clock signal clk through the PID algorithm B , reduce the clock source signal clk A The frequency difference is less than or equal to f rough ;

[0076] Step 3: Enter the s_CLK_STATE_CONTROL state; obtain the voltage-controlled crystal oscillator clock signal clk B With the clock source signal clk AThe clock phase difference measurement data is used to calculate the clock frequency difference according to the clock phase difference change rate, and the current control state is switched according to the execution conditions; wherein,

[0077] Condition 1: Voltage-controlled crystal oscillator clock signal clk B With the clock source signal clk A The frequency difference is greater than f fine , and the clock phase difference measurement data is greater than P lock and less than T clkA -P lock ; If condition 1 is met, switch to s_FREQ_FINE_ADJ state;

[0078] Condition 2: The frequency difference between the local clock and the clock source is less than or equal to f fine , and the clock phase difference measurement data is greater than P lock and less than T clkA -P lock ; If condition 2 is met, switch to s_PHASE_ADJ state;

[0079] Condition 3: The clock phase difference measurement data cannot be obtained; if condition 3 is met, the state switches to s_HOLD;

[0080] Condition 4: The clock phase difference measurement data is less than or equal to P lock Or greater than or equal to T clkA -P lock ; If condition 4 is met, switch to s_LOCK state;

[0081] Among them, f fine The frequency difference threshold for completing the s_FREQ_FINE_ADJ state, f rough The frequency difference threshold for completing the s_FREQ_ROUGH_ADJ state, and there is f fine Less than or equal to f rough ;P lock is the clock phase difference threshold for entering the s_LOCK state, and P lock Less than or equal to T clkA Half of T clkA is the clock source signal clk A cycle.

[0082] It should be noted that the existing high-precision clock synchronization methods have the problem of clock loss. For example, the invention application with publication number CN112311492A provides a high-precision clock synchronization method based on FPGA. This method is based on DDMTD phase measurement and achieves high-precision clock synchronization by dynamically adjusting the phase of the slave system clock. The slave system clock uses FPGAPLL to lock the recovered clock generation; therefore, when the recovered clock is lost, the entire slave device has no system clock and the system cannot work normally.

[0083] This embodiment implements DDMTD high-precision phase detection in FPGA, and quickly calculates clock control parameters and completes control based on DDMTD phase detection data, thereby achieving high-precision synchronization with the clock source; wherein, the clock control method proposed in this embodiment only controls the local clock frequency (clk B ) Dynamically track the clock source (clk A ) frequency and phase, so that the local clock can quickly lock the clock source. In addition, this method will not interrupt the local clock output when the reference clock source is lost, and it can ensure the high-performance output of the local clock within a certain period of time, ensuring the stable and reliable operation of the system.

[0084] In addition, in order to speed up the clock frequency and phase tracking speed, this embodiment, based on the DDMTD clock phase measurement result, cooperates with the PID dynamic clock control algorithm, and dynamically adjusts the PID algorithm parameter P in real time according to the state of the clock control algorithm, the clock frequency deviation and the clock phase difference, while quickly eliminating the clock frequency difference, completing the locking of the clock phase, and realizing the rapid tracking and locking of the frequency and phase between the local clock and the clock source; wherein, when the clock frequency difference is large, the PID algorithm parameter P becomes larger, and when the clock frequency difference is small, the PID algorithm parameter P becomes smaller; when the clock phase difference is large, the PID algorithm parameter P becomes larger, and when the clock phase difference is small, the PID algorithm parameter P becomes smaller; when the s_FREQ_ROUGH_ADJ state is the largest, when the s_FREQ_FINE_ADJ and s_PHASE_ADJ states are the second largest, and when the s_LOCK state is the smallest PID algorithm parameter P; that is, the size of the PID algorithm parameter P is dynamically determined by the state of the clock control algorithm, the size of the clock frequency deviation and the size of the clock phase difference.

[0085] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. A new clock control system based on FPGA, characterized in that: VCXO voltage-controlled crystal oscillator, digital-to-analog converter, PLL phase-locked loop module, DDMTD measurement module and adaptive clock control module; The DDMTD measurement module is electrically connected to the PLL phase-locked loop module, the VCXO voltage-controlled crystal oscillator and the adaptive clock control module respectively; the PLL phase-locked loop module is electrically connected to the VCXO voltage-controlled crystal oscillator; and the adaptive clock control module is electrically connected to the VCXO voltage-controlled crystal oscillator through a digital-to-analog converter; The DDMTD measurement module receives the clock source signal clk input from the outside A And voltage-controlled crystal oscillator clock signal clk B and by measuring the clock source signal clk A And voltage-controlled crystal oscillator clock signal clk B The phase difference is used to obtain the clock phase difference measurement data; the PLL phase-locked loop module is generated by the FPGA IP core, and the FPGA PLL phase-locked loop IP core is based on the voltage-controlled crystal oscillator clock signal clk B Generate DDMTD mixing clock signal clk ddmtd , and input to the DDMTD measurement module; The adaptive clock control module receives and adaptively adjusts the voltage control word according to the clock phase difference measurement data, the digital-to-analog converter adjusts the DAC output voltage according to the voltage control word, and the VCXO voltage-controlled crystal oscillator generates a voltage-controlled crystal oscillator clock signal clk according to the DAC output voltage. B ; Wherein, the voltage-controlled control word controls the voltage-controlled crystal oscillator clock signal clk B Tracking clock source signal clk A , and keep the same frequency and phase locked within the setting range.

2. The novel clock control system based on FPGA according to claim 1, characterized in that: The DDMTD mixing clock signal clk ddmtd And the voltage-controlled crystal oscillator clock signal clk B The signal frequency satisfies the following equation: Where N is a positive integer, Indicates the DDMTD mixing clock signal clk ddmtd The signal frequency, Represents the voltage-controlled crystal oscillator clock signal clk B signal frequency.

3. The novel clock control system based on FPGA according to claim 2 is characterized in that: The phase difference between the DDMTD mixing clock signal and the measured clock input is: Among them, n cycles Indicates the use of clk ddmtd The clock measures the phase difference between two periodically amplified clock signals. [ns] indicates that all calculations are performed in nanoseconds.

4. The novel clock control system based on FPGA according to claim 1, characterized in that: The clock phase difference measurement data measured by the DDMTD measurement module is: the clock source signal clk A The phase of the voltage-controlled crystal oscillator clock signal clk is subtracted B The phase of the voltage-controlled crystal oscillator clock signal clk is taken first B Phase data, and then take the clock source signal clk A phase data and ensure that the measured clock phase difference measurement data is always positive.

5. The novel clock control system based on FPGA according to claim 1, characterized in that: The adaptive clock control module is used to execute a clock control algorithm, and the clock control algorithm is implemented by a state machine control; wherein the control state of the state machine includes: s_IDLE state: used to execute the power-on reset initial parameter configuration function; s_FREQ_ROUGH_ADJ state: used to perform frequency coarse adjustment function; s_CLK_STATE_CONTROL state: used to perform clock state control functions; s_FREQ_FINE_ADJ state: used to perform frequency fine adjustment function; s_PHASE_ADJ state: used to perform phase adjustment function; s_HOLD state: used to execute the clock hold function; s_LOCK state: used to perform frequency phase locking function.

6. A novel clock control method based on FPGA, applied to a novel clock control system based on FPGA as claimed in any one of claims 1 to 5, characterized in that: The adaptive clock control module completes the local voltage-controlled clock control through the following steps: Step 1: Enter the s_IDLE state after power-on reset; in the s_IDLE state: the voltage-controlled crystal oscillator clock signal clk B Initialization, setting the voltage control word to the voltage control word stored before the last power failure or the preset theoretical center value; Step 2: The voltage-controlled crystal oscillator clock signal clk B After stabilization, it enters the s_FREQ_ROUGH_ADJ state; in the s_FREQ_ROUGH_ADJ state: collect clock phase difference measurement data, and control and adjust the voltage-controlled crystal oscillator clock signal clk through the PID algorithm B , reduce the clock source signal clk A The frequency difference is less than or equal to f rough ; Step 3: Enter the s_CLK_STATE_CONTROL state; obtain the voltage-controlled crystal oscillator clock signal clk B With the clock source signal clk A The clock phase difference measurement data is used to calculate the clock frequency difference according to the clock phase difference change rate, and the current control state is switched according to the execution conditions; wherein, Condition 1: Voltage-controlled crystal oscillator clock signal clk B With the clock source signal clk A The frequency difference is greater than f fine , and the clock phase difference measurement data is greater than P lock and less than If condition 1 is met, switch to s_FREQ_FINE_ADJ state; Condition 2: The frequency difference between the local clock and the clock source is less than or equal to f fine , and the clock phase difference measurement data is greater than P lock and less than If condition 2 is met, switch to s_PHASE_ADJ state; Condition 3: The clock phase difference measurement data cannot be obtained; if condition 3 is met, the state switches to s_HOLD; Condition 4: The clock phase difference measurement data is less than or equal to P lock or greater than or equal to If condition 4 is met, switch to s_LOCK state; Among them, f fine The frequency difference threshold for completing the s_FREQ_FINE_ADJ state, f rough The frequency difference threshold for completing the s_FREQ_ROUGH_ADJ state, and there is f fine Less than or equal to f rough ;P lock is the clock phase difference threshold for entering the s_LOCK state, and P lock Less than or equal to half of; is the clock source signal clk A cycle.

7. The novel clock control method based on FPGA according to claim 6, characterized in that: In the s_PHASE_ADJ state, If the clock phase difference measurement data is less than And it is expanding, then the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data B With the clock source signal clk A The frequency difference is then controlled by the PID algorithm to change the expansion trend of the clock phase difference measurement data according to the frequency difference; If the clock phase difference measurement data is less than If the voltage-controlled control word is not changed and the voltage-controlled crystal oscillator clock signal clk is maintained, B The unchanged trend makes the decreasing trend continue; If the clock phase difference measurement data is greater than or equal to If the voltage-controlled control word is not changed, the voltage-controlled crystal oscillator clock signal clk is maintained. B The unchanged trend makes the expansion trend continue; If the clock phase difference measurement data is greater than or equal to And it shows a decreasing trend, the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data B With the clock source signal clk A The frequency difference is then determined by the PID algorithm to change the decreasing trend of the clock phase difference measurement data.

8. The novel clock control method based on FPGA according to claim 6, characterized in that: In the s_HOLD state, if the acquisition of the clock phase difference measurement data is not resumed, the voltage control word is kept unchanged and the s_HOLD state is continued; if the acquisition of the clock phase difference measurement data is resumed, the s_CLK_STATE_CONTROL state is entered.

9. The novel clock control method based on FPGA according to claim 6, characterized in that: In the s_LOCK state, If the clock phase difference measurement data is less than P lock And it is expanding, then the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data B With the clock source signal clk A The frequency difference is then controlled by the PID algorithm to change the expansion trend of the clock phase difference measurement data according to the frequency difference; If the clock phase difference measurement data is less than P lock If the voltage-controlled control word is not changed and the voltage-controlled crystal oscillator clock signal clk is maintained, B The unchanged trend makes the decreasing trend continue; If the clock phase difference measurement data is greater than or equal to If the voltage-controlled control word is not changed, the voltage-controlled crystal oscillator clock signal clk is maintained. B The unchanged trend makes the expansion trend continue; If the clock phase difference measurement data is greater than or equal to And it shows a decreasing trend, the voltage-controlled crystal oscillator clock signal clk is calculated according to the two adjacent clock phase difference measurement data B With the clock source signal clk A The frequency difference is then determined by the PID algorithm to change the decreasing trend of the clock phase difference measurement data.

10. A novel clock control method based on FPGA according to any one of claims 6, 7 or 9, characterized in that: In the s_FREQ_FINE_ADJ state, s_PHASE_ADJ state and s_LOCK state, the voltage-controlled crystal oscillator clock signal clk is adjusted by the PID algorithm. B , reduce the clock source signal clk A The frequency difference and clock phase difference measurement data of the clock are obtained; wherein, the size of the PID algorithm parameter P is dynamically determined by the state of the clock control algorithm, the size of the clock frequency deviation and the size of the clock phase difference.

Images