Printed wiring board, laminated resonator and laminated filter

Abstract

This printed wiring board comprises a dielectric layer, a first conductor layer, a second conductor layer, and a plurality of via conductors. The dielectric layer has a first surface and a second surface positioned opposite the first surface. The first conductor layer is positioned on the first surface of the dielectric layer, and the second conductor layer is positioned on the second surface of the dielectric layer. Each of the plurality of via conductors extends through the dielectric layer from the first surface to the second surface, and connects the first conductor layer and the second conductor layer. The printed wiring board includes a portion surrounded by the plurality of via conductors and in which the first conductor layer and the second conductor layer overlap in a transparent plan view. The plurality of via conductors include some that have a shape with an aspect ratio of greater than one in plan view, with a longer diameter in a first direction and a shorter diameter in a second direction, the longer diameter lying along an outer periphery connecting the arrangement of the plurality of via conductors.

Description

[Technical field]

[0001] The present disclosure relates to a printed wiring board, a laminated resonator, and a laminated filter. [Background technology]

[0002] Conventionally, a technique for forming a laminated resonator and a laminated filter using the same inside a printed wiring board using a lamination technique for laminating dielectric layers and conductor layers is known. For example, Japanese Patent Application Laid-Open No. 10-303618 discloses a resonator configured such that a plurality of via conductors are arranged between a pair of conductor layers in a printed wiring board so as to function as side walls for shielding electromagnetic waves. In this resonator, the region surrounded by the pair of conductor layers and the plurality of via conductors becomes the resonance region. Here, each via conductor has a circular cross section parallel to the conductor layers. Summary of the Invention

[0003] A printed wiring board according to an embodiment of the present disclosure includes a dielectric layer, a first conductor layer, a second conductor layer, and a plurality of via conductors. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductor layer is located on the first surface of the dielectric layer. The second conductor layer is located on the second surface of the dielectric layer. Each of the plurality of via conductors penetrates the dielectric layer from the first surface to the second surface, connecting the first conductor layer and the second conductor layer. The printed wiring board is surrounded by the plurality of via conductors and has a portion where the first conductor layer and the second conductor layer overlap in a planar perspective. The plurality of via conductors have a shape with an aspect ratio of more than 1 in a planar view, and include those whose major axis is along the periphery of a resonance region connecting the rows of the plurality of via conductors when the major axis is in a first direction and the minor axis is in a second direction. The printed wiring board includes a third conductor layer parallel to the first surface between the first conductor layer and the second conductor layer. Each of the plurality of via conductors has at least a portion of an end portion in the first direction in contact with the third conductor layer, and at least a portion of a central portion excluding the end portion is separated from the third conductor layer. The third conductor layer has an opening in a portion surrounded by the plurality of via conductors.

[0004] Moreover, a laminated resonator according to an embodiment of the present disclosure includes a dielectric layer, a first conductor layer, a second conductor layer, and a plurality of via conductors. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductor layer is located on the first surface of the dielectric layer. The second conductor layer is located on the second surface of the dielectric layer. Each of the plurality of via conductors penetrates the dielectric layer from the first surface to the second surface, connecting the first conductor layer and the second conductor layer. The laminated resonator is surrounded by the plurality of via conductors and has a portion where the first conductor layer and the second conductor layer overlap in a planar perspective. The plurality of via conductors have a shape with an aspect ratio of more than 1 in a planar view, and include those with a major axis along the periphery of a resonance region connecting the rows of the plurality of via conductors when the major axis is in a first direction and the minor axis is in a second direction. The laminated resonator includes a third conductor layer parallel to the first surface between the first conductor layer and the second conductor layer. Each of the plurality of via conductors has at least a portion of an end portion in the first direction in contact with the third conductor layer, and at least a portion of a central portion excluding the end portion is separated from the third conductor layer. The third conductor layer has an opening in a portion surrounded by the plurality of via conductors.

[0005] Moreover, the multilayer filter of the present disclosure includes the above-mentioned multilayer resonator. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a transparent perspective view of a printed wiring board according to an embodiment. [Diagram 2] FIG. 13 is a diagram showing a cross section of an elliptical via conductor. [Diagram 3] 13 is a diagram showing a cross section of an oval via conductor according to Modification 1. FIG. [Figure 4] 13 is a diagram showing a cross section of a dumbbell-shaped via conductor according to Modification 1. FIG. [Diagram 5] 13 is a diagram showing a cross section of a bowtie-type via conductor according to Modification 1. FIG. [Figure 6] FIG. 11 is a see-through perspective view of a printed wiring board according to Modification 2. [Figure 7] 13 is a plan view showing an arrangement of via conductors in a printed wiring board according to Modification 3. FIG. [Figure 8]13 is a diagram showing a cross section parallel to the first surface at the position of a third conductor layer of a printed wiring board according to Modification 3. FIG. [Figure 9] 13 is a diagram showing a cross section perpendicular to the Y direction of a printed wiring board according to Modification 3. FIG. [Figure 10] 13 is a diagram showing a cross section perpendicular to the X direction of a printed wiring board according to Modification 3. FIG. [Figure 11] 13 is a diagram showing another example of a cross section perpendicular to the X direction of the printed wiring board according to the third modification. FIG. [Figure 12] 13 is a diagram showing a cross section parallel to the first surface at the position of a third conductor layer of a printed wiring board according to Modification 4. FIG. [Figure 13A] 1A to 1C are plan views illustrating a method for manufacturing a printed wiring board. [Figure 13B] 13B is a diagram showing a cross section passing through line A1-A1 in FIG. 13A and perpendicular to the Y direction. [Figure 13C] 13B is a diagram showing a cross section passing through line B1-B1 in FIG. 13A and perpendicular to the X direction. [Figure 14A] 1A to 1C are plan views illustrating a method for manufacturing a printed wiring board. [Figure 14B] 14B is a diagram showing a cross section passing through line A2-A2 in FIG. 14A and perpendicular to the Y direction. [Figure 14C] 14B is a diagram showing a cross section passing through line B2-B2 in FIG. 14A and perpendicular to the X direction. [Figure 15A] 1A to 1C are plan views illustrating a method for manufacturing a printed wiring board. [Figure 15B] 15B is a diagram showing a cross section passing through line A3-A3 in FIG. 15A and perpendicular to the Y direction. [Figure 15C] 15B is a diagram showing a cross section passing through line B3-B3 in FIG. 15A and perpendicular to the X direction. [Figure 16A] 1A to 1C are plan views illustrating a method for manufacturing a printed wiring board. [Figure 16B] 16B is a diagram showing a cross section passing through line A4-A4 in FIG. 16A and perpendicular to the Y direction. [Figure 16C] 16B is a diagram showing a cross section passing through line B4-B4 in FIG. 16A and perpendicular to the X direction. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, the embodiments will be described with reference to the drawings. However, for the sake of convenience, each of the drawings referred to below shows only the main components necessary for explaining the embodiments in a simplified form. Therefore, the printed wiring board 1 of the present disclosure may include any component not shown in each of the drawings referred to. Furthermore, the dimensions of the components in each drawing do not faithfully represent the dimensions and dimensional ratios of the actual components.

[0008] [Configuration of printed wiring board] The configuration of a printed wiring board 1 according to this embodiment will be described with reference to FIG. The printed wiring board 1 is a multilayer antenna substrate incorporating an antenna used in a millimeter wave radar, a transmission line for transmitting a signal received by the antenna, and the like. Inside the printed wiring board 1, a laminated filter 200 that passes a portion of a predetermined frequency band of a transmission signal, and a laminated resonator 100 that constitutes the laminated filter 200 are formed. In FIG. 1, the configuration of the antenna electrodes and the like other than the laminated resonator 100 and the laminated filter 200 are omitted. In the following, the orientation of each part of the printed wiring board 1 will be described using an XYZ orthogonal coordinate system in which the thickness direction of the printed wiring board 1 is the Z direction. In addition, the surface of each layer that constitutes the printed wiring board 1 facing the +Z direction will also be referred to as the "upper surface", and the surface facing the -Z direction will also be referred to as the "lower surface". The Z direction will also be referred to as the "thickness direction" of the printed wiring board 1.

[0009] The printed wiring board 1 has a dielectric layer 10, a first conductor layer 21, a second conductor layer 22, and a plurality of via conductors 30.

[0010] The dielectric layer 10 is a plate-like member made of a dielectric material. The dielectric layer 10 may be configured by stacking a plurality of dielectric materials in the Z direction. The dielectric layer 10 may be in the shape of a rectangular parallelepiped. Hereinafter, the upper surface of the dielectric layer 10 is referred to as a first surface S1, and the lower surface of the dielectric layer 10 (the surface located opposite to the first surface S1) is referred to as a second surface S2. In addition, a view from a direction perpendicular to the first surface S1 is referred to as a planar view.

[0011] The material of the dielectric layer 10 is not particularly limited as long as it has insulating properties. Examples of the material of the dielectric layer 10 include epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenol resin, polytetrafluoroethylene (PTFE) resin, silicon resin, polybutadiene resin, polyester resin, melamine resin, urea resin, polyphenylene sulfide (PPS) resin, polyphenylene oxide (PPO) resin, and the like. Two or more of these resins may be mixed. The dielectric layer 10 may also contain a reinforcing material such as glass cloth. The dielectric layer 10 may also contain an inorganic filler such as aluminum hydroxide, silica, or barium sulfate, or an organic filler such as a phenol resin or a methacrylic resin.

[0012] The first conductor layer 21 is provided on the first surface S1 of the dielectric layer 10 in an area that overlaps with at least a part of the resonance region R (predetermined region) in a planar view. Fig. 1 illustrates a configuration in which the first conductor layer 21 is provided over the entire resonance region R in a planar view. The material of the first conductor layer 21 can be, for example, copper, but is not limited thereto.

[0013] The resonance region R in FIG. 1 is a rectangular parallelepiped region. The resonance region R is a rectangle whose perimeter Ra in plan view is made up of sides parallel to the X direction and sides parallel to the Y direction. The resonance region R extends from the first surface S1 to the second surface S2 in the Z direction. In other words, the resonance region R is surrounded by a plurality of via conductors 30, and is located in a portion where the first conductor layer 21 and the second conductor layer 22 overlap in a planar perspective view. The shape of the resonance region R is not limited to that shown in FIG. 1, and may be, for example, a polygon other than a rectangle or a circle in a planar view.

[0014] The second conductor layer 22 is provided on the second surface S2 of the dielectric layer 10 in an area that overlaps at least a part of the resonance region R in a planar view. Fig. 1 illustrates a configuration in which the second conductor layer 22 is provided over the entire resonance region R in a planar view. The material of the second conductor layer 22 may be, for example, copper, but is not limited thereto.

[0015] The via conductors 30 are arranged so as to surround the resonance region R along the outer periphery Ra of the resonance region R in a plan view. Each via conductor 30 penetrates the dielectric layer 10 in the thickness direction from the first surface S1 to the second surface S2, and is electrically connected to the first conductor layer 21 and the second conductor layer 22. In other words, the via conductor 30 connects the first conductor layer 21 and the second conductor layer 22. In detail, the dielectric layer 10 is provided with an elliptical cylindrical via hole H at the formation position of the via conductor 30, and the via conductor 30 is made of a conductor formed on the inner wall of the via hole H. That is, the via conductor 30 has an elliptical cylindrical shape. Therefore, as shown in FIG. 2, each via conductor 30 has an elliptical cross section parallel to the first surface S1. The material of the via conductor 30 can be, for example, copper, but is not limited thereto. The via conductor 30 can be, for example, ground potential. The space surrounded by the via conductor 30 is filled with an insulator 33. The material of the insulator 33 can be, for example, a resin, but is not limited to this.

[0016] 2, the via conductor 30 has a length L1 in a first direction along the outer periphery Ra of the resonance region R in a cross section parallel to the first surface S1, which is longer than a length L2 in a second direction perpendicular to the outer periphery Ra. In the example of FIG. 2, since the outer periphery Ra is parallel to the X direction, the first direction is parallel to the X direction, and the second direction is parallel to the Y direction. In other words, each of the multiple via conductors 30 has a shape whose aspect ratio in a planar view exceeds 1. The multiple via conductors 30 include those whose major axis is along the outer periphery Ra that connects the rows of the multiple via conductors 30 in the resonance region R, with the major axis being the first direction and the minor axis being the second direction.

[0017] In addition, for a portion of the outer periphery Ra parallel to the Y direction, the first direction is parallel to the Y direction, and the second direction is parallel to the X direction. Therefore, in the via conductor 30 located along the portion of the outer periphery Ra parallel to the Y direction, the length L1 in the Y direction is longer than the length L2 in the X direction.

[0018] Moreover, the distance D between two adjacent via conductors 30 in the first direction is less than ½ of the signal wavelength λc corresponding to the resonant frequency of the laminated resonator 100. Here, the distance D is defined as the shortest part of the length between the side surfaces of two adjacent via conductors, as shown in FIG.

[0019] The laminated resonator 100 is configured by the dielectric layer 10, the first conductor layer 21, the second conductor layer 22, and the multiple via conductors 30 configured as above. The via conductor group consisting of the multiple via conductors 30 functions as the sidewall of the laminated resonator 100. As described above, since the distance D between the via conductors 30 in the first direction is less than 1 / 2 of the signal wavelength λc, electromagnetic waves of the resonant frequency are reflected without passing through the sidewalls of the multiple via conductors 30. Therefore, inside the resonance region R surrounded by the first conductor layer 21, the second conductor layer 22, and the multiple via conductors 30, a standing wave is generated and resonates at a vibration frequency and vibration mode determined by the capacitance component and inductance component of each of these configurations. When a transmission signal is incident from one side of the first conductor layer 21 and the second conductor layer 22, a signal of a frequency different from the resonant frequency is attenuated, and a signal of the resonant frequency can be extracted and taken out from the other side. Therefore, the laminated resonator 100 functions as a laminated filter 200 (band pass filter).

[0020] The configuration of the first conductor layer 21 and the second conductor layer 22 of the laminated resonator 100 is not limited to that shown in FIG. 1. For example, a coplanar line may be formed on the first conductor layer 21, and a signal may be transmitted through the coplanar line. The first conductor layer 21 may be used as a part of a microstrip line. That is, a dielectric material and a conductor layer may be further laminated on the upper surface of the first conductor layer 21, and a microstrip line may be formed by the laminated conductor layer and the first conductor layer 21. The first conductor layer 21 may be formed in a slot antenna shape, and a separate resonator may be further formed on the upper surface of the first conductor layer 21, and two or more resonators may be electromagnetically coupled by propagating electromagnetic waves through the slot antenna. When patterns such as various lines are formed on the first conductor layer 21 and / or the second conductor layer 22, the first conductor layer 21 and / or the second conductor layer 22 may have a portion that is not electrically connected to the via conductor 30.

[0021] As described above, the printed wiring board 1 and the laminated resonator 100 of the present embodiment have the dielectric layer 10, the first conductor layer 21, the second conductor layer 22, and a plurality of via conductors 30. The dielectric layer 10 has a first surface S1 and a second surface S2 located opposite to the first surface S1. The first conductor layer 21 is located on the first surface S1 of the dielectric layer 10. The second conductor layer 22 is located on the second surface S2 of the dielectric layer 10. Each of the plurality of via conductors 30 penetrates the dielectric layer 10 from the first surface S1 to the second surface S2, and connects the first conductor layer 21 and the second conductor layer 22. The printed wiring board 1 is surrounded by the plurality of via conductors 30, and has a resonance region R in a portion where the first conductor layer 21 and the second conductor layer 22 overlap in a planar perspective view. The multiple via conductors 30 have a shape with an aspect ratio of more than 1 when viewed in a plane, and include those whose major axis is along the outer periphery Ra that connects the arrangement of the multiple via conductors 30 in the resonance region R, with the major axis being the first direction and the minor axis being the second direction. From another perspective, the printed wiring board 1 and the laminated resonator 100 of the present embodiment have a dielectric layer 10, a first conductor layer 21, a second conductor layer 22, and a plurality of via conductors 30. The first conductor layer 21 is provided on the first surface S1 of the dielectric layer 10 in a range that overlaps with at least a part of a resonance region R as a predetermined region in a plan view from a direction perpendicular to the first surface S1. The second conductor layer 22 is provided on the second surface S2 of the dielectric layer 10 opposite to the first surface S1 in a range that overlaps with at least a part of the resonance region R in a plan view. The plurality of via conductors 30 are arranged so as to surround the resonance region R along the outer periphery Ra of the resonance region R in a plan view. Each of the plurality of via conductors 30 penetrates the dielectric layer 10 from the first surface S1 to the second surface S2. Each of the multiple via conductors 30 has a length in a first direction along the outer periphery Ra of the resonance region R in a cross section parallel to the first surface S1 that is longer than the length in a second direction perpendicular to the outer periphery Ra. This can reduce the distance D between the via conductors 30 on the sidewall formed by the multiple via conductors 30. This can improve the electromagnetic wave shielding performance on the sidewall surrounding the resonance region R. Furthermore, the via conductor 30 of this embodiment has a larger surface area than a conventional via conductor having a circular cross section (hereinafter, referred to as a round hole via conductor), and therefore has excellent heat dissipation performance and can increase the rigidity of the printed wiring board 1.

[0022] Moreover, the multilayer filter 200 has the multilayer resonator 100 configured as described above. Since the multilayer resonator 100 has a high shielding property, the multilayer filter 200 has an excellent wavelength selection performance.

[0023] Next, various modifications of the above embodiment will be described. The following modifications may be combined with each other.

[0024] [Variation 1] Printed wiring board 1 according to Modification 1 differs from the above embodiment in the cross-sectional shape of via conductors 30. The differences from the above embodiment will be described below.

[0025] The cross-sectional shape of the via conductor 30 is not limited to the elliptical shape shown in FIG. 2, but may be any shape in which the length L1 in the first direction is longer than the length L2 in the second direction.

[0026] For example, as shown in FIG. 3, the via conductor 30 may have an elliptical (racetrack) shape in a cross section parallel to the first surface S1 extending in the first direction (the X-direction in FIG. 3).

[0027] 4, the via conductor 30 may have a dumbbell-shaped cross section parallel to the first surface S1. Here, the dumbbell shape is a shape in which the ends 31 on one side and the other side in the first direction are both circular, and the central portion 32 excluding the ends 31 is strip-shaped. In other words, the dumbbell shape is a shape in which the two circular ends 31 are connected by the strip-shaped central portion 32 whose width is narrower than the diameter of the circles. In the dumbbell-shaped via conductor 30, the width (length L3) of the central portion 32 in the second direction (Y direction in FIG. 4) is narrower than the width (length L2) of the ends 31 in the second direction. Here, in the case of the racetrack-shaped via conductor 30 shown in Fig. 3, the ends are defined as the parts of the via conductor 30 whose outer periphery is curved. The center part is defined as the part sandwiched between the ends and whose outer periphery is linear.

[0028] 5, the via conductor 30 may have a bowtie-shaped cross section parallel to the first surface S1. Here, in the bowtie-shaped via conductor 30, both ends 31 on one side and the other side in the first direction are trapezoidal, and the central portion 32 excluding the ends 31 is strip-shaped. The trapezoidal shape of each end 31 is such that the width in the second direction is wider the closer it is to the end in the first direction. In the bowtie-shaped via conductor 30, the width (length L3) of the central portion 32 in the second direction (Y direction in FIG. 5) is smaller than the width (length L2) of the end 31 in the second direction.

[0029] Even when the via conductors 30 of these modified examples are used, the same effects as those of the above embodiment can be obtained.

[0030] [Modification 2] Printed wiring board 1 according to Modification 2 differs from the above embodiment in that it has third conductor layer 23. The differences from the above embodiment will be described below.

[0031] As shown in FIG. 6, the printed wiring board 1 according to the second modification has a third conductor layer 23 parallel to the first surface S1 between the first conductor layer 21 and the second conductor layer 22 inside the dielectric layer 10. The material of the third conductor layer 23 may be, for example, copper, but is not limited thereto. The third conductor layer 23 may be referred to as an inner layer conductor since it is located inside the dielectric layer 10. The first conductor layer 21 and the second conductor layer 22 may be referred to as a main conductor layer. The via conductor 30 penetrates the third conductor layer 23 and is electrically connected to the third conductor layer 23. The third conductor layer 23 may be provided in two or more layers. By providing such a third conductor layer 23, the reflection effect of the electromagnetic wave on the side wall of the laminated resonator 100 can be improved.

[0032] In the example of FIG. 6, the third conductor layer 23 has an opening in a portion surrounded by a plurality of via conductors 30. However, the shape of the third conductor layer 23 is not limited to that shown in FIG. 6. For example, the third conductor layer 23 may have a slot antenna shape. In this case, adjacent portions sandwiching the third conductor layer 23 function as resonators, and two or more resonators can be electromagnetically coupled by propagating electromagnetic waves through the openings of the third conductor layer 23. This can enhance the frequency selection effect of the multilayer filter 200.

[0033] [Modification 3] Printed wiring board 1 according to Modification 3 differs from the above embodiment in that two or more via conductors 30 are arranged adjacent to each other in the second direction. The differences from the above embodiment will be described below.

[0034] As shown in Fig. 7, in the printed wiring board 1 according to the third modification, the multiple via conductors 30 are arranged to form a double rectangle along the outer periphery Ra of the resonance region R. That is, two via conductors 30 are arranged adjacent to each other in a second direction perpendicular to the outer periphery Ra. The number of adjacent via conductors 30 is not limited to two, and three or more via conductors 30 may be arranged adjacent to each other in the second direction. In other words, the multiple via conductors 30 may be arranged to form a triple or more rectangular shape.

[0035] Moreover, the printed wiring board 1 of the third modification has four third conductor layers 23 provided between the first conductor layer 21 and the second conductor layer 22. In detail, the dielectric layer 10 has a structure in which five dielectric materials 11-15 are laminated in the Z direction (see FIG. 9), and the third conductor layers 23 are formed at the interfaces between these five dielectric materials 11-15. Each via conductor 30 penetrates these four third conductor layers 23.

[0036] Hereinafter, the connection state between each of the third conductor layers 23 and the via conductors 30 will be described with reference to Fig. 8. The end 31 of each of the via conductors 30 is in contact with the third conductor layer 23. In Fig. 8, the entire outer periphery of the end 31 is in contact with the third conductor layer 23, but this is not limited thereto, and only a part of the outer periphery of the end 31 may be in contact with the third conductor layer 23.

[0037] On the other hand, the central portion 32 of each via conductor 30 is spaced from the third conductor layer 23. In other words, the third conductor layer 23 is formed in an area excluding a predetermined distance range from the central portion 32 of the via conductor 30, and a clearance portion 23a where the third conductor layer 23 is not formed is provided between the third conductor layer 23 and the central portion 32. The clearance portion 23a is, for example, an opening provided in the third conductor layer 23. The clearance portion 23a is filled with the material of the dielectric layer 10. The clearance portion 23a may be provided between a part of the central portion 32 and the third conductor layer 23.

[0038] The positional relationship between the third conductor layer 23 and the via conductor 30 will be further described with reference to the cross-sectional views of FIG. 9 and FIG. 10. FIG. 9 shows a cross section passing through the line AA in FIG. 8 and perpendicular to the Y direction. The line AA passes through the tip of the end 31 of the via conductor 30. As shown in FIG. 9, the end 31 is in contact with each of the third conductor layers 23. In addition, in the cross section passing through the end 31, the wall surface of the via hole H in which the via conductor 30 is formed is parallel to the Z direction. In other words, the portion of the via hole H in which the end 31 is formed has the same width in the second direction at each position in the thickness direction. Here, "same" means that the difference between the width at the upper end and the width at the lower end of the via hole H is within 20 μm including processing errors.

[0039] Fig. 10 shows a cross section perpendicular to the X direction and passing through line BB in Fig. 8. Line BB crosses central portions 32 of two via conductors 30 in the width direction. As shown in Fig. 10, central portions 32 are spaced apart from each third conductor layer 23, and clearance portions 23a are provided between central portions 32 and third conductor layers 23.

[0040] Also, each via conductor 30 has a shape in which the width in the second direction (Y direction in FIG. 10) in the central portion 32 gradually decreases as the distance from the first surface S1 increases. In other words, the central portion 32 has a tapered shape in the cross section of FIG. 10. Meanwhile, the formation ranges of the multiple third conductor layers 23 are the same in a plan view. Therefore, the maximum value of the distance in the second direction between the via conductor 30 and the third conductor layer 23 gradually increases as the distance from the first surface S1 increases. In detail, when the four third conductor layers 23 are the first layer to the fourth layer in order from the side closer to the first surface S1, the distance d2 between the second layer and the via conductor 30 is longer than the distance d1 (the width of the clearance portion 23a) between the first layer and the via conductor 30. Also, the distance d3 between the third layer and the via conductor 30 is longer than the distance d2. Also, the distance d4 between the fourth layer and the via conductor 30 is longer than the distance d3. The distances d1 to d4 may be, for example, 1 / 10 or less of the signal wavelength λc corresponding to the resonant frequency.

[0041] Note that the configuration of Fig. 10 may be replaced with the configuration of Fig. 11. Each via conductor 30 of Fig. 11 has a shape in which the width in the second direction gradually decreases as the distance from the first surface S1 increases within a first distance range from the first surface S1, and gradually decreases as the distance from the second surface S2 increases within a second distance range from the second surface S2. Here, the first distance range and the second distance range can be, for example, 1 / 2 the thickness of the dielectric layer 10, but are not limited thereto. When the first distance range and the second distance range are 1 / 2 the thickness of the dielectric layer 10, the central portion 32 of the via conductor 30 has a shape in which the width is narrowest at the middle position in the thickness direction and the width increases toward the first surface S1 and the second surface S2.

[0042] Furthermore, within a first distance range from the first surface S1, the maximum value of the distance in the second direction between the via conductor 30 and the third conductor layer 23 gradually increases as the distance from the first surface S1 increases, and within a second distance range from the second surface S2, the maximum value of the distance in the second direction between the via conductor 30 and the third conductor layer 23 gradually increases as the distance from the second surface S2 increases.

[0043] In addition, the width of the central portion 32 in the second direction may be constant regardless of the distance from the first surface S1, and the formation range of the clearance portion 23a may be changed depending on the distance from the first surface S1, so that the maximum value of the distance in the second direction between the via conductor 30 and the third conductor layer 23 gradually increases as the distance from the first surface S1 increases.

[0044] As described above, printed wiring board 1 according to modification 3 has third conductor layer 23 parallel to first surface S1 between first conductor layer 21 and second conductor layer 22. The multiple via conductors 30 are arranged such that two or more via conductors 30 are adjacent to each other in the second direction. At least a portion of end portion 31 of each of the multiple via conductors 30 in the first direction is in contact with third conductor layer 23, and at least a portion of central portion 32 excluding end portion 31 is spaced apart from third conductor layer 23. When a via conductor 30 having a cross section long in a first direction is used as in this embodiment, the first conductor layer 21 remaining after the formation of the via hole H has a larger portion adjacent to the via conductor 30 in the short direction than the portion adjacent to the via conductor 30 in the long direction. Therefore, the stress in the short direction that the via conductor 30 receives from the first conductor layer 21 is larger than the stress in the long direction that the via conductor 30 receives from the first conductor layer 21, and the stress distribution becomes unbalanced. The same problem applies to the second conductor layer 22. These stresses can be caused by differences in the thermal expansion coefficients between materials, for example, when a temperature change occurs in the printed wiring board 1. In contrast, as in the present embodiment, by separating at least a part of the central portion 32 of the via conductor 30 from the third conductor layer 23 inside the dielectric layer 10, the stress in the short-side direction that the via conductor 30 receives from the third conductor layer 23 can be reduced. Therefore, the increase in the short-side stress that the via conductor 30 receives from the first conductor layer 21 and the second conductor layer 22 can be offset by reducing the short-side stress that the via conductor 30 receives from the third conductor layer 23. As a result, the stresses in the short-side direction and the longitudinal direction that the via conductor 30 receives from the first conductor layer 21, the second conductor layer 22, and the third conductor layer 23 can be balanced. Therefore, even if a temperature change occurs in the printed wiring board 1, the occurrence of warping or disconnection due to an imbalance in stress can be reduced.

[0045] In each of the multiple via conductors 30, the width in the second direction at the center portion 32 is narrower than the width in the second direction at the end portions 31 in any cross section parallel to the first surface S1. This reduces the area occupied by the via conductor 30. In addition, since it is easy to provide the clearance portion 23a in the region adjacent to the central portion 32, the stress in the short side direction that the via conductor 30 receives from the third conductor layer 23 can be more effectively reduced.

[0046] Printed wiring board 1 also has a plurality of third conductor layers 23. Each of the plurality of via conductors 30 has a shape in which the width in the second direction at central portion 32 gradually decreases with increasing distance from first surface S1. In addition, the multiple via conductors 30 and the multiple third conductor layers 23 are positioned such that the maximum value of the distance (clearance portion 23a) between the via conductors 30 and the third conductor layer 23 in a cross section parallel to the first surface S1 gradually increases as the distance from the first surface S1 increases. In the portions close to the first surface S1 and the second surface S2 of the printed wiring board 1, deformations such as warping and undulation of the printed wiring board 1 are likely to occur, and therefore the stress that the via conductors 30 experience due to these deformations is likely to be reduced. In contrast, the interior of the printed wiring board 1 is less likely to experience such deformations, and therefore the stress that the via conductors 30 experience is likely to be maintained. Therefore, by configuring the width of the central portion 32 to gradually decrease as the distance from the first surface S1 increases, the width of the clearance portion 23a can be increased inside the printed wiring board 1. As a result, the stress that the via conductors 30 experience inside the printed wiring board 1 can be reduced, and the occurrence of defects such as disconnections can be reduced.

[0047] [Modification 4] Printed wiring board 1 according to Variation 4 differs from Variation 3 in terms of the positional relationship between via conductors 30 adjacent in the second direction, etc. The differences from Variation 3 will be described below.

[0048] In FIG. 12, the via conductor 30 located on the -Y direction side in the figure is referred to as the "first via conductor 30A", and the via conductor 30 adjacent to the first via conductor in the second direction (Y direction in FIG. 12) is referred to as the "second via conductor 30B". In the printed wiring board 1 of the fourth modification, the first via conductor 30A and the second via conductor 30B are staggered in the first direction (X direction in FIG. 12). More specifically, one maximum width end 31A of the first via conductor 30A is provided in a positional relationship facing at least a part of the central portion 32 of the second via conductor 30B in the second direction. Moreover, by adopting this positional relationship, one end 31B of the second via conductor 30B faces at least a part of the central portion 32 of the first via conductor 30A in the second direction.

[0049] At least a part of a surface of the end 31A of the first via conductor 30A facing the central portion 32 of the second via conductor 30B is spaced from the third conductor layer 23. Similarly, at least a part of a surface of the end 31B of the second via conductor 30B facing the central portion 32 of the first via conductor 30A is spaced from the third conductor layer 23. In other words, the clearance portion 23a adjacent to the second via conductor 30B side of the first via conductor 30A extends from the central portion 32 to the end portion 31A. Moreover, the clearance portion 23a adjacent to the second via conductor 30B side of the first via conductor 30A extends from the central portion 32 to the end portion 31B. From another perspective, the clearance portion 23a may be adjacent to the entire portion of each via conductor 30 that faces the adjacent via conductor 30 in the second direction.

[0050] As described above, in the printed wiring board 1 according to the fourth modification, the plurality of via conductors 30 are arranged such that one end 31 of a first via conductor 30 among the plurality of via conductors 30 faces, in the second direction, at least a part of a central portion 32 of a second via conductor 30 adjacent to the first via conductor 30 in the second direction. At least a part of a surface of the end 31 of the first via conductor 30 facing the central portion 32 of the second via conductor 30 is separated from the third conductor layer 23. With such a staggered arrangement, electromagnetic waves leaking from gaps between adjacent via conductors 30 in the first direction can be shielded by adjacent via conductors 30 in the second direction. This can further improve the shielding performance. In addition, since the clearance portions 23a are adjacent to the ends 31 of the via conductors 30, the stress in the short side direction that the via conductors 30 receive from the third conductor layer 23 can be further reduced.

[0051] [Method for manufacturing printed wiring board] Next, a method for manufacturing printed wiring board 1 will be described using an example in which via conductors 30 are dumbbell-shaped.

[0052] First, as shown in Figures 13A to 13C, a laminate is produced having a dielectric layer 10 in which five layers of dielectric materials 11 to 15 are stacked, a first conductor layer 21, a second conductor layer 22, and four third conductor layers 23.

[0053] Specifically, plate-shaped dielectric materials 11, 13, and 15 (copper-clad laminates) having copper foil formed on both sides are prepared. The copper foil on the upper surface of the dielectric material 11 becomes the first conductor layer 21, and the copper foil on the lower surface becomes the third conductor layer 23 of the first layer. The copper foil on the upper surface of the dielectric material 13 becomes the third conductor layer 23 of the second layer, and the copper foil on the lower surface becomes the third conductor layer 23 of the third layer. The copper foil on the upper surface of the dielectric material 15 becomes the third conductor layer 23 of the fourth layer, and the copper foil on the lower surface becomes the second conductor layer 22. The copper foil that becomes each of the third conductor layers 23 is patterned to form openings that become the clearance portions 23a in advance. The patterning is performed, for example, by photolithography. Then, the dielectric material 11 and the dielectric material 13 are laminated via a prepreg that becomes the dielectric material 12, and the dielectric material 13 and the dielectric material 15 are laminated via a prepreg that becomes the dielectric material 14. Here, the prepreg is a member that is semi-cured by impregnating a resin into a glass cloth. By heating the structure in this state and applying pressure in the Z direction, the resin impregnated in the prepreg melts and then hardens, becoming hardened dielectric materials 12 and 14, and the laminate shown in Figures 13A to 13C is obtained.

[0054] 14A to 14C, through holes 30a are formed by drilling at positions corresponding to ends 31 of via conductors 30. Here, through holes 30a are formed whose wall surfaces are parallel to the Z direction.

[0055] Next, as shown in FIG. 15A to FIG. 15C, a position between adjacent through holes 30a, that is, a position corresponding to the central portion 32 of the via conductor 30, is drilled a plurality of times. As a result, adjacent through holes 30a are connected to each other to form a via hole H. More specifically, a through hole having a smaller diameter than the through hole 30a is provided at each of the positions shown by the dashed circle in FIG. 15A, thereby connecting the through holes 30a to each other. Also, the dashed circle in FIG. 15A is narrower than the width of the opening (clearance portion 23a) provided in the third conductor layer 23. Therefore, as shown in FIG. 15C, the wall surface of the portion corresponding to the central portion 32 of the via hole H is separated from the third conductor layer 23, and the clearance portion 23a is formed. Also, here, the processing is performed using a drill having a reamer shape. 15C, the width of the portion of the via hole H corresponding to the central portion 32 in the second direction (Y direction in FIG. 15C) can be gradually decreased as the distance from the first surface S1 increases. As a result, the width of the clearance portion 23a in the second direction can be gradually increased as the distance from the first surface S1 increases. In addition, when forming the via hole H having a shape that is narrowest in the middle in the thickness direction as shown in FIG. 11, it is sufficient to perform processing using a drill having a reamer shape from each of the upper and lower surfaces of the laminate.

[0056] 16A to 16C, the laminate is then plated to form via conductors 30 on the wall surfaces of the via holes H. Thereafter, an insulator 33 (e.g., resin) is filled into the space surrounded by the via conductors 30. Through the above steps, printed wiring board 1 is completed.

[0057] When using conventional round-hole via conductors, the diameter of the via conductor needs to be reduced to reduce the area occupied by the via conductor, but this reduction in diameter increases the aspect ratio of the length in the Z direction to the diameter of the round-hole via conductor. As a result, it becomes difficult for the plating solution to circulate, and there is a problem that a plating layer cannot be properly formed on the inner wall of the via hole. In contrast, by making the length of the cross section of the via conductor 30 in the first direction larger than the length in the second direction as in this embodiment, even if the length in the short direction is the same as the diameter of the round hole via conductor, the aspect ratio in the long direction is smaller than that of the round hole via conductor. This makes it easier to supply a plating solution to the via hole H, and a plating layer (via conductor 30) of the desired thickness can be formed. This makes it difficult for defects such as breaks to occur. The multilayer filter 200 and printed wiring board 1 incorporating the multilayer resonator 100, which is thus less prone to defects, have excellent durability.

[0058] The specific details of the configuration, structure, positional relationship, shape, etc. shown in the above embodiment can be changed as appropriate without departing from the spirit of the present disclosure. Furthermore, the configurations, structures, positional relationships, and shapes shown in the above embodiment can be combined as appropriate without departing from the spirit of the present disclosure. [Industrial Applicability]

[0059] The present disclosure can be utilized in printed wiring boards, laminated resonators, and laminated filters. [Explanation of symbols]

[0060] 1 Printed wiring board 10 Dielectric layer 11~15 Dielectric materials 21 First conductor layer 22 Second conductor layer 23 Third conductor layer 23a Clearance section 30 Via conductor 30A 1st via conductor 30B Second via conductor 30a through hole 31, 31A, 31B ends 311 Protrusion 32 Central part 33 Insulators 100 stacked resonator 200 Multilayer Filter H via hole R resonance area (predetermined area) Ra Peripheral S1 Page 1 S2 Page 2

Claims

1. a dielectric layer, a first conductor layer, a second conductor layer, and a plurality of via conductors; the dielectric layer has a first surface and a second surface opposite the first surface; the first conductor layer is located on the first surface of the dielectric layer; the second conductor layer is located on the second surface of the dielectric layer; each of the plurality of via conductors penetrates the dielectric layer from the first surface to the second surface and connects the first conductor layer and the second conductor layer; a portion surrounded by the plurality of via conductors and in which the first conductor layer and the second conductor layer overlap in a planar perspective view; the plurality of via conductors have a shape with an aspect ratio of more than 1 in a plan view, and when a major axis is a first direction and a minor axis is a second direction, the major axis includes an conductor that is aligned along an outer periphery of a resonance region that connects the plurality of via conductors; a third conductor layer between the first conductor layer and the second conductor layer and parallel to the first surface; Each of the plurality of via conductors has at least a portion of an end portion in the first direction that is in contact with the third conductor layer, and at least a portion of a central portion excluding the end portion is separated from the third conductor layer, the third conductor layer has an opening in a portion surrounded by the plurality of via conductors.

2. The printed wiring board according to claim 1 , wherein the plurality of via conductors are arranged such that two or more via conductors are adjacent to each other in the second direction.

3. The printed wiring board according to claim 2 , wherein each of the plurality of via conductors has a width in the second direction at the central portion narrower than a width in the second direction at the end portions in any cross section parallel to the first surface.

4. the plurality of via conductors are arranged such that one end of a first via conductor among the plurality of via conductors faces at least a part of a central portion of a second via conductor adjacent to the first via conductor in the second direction, The printed wiring board according to claim 3 , wherein at least a portion of a surface of the end of the first via conductor that faces the central portion of the second via conductor is spaced from the third conductor layer.

5. A plurality of the third conductor layers are provided. A printed wiring board as described in any one of claims 2 to 4, wherein each of the plurality of via conductors has a shape in which the width in the second direction at the central portion gradually decreases as the distance from the first surface increases.

6. A plurality of the third conductor layers are provided. A printed wiring board as described in any one of claims 2 to 5, wherein the multiple via conductors and the multiple third conductor layers are arranged in a positional relationship such that the maximum distance between the via conductors and the third conductor layers in a cross section parallel to the first surface gradually increases as the distance from the first surface increases.

7. a dielectric layer, a first conductor layer, a second conductor layer, and a plurality of via conductors; the dielectric layer has a first surface and a second surface opposite the first surface; the first conductor layer is located on the first surface of the dielectric layer; the second conductor layer is located on the second surface of the dielectric layer; each of the plurality of via conductors penetrates the dielectric layer from the first surface to the second surface and connects the first conductor layer and the second conductor layer; a portion surrounded by the plurality of via conductors and in which the first conductor layer and the second conductor layer overlap in a planar perspective view; the plurality of via conductors have a shape with an aspect ratio of more than 1 in a plan view, and when a major axis is a first direction and a minor axis is a second direction, the major axis includes an conductor that is aligned along an outer periphery of a resonance region that connects the plurality of via conductors; a third conductor layer between the first conductor layer and the second conductor layer and parallel to the first surface; Each of the plurality of via conductors has at least a portion of an end portion in the first direction that is in contact with the third conductor layer, and at least a portion of a central portion excluding the end portion is separated from the third conductor layer, the third conductor layer has an opening in a portion surrounded by the plurality of via conductors.

8. The laminated resonator according to claim 7 , wherein the plurality of via conductors are arranged such that two or more via conductors are adjacent to each other in the second direction.

9. 9. A multilayer filter comprising the multilayer resonator according to claim 7.

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