Ceramic Electronic Components

Abstract

To provide a ceramic electronic component that can be improved in reliability.SOLUTION: With TSDC for a dielectric layer under conditions of a polarization temperature of 150°C, a polarization electric field of 15-20 V / μm, a polarization time of 60 min., and a temperature raising rate of 10°C / min., IA / IB>0.30 holds for a low temperature-side peak current value IA of ≥160°C and <230°C and a high temperature-side peak current value IB of 230-350°C, and IB is 100 pA / mm2 or less.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a ceramic electronic component. [Background technology]

[0002] In ceramic electronic components such as multilayer ceramic capacitors, the insulation deterioration mechanism occurs when oxygen defects in the dielectric layer are deposited on the cathode by an electric field, lowering the electrical resistance at the interface between the cathode and the dielectric layer, and it has been reported that the time until this deposition determines the lifespan (for example, see Non-Patent Document 1).

[0003] It is known that reliability, such as life span and withstand voltage, can be improved by reducing the amount of oxygen defects according to this model (see, for example, Patent Documents 1 and 2). In Patent Documents 1 and 2, thermally stimulated depolarization current (TSDC) is used to quantify the concentration of oxygen defects. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2004-356305 A [Patent Document 2] JP 2014-165447 A [Non-patent literature]

[0005] [Non-Patent Document 1] "dc-Electrical Degradation of the BT-Based Material for Multilayer Ceramic Capacitor with Ni internal Electrode: Impedance Analysis and Microstructure", Jpn J Appl Phys, 40(2001) pp.5624-5629 Summary of the Invention [Problem to be solved by the invention]

[0006] In Patent Documents 1 and 2, the amount of oxygen defects is estimated from the integral value of the current of the TSDC data. However, in the TSDC data, the part that has a large effect on the lifespan of ceramic electronic components is the part that corresponds to the oxygen defects that cross the crystal grain boundaries of the dielectric layer and move to the cathode. Patent Documents 1 and 2 do not disclose this.

[0007] The present invention has been made in consideration of the above-mentioned problems, and an object of the present invention is to provide a ceramic electronic component that can improve reliability. [Means for solving the problem]

[0008] The ceramic electronic component according to the present invention has a laminated structure in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, and in TSDC for the dielectric layers, a low-temperature peak current value of I is greater than or equal to 160°C and less than 230°C, and the low-temperature peak current value is greater than or equal to I in TSDC. The low-temperature peak current value is ... A The peak current value on the high temperature side between 230℃ and 350℃ is I B In this case, I A / I B >0.30 relationship is established and I B is 100pA / mm 2 The present invention is characterized in that:

[0009] In the above ceramic electronic components, A / I B It may be ≧0.50.

[0010] In the above ceramic electronic components, A / I B It may be ≧0.70.

[0011] In the above ceramic electronic components, A / I B It may be ≧2.00.

[0012] In the above ceramic electronic component, B is 95pA / mm 2 It may be the following.

[0013] In the above ceramic electronic component, B is 90pA / mm 2 It may be the following.

[0014] In the above ceramic electronic component, B is 80pA / mm 2 It may be the following.

[0015] Another ceramic electronic component according to the present invention has a laminated structure in which dielectric layers mainly composed of ceramic and internal electrode layers are alternately laminated, and the dielectric layers are polarized with a polarization time of 60 min, a polarization electric field of 10 V / μm, and a polarization temperature changed in the range of 150° C. to 210° C., and then cooled to 130° C. and a heating rate of 10° C. / min. In TSDC, the peak current value of the peak occurring at the lowest temperature side among the peak currents when heated to 350° C. is defined as J150 when the peak current value when polarized at 150° C. is set to J150, and the peak current value when polarized at 170° C. is set to J170, where J170 is the peak current value when polarized at 170° C., and a relationship of (J170-J150) / J150≧0 is established.

[0016] In the ceramic electronic component, the dielectric layer may have an average thickness of 1 μm or more.

[0017] In the ceramic electronic component, the dielectric layer may have an average thickness of 3.5 μm or more.

[0018] In the ceramic electronic component, the average number of crystal grains in the thickness direction of the dielectric layer may be 3 or more.

[0019] In the ceramic electronic component, the number of laminated dielectric layers may be 1000 or more.

[0020] In the above ceramic electronic component, the main component of the dielectric layer may be BaTiO3.

[0021] In the ceramic electronic component, there may be two or more TSDC peaks occurring in the temperature range of 130° C. or higher and 350° C. or lower.

[0022] In the ceramic electronic component, the number of TSDC peaks occurring in the temperature range of 130° C. or higher and 350° C. or lower may be three or more. Effect of the Invention

[0023] According to the present invention, it is possible to provide a ceramic electronic component that can improve reliability. [Brief description of the drawings]

[0024] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Diagram 2] 1(a) to 1(e) are diagrams illustrating a procedure for estimating the amount of oxygen defect migration using TSDC. [Diagram 3] FIG. 2A is a diagram illustrating the movement of oxygen defects, and FIG. 2B is a diagram illustrating the relationship between temperature and thermally stimulated current value. [Figure 4] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Diagram 5] FIG. 13 is a diagram illustrating a relationship between temperature and a thermal stimulation current value. [Figure 6] FIG. 1 is a graph showing the results of Examples 6 to 10 and Comparative Examples 4 and 5. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, an embodiment will be described with reference to the drawings.

[0026] (First embodiment) First, an overview of the multilayer ceramic capacitor will be described. FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to the first embodiment. As illustrated in FIG. 1, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a rectangular parallelepiped shape, and external electrodes 20a, 20b provided on any two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the upper and lower faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the upper face, lower face and two side faces in the stacking direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other.

[0027] The laminated chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately laminated. The edges of the internal electrode layers 12 are alternately exposed to the end face on which the external electrode 20a of the laminated chip 10 is provided and the end face on which the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately conductive to the external electrode 20a and the external electrode 20b. As a result, the laminated ceramic capacitor 100 has a configuration in which a plurality of dielectric layers 11 are laminated via the internal electrode layers 12. In addition, in the laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layers 12 are arranged on the outermost layer in the lamination direction, and the upper and lower surfaces of the laminate are covered by the cover layer 13. The cover layer 13 is mainly composed of a ceramic material. For example, the material of the cover layer 13 is the same as that of the dielectric layers 11 and the ceramic material.

[0028] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 1.6 mm in length, 0.8 mm in width, and 0.8 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0029] The internal electrode layers 12 are mainly composed of base metals such as Ni (nickel), Cu (copper), Sn (tin), etc. The internal electrode layers 12 may be made of precious metals such as Pt (platinum), Pd (palladium), Ag (silver), Au (gold), etc., or alloys containing these metals.

[0030] The dielectric layer 11 is mainly composed of a ceramic material having a perovskite structure represented by the general formula ABO3 as a main phase. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1) can be used. The dielectric layer 11 is obtained by firing a ceramic raw material powder containing as a main component a ceramic material having a perovskite structure, for example.

[0031] In such a multilayer ceramic capacitor 100, the insulation deterioration mechanism occurs when oxygen defects in the dielectric layer 11 are deposited on the interface between the internal electrode layer 12, which acts as a cathode, and the dielectric layer 11 by an electric field, lowering the electrical resistance at the interface, and the time until this deposition determines the lifespan, which has been reported and widely accepted. It is known that reliability such as lifespan and withstand voltage can be improved by reducing the amount of oxygen defects according to this model. For example, the amount of oxygen defect migration can be estimated by thermally stimulated depolarization current (TSDC).

[0032] For example, Figures 2(a) to 2(e) are diagrams illustrating a procedure for estimating the amount of oxygen defect migration using TSDC. Figure 2(a) is a cross-sectional view illustrating a dielectric layer 11 sandwiched between an internal electrode layer 12 connected to one external electrode and an internal electrode layer 12 connected to the other external electrode. As illustrated in Figure 2(a), oxygen defects 14 exist in the dielectric layer 11, and are distributed, for example, approximately uniformly in the dielectric layer 11.

[0033] FIG. 2(b) partially illustrates the multilayer ceramic capacitor 100 when it is placed at a heated predetermined temperature and a DC voltage is applied between two adjacent internal electrode layers 12. When the unloaded multilayer ceramic capacitor 100 is heated and a DC voltage is applied between two adjacent internal electrode layers 12, the oxygen defects 14 distributed in the dielectric layer 11 become unevenly distributed on one electrode side (here, the negative electrode side). In this case, the temperature is, for example, 200° C. The electric field strength applied to the dielectric layer 11 is, for example, 10 V / μm.

[0034] 2(c) shows the state when the multilayer ceramic capacitor 100 that was in the high-temperature load state is returned to an unloaded state at room temperature (25° C.) Even after the temperature is returned to room temperature (25° C.) and the voltage is released, the oxygen defects 14 remain unevenly distributed in one of the internal electrode layers 12 (negative electrode side).

[0035] From this state, as shown in FIG. 2(d), an ammeter is attached to the multilayer ceramic capacitor 100 and the multilayer ceramic capacitor 100 is heated again. The oxygen defects 14 that were unevenly distributed on one of the internal electrode layers 12 (here, the negative electrode side) in the dielectric layer 11 gradually move to the opposing internal electrode layer 12 side. These oxygen defects 14 act as carriers and a current flows. This current is called a thermally stimulated current. The heating temperature is about 300°C. The thermally stimulated current continues to occur until the polarization caused by the oxygen defects 14 is released, as shown in FIG. 2(e), and the time integral value of the current value until the polarization is released is the total amount of charge Q of the carriers in the dielectric layer 11.

[0036] The charge Q obtained by the above measurement was calculated as the charge per oxygen vacancy 14 (2 × 1.6 × 10 -19 Coulomb: V0 as a negative fixed charge +2 Since the absolute value is twice the elementary charge, the concentration of oxygen defects in the multilayer ceramic capacitor 100 is calculated by dividing the current density by the volume of the dielectric layer 11. In this way, the amount of oxygen defects can be estimated from the integral of the current value.

[0037] Here, the movement of oxygen defects when a thermally stimulated current is generated will be described. FIG. 3(a) is a diagram illustrating the movement of oxygen defects. As illustrated in FIG. 3(a), the dielectric layer 11 includes a plurality of crystal grains 15. A crystal grain boundary 16 is formed between two crystal grains 15. As illustrated in the upper part of FIG. 3(a), the oxygen defects 14 move within the crystal grains 15. Also, as illustrated in the middle part of FIG. 3(a), the oxygen defects 14 move across the crystal grain boundaries 16. It is the oxygen defects 14 that move across the crystal grain boundaries 16 in the dielectric layer 11 that have a large effect on the life of the multilayer ceramic capacitor 100.

[0038] FIG. 3(b) illustrates the relationship between the temperature and the thermally stimulated current value when the temperature is raised to about 350° C. in TSDC with a polarization temperature of 150° C., a polarization electric field of 15 V / μm to 20 V / μm, a polarization time of 60 min, and a heating rate of 10° C. / min. As illustrated in FIG. 3(b), multiple peaks appear in the TSDC data. Roughly speaking, two typical main peaks appear at 160° C. or higher. These peaks are a low-temperature peak (peak A) between 160° C. and less than 230° C., and a high-temperature peak (peak B) between 230° C. and 350° C. In the procedure of FIG. 2(a) to FIG. 2(e), the amount of oxygen defects is estimated from the integral value of these current peaks. Here, the polarization temperature refers to the temperature at which the dielectric layer 11 is polarized. The polarization electric field refers to the strength of the electric field that polarizes the dielectric layer 11. The polarization time refers to the time for polarizing the dielectric layer 11. Moreover, the peak refers to the maximum value (the upwardly convex inflection point) when the current value is represented on a graph.

[0039] 3(b), the difference between the solid line and the dotted line appears due to oxygen defects in the dielectric layer 11. In both the solid line and the dotted line, a low-temperature peak (Peak A) of 160° C. or more and less than 230° C. and a high-temperature peak (Peak B) of 230° C. or more and 350° C. or less appear. In the temperature range of 130° C. or more and 350° C. or less, two or more TSDC peaks appear, and sometimes three or more TSDC peaks appear.

[0040] This integral value alone is not sufficient to link the actual reliability of the multilayer ceramic capacitor 100 with the TSDC data. As described above, it is the oxygen defects 14 that move across the grain boundaries 16 in the dielectric layers 11 that have a large effect on the reliability of the multilayer ceramic capacitor 100. The movement of these oxygen defects 14 is the current represented by peak B. In contrast, the current represented by peak A is the movement of oxygen defects within the crystal grains 15 without crossing the grain boundaries 16. The effect of peak A on the life of the multilayer ceramic capacitor is smaller than the effect of peak B. Therefore, in order to improve the reliability, it is necessary to reduce peak B.

[0041] The inventor has studied and found that the peak current value I A and the peak current value I B Ratio to (I A / I B ) is important for controlling reliability. Specifically, the inventors found that in TSDC with a polarization temperature of 150° C., a polarization electric field of 15 V / μm to 20 V / μm, a polarization time of 60 min, and a temperature rise rate of 10° C. / min, A / I B >0.30 and the peak current I B is 100pA / mm 2 It has been found that a long life can be obtained even when a relatively strong electric field is applied when the temperature is below 0.5° C. Furthermore, by using this method, the reliability of the multilayer ceramic capacitor 100 can be estimated in a short time.

[0042] In the multilayer ceramic capacitor 100 according to this embodiment, at least one of the dielectric layers 11 is I A / I B is greater than 0.30 and I B ≦100pA / mm 2 All the dielectric layers 11 included in the multilayer ceramic capacitor 100 have a structure such that A / I B is greater than 0.30 and I B ≦100pA / mm 2 It is preferable that the optical fiber has a configuration in which

[0043] For example, by adjusting parameters such as the composition, crystal grain size, and firing conditions of the dielectric layer 11, A / I B is greater than 0.30 and I B ≦100pA / mm 2 From the viewpoint of improving reliability, A / I B is preferably 0.50 or more, more preferably greater than 0.5, more preferably 0.70 or more, more preferably greater than 1.0, and more preferably 2.00 or more. B is 95pA / mm 2 It is preferable that the value is less than 90 pA / mm 2 It is preferable that the value is less than 85 pA / mm 2 It is preferable that the value is less than 80 pA / mm 2 It is preferable that the value is less than 50 pA / mm 2 The unit of the current value is A / mm 2 This indicates the current value per unit area. This value can be obtained by dividing the current value measured in the multilayer ceramic capacitor 100 by the total area of ​​the regions where the internal electrodes included in the multilayer ceramic capacitor 100 face each other with the dielectric layer sandwiched therebetween.

[0044] For example, by increasing the number of grain boundaries that cross the electric field or by thickening the grain boundaries, I A / I Bcan be increased. Also, I B The smaller the value, the higher the product reliability, which is preferable. B When the value of approaches 0, I A / I B The value of can be very large.

[0045] In addition, when the dielectric layer 11 contains a plurality of crystal grains in the thickness direction, the peaks A and B are prominent. Therefore, it is preferable that the dielectric layer 11 contains a plurality of crystal grains in the thickness direction. For example, it is preferable that the average number of crystal grains per layer of the dielectric layer 11 is 3 to 8. The average value of the crystal grains per layer of such a dielectric layer 11 can be obtained by observing a cut surface parallel to the stacking direction with an electron microscope, determining the number of crystal grains intersected by an arbitrary straight line drawn parallel to the stacking direction for one dielectric layer, and performing this for 20 arbitrarily selected points in the dielectric layer, and calculating the average value of the obtained 20 pieces of data.

[0046] The average thickness of the dielectric layer 11 is, for example, 1 μm or more and 3.5 μm or more. This is because it is preferable that a plurality of crystal grains is contained in the thickness direction of the dielectric layer 11. The average thickness of the dielectric layer 11 can be obtained by observing a cut surface parallel to the lamination direction with an electron microscope, and taking the average value of thicknesses at, for example, 20 arbitrarily selected points.

[0047] In addition, I A , I B , (I A +I B Since each value of I varies depending on the size of the multilayer ceramic capacitor 100, the electrode configuration, the dielectric layer thickness, the polarization conditions, and other conditions, it is difficult to control the life span using only these individual values. A and I B We focus on the ratio of

[0048] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0049] (Raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known so far as a method for synthesizing the main component ceramic of the dielectric layer 11, such as a solid-phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these methods can be adopted.

[0050] The obtained ceramic powder is added with a specific additive compound according to the purpose. Examples of the additive compound include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium), and Yb (ytterbium)), as well as oxides or glasses of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

[0051] For example, a compound containing an additive compound is wet-mixed with a ceramic raw material powder, and then dried and pulverized to prepare a ceramic material. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

[0052] (Lamination process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a strip-shaped dielectric green sheet, for example, 1 μm or more thick, on a substrate by, for example, a die coater method or a doctor blade method, and then dried.

[0053] Next, a metal conductive paste for forming an internal electrode containing an organic binder is printed on the surface of the dielectric green sheet by screen printing, gravure printing, or the like to arrange an internal electrode layer pattern that is alternately drawn to a pair of external electrodes with different polarities. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. For example, BaTiO3 with an average particle size of 50 nm or less may be uniformly dispersed.

[0054] Thereafter, the dielectric green sheet on which the internal electrode layer pattern is printed is punched out to a predetermined size, and the punched dielectric green sheet is laminated by a predetermined number of layers (for example, 100 to 1000 layers) with the base material peeled off so that the internal electrode layers 12 and the dielectric layers 11 are alternately arranged, and the edges of the internal electrode layers 12 are alternately exposed at both end faces in the length direction of the dielectric layers 11 and alternately drawn out to a pair of external electrodes 20a, 20b with different polarities. Cover sheets for forming the cover layer 13 are pressure-bonded to the top and bottom of the laminated dielectric green sheets, and the laminated dielectric green sheets are cut to a predetermined chip size (for example, 1.0 mm x 0.5 mm).

[0055] The obtained ceramic laminate is debindered in an N2 atmosphere, and then a metal paste that contains a metal filler including the main component metal of the external electrodes 20a, 20b, a co-material, a binder, a solvent, etc. and that serves as a base layer for the external electrodes 20a, 20b is applied to both end faces and each side face of the ceramic laminate, and then dried.

[0056] (Firing process) The molded body thus obtained was subjected to binder removal treatment in a N2 atmosphere at 250 to 500°C, and then subjected to a 10-8 ~10 -13 The particles of the molded body are sintered by firing in a reducing atmosphere of 1 atm at 1100 to 1300° C. for 10 minutes to 2 hours, thus obtaining a ceramic laminate.

[0057] (Reoxidation treatment process) Then, reoxidation is performed at 600°C to 1000°C in an N2 gas atmosphere. For example, reoxidation is performed at 950°C for 1 hour. Thereafter, the N2 gas atmosphere is cooled to 500°C, the atmosphere is switched to air, and the temperature is maintained at 500°C for 24 hours, and then the temperature is cooled to room temperature. By performing such a process, the oxygen concentration of the grain boundaries 16 of the dielectric layer 11 can be increased. This can significantly reduce the peak current value of TSDC, and can suppress the migration of oxygen defects 14 beyond or along the grain boundaries 16. As a result, I A For I B In addition, by holding the capacitor at 500°C for a long period of time, it is possible to sufficiently re-oxidize large multilayer ceramic capacitors with more than 1,000 layers, such as 4532 size (length 4.5 mm, width 3.2 mm, height 2.5 mm).

[0058] (Plating process) Thereafter, the underlayers of the external electrodes 20a, 20b are coated with a metal such as Cu, Ni, Sn, etc. by plating. Through the above steps, the multilayer ceramic capacitor 100 is completed.

[0059] According to the manufacturing method of this embodiment, at least one of the plurality of dielectric layers 11 is made of I A / I B is greater than 0.30 and I B ≦100pA / mm 2 As a result, even when a relatively high electric field is applied, a long life is obtained and reliability is improved.

[0060] Second embodiment Next, a description will be given of a second embodiment. In the second embodiment, the TSDC conditions are changed in the multilayer ceramic capacitor 100 described with reference to FIG.

[0061] The present inventors have conducted extensive research and found that in a TSDC in which the dielectric layer 11 is polarized for a polarization time of 60 minutes, the polarization electric field is 10 V / μm, and the polarization temperature is changed in the range of 150°C to 210°C, and then cooled to 130°C and then heated at a rate of 10°C / min, the peak current value of the peak generated at the lowest temperature side (near 150°C) when the temperature is raised to about 350°C does not show a decreasing tendency with increasing polarization temperature, and therefore a long life can be obtained.

[0062] The peak that appears on the lowest temperature side (near 150°C) is thought to be a peak derived from defect dipoles (clusters of oxygen defects and cation defects, metal defects, etc.). The fact that this peak does not tend to decrease as the polarization temperature increases can be interpreted as meaning that this cluster does not dissociate and oxygen defects are less likely to migrate. This is thought to suppress the increase in the peak that appears on the high temperature side, which is thought to have a significant impact on the reliability of multilayer ceramic capacitors.

[0063] Specifically, if the peak current value of the TSDC peak occurring near 150° C. when polarization is performed at a polarization temperature of 150° C. is J150, and the peak current value of the TSDC peak occurring near 150° C. when polarization is performed at a polarization temperature of 170° C. is J170, then a long life can be obtained by satisfying the relationship ΔJ=(J170-J150) / J150≧0. Note that while normal TSDC requires a temperature rise to 350° C. or higher, in this embodiment, it is sufficient to raise the temperature to about 350° C., so that the reliability of the multilayer ceramic capacitor 100 can be evaluated easily.

[0064] FIG. 5 is a diagram illustrating J170 and J150. In FIG. 5, the solid line represents TSDC when polarized at 170° C., and the dotted line represents TSDC when polarized at 150° C. As illustrated in FIG. 5, both J170 and J150 have peaks near 150° C. Furthermore, J170 is larger than J150. The temperatures at which J170 and J150 peaks are observed are, for example, within a range of 130° C. to 160° C.

[0065] In the multilayer ceramic capacitor 100 according to this embodiment, at least one of the multiple dielectric layers 11 has a configuration in which the relationship ΔJ=(J170-J150) / J150≧0 is satisfied. It is preferable that all of the dielectric layers 11 included in the multilayer ceramic capacitor 100 have a configuration in which the relationship ΔJ=(J170-J150) / J150≧0 is satisfied.

[0066] For example, by adjusting parameters such as the composition, crystal grain size, and firing conditions of the dielectric layer 11, the relationship ΔJ=(J170-J150) / J150≧0 is established. From the viewpoint of improving reliability, it is preferable that the relationship ΔJ=(J170-J150) / J150≧0.5 is established, and it is more preferable that the relationship ΔJ=(J170-J150) / J150≧1.0 is established.

[0067] For example, ΔJ=(J170-J150) / J150 can be increased by increasing the number of grain boundaries that cross the electric field or by thickening the grain boundaries. However, if ΔJ=(J170-J150) / J150 is made too large, the capacitance of the product may decrease. Therefore, from the viewpoint of ensuring capacitance and high reliability, it is preferable to set an upper limit on ΔJ=(J170-J150) / J150. For example, ΔJ=(J170-J150) / J150 is preferably 2.0 or less, more preferably 1.5 or less, and even more preferably 1.25 or less.

[0068] In the above TSDC, regardless of whether the polarization temperature is 150°C to 210°C, it is preferable that, in the TSDC in which the temperature is increased at a rate of 10°C / min after cooling to 130°C, among the peak currents generated when the temperature is increased to about 350°C, the peak current value generated at the lowest temperature side (near 150°C) does not show a decreasing tendency with increasing polarization temperature.

[0069] The multilayer ceramic capacitor 100 according to this embodiment can be manufactured by the same manufacturing method as that of the first embodiment. According to this manufacturing method, at least one of the dielectric layers 11 satisfies the relationship ΔJ=(J170-J150) / J150≧0. As a result, even when used in a relatively high temperature environment, a long life is obtained and reliability is improved.

[0070] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may be used. EXAMPLES

[0071] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0072] Example 1 Barium titanate powder was prepared as the dielectric material. Necessary additives were added to the barium titanate powder, and the dielectric material was obtained by thoroughly wet mixing and grinding in a ball mill. An organic binder and solvent were added to the dielectric material, and a dielectric green sheet was produced using the doctor blade method. Polyvinyl butyral (PVB) and the like were used as the organic binder, and ethanol, toluene, and the like were added as the solvent. Plasticizers and other additives were also added.

[0073] Next, a metal conductive paste for forming the internal electrodes, which contains the main component metal of the internal electrode layer 12, a common material, a binder (ethyl cellulose), a solvent, and other auxiliary agents as required, was prepared using a planetary ball mill.

[0074] A metal conductive paste for forming internal electrodes was screen-printed on the dielectric green sheet. 301 sheets of the sheet members with the metal conductive paste printed on the dielectric green sheet were stacked on top and bottom of the sheet members, and cover sheets were laminated on the top and bottom of the sheet members. After that, a laminate was obtained by thermocompression bonding and cut into a specified shape.

[0075] After removing the binder from the obtained laminate in a N2 atmosphere, a metal conductive paste containing a metal filler mainly composed of Ni, co-materials, binder, solvent, etc. was applied to both end faces and each side of the laminate for the base layer, and then dried. The metal conductive paste for the base layer was then fired simultaneously with the laminate in a reducing atmosphere at 1100°C to 1300°C for 10 minutes to 2 hours to obtain a sintered body. The shape dimensions of the obtained sintered body were 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height.

[0076] Then, a reoxidation treatment was performed. First, the product was held at 950°C for 1 hour in an N2 gas atmosphere. Then, the product was cooled to 500°C in the N2 gas atmosphere, the atmosphere was switched to air, and the product was held at 500°C for 24 hours, and then cooled to room temperature. Then, a plating treatment was performed to form a Cu plating layer, a Ni plating layer, and a Sn plating layer on the surface of the underlayer, thereby obtaining a multilayer ceramic capacitor 100. The thickness of the dielectric green sheet was adjusted so that the average thickness of the dielectric layer 11 confirmed from the cross section of the product was 1.2 μm.

[0077] Example 2 In Example 2, compared to Example 1, the temperature holding condition after switching the atmosphere to air was changed to 500° C. for 20 hours. The other conditions were the same as in Example 1.

[0078] Example 3 In Example 3, compared to Example 1, the temperature holding condition after switching the atmosphere to air was changed to 500° C. for 30 hours. The other conditions were the same as in Example 1.

[0079] Example 4 In Example 4, compared to Example 1, the number of laminated layers of the dielectric layers 11 was changed to 1100, and the average thickness of the dielectric layers 11 confirmed from the cross section of the product was changed to 0.7 μm. The other conditions were the same as those of Example 1.

[0080] Example 5 In Example 5, compared to Example 1, the number of laminated dielectric layers 11 was changed to 100, and the average thickness of the dielectric layers 11 confirmed from the cross section of the product was changed to 3.6 μm. The other conditions were the same as in Example 1.

[0081] Comparative Example 1 In Comparative Example 1, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an N2 gas atmosphere, then cooled to 500°C in the N2 gas atmosphere, and then cooled to room temperature by switching the atmosphere to air. In other words, the sample was not held at 500°C. The other conditions were the same as those in Example 1.

[0082] Comparative Example 2 In Comparative Example 2, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an N2 gas atmosphere, cooled to 500°C while still in the N2 gas atmosphere, switched to air, held at 500°C for 5 hours, and then cooled to room temperature. That is, the holding time at 500°C was shorter than in Example 1. The other conditions were the same as in Example 1.

[0083] Comparative Example 3 In Comparative Example 3, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an N2 gas atmosphere, cooled to 500°C while still in the N2 gas atmosphere, switched to air, held at 500°C for 15 hours, and then cooled to room temperature. That is, the holding time at 500°C was shorter than in Example 1. The other conditions were the same as in Example 1.

[0084] (Analysis 1) For Examples 1 to 5 and Comparative Examples 1 to 3, the polarization temperature was 150° C., the polarization time was 60 min, the polarization electric field was 20 V / μm, and the heating rate was 10° C. / min. In TSDC, A / I BIn addition, a high temperature and high electric field accelerated life test (HALT) was performed at 150°C and 40V / μm. The results are shown in Table 1. For the MTTF (Mean Time To Failure), the time until conduction was measured for 20 pieces each of Examples 1 to 5 and Comparative Examples 1 to 3, and the average of the obtained life times was taken as the MTTF. [Table 1]

[0085] In addition, in Examples 1 to 5 and Comparative Examples 1 to 3, the average number of crystal grains in the thickness direction of the dielectric layer was 3 to 10.

[0086] As shown in Table 1, in Example 1, I A / I B is 0.35, and I B is 90pA / mm 2 In Example 2, I A / I B is 0.70, and I B is 95pA / mm 2 In Example 3, I A / I B is 2.00, and I B is 20pA / mm 2 In Example 4, I A / I B is 0.50, and I B is 80pA / mm 2 In Example 5, I A / I B is 3.00, and I B is 20pA / mm 2 In Comparative Example 1, I A / I B is 0.15, and I B is 500pA / mm 2 In Comparative Example 2, I A / I B is 0.35, and I B is 250pA / mm 2 In Example 3, I A / I Bis 1.50, and I B is 105pA / mm 2 It was.

[0087] In Examples 1 to 5, the MTTF exceeded 2000 min, and a long life was obtained. A / I B > 0.30 and the peak current I B is 100pA / mm 2 This is believed to be because the MTTF was less than 100 min. In contrast, in Comparative Example 1, the MTTF was short at 100 min. A / I B is low at 0.15, and I B It is considered that this is because the MTTF was not able to be sufficiently reduced. In Comparative Example 2, the MTTF was short at 500 min. This is because the A / I B Although the value of I has increased to 0.35, B is 250pA / mm 2 And high, I B It is considered that this is because the MTTF was short at 2000 min in Comparative Example 3. A / I B Although the value of I has increased to 1.50, B is 105pA / mm 2 And high, I B It is believed that this is because it was not possible to make

[0088] Example 6 In Example 6, the same manufacturing method and specifications as in Example 1 were used.

[0089] Example 7 In Example 7, the same manufacturing method and specifications as in Example 2 were used.

[0090] Example 8 In Example 8, the same manufacturing method and specifications as in Example 3 were used.

[0091] Example 9 In Example 9, the same manufacturing method and specifications as in Example 4 were used.

[0092] Example 10 In Example 10, the same manufacturing method and specifications as in Example 5 were used.

[0093] Comparative Example 4 In Comparative Example 4, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an N2 gas atmosphere, then cooled to 500°C in the N2 gas atmosphere, and then cooled to room temperature by switching the atmosphere to air. In other words, the sample was not held at 500°C. The other conditions were the same as those in Example 1.

[0094] Comparative Example 5 In Comparative Example 5, in the reoxidation treatment, the sample was held at 950°C for 1 hour in an N2 gas atmosphere, cooled to 500°C while still in the N2 gas atmosphere, switched to air, held at 500°C for 10 hours, and then cooled to room temperature. That is, the holding time at 500°C was shorter than in Example 1. The other conditions were the same as in Example 1.

[0095] (Analysis 2) For Examples 6 to 10 and Comparative Examples 4 and 5, the polarization time was set to 60 min, the polarization electric field was set to 10 V / μm, and the polarization temperature was changed in the range of 150°C to 210°C. After cooling to 130°C, the temperature was increased at a rate of 10°C / min. In this manner, J150 and J170 were measured in TSDC, and ΔJ=(J170-J150) / J150 was measured. In addition, an accelerated life test (HALT) was performed at a high temperature and high electric field of 150°C and 40 V / μm. The results are shown in Table 1. For the MTTF (Mean Time To Failure), the time until conduction was measured for 20 pieces each for Examples 6 to 10 and Comparative Examples 4 and 5, and the average value of the obtained life times was taken as the MTTF.

[0096] In addition, in Examples 6 to 10 and Comparative Examples 4 and 5, the average number of crystal grains in the thickness direction of the dielectric layer was 3 to 10.

[0097] As shown in FIG. 6, in Example 6, the MTTF was 15000 min and ΔJ was 0.07. In Example 7, the MTTF was 12500 min and ΔJ was 0.04. In Example 8, the MTTF was 23000 and ΔJ was 0.18. In Example 9, the MTTF was 12000 and ΔJ was 0.02. In Example 10, the MTTF was 30000 and ΔJ was 0.3. In Comparative Example 4, the MTTF was 100 min and ΔJ was -0.2. In Comparative Example 5, the MTTF was 1200 min and ΔJ was -0.05.

[0098] In Examples 6 to 10, the MTTF exceeded 2000 min, and a long life was obtained. This is believed to be because ΔJ was equal to or greater than 0. In contrast, in Comparative Examples 4 and 5, the MTTF fell below 2000 min. This is believed to be because ΔJ was below 0.

[0099] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0100] 10 Stacked Chip 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Oxygen vacancies 15 Grains 16 Grain Boundaries 20a,20b external electrode 100 Multilayer ceramic capacitors

Claims

1. The ceramic-based dielectric layer and the internal electrode layer are alternately laminated to form a laminate structure. For the dielectric layer, in a TSDC in which the polarization temperature is 150° C., the polarization electric field is 15 V / μm to 20 V / μm, the polarization time is 60 min, and the temperature rise rate is 10° C. / min, the low-temperature peak current value is I Ａ The peak current value on the high temperature side at temperatures between 230°C and 350°C is I Ｂ In this case, I Ａ / I Ｂ > 0.30, and I Ｂ is 100 pA / mm ２ A ceramic electronic component characterized by:

2. I Ａ and I Ｂ In the Ａ / I Ｂ 2. The ceramic electronic component according to claim 1, wherein the ratio of the saturation coefficient to the surface tension coefficient is ≧0.

50.

3. I Ａ and I Ｂ In the Ａ / I Ｂ 2. The ceramic electronic component according to claim 1, wherein the ratio of the saturation coefficient to the surface tension coefficient is ≧0.

70.

4. I Ａ and I Ｂ In the Ａ / I Ｂ 2. The ceramic electronic component according to claim 1, wherein the R2 is ≧2.

00.

5. I Ｂ is 95 pA / mm ２ 2. The ceramic electronic component according to claim 1, wherein:

6. I Ｂ is 90 pA / mm ２ 2. The ceramic electronic component according to claim 1, wherein:

7. I Ｂ is 80 pA / mm ２ 2. The ceramic electronic component according to claim 1, wherein:

8. The ceramic-based dielectric layer and the internal electrode layer are alternately laminated to form a laminate structure. The dielectric layer is polarized for a polarization time of 60 min, a polarization electric field of 10 V / μm, and a polarization temperature of 150° C. or 170° C., and then cooled to 130° C. and heated at a rate of 10° C. / min. In this TSDC, the peak current value of the peak occurring at the lowest temperature side when the temperature is raised to 350° C. is defined as J150 when the peak current value is polarized at 150° C., and as J170 when the peak current value is polarized at 170° C., and the relationship (J170-J150) / J150≧0 is established.

9. 9. The ceramic electronic component according to claim 1, wherein the dielectric layer has an average thickness of 1 μm or more.

10. 10. The ceramic electronic component according to claim 1, wherein the dielectric layer has an average thickness of 3.5 μm or more.

11. 11. The ceramic electronic component according to claim 1, wherein an average number of crystal grains in a thickness direction of the dielectric layer is 3 or more.

12. 12. The ceramic electronic component according to claim 1, wherein the number of laminations of the dielectric layers is 1000 or more.

13. The main component of the dielectric layer is BaTiO ３ The ceramic electronic component according to any one of claims 1 to 12, characterized in that

14. 8. The ceramic electronic component according to claim 1, wherein there are two or more TSDC peaks occurring in a temperature range of 130° C. or higher and 350° C. or lower.

15. 8. The ceramic electronic component according to claim 1, wherein three or more TSDC peaks are generated in a temperature range of 130° C. or higher and 350° C. or lower.

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