Photodetector

Abstract

To make it possible to perform FD addition even in a state other than low conversion efficiency.SOLUTION: A first and second pixel units that perform FD addition are provided. The first pixel unit includes: a first switch transistor of which one source / drain electrode is connected to an FD; and a reset transistor that is connected between another source / drain electrode of the first switch transistor and a power supply node. The second pixel unit includes: a second switch transistor of which one source / drain electrode is connected to an FD; a third switch transistor of which one source / drain electrode is connected to another source / drain electrode of the second switch transistor; and a capacitive element that is connected between another source / drain electrode of the third switch transistor and a reference potential node. The respective other source / drain electrodes of the first switch transistor and the second switch transistor are electrically connected to each other.SELECTED DRAWING: Figure 13

Description

[Technical field]

[0001] The present disclosure relates to an imaging device and an electronic device. [Background technology]

[0002] Electronic devices such as cameras equipped with an image capture device are required to support both a still image mode in which pixel signals are read out at the full angle of view of all pixels of the image capture device, and a video mode in which pixel signals are read out at a smaller angle of view, such as HD (High Definition) / 4K.

[0003] In video mode, pixel signals are thinned out or added, but simple thinned out readout reduces spatial resolution and contrast sensitivity, so added readout, in which pixel signals are added between multiple pixels and read out, is more desirable than thinned out readout. One method of added readout is the FD addition method, in which addition is performed between floating diffusions (FD) of pixels (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2015-103958 A Summary of the Invention [Problem to be solved by the invention]

[0005] The conventional technology described in the above Patent Document 1 is configured to selectively connect the FD nodes of two pixels via a switch for switching the conversion efficiency (efficiency of converting charge into voltage). Therefore, in this conventional technology, when the switch is in a non-conducting state, the parasitic capacitance of the wiring for shorting the FD nodes of the two pixels is not added to the FD node as an unnecessary capacitance, so that the conversion efficiency does not decrease in the still image mode. However, the conventional technology has a problem in that the addition readout by FD addition can be performed only in a state of low conversion efficiency.

[0006] In view of the above, an object of the present disclosure is to provide an imaging device capable of performing addition readout using FD addition even in states other than a state of low conversion efficiency, and an electronic device having the imaging device. [Means for solving the problem]

[0007] In order to achieve the above object, the imaging device of the present disclosure comprises: The display device includes a first pixel unit and a second pixel unit, each of which has a floating diffusion that converts electric charges transferred from a light receiving unit into a voltage, and which selectively performs pixel addition to add up pixel signals by electrically connecting the floating diffusions between pixels; the first pixel unit has a first switch transistor having one source / drain electrode connected to a floating diffusion, and a reset transistor connected between the other source / drain electrode of the first switch transistor and a power supply node; the second pixel unit has a second switch transistor having one source / drain electrode connected to the floating diffusion, a third switch transistor having one source / drain electrode connected to the other source / drain electrode of the second switch transistor, and a capacitance element connected between the other source / drain electrode of the third switch transistor and a reference potential node; The other source / drain electrodes of the first switch transistor and the second switch transistor are electrically connected to each other. In order to achieve the above object, an electronic device according to the present disclosure includes an imaging device having the above configuration. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing an outline of the basic configuration of a CMOS image sensor, which is an example of an imaging device according to the present disclosure. [Diagram 2] FIG. 2 is a circuit diagram showing an example of a circuit configuration of a pixel. [Diagram 3] FIG. 3 is a block diagram showing an example of the configuration of a column-parallel analog-to-digital conversion unit mounted on a CMOS image sensor. [Figure 4] FIG. 4 is a plan view showing an outline of a flat-type chip structure. [Diagram 5] FIG. 5 is an exploded perspective view showing an outline of a stacked chip structure. [Figure 6] FIG. 6 is an explanatory diagram of an outline of addition and reading in the logic addition method. [Figure 7] FIG. 7 is an explanatory diagram for explaining an outline of addition and reading in an AD (analog-digital) addition method. [Figure 8] FIG. 8 is an explanatory diagram of an outline of addition and reading in the SF (source follower) addition method. [Figure 9] FIG. 9 is an explanatory diagram illustrating an outline of addition readout in the FD (floating diffusion) addition method. [Figure 10] FIG. 10 is a diagram for explaining a comparison of power consumption and linearity of a signal after addition among the logic addition method, the AD addition method, the SF addition method, and the FD addition method. [Figure 11] FIG. 11 is a diagram for explaining the linearity problem of the SF addition method. [Figure 12] FIG. 12 is a diagram for explaining the deterioration of the number of circuit noise electrons in terms of input in the FD addition method. [Figure 13] FIG. 13 is a circuit diagram showing a circuit configuration of a pixel circuit according to the first embodiment. [Figure 14]FIG. 14 is a timing chart for explaining the operation in the case of high conversion efficiency in a still image mode without pixel addition. [Figure 15] FIG. 15 is a timing chart for explaining the operation in the case of medium conversion efficiency in a still image mode without pixel addition. [Figure 16] FIG. 16 is a timing chart for explaining the operation in the case of low conversion efficiency in a still image mode without pixel addition. [Figure 17] FIG. 17A is a timing chart for explaining the operation in the case of additive readout at a medium conversion efficiency, and FIG. 17B is a timing chart for explaining the operation in the case of additive readout at a low conversion efficiency. [Figure 18] FIG. 18 is a plan view showing the layout of the pixel circuit according to the first embodiment. [Figure 19] FIG. 19 is a cross-sectional view taken along line XX in FIG. [Figure 20] FIG. 20 is a circuit diagram showing a circuit configuration of a pixel circuit according to the second embodiment. [Figure 21] FIG. 21 is a diagram illustrating pixel addition in a Bayer pixel array. [Figure 22] FIG. 22 is a timing chart for explaining the operation in the case of high conversion efficiency in a still image mode without pixel addition. [Figure 23] FIG. 23 is a timing chart for explaining the operation in the case of medium conversion efficiency in a still image mode without pixel addition. [Figure 24] FIG. 24 is a timing chart for explaining the operation in the case of low conversion efficiency in a still image mode without pixel addition. [Diagram 25] Figure 25A is a timing chart for explaining the operation when pixels 1 and 3 are read out together at medium conversion efficiency, and Figure 25B is a timing chart for explaining the operation when pixels 2 and 4 are read out together at medium conversion efficiency. [Figure 26]FIG. 26A is a timing chart for explaining the operation when pixels 1 and 3 are read out together at low conversion efficiency, and FIG. 26B is a timing chart for explaining the operation when pixels 2 and 4 are read out together at low conversion efficiency. [Figure 27] FIG. 27 is a plan view showing a layout of a pixel circuit according to the second embodiment. [Figure 28] FIG. 28 is a cross-sectional view taken along line YY in FIG. [Figure 29] FIG. 29 is a diagram showing an application example of the technology disclosed herein. [Diagram 30] FIG. 30 is a block diagram showing an outline of the configuration of an imaging system that is an example of an electronic device according to the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a form for carrying out the technology according to the present disclosure (hereinafter, referred to as "embodiment") will be described in detail with reference to the drawings. The technology of the present disclosure is not limited to the embodiment. In the following description, the same reference numerals will be used for the same elements or elements having the same functions, and duplicated description will be omitted. The description will be given in the following order. 1. General Description of the Imaging Device and Electronic Device of the Present Disclosure 2. Imaging device of the present disclosure 2-1.Example of CMOS image sensor configuration 2-2. Example of pixel circuit configuration 2-3.Example of analog-to-digital conversion section 2-4. Chip structure 2-4-1. Flat-laying type chip structure (so-called flat-laying structure) 2-4-2. Stacked chip structure (so-called stacked structure) 2-5.Additional reading of pixel signals 2-5-1.Logic addition method 2-5-2.AD Addition Method 2-5-3.SF Addition Method 2-5-4.FD Addition Method 2-5-5. Comparison of power consumption and linearity of each addition method 2-5-6.Linearity issues with the SF addition method 2-5-7.Deterioration of the number of circuit noise electrons converted into inputs using the FD addition method 3. Embodiments of the present disclosure 3-1. Example 1 (Example in which the first and second pixel sections each consist of a single pixel) 3-2. Example 2 (Example in which the first and second pixel sections each consist of multiple pixels and the FD is shared between the multiple pixels) 4. Variations 5. Application Examples 6. Electronic Device of the Present Disclosure (Example of Imaging Device) 7. Configurations that the present disclosure can take

[0010] <General Description of Imaging Device and Electronic Device of the Present Disclosure> In the imaging device and electronic device disclosed herein, the first pixel unit or the second pixel unit can be configured to achieve high conversion efficiency with respect to the conversion efficiency of the floating diffusion when the first switch transistor or the second switch transistor is in a non-conducting state in the absence of pixel addition.

[0011] In the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, the first pixel unit and the second pixel unit can be configured to realize high conversion efficiency with respect to the conversion efficiency of the floating diffusion when the first switch transistor and the second switch transistor are each in a non-conducting state in the absence of pixel addition. Also, the first pixel unit and the second pixel unit can be configured to realize low conversion efficiency with respect to the conversion efficiency of the floating diffusion when the first switch transistor, the second switch transistor, and the third switch transistor are all in a conducting state in the absence of pixel addition.

[0012] In addition, in the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, the first pixel unit and the second pixel unit may be configured to perform pixel addition and achieve a medium conversion efficiency with respect to the conversion efficiency of the floating diffusion when the first switch transistor and the second switch transistor are both in a conductive state.Furthermore, the first pixel unit and the second pixel unit may be configured to achieve a low conversion efficiency with respect to the conversion efficiency of the floating diffusion when the third switch transistor is in a conductive state.

[0013] In the imaging device and electronic device according to the present disclosure including the above-mentioned preferred configuration, the capacitance element may be divided and arranged in each pixel of the first pixel unit and the second pixel unit, and may be realized by a coupling capacitance between metal wirings.

[0014] In the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, the first pixel section and the second pixel section each may be configured to include a plurality of pixels, and a floating diffusion may be shared between the plurality of pixels. Also, the first pixel section and the second pixel section may be configured to perform pixel addition between pixels of the same color.

[0015] In addition, in the imaging device and electronic device of the present disclosure including the above-mentioned preferred configuration, the components of the first pixel unit and the components of the second pixel unit may be configured to have a pixel layout that ensures symmetry with respect to a center line between the first pixel unit and the second pixel unit. Also, the floating diffusions of the first pixel unit and the second pixel unit may be configured to be disposed closer to the center line between the first pixel unit and the second pixel unit than to the centers of the first pixel unit and the second pixel unit.

[0016] In the imaging device and electronic device according to the present disclosure including the above-described preferred configuration, the first pixel unit and the second pixel unit can be configured to have a back-illuminated pixel structure.

[0017] <Imaging device of the present disclosure> The basic configuration of an imaging device to which the technology according to the present disclosure is applied (i.e., the imaging device of the present disclosure) will be described. Here, a CMOS (Complementary Metal Oxide Semiconductor) image sensor, which is a type of imaging device of an XY address type, will be taken as an example of the imaging device. A CMOS image sensor is an image sensor that is manufactured by applying or partially using a CMOS process.

[0018] [Example of CMOS image sensor configuration] FIG. 1 is a block diagram showing an outline of the basic configuration of a CMOS image sensor, which is an example of an imaging device according to the present disclosure.

[0019] The CMOS image sensor 1 according to this example has a configuration including a pixel array section 11 and a peripheral circuit section of the pixel array section 11. The pixel array section 11 is configured by arranging pixels 2 including light receiving sections (photoelectric conversion sections) in row and column directions, that is, two-dimensionally in a matrix. Here, the row direction refers to the arrangement direction of the pixels 2 in a pixel row (so-called horizontal direction), and the column direction refers to the arrangement direction of the pixels 2 in a pixel column (so-called vertical direction). The pixels 2 generate and accumulate photoelectric charges according to the amount of light received by performing photoelectric conversion.

[0020] The peripheral circuit section of the pixel array section 11 is made up of, for example, a row selection section 12, a constant current source section 13, an analog-to-digital conversion section 14, a horizontal transfer scanning section 15, a signal processing section 16, and a timing control section 17.

[0021] In the pixel array section 11, pixel control lines 311 to 31 m (hereinafter, these may be collectively referred to as "pixel control lines 31") are wired in the row direction. n(hereinafter, may be collectively referred to as "vertical signal lines 32") are wired in the column direction. The pixel control lines 31 transmit drive signals for driving the pixels 2 when reading out signals. Although FIG. 1 illustrates the pixel control lines 31 as a single wire, the number of lines is not limited to one. One end of the pixel control line 31 is connected to an output terminal of the row selection section 12 corresponding to each row.

[0022] Each circuit portion of the peripheral circuit section of the pixel array section 11, that is, the row selection section 12, the constant current source section 13, the analog-to-digital conversion section 14, the horizontal transfer scanning section 15, the signal processing section 16, and the timing control section 17 will be described below.

[0023] The row selection unit 12 is composed of a shift register, an address decoder, etc., and controls scanning of pixel rows and addresses of pixel rows when selecting each pixel 2 in the pixel array unit 11. Although the specific configuration of the row selection unit 12 is not shown in the figure, it is generally configured to have two scanning systems, a read scanning system and a sweep scanning system.

[0024] The readout scanning system sequentially selects and scans the pixels 2 in the pixel array section 11 row by row to read out pixel signals from the pixels 2. The pixel signals read out from the pixels 2 are analog signals. The sweep scanning system performs sweep scanning on the readout rows to be read out scanned by the readout scanning system, prior to the readout scanning by the shutter speed.

[0025] The sweep-out scanning by this sweep-out scanning system sweeps out unnecessary charges from the photoelectric conversion units of the pixels 2 in the readout row, thereby resetting the photoelectric conversion units. Then, by sweeping out (resetting) the unnecessary charges by this sweep-out scanning system, a so-called electronic shutter operation is performed. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charges in the photoelectric conversion units and starting a new exposure (starting the accumulation of photoelectric charges).

[0026] The constant current source unit 13 supplies vertical signal lines 321 to 32 nThe vertical signal lines 321 to 32 are connected to the pixels 2 in the pixel row selected and scanned by the row selection unit 12. n A bias current is provided through each of the

[0027] The analog-digital conversion unit 14 is provided corresponding to the pixel columns of the pixel array unit 11, for example, a set of a plurality of analog-digital converters provided for each pixel column. The analog-digital conversion unit 14 is connected to vertical signal lines 321 to 32 for each pixel column. n The column-parallel analog-to-digital converter converts the analog pixel signals output through each of the columns into N-bit digital signals.

[0028] As the analog-digital converter in the column-parallel analog-digital conversion unit 14, for example, a single-slope analog-digital converter, which is an example of a reference signal comparison type analog-digital converter, can be used. However, the analog-digital converter is not limited to the single-slope analog-digital converter, and a successive approximation type analog-digital converter, a delta-sigma modulation type (ΔΣ modulation type) analog-digital converter, etc. can be used.

[0029] The horizontal transfer scanning unit 15 is composed of a shift register, an address decoder, etc., and controls the scanning of pixel columns and the addresses of pixel columns when reading out signals from each pixel 2 in the pixel array unit 11. Under the control of this horizontal transfer scanning unit 15, the pixel signals converted into digital signals by the analog-to-digital conversion unit 14 are read out to a horizontal transfer line 18 with a width of 2N bits for each pixel column.

[0030] The signal processing unit 16 performs predetermined signal processing on the digital pixel signals supplied through the horizontal transfer line 18 to generate two-dimensional image data. For example, the signal processing unit 16 corrects vertical line defects and point defects, clamps the signal, and performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing unit 16 outputs the generated image data to a downstream device as an output signal of the CMOS image sensor 1.

[0031] The timing control unit 17 generates various timing signals, clock signals, control signals, etc., and based on these generated signals, controls the driving of the row selection unit 12, the constant current source unit 13, the analog-to-digital conversion unit 14, the horizontal transfer scanning unit 15, and the signal processing unit 16, etc.

[0032] [Pixel circuit configuration example] 2 is a circuit diagram showing an example of a circuit configuration of the pixel 2. The pixel 2 has, for example, a photodiode 21 as a photoelectric conversion unit which is a light receiving unit. In addition to the photodiode 21, the pixel 2 has a pixel configuration having a transfer transistor 22, a reset transistor 23, an amplification transistor 24, and a selection transistor 25.

[0033] For example, N-channel MOS field effect transistors (FETs) are used as the four transistors, ie, the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25. By configuring the pixel 2 with only N-channel transistors, it is possible to optimize the area efficiency and the number of processes. However, the combinations of the conductivity types of the four transistors 22 to 25 illustrated here are merely examples, and are not limited to these combinations.

[0034] For these pixels 2, a plurality of control lines are wired in common to each pixel 2 in the same pixel row as the above-mentioned pixel control line 31. These control lines are connected on a pixel row basis to output terminals of the row selection unit 12 corresponding to each pixel row. The row selection unit 12 appropriately outputs a transfer signal TRG, a reset signal RST, and a selection signal SEL to the plurality of control lines.

[0035] The photodiode 21 has an anode electrode connected to a low potential power supply (for example, ground), and photoelectrically converts received light into photocharges (here, photoelectrons) with an amount of charge corresponding to the amount of light, and accumulates the photocharges. The cathode electrode of the photodiode 21 is electrically connected to the gate electrode of the amplification transistor 24 via the transfer transistor 22. Here, the region electrically connected to the gate electrode of the amplification transistor 24 is a floating diffusion (floating diffusion region / impurity diffusion region) FD. The floating diffusion FD is a charge-voltage converter that converts charge into voltage.

[0036] A high level (e.g., V DD A transfer signal TRG in which a signal level (signal level) becomes active is provided from the row selection unit 12. The transfer transistor 22 becomes conductive in response to the transfer signal TRG, and transfers the photoelectric charge that is photoelectrically converted by the photodiode 21 and accumulated in the photodiode 21 to the floating diffusion FD.

[0037] The reset transistor 23 is connected to the high-potential power supply voltage V DD A reset signal RST, which is active at a high level, is applied to the gate electrode of the reset transistor 23 from the row selection unit 12. In response to the reset signal RST, the reset transistor 23 becomes conductive and transfers the charge of the floating diffusion FD to a voltage V DD Reset the floating diffusion FD by dumping it into the node.

[0038] The gate electrode of the amplifier transistor 24 is connected to the floating diffusion FD, and the drain electrode is connected to the high-potential power supply voltage V DD The amplification transistor 24 serves as an input section of a source follower that reads out a signal obtained by photoelectric conversion in the photodiode 21. That is, the source electrode of the amplification transistor 24 is connected to a vertical signal line 32 via a selection transistor 25. The amplification transistor 24 and a current source I connected to one end of the vertical signal line 32 constitute a source follower that converts the voltage of the floating diffusion FD into the potential of the vertical signal line 32.

[0039] The selection transistor 25 has a drain electrode connected to the source electrode of the amplification transistor 24, and a source electrode connected to the vertical signal line 32. A selection signal SEL that becomes active at a high level is provided to a gate electrode of the selection transistor 25 from the row selection unit 12. The selection transistor 25 becomes conductive in response to the selection signal SEL, thereby selecting the pixel 2 and transmitting a signal output from the amplification transistor 24 to the vertical signal line 32.

[0040] The selection transistor 25 is connected to the high-potential power supply voltage V DD and the drain electrode of the amplification transistor 24. In this example, the pixel circuit of the pixel 2 is configured as a 4Tr configuration including the transfer transistor 22, the reset transistor 23, the amplification transistor 24, and the selection transistor 25, i.e., four transistors (Tr), but the present invention is not limited to this. For example, the selection transistor 25 can be omitted and the amplification transistor 24 can have the function of the selection transistor 25, resulting in a 3Tr configuration, or the number of transistors can be increased to 5Tr or more, as necessary.

[0041] [Example of analog-to-digital conversion section] Next, a configuration example of the column-parallel analog-digital conversion unit 14 will be described. FIG. 3 is a block diagram showing an example of the configuration of the column-parallel analog-digital conversion unit 14. The analog-digital conversion unit 14 in the CMOS image sensor 1 of the present disclosure includes vertical signal lines 321 to 32 n Here, the n-th column of single-slope analog-to-digital converters 140 will be described as an example.

[0042] The single-slope analog-digital converter 140 has a circuit configuration including a comparator 141, a counter circuit 142, and a latch circuit 143. The single-slope analog-digital converter 140 uses a reference signal having a so-called RAMP waveform (slope waveform) whose voltage value changes linearly over time. The reference signal having the ramp waveform is generated by a reference signal generating unit 19. The reference signal generating unit 19 can be configured using, for example, a DAC (digital-analog conversion) circuit.

[0043] Comparator 141 receives an analog pixel signal read from pixel 2 as a comparison input, receives a ramp waveform reference signal generated by reference signal generator 19 as a reference input, and compares the two signals. When the reference signal is greater than the pixel signal, comparator 141 outputs a first state (e.g., high level), for example, and when the reference signal is equal to or less than the pixel signal, comparator 141 outputs a second state (e.g., low level). As a result, comparator 141 outputs a pulse signal that corresponds to the signal level of the pixel signal, specifically, a pulse width that corresponds to the magnitude of the signal level, as a comparison result.

[0044] The counter circuit 142 receives a clock signal CLK from the timing control unit 17 at the same timing as the start timing of supplying the reference signal to the comparator 141. The counter circuit 142 performs a counting operation in synchronization with the clock signal CLK to measure the period of the pulse width of the output pulse of the comparator 141, that is, the period from the start of the comparison operation to the end of the comparison operation. The count result (count value) of the counter circuit 142 becomes a digital value obtained by digitizing the analog pixel signal.

[0045] The latch circuit 143 holds (latches) a digital value that is a count result of the counter circuit 142. The latch circuit 143 also performs CDS (Correlated Double Sampling), which is an example of noise removal processing, by calculating the difference between a count value of a D phase corresponding to a pixel signal at a signal level and a count value of a P phase corresponding to a pixel signal at a reset level. Then, under the drive of the horizontal transfer scanning unit 15, the latched digital value is output to the horizontal transfer line 18.

[0046] As described above, the column-parallel analog-digital conversion unit 14 consisting of a set of single-slope analog-digital converters 140 obtains a digital value from time information until a change in the magnitude relationship between the reference signal of a linearly changing analog value generated by the reference signal generation unit 19 and the analog pixel signal output from the pixel 2. Note that, although the above example illustrates an analog-digital conversion unit 14 in which the analog-digital converters 140 are arranged in a one-to-one relationship with respect to the pixel columns, it is also possible to configure the analog-digital conversion unit 14 in which the analog-digital converters 140 are arranged in units of multiple pixel columns.

[0047] [Chip structure] The chip (semiconductor integrated circuit) structure of the CMOS image sensor 1 having the above configuration can be exemplified by a flat-type chip structure and a stacked-type chip structure. The flat-type chip structure and the stacked-type chip structure will be specifically described below.

[0048] Flat chip structure Fig. 4 is a plan view showing an outline of a flat-type chip structure of the CMOS image sensor 1. As shown in Fig. 4, the flat-type chip structure, or the so-called flat-type structure, is a structure in which a peripheral circuit portion of a pixel array section 11 is formed on the same semiconductor substrate 41 as the pixel array section 11 in which pixels 2 are arranged in a matrix. Specifically, a row selection section 12, a constant current source section 13, an analog-digital conversion section 14, a horizontal transfer scanning section 15, a signal processing section 16, a timing control section 17, and the like are formed on the same semiconductor substrate 41 as the pixel array section 11.

[0049] -Stacked chip structure Fig. 5 is an exploded perspective view showing an outline of the stacked chip structure of the CMOS image sensor 1. As shown in Fig. 5, the stacked chip structure, or so-called stacked structure, is a structure in which at least two semiconductor substrates, a first semiconductor substrate 42 and a second semiconductor substrate (so-called logic chip) 43, are stacked. The first semiconductor substrate 42 is a so-called pixel chip, and the second semiconductor substrate 43 is a so-called logic chip.

[0050] In this laminated structure, the pixel array section 11 is formed on a first semiconductor substrate 42 in the first layer. Circuit parts such as the row selection section 12, the constant current source section 13, the analog-digital conversion section 14, the horizontal transfer scanning section 15, the signal processing section 16, and the timing control section 17 are formed on a second semiconductor substrate 43 in the second layer. The first semiconductor substrate 42 in the first layer and the second semiconductor substrate 43 in the second layer are electrically connected through connection sections 44 such as bumps, vias (VIAs), and Cu-Cu connections.

[0051] According to the CMOS image sensor 1 having this stacked structure, the first semiconductor substrate 42 only needs to be large enough (area) to form the pixel array section 11, so that the size (area) of the first semiconductor substrate 42 in the first layer and, in turn, the size of the entire chip can be reduced. Furthermore, since a process suitable for fabricating the pixels 2 can be applied to the first semiconductor substrate 42 in the first layer and a process suitable for fabricating the circuit portion can be applied to the second semiconductor substrate 43 in the second layer, there is also the advantage that the process can be optimized when manufacturing the CMOS image sensor 1. In particular, advanced processes can be applied when fabricating the circuit portion.

[0052] Although a two-layered structure formed by stacking the first semiconductor substrate 42 and the second semiconductor substrate 43 has been exemplified here, the stacked structure is not limited to a two-layered structure, and may be a three-layered or more structure. In the case of a three-layered or more stacked structure, circuit parts such as the row selection section 12, the constant current source section 13, the analog-digital conversion section 14, the horizontal transfer scanning section 15, the signal processing section 16, and the timing control section 17 may be formed in a distributed manner on the second and subsequent semiconductor substrates.

[0053] [Additive reading of pixel signals] Electronic devices such as cameras incorporating an imaging device such as the above-mentioned CMOS image sensor 1 are required to support both still image and video modes. In the still image mode, all pixels are read out. In the video mode, pixel signal thinning readout and additive readout are performed, but in terms of spatial resolution and contrast sensitivity, additive readout is more desirable than thinning readout.

[0054] The methods of adding and reading out include a logic addition method in which addition is performed downstream of the analog-digital conversion unit 14, an AD (analog-digital) addition method in which addition is performed in the analog-digital conversion unit 14, a SF (source follower) addition method in which addition is performed on the vertical signal line 32, and an FD addition method in which addition is performed between the floating diffusions FD of the pixels 2.

[0055] Below, we will explain the outline of each addition readout method, including the logic addition method, AD addition method, SF addition method, and FD addition method. Here, we will explain by taking pixel addition, which adds up pixel signals between pixel 1 and pixel 2 that are vertically adjacent in the first pixel column, as an example. Logic addition method An explanatory diagram of an outline of addition readout using the logic addition method is shown in Fig. 6. The output terminals of the vertical signal lines 321 and 322 are connected to the input terminals of analog-to-digital converters (ADCs) 1401 and 1402, respectively.

[0056] The pixel signal of pixel 1 is supplied to an analog-digital converter 1401 through a vertical signal line 321 and converted into a digital signal. The pixel signal of pixel 2 is supplied to an analog-digital converter 1402 through a vertical signal line 322 and converted into a digital signal. Then, in a logic circuit 30 subsequent to the analog-digital converters 1401 and 1402, an addition process is performed on the pixel signals of pixels 1 and 2 that have been converted into digital signals by the analog-digital converters 1401 and 1402.

[0057] AD addition method An explanatory diagram of an outline of addition readout using the AD addition method is shown in Fig. 7. The output terminals of the vertical signal lines 321 and 322 are connected to one terminal of each of the switches SW1 and SW2. Sample-and-hold capacitors SH1 and SH2 are connected between the other terminals of each of the switches SW1 and SW2 and ground. In addition, a switch SW3 is connected between the other terminals of the switches SW1 and SW2.

[0058] Then, the pixel signals of pixels 1 and 2 read out through vertical signal lines 321 and 322 are sampled and held in sample-and-hold capacitances SH1 and SH2, and then supplied to an analog-to-digital converter 1401, where they are added together and subjected to analog-to-digital conversion processing.

[0059] SF addition method FIG. 8 is a diagram for explaining an outline of the SF addition method of adding and reading. As described above, the amplifier transistor 24 of each pixel and the vertical signal line 32 (321 to 32 n ) constitutes a source follower together with a current source I connected to one end of the vertical signal line 321. The pixel signals of the pixels 1 and 2 are both read out to the same vertical signal line 321 and are added up in the source follower.

[0060] FD addition method An explanatory diagram of an outline of addition readout in the FD addition method is shown in Fig. 9. A switch transistor 26 that selectively connects the FD nodes is connected between the floating diffusions FD of pixels 1 and 2. When the switch transistor 26 is turned on, an addition process is performed between the floating diffusions FD of pixels 1 and 2 for the pixel signals of pixels 1 and 2.

[0061] Here, the power consumption of the logic addition method, the AD addition method, the SF addition method, and the FD addition method, and the linearity of the signal after addition will be described with reference to Fig. 10. The numerical values ​​shown in Fig. 10 are relative values ​​of the current consumption of the current source I connected to one end of the vertical signal line 32 and the analog-digital converter 140.

[0062] In the case of the logic addition method and the AD addition method, the pixel signals of the pixels 1 and 2 are read out through two vertical signal lines 321 and 322, and in the case of the logic addition method, the addition process is performed using two analog-to-digital converters 1401 and 1402. Therefore, the SF addition method and the FD addition method, which read out the pixel signals of the pixels 1 and 2 through one vertical signal line 321, consume less power than the logic addition method and the AD addition method.

[0063] The SF addition method has a problem with the linearity of the signal after addition. This linearity problem with the SF addition method will be explained with reference to FIG.

[0064] When the potential difference between the pixel signals V1 and V2 input to the amplification transistors 24 of the two pixels is small (area a), the signal V o However, when the potential difference between the pixel signals V1 and V2 becomes large (area b), the signal V o However, the potential of the pixel signals V1 and V2 is clipped to the higher potential side, and the signal V1 cannot ideally follow the average value of the pixel signals V1 and V2.

[0065] The FD addition method does not have the linearity problem that occurs with the SF addition method. Therefore, in terms of power consumption and linearity of the signal after addition, it can be said that the FD addition method is the most superior of the logic addition method, AD addition method, SF addition method, and FD addition method as an addition readout method.

[0066] However, when implementing FD addition, simply providing wiring L1, L2 and a switch transistor 26 that selectively connects the FD nodes (FD1-FD2) of two pixels as shown in FIG. 12 results in extra parasitic capacitance being added to the FD node. The extra parasitic capacitance added to the FD node is the parasitic capacitance c 11 ,c 12 , the coupling capacitance c between the gate electrode and the drain / source region of the switch transistor 26 21 ,c 22 , and the diffusion capacitance c of the drain / source region 31 ,c 32 etc.

[0067] In the case of the FD addition method, if an unnecessary parasitic capacitance is added to the FD node, the conversion efficiency in the still image mode in which the switch transistor 26 is in a non-conductive state and pixel addition is not performed decreases compared to the case in which the switch transistor 26 is in a conductive state and pixel addition is performed, and the number of input-equivalent circuit noise electrons increases. Here, "conversion efficiency" refers to the efficiency of converting charge into voltage in the floating diffusion FD. This conversion efficiency is determined by the capacitance (including parasitic capacitance) of the floating diffusion FD.

[0068] Incidentally, in the conventional technology described in Patent Document 1, the FD nodes of two pixels are selectively connected via a switch for switching the conversion efficiency, and when the switch is in a non-conducting state, the parasitic capacitance of the wiring for shorting the FD nodes of the two pixels is not added to the FD node as an unnecessary capacitance. Therefore, in this conventional technology, although the conversion efficiency does not decrease in the still image mode, pixel addition by FD addition can only be performed in a state of low conversion efficiency.

[0069] <Embodiments of the present disclosure> In an embodiment of the present disclosure, in order to enable addition readout (pixel addition) by FD addition even in a state other than a state of low conversion efficiency, a configuration is adopted in which the conversion efficiency can be switched in multiple stages in both a readout mode without pixel addition by FD addition (still image mode) and a readout mode with pixel addition (moving image mode). Specifically, the conversion efficiency in the readout mode without pixel addition can be switched between three stages: low, medium, and high. This allows the noise characteristics / maximum charge amount Q to be adjusted according to the ISO sensitivity. s This increases the degree of freedom in optimal settings. In addition, in the readout mode with pixel addition, since it is possible to achieve medium conversion efficiency in addition to low conversion efficiency, it is possible to improve noise characteristics at high ISO sensitivity settings. In this way, it is possible to achieve both the function of multi-stage switching of the floating diffusion FD conversion efficiency and the function of FD addition between pixels.

[0070] A specific example of this embodiment that enables addition readout (pixel addition) by FD addition even in states other than the state of low conversion efficiency will be described below.

[0071] [Example 1] Example 1 is a basic form of a pixel circuit according to an embodiment that performs pixel addition by FD addition, and is an example in which the first and second pixel sections each consist of a single pixel. The circuit configuration of the pixel circuit according to Example 1 is shown in FIG. 13. Here, an example will be described in which pixel addition is selectively performed between a first pixel section 20A and a second pixel section 20B that are adjacent vertically in a pixel column. In Example 1, the first pixel section 20A consists of a single pixel 1, and the second pixel section 20B consists of a single pixel 2.

[0072] Each of the pixel 1 and the pixel 2 includes a photodiode 21, which is an example of a light receiving section, a transfer transistor 22, a floating diffusion FD (FD1 / FD2), an amplification transistor 24, and a selection transistor 25.

[0073] In addition to the above circuit elements, the pixel 1 includes a first switch transistor 261, a reset transistor 23, and a capacitance element C1. One of the source / drain electrodes of the first switch transistor 261 is connected to a floating diffusion FD1. The reset transistor 23 is connected to the other source / drain electrode of the first switch transistor 261 and a power supply voltage V DD Here, the common connection node between the other source / drain electrode of the first switch transistor 261 and one source / drain electrode of the reset transistor 23 is referred to as a node FD s Let us assume that.

[0074] In addition to the above circuit elements, the pixel 2 has a second switch transistor 262, a third switch transistor 27, and a capacitance element C2. One source / drain electrode of the second switch transistor 262 is connected to a floating diffusion FD2. One source / drain electrode of the third switch transistor 27 is connected to the other source / drain electrode of the second switch transistor 262. Here, a common connection node between the other source / drain electrode of the second switch transistor 262 and one source / drain electrode of the third switch transistor 27 is referred to as a node FDs Let us assume that.

[0075] The capacitance elements C1 and C2 are arranged separately in the pixel 1 and the pixel 2. Specifically, the capacitance element C1 arranged in the pixel 1 has one end connected to the wiring L b The other end of the capacitance element C1 is connected to the other source / drain electrode of the third switch transistor 27 via the line L, and the other end is connected to the GND node which is the reference potential node. b The common connection node with node FD b The capacitance element C2 disposed in the pixel 2 has one end connected to the other source / drain electrode of the third switch transistor 27, and the other end connected to the GND node. The common connection node between the one end of the capacitance element C2 and the other source / drain electrode of the third switch transistor 27 is referred to as node FD. b Let us assume that.

[0076] In the pixel 1 and the pixel 2, a node FD is a connection node between the other source / drain electrode of the second switch transistor 261 and the other source / drain electrode of the second switch transistor 262. s Between them, wiring L s The capacitance elements C1 and C2 are electrically connected to each other by a node FD b Between them is wiring L b The two are electrically connected by

[0077] In the pixel circuit according to the first embodiment having the above configuration, the conversion efficiency in the readout mode (still image mode) without pixel addition can be switched among three levels: low, medium, and high.

[0078] Specifically, in pixel 1 / pixel 2, the first switch transistor 261 / second switch transistor 262 are turned off when the pixel signal is read out. As a result, the conversion efficiency of each of the floating diffusions FD1 and FD2 is determined by the capacitance of each of the FD1 node and the FD2 node, resulting in high conversion efficiency.

[0079] In the pixel 1 / pixel 2, when the pixel signal is read out, the first switch transistor 261 / second switch transistor 262 are both turned on. As a result, the capacitances of the FD1 node and the FD2 node are the gate capacitances of the first and second switch transistors 261 and 262, and the capacitances of the nodes FD s Wiring L connecting s As a result, the conversion efficiency of each of the floating diffusions FD1 and FD2 is medium.

[0080] In the pixel 1 / pixel 2, when the pixel signal is read out, the first switch transistor 261 / the second switch transistor 262 / the third switch transistor 27 are all turned on. As a result, the capacitances of the FD1 node and the FD2 node are the gate capacitances of the first and second switch transistors 261 and 262 and the line L s In addition to the parasitic capacitance of the capacitance elements C1 and C2, the capacitance of the node FD b Wiring L connecting b As a result, the conversion efficiency of each of the floating diffusions FD1 and FD2 becomes low.

[0081] In addition, the conversion efficiency of the readout mode with pixel addition (video mode) can be switched between two levels: low and medium.

[0082] Specifically, when the first switch transistor 261 and the second switch transistor 262 are both in a conductive state during addition and reading, the conversion efficiency is determined by the capacitances of the FD1 node and the FD2 node, the gate capacitances of the first and second switch transistors 261 and 262, and the capacitance of the wiring L s It is determined by the parasitic capacitance and has a medium conversion efficiency.

[0083] In addition, at the time of addition reading, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 are all in a conductive state, and the conversion efficiency is s The parasitic capacitance of the wiring L b This is determined by the parasitic capacitance of the MOSFET and results in low conversion efficiency.

[0084] Next, a circuit operation in a still image mode without pixel addition and in a moving image mode with pixel addition in the pixel circuit according to the first embodiment will be described.

[0085] (Still image mode without pixel binning) (1) High conversion efficiency Fig. 14 is a timing chart for explaining the operation in the case of high conversion efficiency in a still image mode without pixel addition. The timing chart in Fig. 14 shows the timing relationship between the horizontal synchronization signal XHS, the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, the third switch signal FDG, and the transfer signals TRG1 and TRG2. The same applies to each timing chart described later.

[0086] Read pixel 1 In the readout of the pixel signal of pixel 1, at time t 11 When the reset signal RST and the first switch signal FDL1 transition from low to high, the reset transistor 23 and the first switch transistor 261 become conductive. This resets the floating diffusion FD1 of the pixel 1. In this case, the level of the second switch signal FDL2 does not matter.

[0087] Next, at time t 12 After the first switch signal FDL1 transitions from a high level to a low level at time t 13At time t 14 After the transfer signal TRG1 transitions from high to low at time t 15 The reset signal RST transitions from high to low.

[0088] Read pixel 2 In the readout of the pixel signal of pixel 2, at time t 11 When the reset signal RST and the second switch signal FDL2 transition from low to high, the reset transistor 23 and the second switch transistor 262 become conductive. This resets the floating diffusion FD2 of the pixel 2. In this case, the level of the first switch signal FDL1 does not matter.

[0089] Next, at time t 12 After the second switch signal FDL2 transitions from a high level to a low level at time t 13 At time t 14 After the transfer signal TRG2 transitions from high to low at time t 15 The reset signal RST transitions from high to low.

[0090] (2) Medium conversion efficiency FIG. 15 is a timing chart for explaining the operation in the case of medium conversion efficiency in a still image mode without pixel addition.

[0091] Read pixel 1 In the readout of the pixel signal of pixel 1, at time t 21When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from low level to high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive. This causes the floating diffusion FD1 of pixel 1 and the floating diffusion FD2 of pixel 2 to be reset.

[0092] Next, at time t 22 After the reset signal RST transitions from high to low at time t 23 At time t 24 After the transfer signal TRG1 transitions from high to low at time t 25 The first switch signal FDL1 and the second switch signal FDL2 transition from high level to low level.

[0093] Read pixel 2 In the readout of the pixel signal of pixel 2, at time t 21 When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from low level to high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive. This causes the floating diffusion FD1 of pixel 1 and the floating diffusion FD2 of pixel 2 to be reset.

[0094] Next, at time t 22 After the reset signal RST transitions from high to low at time t 23 At time t 24 After the transfer signal TRG2 transitions from high to low at time t 25The first switch signal FDL1 and the second switch signal FDL2 transition from high level to low level.

[0095] (3) Low conversion efficiency FIG. 16 is a timing chart for explaining the operation in the case of low conversion efficiency in a still image mode without pixel addition.

[0096] Read pixel 1 In the readout of the pixel signal of pixel 1, at time t 31 When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from low to high, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive. As a result, the floating diffusion FD1 of pixel 1 and the floating diffusion FD2 of pixel 2 are reset, and the node FD s Capacitive elements C1 and C2 are connected to

[0097] Next, at time t 32 After the reset signal RST transitions from high to low at time t 33 At time t 34 After the transfer signal TRG1 transitions from high to low at time t 35 The first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from a high level to a low level.

[0098] Read pixel 2 In the readout of the pixel signal of pixel 2, at time t 31When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from low to high, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive. As a result, the floating diffusion FD1 of pixel 1 and the floating diffusion FD2 of pixel 2 are reset, and the node FD s Capacitive elements C1 and C2 are connected to

[0099] Next, at time t 32 After the reset signal RST transitions from high to low at time t 33 At time t 34 After the transfer signal TRG2 transitions from high to low at time t 35 The first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from a high level to a low level.

[0100] (Video mode with pixel binning) Next, a circuit operation in a moving image mode with pixel addition will be described. In the moving image mode with pixel addition, additive readout at a medium conversion efficiency and additive readout at a low conversion efficiency are performed.

[0101] Additive readout with medium conversion efficiency FIG. 17A is a timing chart for explaining the operation in the case of additive reading at a medium conversion efficiency.

[0102] time t 41When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from low level to high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive. This causes the floating diffusion FD1 of pixel 1 and the floating diffusion FD2 of pixel 2 to be reset.

[0103] Next, at time t 42 After the reset signal RST transitions from high to low at time t 43 At time t 44 After the transfer signals TRG1 and TRG2 transition from high to low, at time t 45 The first switch signal FDL1 and the second switch signal FDL2 transition from high level to low level.

[0104] Additive readout with low conversion efficiency FIG. 17B is a timing chart for explaining the operation in the case of additive reading at low conversion efficiency.

[0105] time t 41 When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from low to high, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive. As a result, the floating diffusion FD1 of pixel 1 and the floating diffusion FD2 of pixel 2 are reset, and the node FD s Capacitive elements C1 and C2 are connected to

[0106] Next, at time t 42After the reset signal RST transitions from high to low at time t 43 At time t 44 After the transfer signals TRG1 and TRG2 transition from high to low, at time t 45 The first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from a high level to a low level.

[0107] (Pixel circuit layout) A layout diagram (plan view) of the pixel circuit according to Example 1 is shown in Fig. 18, and a cross-sectional view taken along line XX in Fig. 18 is shown in Fig. 19. In Fig. 18, the gate electrodes of the transistors are shown with oblique lines for ease of understanding.

[0108] The components of pixel 1, which is the first pixel section 20A, and the components of pixel 2, which is the second pixel section 20B, are arranged in a pixel layout that ensures symmetry with respect to a center line O between pixel 1 and pixel 2. Specifically, the components of pixel 1 are arranged in the following order from the center line O: a first switch transistor 261, a floating diffusion FD1, an amplifier transistor 24, a selection transistor 25, and a reset transistor 23. The components of pixel 2 are arranged in the following order from the center line O: a second switch transistor 262, a floating diffusion FD1, an amplifier transistor 24, a selection transistor 25, and a third switch transistor 27.

[0109] In the above layout of pixel 1 and pixel 2, the floating diffusion FD1 and the floating diffusion FD2 are disposed closer to the center line O than to the center of pixel 1 and pixel 2. This results in a close arrangement between the floating diffusion FD1 and the floating diffusion FD2. According to this arrangement, each node FD of pixel 1 and pixel 2 b Wiring L s The wiring L s Since the parasitic capacitance can be reduced, the conversion efficiency during pixel addition can be increased.

[0110] The capacitance element C1 of pixel 1 and the capacitance element C2 of pixel 2, which determine the conversion efficiency, can be configured as one capacitance element common to pixel 1 and pixel 2. However, it is preferable to arrange it separately for pixel 1 and pixel 2, since this improves the symmetry of the pixel layout and ensures uniformity of the pixel characteristics.

[0111] As shown in FIG. 19, the capacitance element C1 of pixel 1 and the capacitance element C2 of pixel 2 are connected to a metal wiring M 11 and metal wiring M 12 However, this can be realized by the coupling capacitance with the metal wiring M 11 ,M 12 The present invention is not limited to the implementation of coupling capacitance between the two terminals, but may be implemented by a capacitance element using an oxide film, for example.

[0112] Incidentally, with regard to the pixel structures of the first pixel section 20A and the second pixel section 20B, when the substrate surface on which the wiring layer is arranged is regarded as the front surface (front side), the pixel structure can be a back-illuminated type that takes in light irradiated from the opposite back surface side, or a front-illuminated type that takes in light irradiated from the front surface side.

[0113] In the case of a front-illuminated pixel structure, the metal wiring M constituting the capacitance element C1 and the capacitance element C2 11 ,M 12It is important that the metal wiring M does not extend into the area of ​​the photodiodes 21 (PD1, PD2). 11 ,M 12 If the light beam extends into the area of ​​the photodiode 21, the aperture area of ​​the photodiode 21 will be reduced.

[0114] In contrast, in the case of a back-illuminated pixel structure, light is taken in from the side opposite to the side where the wiring layer is arranged, so the metal wiring M 11 ,M 12 There is no restriction on the arrangement of the metal wiring M constituting the capacitance elements C1 and C2 in the case of the back-illuminated pixel structure. 11 ,M 12 can be arranged to extend to the region of the photodiode 21, so that the capacitive elements C1 and C2 having larger capacitance values ​​can be realized.

[0115] [Example 2] Example 2 is an example in which the first and second pixel units each consist of a plurality of pixels, and the floating diffusion FD is shared between the plurality of pixels. The circuit configuration of a pixel circuit according to Example 2 is shown in Fig. 20. Here, an example is shown of a circuit configuration in which the first and second pixel units 20A and 20B each consist of two pixels, and the floating diffusion FD is shared between the photodiodes (PD) 21 of the two pixels.

[0116] In the pixel circuit according to the first embodiment without FD sharing, a set of the reset transistor 23 / the third switch transistor 27, the amplification transistor 24, the selection transistor 25, and the first switch transistor 261 / the second switch transistor 262 is exclusively assigned to each photodiode 21 (PD1 / PD2). Therefore, the aperture area of ​​the pixel is reduced.

[0117] In contrast, in the pixel circuit according to the second embodiment with FD sharing, the photodiodes (PD 11 ,PD 12 / PD 21By sharing the floating diffusion FD and subsequent circuit elements between the first pixel section 20A and the second pixel section 20B (PD1 and PD2), the aperture ratio of each pixel can be improved. The circuit elements subsequent to the floating diffusion FD are a reset transistor 23, an amplifier transistor 24, a selection transistor 25, and a first switch transistor 261 in the first pixel section 20A, and a third switch transistor 27, an amplifier transistor 24, a selection transistor 25, and a second switch transistor 262 in the second pixel section 20B.

[0118] The technology of the pixel circuit according to the embodiment 1 can also be applied to the pixel circuit according to the embodiment 2 with FD sharing. As a result, similarly to the case of the pixel circuit according to the embodiment 1, the conversion efficiency in the readout mode (still image mode) without pixel addition can be switched between three levels, low / medium / high, and in the moving image mode with pixel addition, additive readout at medium conversion efficiency and additive readout at low conversion efficiency can be performed.

[0119] Here, pixel addition in a pixel circuit according to Example 2 with FD sharing will be described. In the Bayer pixel array (color filter array) shown in Fig. 21, two vertical pixels form a pair that shares a floating diffusion FD (a pair of pixels surrounded by a dashed line in the figure). Specifically, a red pixel R and a green pixel Gb, and a green pixel Gr and a blue pixel B each form a pair that shares a floating diffusion FD.

[0120] In still image mode, the charges photoelectrically converted by the photodiode (PD) 21 of each pixel in the group are read out, but in moving image mode, pixel signals are added between two adjacent vertical pixels of the same color. Specifically, pixels R1 and R2, pixels Gb1 and Gb2, pixels Gr1 and Gr2, and pixels B1 and B2 are added.

[0121] The unit circuit for pixel addition of the same color is shown surrounded by a dashed line in FIG. 21. In correspondence with the pixel circuit in FIG. 20, the photodiode PD 11 Pixel 1 includes pixel R1 and photodiode PD12 The pixel 2 includes the pixel Gb1 and the photodiode PD 21 Pixel 3 includes pixel R2 and photodiode PD 22 Pixel 4 including these corresponds to pixel Gb2.

[0122] Next, a description will be given of circuit operations in a still image mode without pixel addition and in a moving image mode with pixel addition in the pixel circuit according to Example 2. In the pixel circuit according to Example 2, two pixels in the first pixel section 20A are pixel 1 and pixel 2, and two pixels in the second pixel section 20B are pixel 3 and pixel 4.

[0123] (Still image mode without pixel binning) (1) High conversion efficiency 22 is a timing chart for explaining the operation in the case of high conversion efficiency in a still image mode without pixel addition. The timing chart in FIG. 22 includes a horizontal synchronization signal XHS, a reset signal RST, a first switch signal FDL1, a second switch signal FDL2, a third switch signal FDG, and a transfer signal TRG 11 ,TRG 12 ,TRG 21 ,TRG 22 This also applies to the timing charts described later.

[0124] Read pixel 1 In the readout of pixel 1, at time t 51 When the reset signal RST and the first switch signal FDL1 transition from low to high, the reset transistor 23 and the first switch transistor 261 become conductive. This resets the floating diffusion FD1 shared by the pixel of the first pixel unit 20A. In this case, the level of the second switch signal FDL2 does not matter.

[0125] Next, at time t 52 After the first switch signal FDL1 transitions from a high level to a low level at time t 53 Transfer signal TRG 11When the transition from low level to high level occurs, the transfer transistor 22 of the pixel 1 becomes conductive, and the photodiode PD 11 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 11 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0126] Read pixel 2 In the readout of pixel 2, at time t 51 When the reset signal RST and the first switch signal FDL1 transition from low to high, the reset transistor 23 and the first switch transistor 261 become conductive. This resets the floating diffusion FD1 shared by the pixel of the first pixel unit 20A. In this case, the level of the second switch signal FDL2 does not matter.

[0127] Next, at time t 52 After the second switch signal FDL2 transitions from a high level to a low level at time t 53 Transfer signal TRG 12 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 12 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 12 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0128] Read pixel 3 In the readout of pixel 3, at time t 51When the reset signal RST and the second switch signal FDL1 transition from low to high, the reset transistor 23 and the second switch transistor 262 become conductive. This resets the floating diffusion FD2 shared by the pixel in the second pixel unit 20B. In this case, the level of the first switch signal FDL1 does not matter.

[0129] Next, at time t 52 After the second switch signal FDL2 transitions from a high level to a low level at time t 53 Transfer signal TRG 21 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 21 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 21 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0130] Read pixel 4 In the readout of pixel 4, at time t 51 When the reset signal RST and the second switch signal FDL1 transition from low to high, the reset transistor 23 and the second switch transistor 262 become conductive. This resets the floating diffusion FD2 shared by the pixel in the second pixel unit 20B. In this case, the level of the first switch signal FDL1 does not matter.

[0131] Next, at time t 52 After the second switch signal FDL2 transitions from a high level to a low level at time t 53 Transfer signal TRG 22 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 22 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 22After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0132] (2) Medium conversion efficiency FIG. 23 is a timing chart for explaining the operation in the case of high conversion efficiency in a still image mode without pixel addition.

[0133] Read pixel 1 In the readout of pixel 1, at time t 51 When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive, thereby resetting the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B.

[0134] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 11 When the transition from low level to high level occurs, the transfer transistor 22 of the pixel 1 becomes conductive, and the photodiode PD 11 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 11 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0135] Read pixel 2 In the readout of pixel 2, at time t 51When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive, thereby resetting the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B.

[0136] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 12 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 12 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 12 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0137] Read pixel 3 In the readout of pixel 3, at time t 51 When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive, thereby resetting the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B.

[0138] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 21 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 21The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 21 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0139] Read pixel 4 In the readout of pixel 4, at time t 51 When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive, thereby resetting the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B.

[0140] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 22 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 22 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 22 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0141] (3) Low conversion efficiency FIG. 24 is a timing chart for explaining the operation in the case of low conversion efficiency in a still image mode without pixel addition.

[0142] Read pixel 1 In the readout of pixel 1, at time t 51When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive.

[0143] This resets the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B. s 2, the capacitance element C of pixel 1 11 , the capacitance element C of pixel 2 12 , the capacitance element C of pixel 3 21 , and the capacitance element C of pixel 4 22 is connected.

[0144] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 11 When the transition from low level to high level occurs, the transfer transistor 22 of the pixel 1 becomes conductive, and the photodiode PD 11 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 11 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0145] Read pixel 2 In the readout of pixel 2, at time t 51 When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive.

[0146] This resets the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B. s 2, the capacitance element C of pixel 1 11 , the capacitance element C of pixel 2 12 , the capacitance element C of pixel 3 21 , and the capacitance element C of pixel 4 22 is connected.

[0147] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 12 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 12 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 12 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0148] Read pixel 3 In the readout of pixel 3, at time t 51 When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive.

[0149] This resets the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B. s 2, the capacitance element C of pixel 1 11 , the capacitance element C of pixel 2 12 , the capacitance element C of pixel 3 21 , and the capacitance element C of pixel 4 22is connected.

[0150] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 21 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 21 The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 21 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0151] Read pixel 4 In the readout of pixel 4, at time t 51 When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive.

[0152] This resets the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B. s 2, the capacitance element C of pixel 1 11 , the capacitance element C of pixel 2 12 , the capacitance element C of pixel 3 21 , and the capacitance element C of pixel 4 22 is connected.

[0153] Next, at time t 52 After the reset signal RST transitions from high to low at time t 53 Transfer signal TRG 22 When the level of the transfer transistor 22 of the pixel 2 changes from low to high, the transfer transistor 22 of the pixel 2 becomes conductive, and the photodiode PD 22The photoelectrically converted charge is read out at time t 54 Transfer signal TRG 22 After transition from high to low, at time t 55 The reset signal RST transitions from high to low.

[0154] As described above, in the pixel circuit of Example 2 as well, in the same manner as in the pixel circuit of Example 1, in a readout mode (still image mode) without pixel addition, the conversion efficiency of the pixel-shared floating diffusions FD1 and FD2 is switched between three levels: high, medium, and low.

[0155] (Video mode with pixel binning) Next, the circuit operation in the moving image mode with pixel addition will be described. In the moving image mode with pixel addition, pixel 1 and pixel 3 are added together and pixel 2 and pixel 4 are added together and read out at medium conversion efficiency, and pixel 1 and pixel 3 are added together and pixel 2 and pixel 4 are added together and read out at low conversion efficiency.

[0156] In the video mode with pixel addition, the addition and readout of pixels 1 and 3 is performed using the photodiode PD 11 and photodiode PD 21 The charges of pixels 2 and 4 are added together and read out. The charges of pixels 2 and 4 are added together and read out by the photodiode PD 12 and photodiode PD 22 The charges are added together and read out.

[0157] -Additional readout of pixels 1 and 3 at medium conversion efficiency FIG. 25A is a timing chart for explaining the operation in the case of additive readout of pixel 1 and pixel 3 at medium conversion efficiency.

[0158] time t 61When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive, thereby resetting the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B.

[0159] Next, at time t 62 After the reset signal RST transitions from high to low at time t 63 The transfer signal TRG for pixel 1 is 11 and the transfer signal TRG of pixel 3 21 When both of them transition from a low level to a high level, the transfer transistor 22 of the pixel 1 and the transfer transistor 22 of the pixel 3 are both turned on. As a result, the photodiode PD 11 and the photodiode PD of pixel 3 21 In other words, in FIG. 21, pixel signals are added and read out between pixels R1 and R2 of the same color. Then, at time t 64 Transfer signal TRG 11 ,TRG 21 After transition from high to low, at time t 65 The first switch signal FDL1 and the second switch signal FDL2 transition from high level to low level.

[0160] -Additional readout of pixels 2 and 4 at medium conversion efficiency FIG. 25B is a timing chart for explaining the operation in the case of additive readout of pixel 2 and pixel 4 at the medium conversion efficiency.

[0161] time t 61When the reset signal RST, the first switch signal FDL1, and the second switch signal FDL2 transition from a low level to a high level, the reset transistor 23, the first switch transistor 261, and the second switch transistor 262 become conductive, thereby resetting the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B.

[0162] Next, at time t 62 After the reset signal RST transitions from high to low at time t 63 The transfer signal TRG of pixel 2 12 and the transfer signal TRG of pixel 4 22 When both of them transition from a low level to a high level, the transfer transistor 22 of the pixel 1 and the transfer transistor 22 of the pixel 3 are both turned on. As a result, the photodiode PD 12 and the photodiode PD of pixel 4 22 In other words, in FIG. 21, pixel signals are added and read out between the pixel Gb1 and pixel Gb2 of the same color. Then, at time t 64 Transfer signal TRG 11 ,TRG 21 After transition from high to low, at time t 65 The first switch signal FDL1 and the second switch signal FDL2 transition from high level to low level.

[0163] -Additional readout of pixels 1 and 3 at low conversion efficiency FIG. 26A is a timing chart for explaining the operation in the case of additive readout of pixel 1 and pixel 3 at low conversion efficiency.

[0164] time t 61When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from low level to high level, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive. This resets the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B. Furthermore, the node FD s 2, the capacitance element C of pixel 1 11 , the capacitance element C of pixel 2 12 , the capacitance element C of pixel 3 21 , and the capacitance element C of pixel 4 22 is connected.

[0165] Next, at time t 62 After the reset signal RST transitions from high to low at time t 63 The transfer signal TRG for pixel 1 is 11 and the transfer signal TRG of pixel 3 21 When both of them transition from a low level to a high level, the transfer transistor 22 of the pixel 1 and the transfer transistor 22 of the pixel 3 are both turned on. As a result, the photodiode PD 11 and the photodiode PD of pixel 3 21 That is, pixel signals are added and read out between the pixels R1 and R2 of the same color. 64 Transfer signal TRG 11 ,TRG 21 After transition from high to low, at time t 65 The first switch signal FDL1 and the second switch signal FDL2 transition from high level to low level.

[0166] Additive reading of pixels 2 and 4 at low conversion efficiency FIG. 26B is a timing chart for explaining the operation in the case of additive readout of pixel 2 and pixel 4 at low conversion efficiency.

[0167] time t 61When the reset signal RST, the first switch signal FDL1, the second switch signal FDL2, and the third switch signal FDG transition from low level to high level, the reset transistor 23, the first switch transistor 261, the second switch transistor 262, and the third switch transistor 27 become conductive. This resets the pixel-shared floating diffusion FD1 of the first pixel section 20A and the pixel-shared floating diffusion FD2 of the second pixel section 20B. Furthermore, the node FD s 2, the capacitance element C of pixel 1 11 , the capacitance element C of pixel 2 12 , the capacitance element C of pixel 3 21 , and the capacitance element C of pixel 4 22 is connected.

[0168] Next, at time t 62 After the reset signal RST transitions from high to low at time t 63 The transfer signal TRG of pixel 2 12 and the transfer signal TRG of pixel 4 22 When both of them transition from a low level to a high level, the transfer transistor 22 of the pixel 2 and the transfer transistor 22 of the pixel 4 are both turned on. As a result, the photodiode PD 12 and the photodiode PD of pixel 4 22 That is, pixel signals are added and read out between the pixels Gb1 and Gb2 of the same color. 64 Transfer signal TRG 12 ,TRG 22 After transition from high to low, at time t 65 The first switch signal FDL1 and the second switch signal FDL2 transition from high level to low level.

[0169] As described above, in the pixel circuit of Example 2 as well, in the same manner as in the pixel circuit of Example 1, in a readout mode with pixel addition (moving image mode), the conversion efficiency of the pixel-shared floating diffusions FD1 and FD2 is switched between two levels, medium and low.

[0170] (Pixel circuit layout) A layout diagram (plan view) of a pixel circuit according to Example 2 is shown in Fig. 27, and a cross-sectional view taken along line YY in Fig. 27 is shown in Fig. 28. In Fig. 27, for ease of understanding, the gate electrodes of each transistor are shown with oblique lines.

[0171] The components of pixel 1 and pixel 2, which are the first pixel section 20A, and the components of pixel 3 and pixel 4, which are the second pixel section 20B, are arranged in a pixel layout that ensures symmetry with respect to a center line O between the first pixel section 20A and the second pixel section 20B.

[0172] The capacitance element C of the first pixel section 20A that determines the low conversion efficiency 11 ,C 12 , and the capacitance element C of the second pixel section 20B 21 ,C 22 can be configured as one capacitive element common to the first pixel section 20A and the second pixel section 20B. However, it is preferable to divide the pixel section into pixels 1, 2, 3, and 4, since this improves the symmetry of the pixel layout and ensures uniformity of the pixel characteristics.

[0173] As shown in FIG. 27, the capacitance element C 11 , the capacitance element C of pixel 2 12 , the capacitance element C of pixel 3 21 , and the capacitance element C of pixel 4 22 Regarding metal wiring M 11 and metal wiring M 12 However, this can be realized by the coupling capacitance with the metal wiring M 11 ,M 12 The present invention is not limited to the implementation of coupling capacitance between the two terminals, but may be implemented by a capacitance element using an oxide film, for example.

[0174] For the same reason as in the pixel circuit according to the first embodiment, the pixel structures of the first pixel section 20A and the second pixel section 20B are similar to those of the pixel circuit according to the first embodiment. 11 ,M 12It is preferable to use a back-illuminated pixel structure, which does not have the restrictions on the arrangement of the capacitance element C 11 ,C 12 ,C 21 ,C 22 Metal wiring M 11 ,M 12 Since the capacitance element C can be extended to the area of ​​the photodiode 21, the capacitance element C 11 ,C 12 ,C 21 ,C 22 It is possible to achieve this.

[0175] <Modification> Although the technology according to the present disclosure has been described above based on a preferred embodiment, the technology according to the present disclosure is not limited to the embodiment. The configuration and structure of the imaging device described in the above embodiment are examples and can be changed as appropriate.

[0176] For example, in the above embodiment, the application to a CMOS image sensor in which the pixels 2 are arranged in a matrix has been described as an example, but the technology according to the present disclosure is not limited to application to a CMOS image sensor. In other words, the technology according to the present disclosure is applicable to all imaging devices of the XY address type in which the pixels 2 are arranged two-dimensionally in a matrix.

[0177] <Application Examples> The imaging device according to the present embodiment described above can be used in various devices for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, as shown in Fig. 29. Specific examples of various devices are listed below.

[0178] ·Digital cameras, mobile devices with camera functions, and other devices that take images for viewing purposes - Devices used for traffic purposes, such as on-board sensors that take pictures of the front, rear, surroundings, and interior of a vehicle for safe driving (such as automatic stopping) and for recognition of the driver's condition, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles, etc. A device used in home appliances such as TVs, refrigerators, and air conditioners to capture user gestures and operate the appliances according to those gestures. -Medical and healthcare equipment, such as endoscopes and devices that take blood vessel images using infrared light - Equipment used for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication - Devices used for beauty purposes, such as skin measuring devices that take pictures of the skin and microscopes that take pictures of the scalp - Devices used for sports, such as action cameras and wearable cameras for sports use Agricultural equipment, such as cameras for monitoring fields and crop conditions

[0179] <Application Examples> The technology according to the present disclosure can be applied to various products. More specifically, the technology can be applied to imaging systems such as digital still cameras and video cameras, portable terminal devices having an imaging function such as mobile phones, and electronic devices such as copiers that use an imaging device in an image reading unit. The following describes the case where the technology is applied to imaging systems such as digital still cameras and video cameras.

[0180] [Imaging system] Fig. 30 is a block diagram showing a configuration of an imaging system, which is an example of an electronic device. As shown in Fig. 30, the imaging system 100 according to this example includes an imaging optical system 101 including a lens group, an imaging unit 102, a DSP (Digital Signal Processor) circuit 103, a frame memory 104, a display device 105, a recording device 106, an operation system 107, and a power supply system 108. The DSP circuit 103, the frame memory 104, the display device 105, the recording device 106, the operation system 107, and the power supply system 108 are connected to each other via a bus line 109.

[0181] The imaging optical system 101 captures incident light (image light) from a subject and forms an image on the imaging surface of the imaging unit 102. The imaging unit 102 converts the amount of incident light imaged on the imaging surface by the optical system 101 into an electrical signal on a pixel-by-pixel basis and outputs the signal as a pixel signal. The DSP circuit 103 performs general camera signal processing, such as white balance processing, demosaic processing, and gamma correction processing.

[0182] The frame memory 104 is used to store data as appropriate during signal processing in the DSP circuit 103. The display device 105 is made up of a panel-type display device such as a liquid crystal display device or an organic EL (electro luminescence) display device, and displays moving images or still images captured by the imaging unit 102. The recording device 106 records the moving images or still images captured by the imaging unit 102 on a recording medium such as a portable semiconductor memory, an optical disc, or an HDD (Hard Disk Drive).

[0183] An operation system 107, under the operation of a user, issues operation commands for various functions of the imaging system 100. A power supply system 108 appropriately supplies various types of power to the DSP circuit 103, frame memory 104, display device 105, recording device 106, and operation system 107 as operating power sources to these devices.

[0184] In the imaging system 100 having the above configuration, the imaging device according to the above-described embodiment can be used as the imaging unit 102. By using the imaging device as the imaging unit 102, addition readout by FD addition can be performed even in a state other than a state of low conversion efficiency.

[0185] <Configurations that the present disclosure can take> The present disclosure may also be configured as follows.

[0186] A. Imaging device [A-1] A first pixel unit and a second pixel unit have a floating diffusion that converts electric charges transferred from a light receiving unit into a voltage, and selectively perform pixel addition to add up pixel signals by electrically connecting the floating diffusions between pixels; the first pixel unit has a first switch transistor having one source / drain electrode connected to a floating diffusion, and a reset transistor connected between the other source / drain electrode of the first switch transistor and a power supply node; the second pixel unit has a second switch transistor having one source / drain electrode connected to the floating diffusion, a third switch transistor having one source / drain electrode connected to the other source / drain electrode of the second switch transistor, and a capacitance element connected between the other source / drain electrode of the third switch transistor and a reference potential node; The other source / drain electrodes of the first switch transistor and the second switch transistor are electrically connected to each other. Imaging device. [A-2] The first pixel unit or the second pixel unit realizes high conversion efficiency with respect to the conversion efficiency of the floating diffusion when the first switch transistor or the second switch transistor is in a non-conducting state in a case where pixel addition is not performed. The imaging device described in [A-1] above. [A-3] In the first pixel unit and the second pixel unit, when pixel addition is not performed, when the first switch transistor and the second switch transistor are both in a non-conducting state, a medium conversion efficiency is realized with respect to the conversion efficiency of the floating diffusion. The imaging device described in [A-1] above. [A-4] In the first pixel unit and the second pixel unit, when pixel addition is not performed, when the first switch transistor, the second switch transistor, and the third switch transistor are all in a conductive state, a low conversion efficiency is realized with respect to the conversion efficiency of the floating diffusion. The imaging device described in [A-1] above. [A-5] When the first switch transistor and the second switch transistor are both in a conductive state, the first pixel unit and the second pixel unit perform pixel addition and realize a medium conversion efficiency with respect to the conversion efficiency of the floating diffusion. The imaging device described in [A-1] above. [A-6] When the first switch transistor, the second switch transistor, and the third switch transistor are all in a conductive state, the first pixel unit and the second pixel unit perform pixel addition and realize a low conversion efficiency with respect to the conversion efficiency of the floating diffusion. The imaging device described in [A-1] above. [A-7] The capacitance element is divided and arranged in each pixel of the first pixel section and the second pixel section, The imaging device according to any one of [A-1] to [A-6] above. [A-8] Capacitive elements are realized by coupling capacitance between metal wiring. The imaging device described in [A-7] above. [A-9] The first pixel section and the second pixel section each include a plurality of pixels, Sharing a floating diffusion between multiple pixels, The imaging device according to any one of [A-1] to [A-8] above. [A-10] The first pixel unit and the second pixel unit perform pixel addition between pixels of the same color. The imaging device described in [A-9] above. [A-11] The components of the first pixel unit and the second pixel unit have a pixel layout that ensures symmetry with respect to a center line between the first pixel unit and the second pixel unit. The imaging device according to any one of [A-1] to [A-10] above. [A-12] Each floating diffusion of the first pixel unit and the second pixel unit is disposed closer to a center line between the first pixel unit and the second pixel unit than the center of each of the first pixel unit and the second pixel unit. The imaging device according to [A-11] above. [A-13] The first pixel unit and the second pixel unit have a back-illuminated pixel structure, The imaging device according to any one of [A-1] to [A-12] above.

[0187] ≪B.Electronic equipment≫ [B-1] A first pixel unit and a second pixel unit have a floating diffusion that converts electric charges transferred from a light receiving unit into a voltage, and selectively perform pixel addition to add up pixel signals by electrically connecting the floating diffusions between pixels; the first pixel unit has a first switch transistor having one source / drain electrode connected to a floating diffusion, and a reset transistor connected between the other source / drain electrode of the first switch transistor and a power supply node; the second pixel unit has a second switch transistor having one source / drain electrode connected to the floating diffusion, a third switch transistor having one source / drain electrode connected to the other source / drain electrode of the second switch transistor, and a capacitance element connected between the other source / drain electrode of the third switch transistor and a reference potential node; The other source / drain electrodes of the first switch transistor and the second switch transistor are electrically connected to each other. An electronic device having an imaging device. [B-2] The first pixel unit or the second pixel unit realizes high conversion efficiency with respect to the conversion efficiency of the floating diffusion when the first switch transistor or the second switch transistor is in a non-conducting state in a case where pixel addition is not performed. The electronic device described in [B-1] above. [B-3] In the first pixel unit and the second pixel unit, when pixel addition is not performed, when the first switch transistor and the second switch transistor are both in a non-conducting state, a medium conversion efficiency is realized with respect to the conversion efficiency of the floating diffusion. The electronic device described in [B-1] above. [B-4] In the first pixel unit and the second pixel unit, in the case of no pixel addition, when the first switch transistor, the second switch transistor, and the third switch transistor are all in a conductive state, a low conversion efficiency is realized with respect to the conversion efficiency of the floating diffusion. The electronic device described in [B-1] above. [B-5] When the first switch transistor and the second switch transistor are both in a conductive state, the first pixel unit and the second pixel unit perform pixel addition and realize a medium conversion efficiency with respect to the conversion efficiency of the floating diffusion. The electronic device described in [B-1] above. [B-6] When the first switch transistor, the second switch transistor, and the third switch transistor are all in a conductive state, the first pixel unit and the second pixel unit perform pixel addition and realize a low conversion efficiency with respect to the conversion efficiency of the floating diffusion. The electronic device described in [B-1] above. [B-7] The capacitance element is divided and arranged in each pixel of the first pixel unit and the second pixel unit, The electronic device according to any one of [B-1] to [B-6] above. [B-8] Capacitive elements are realized by coupling capacitance between metal wiring. The electronic device described in [B-7] above. [B-9] The first pixel portion and the second pixel portion each include a plurality of pixels; Sharing a floating diffusion between multiple pixels, The electronic device according to any one of [B-1] to [B-8] above. [B-10] The first pixel unit and the second pixel unit perform pixel addition between pixels of the same color. The electronic device described in [B-9] above. [B-11] The components of the first pixel unit and the second pixel unit have a pixel layout that ensures symmetry with respect to a center line between the first pixel unit and the second pixel unit. The electronic device according to any one of [B-1] to [B-10] above. [B-12] Each floating diffusion of the first pixel unit and the second pixel unit is disposed closer to the center line between the first pixel unit and the second pixel unit than the center of each of the first pixel unit and the second pixel unit. The electronic device described in [B-11] above. [B-13] The first pixel unit and the second pixel unit have a back-illuminated pixel structure, The electronic device according to any one of [B-1] to [B-12] above. [Explanation of symbols]

[0188] REFERENCE SIGNS LIST 1 CMOS image sensor, 2 pixel, 11 pixel array section, 12 row selection section, 13 constant current source section, 14 analog-to-digital conversion section, 15 horizontal transfer scanning section, 16 signal processing section, 17 timing control section, 18 horizontal transfer line, 19 reference signal generation section, 20A first pixel section, 20B second pixel section, 21 photodiode (photoelectric conversion section), 22 transfer transistor, 23 reset transistor, 24 amplifying transistor, 25 selection transistor, 261 first switch transistor, 262 second switch transistor, 27 third switch transistor, 31 (311 to 31 m ) Pixel drive line, 32 (321 to 32 n )...Vertical signal line, C1,C2,C 11 ,C 12 ,C 21 ,C 22 Capacitor element, FD (FD1, FD2) Floating diffusion

Claims

1. a first pixel circuit including a photodiode, a first floating diffusion, a first switch transistor, and a reset transistor; a second pixel circuit including a photodiode, a second floating diffusion, a second switch transistor, and a third switch transistor; a wiring connected to the first floating diffusion and the second floating diffusion; a first capacitance selectively connected to the first floating diffusion and the second floating diffusion; Equipped with the first floating diffusion is connected to the second floating diffusion via the first switch transistor, the second switch transistor, and the wiring; Light detection device.

2. the first pixel circuit includes a first amplification transistor and a first selection transistor; the second pixel circuit includes a second amplification transistor and a second selection transistor; 2. The optical detection device according to claim 1.

3. the first capacitance is connected to the first floating diffusion and the second floating diffusion via the third switch transistor; 2. The optical detection device according to claim 1.

4. At least one terminal of the first capacitor is disposed in a wiring layer.

2. The optical detection device according to claim 1.

5. the first floating diffusion and the second floating diffusion share the reset transistor; 2. The optical detection device according to claim 1.

6. Further, a second capacitance is selectively connected to the first floating diffusion and the second floating diffusion.

2. The optical detection device according to claim 1.

7. At least one terminal of the second capacitor is disposed in a wiring layer.

7. The optical detection device according to claim 6.

8. the reset transistor, the first switch transistor, the first amplification transistor, and the first selection transistor are arranged along a first direction in a plan view; 3. The optical detection device according to claim 2.

9. the first selection transistor is connected to a vertical signal line; 9. The optical detection device according to claim 8.

10. the first floating diffusion is connected to a gate of the first amplifying transistor; the second floating diffusion is connected to a gate of the second amplifying transistor; 10. The optical detection device according to claim 9.

11. the photodiode included in the first pixel circuit is one of a plurality of first photodiodes included in the first pixel circuit; 2. The optical detection device according to claim 1.

12. the photodiode included in the second pixel circuit is one of a plurality of second photodiodes included in the second pixel circuit; The optical detection device according to claim 11.

13. the first floating diffusion is shared by the plurality of first photodiodes; the second floating diffusion is shared by the plurality of second photodiodes; 13. The optical detection device of claim 12.

14. the first photodiodes are connected to the first floating diffusion via corresponding first transfer transistors; the second photodiodes are connected to the second floating diffusion via corresponding second transfer transistors; 14. The optical detection device of claim 13.

15. the first photodiodes are connected to the first floating diffusion via corresponding first transfer transistors; The optical detection device according to claim 11.

16. A terminal of the reset transistor is connected to a predetermined power supply voltage.

6. The optical detection device according to claim 5.

17. the first floating diffusion and the second floating diffusion share the reset transistor, and a terminal of the reset transistor, a terminal of the first amplification transistor, and a terminal of the second amplification transistor are connected to the same predetermined power supply voltage; 3. The optical detection device according to claim 2.

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