Probability shaping decoding circuit and probability shaping decoding method

Abstract

The probability shaping decoding circuit (5) includes a (2m-1)th lookup table (51) for layer x that restores, from the (2m-1)th received shaped bit sequence of layer x, a (2m-1)th received address bit sequence of layer x and a (2m-1)th received information bit sequence of layer x, which is a part of the information bit sequence of the communication target, from the 2m-1)th received shaped bit sequence of layer x, where x, m, and n[x] are natural numbers (m=1, 2, . . . , n[x]), and a 2mth lookup table (52) for layer x that restores, from the 2mth received shaped bit sequence of layer x, a 2mth received address bit sequence of layer x and a 2mth received information bit sequence of layer x, which is a part of the information bit sequence of the communication target, the mth address conversion lookup table (53) of layer x converting the (2m-1)th converted received address bit sequence of layer x into a (2m-1)th converted received address bit sequence of layer x corresponding to an offset value to be added to the received address bit sequence of layer x, an mth adder (54) of layer x adding the (2m-1)th converted received address bit sequence of layer x to the 2mth received address bit sequence of layer x and outputting a bit sequence indicating the addition result as the mth received shaped bit sequence of layer x+1, and an mth lookup table (55) of layer x+1 restoring the mth received address bit sequence of layer x+1 and the mth received information bit sequence of layer x, which is a part of the information bit sequence of the communication target, from the mth received shaped bit sequence of layer x+1. The received shaped bit sequence input to each lookup table corresponds to designation information designating a combination of signal points in a signal space managed by each of the lookup tables, or signal point information indicating a signal point arrangement in the signal space.

Description

[Technical field]

[0001] The present disclosure relates to a probability shaping decoding circuit and a probability shaping decoding method. [Background technology]

[0002] In order to achieve high throughput in optical communications, for example, it is effective to increase the modulation level. When increasing the modulation level, it is common to perform quadrature amplitude modulation (hereinafter referred to as QAM) on the transmitting side of signal communications, and to perform coherent detection and digital signal processing on the receiving side.

[0003] On the other hand, if the number of bits carried in a QAM signal is increased, the number of signal points also increases, and the minimum distance between signal points for the average power of the signal decreases. This increases the signal-to-noise ratio (SNR) required to obtain a certain communication quality, and limits the applicable transmission conditions.

[0004] In optical communications, the error rate tolerance is often very small, and error correction is usually performed in high-end equipment. In particular, when performance is important, soft-decision error correction is used. Up until now, the combination of multilevel QAM and soft-decision error correction has been considered, but further combination with probabilistic shaping is also being considered.

[0005] There are two types of signal point shaping techniques: geometric shaping, which shapes the positions of multiple signal points, and probabilistic shaping, which shapes the probabilities that each of multiple signal points can take. Either technique can make the relationship between SNR and transmission capacity asymptotically approach the Shannon limit. This contributes to increasing the communication capacity of client signals under given transmission conditions, for example.

[0006] Among these, when inputting symbols to which stochastic shaping, which improves performance by biasing the occurrence probability of each signal point, is applied to a communication channel, coding processing corresponding to stochastic shaping is required. For example, Patent Document 1 discloses a stochastic shaping coding technology based on hierarchical distribution matching, and it is assumed that coding processing using this stochastic shaping coding technology will be performed on the transmitting side of signal communication.

[0007] When the above encoding process is performed on the transmitting side of signal communication, it is necessary to perform a decoding process that is a counterpart of the encoding process on the receiving side of signal communication. Therefore, Patent Document 1 also discloses a probability shaping decoding technique that is a counterpart of the probability shaping encoding technique.

[0008] In a circuit using the probability shaping decoding technology described in Patent Document 1 (hereinafter also referred to as the "conventional circuit"), on the premise that the above encoding process is performed on the transmitting side of signal communication, a bit string corresponding to the shaped received symbol string (received shaped bit string) is converted into a received information bit string using a hierarchically arranged lookup table (LUT). When a single LUT is used, the circuit scale of the LUT increases exponentially as the number of input / output bits of the LUT increases, but the conventional circuit allows the LUT to be divided. As a result, in the conventional circuit, the number of input / output bits of each LUT can be suppressed to reduce the circuit scale while increasing the number of input / output bits (block length) of the entire circuit to achieve high performance. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] Patent No. 6820131 Summary of the Invention [Problem to be solved by the invention]

[0010] However, in the above conventional circuit, when the number of input / output bits of each divided LUT is small, performance degradation occurs in probability distribution shaping. For example, in the above conventional circuit, when the number of input / output bits of each LUT is small, the relationship of the transmission capacity to a given SNR deviates from the Shannon limit, or the SNR required to achieve a given transmission capacity becomes large. In order to prevent such performance degradation, it is necessary to increase the number of input / output bits of each LUT, but there is a problem that increasing the number of input / output bits of each LUT increases the circuit size.

[0011] The present disclosure has been made to solve the above-mentioned problems, and aims to obtain a probability shaping decoding circuit that has a reduced circuit scale while suppressing performance degradation compared to conventional circuits. [Means for solving the problem]

[0012] The probability shaping decoding circuit according to the present disclosure includes a (2m-1)th lookup table for layer x that restores, from the (2m-1)th received shaping bit sequence of layer x, a (2m-1)th received address bit sequence of layer x and a (2m-1)th received information bit sequence of layer x, which is a part of an information bit sequence of a communication target, from the (2m-1)th received shaping bit sequence of layer x; a 2mth lookup table for layer x that restores, from the 2mth received shaping bit sequence of layer x, a 2mth received address bit sequence of layer x and a 2mth received information bit sequence of layer x, which is a part of an information bit sequence of a communication target; and a 2mth lookup table for layer x that converts the (2m-1)th received address bit sequence of layer x into a (2m-1)th converted received address bit sequence of layer x that corresponds to an offset value to be added to the 2mth received address bit sequence of layer x. the mth address conversion lookup table; an mth adder of layer x that adds the (2-1)th converted received address bit sequence of layer x and the 2mth received address bit sequence of layer x and outputs a bit sequence indicating the addition result as the mth received shaped bit sequence of layer x+1; and an mth lookup table of layer x+1 that restores the mth received address bit sequence of layer x+1 and the mth received information bit sequence of layer x, which is a part of an information bit sequence of a communication target, from the mth received shaped bit sequence of layer x+1, wherein each lookup table is hierarchically arranged in a tree shape, and the received shaped bit sequence input to each lookup table corresponds to designation information that designates a combination of signal points in a signal space managed by each of the lookup tables, or signal point information that indicates a signal point arrangement in the signal space. Effect of the Invention

[0013] According to the present disclosure, it is possible to obtain a probability shaping decoding circuit that has a reduced circuit scale while suppressing performance degradation compared to conventional circuits. [Brief description of the drawings]

[0014] [Figure 1] 1 is a block diagram showing a configuration of a probability shaping coding circuit according to a first embodiment. [Diagram 2] FIG. 2 is a diagram showing, as a representative example, the circuit configuration between the (x+1)th layer and the xth layer immediately below it, of the probability shaping coding circuit shown in FIG. 1. [Diagram 3] FIG. 4 is a diagram illustrating an example of a process performed by a distribution circuit in the first embodiment. [Figure 4] FIG. 4 is a diagram illustrating an example of a process performed by a distribution circuit in the first embodiment. [Diagram 5] FIG. 2 is a diagram showing an example of an algorithm describing the processing by an address swapping circuit in the stochastic shaping coding circuit in the first embodiment. [Figure 6] 6A and 6B are diagrams illustrating the effect of the stochastic shaping coding circuit according to the first embodiment, in which FIG. 6A shows an example of the configuration of a conventional stochastic shaping coding circuit, and FIG. 6B shows an example of the configuration of the stochastic shaping coding circuit according to the first embodiment. [Figure 7] 4 is a flowchart showing an example of the operation of the stochastic shaping coding circuit according to the first embodiment. [Figure 8] FIG. 8A is a block diagram showing a hardware configuration for implementing the functions of the stochastic shaping coding circuit, and FIG. 8B is a block diagram showing a hardware configuration for executing software for implementing the functions of the stochastic shaping coding circuit. [Figure 9] 1 is a block diagram showing a configuration of a probability shaping decoding circuit according to a first embodiment. [Figure 10] FIG. 10 is a diagram illustrating an excerpt of a circuit configuration between the (x+1)th layer and the xth layer immediately below it, as a representative example of the probability shaping decoding circuit shown in FIG. [Figure 11] 11A and 11B are diagrams illustrating the effect of the probability shaping decoding circuit according to embodiment 1, where FIG. 11A shows an example of the configuration of a conventional probability shaping decoding circuit, and FIG. 11B shows an example of the configuration of the probability shaping decoding circuit according to embodiment 1. [Figure 12] 5 is a flowchart showing an operation example of the probability shaping decoding circuit according to the first embodiment. [Figure 13]FIG. 13A is a block diagram showing a hardware configuration for implementing the functions of the probability shaping decoding circuit, and FIG. 13B is a block diagram showing a hardware configuration for executing software for implementing the functions of the probability shaping decoding circuit. [Figure 14] FIG. 11 is a block diagram showing the configuration of a probability shaping decoding circuit according to a second embodiment, illustrating, as a representative example, the circuit configuration between the (x+1)th layer and the xth layer immediately below it. [Figure 15] FIG. 11 is a diagram showing an example of an algorithm describing the processing by an address swapping circuit in a probability shaping decoding circuit in the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, the embodiment of the present disclosure will be described in detail with reference to the drawings. First, a probability shaping coding circuit that performs coding processing using the above-mentioned probability shaping coding technique will be described, and then a probability shaping decoding circuit that performs decoding processing that is paired with the coding processing will be described.

[0016] Embodiment 1 <Probability shaping coding circuit 1> 1 is a block diagram showing the configuration of a probability shaping coding circuit 1 according to embodiment 1. The probability shaping coding circuit 1 is provided in, for example, an optical transmission device, and generates (encodes) a probability distribution shaping signal in the optical modulation of a transmission signal performed by the optical transmission device.

[0017] The probability shaping coding circuit 1 is configured on the premise of a circuit consisting of a group of hierarchically arranged look-up tables (LUTs) in the above-mentioned conventional circuit, and is configured such that a distribution circuit and an address swapping circuit are additionally provided between the hierarchically arranged LUTs.

[0018] For example, as shown in Fig. 1, the stochastic shaping coding circuit 1 includes a group of LUTs arranged hierarchically in a tree shape, namely, LUT2-0, LUT3-0, LUT3-1, LUT4-0, LUT4-1, LUT4-2, and LUT4-3, and distribution circuits 12 (12a, 12b, 12c) and address exchange circuits 13 (13a, 13b, 13c) provided between these LUTs. Data associated with an address is registered in each of these LUTs.

[0019] 1 shows a stochastic shaping coding circuit 1 having LUTs arranged in a three-layer tree structure. However, the number of layers of the LUTs may be two or less or four or more. LUT2-0 is the LUT in the second layer, which is the top layer. LUT3-0 and LUT3-1 are LUTs in the first layer, which is an intermediate layer, and LUT2-0 is connected to LUT3-0 and LUT3-1 in the layer immediately below via a distribution circuit 12a and an address swapping circuit 13a.

[0020] LUT4-0, LUT4-1, LUT4-2, and LUT4-3 are LUTs in the lowest layer, ie, the 0th layer. LUT3-0 is connected to LUT4-0 and LUT4-1 in the immediately lower layer via the distribution circuit 12b and the address exchange circuit 13b, and LUT3-1 is connected to LUT4-2 and LUT4-3 in the immediately lower layer via the distribution circuit 12c and the address exchange circuit 13c.

[0021] Each of LUT2-0, LUT3-0, LUT3-1, LUT4-0, LUT4-1, LUT4-2 and LUT4-3 manages a signal space. For example, the signal space managed by LUT4-0 is the space (S0) of two QAM signals, the signal space managed by LUT4-1 is the space (S1) of another two QAM signals, the signal space managed by LUT4-2 is the space (S2) of still another two QAM signals, and the signal space managed by LUT4-3 is the space (S3) of still another two QAM signals. In this case, the signal space managed by LUT3-0 is the signal space S0 and S1 managed by LUT4-0 and LUT4-1, and the signal space managed by LUT3-1 is the signal space S2 and S3 managed by LUT4-2 and LUT4-3. The signal space managed by LUT2-0 is the signal spaces S0, S1, S2, and S3 managed by LUT3-0 and LUT3-1. The signal points are points of complex amplitude values ​​in the signal space diagram.

[0022] A part of the transmission information bit string, which is external input information, is input to each of LUT2-0, LUT3-0, LUT3-1, LUT4-0, LUT4-1, LUT4-2, and LUT4-3. Also, a part of the bits of the transmission information bit string is input to the address swapping circuit 13 (13a, 13b, 13c) as transmission address swapping bits. The transmission information bit string, which is external input information, is an information bit sequence to be communicated, and is input from the outside to the stochastic shaping coding circuit 1 as a client signal or a framed signal. In one clock cycle, the total value of the number of bits of the transmission information bit string is a number expressed by any positive integer. For example, if the operating frequency of the logic circuit is 500 MHz, the clock cycle is 2 nanoseconds. The number of input bits to each LUT is any integer equal to or greater than 0.

[0023] The LUT2-0 in the second layer, which is the top layer, converts a part of the transmission information bit string into a transmission shaping bit string, and outputs the transmission shaping bit string obtained by this conversion to the distribution circuit 12a in the first layer, which is the immediately lower layer. The transmission shaping bit string is an information bit string for generating designation information that designates a combination of signal point groups in a signal space managed by the LUT3-0 and LUT3-1 in the first layer. This conversion process is performed by table reference. Note that table reference is a process in which the relationship between addresses and data is stored in advance, and when an address is designated, the data corresponding to that address is read out. The input to the LUT corresponds to the address of the LUT, and the output from the LUT corresponds to the data of the LUT. The relationship between addresses and data is usually one-to-one.

[0024] The first-layer sorting circuit 12a converts the transmission shaping bit string into a combination of a first source address bit string and a second source address bit string, and outputs each bit string obtained by the conversion to the first-layer address swapping circuit 13a. The first source address bit string and the second source address bit string are information bit strings that become designation information for designating a combination of signal points in the signal space managed by the first-layer LUT3-0 and LUT3-1.

[0025] The address replacement circuit 13a of the first layer performs processing on the first source address bit string and the second source address bit string according to the value of the transmission address replacement bit to obtain a first transmission address bit string and a second transmission address bit string. The address replacement circuit 13a of the first layer outputs the obtained first transmission address bit string to the LUT3-1 of the first layer, and outputs the second transmission address bit string to the LUT3-0 of the first layer.

[0026] The LUT3-0 in the first layer converts a bit sequence consisting of a part of the transmission information bit sequence, which is external input information, and the second transmission address bit sequence from the address swapping circuit 13a in the first layer, into a transmission shaping bit sequence, and outputs the transmission shaping bit sequence obtained by the conversion to the distribution circuit 12b in the immediately lower layer, the 0th layer. The transmission shaping bit sequence is an information bit sequence for generating designation information that designates a combination of signal points in a signal space managed by the LUT4-0 and LUT4-1 in the immediately lower layer, the 0th layer.

[0027] The layer 0 sorting circuit 12b converts the transmission shaping bit sequence into a combination of a first source address bit sequence and a second source address bit sequence, and outputs each bit sequence obtained by the conversion to the layer 0 address swapping circuit 13b. The first source address bit sequence and the second source address bit sequence are information bit sequences that become designation information for designating a combination of signal point groups in a signal space managed by the layer 0 LUT4-0 and LUT4-1.

[0028] The address swapping circuit 13b in the 0th layer processes the first and second source address bit strings according to the value of the transmission address swapping bit to obtain the first and second transmission address bit strings. The address swapping circuit 13b in the 0th layer outputs the obtained first transmission address bit string to the LUT4-1 in the 0th layer, and outputs the second transmission address bit string to the LUT4-0 in the 0th layer.

[0029] The LUT 3-1 in the first layer also operates basically in the same way as the LUT 3-0 in the first layer. In addition, the distribution circuit 12c and the address switching circuit 13c in the 0th layer subsequent to the LUT 3-1 in the first layer also operate basically in the same way as the distribution circuit 12b and the address switching circuit 13b in the 0th layer subsequent to the LUT 3-0 in the first layer described above.

[0030] The LUT4-0 and LUT4-1 in the lowest layer, the 0th layer, convert a bit sequence consisting of a part of the transmission information bit sequence, which is external input information, and the second transmission address bit sequence from the address swapping circuit 13b in the 0th layer, into signal point information indicating a signal point arrangement in a signal space managed by the LUT4-0 and LUT4-1, and output the signal point information to the outside. The LUT4-2 and LUT4-3 convert a bit sequence consisting of a part of the transmission information bit sequence, which is external input information, and the first transmission address bit sequence from the address swapping circuit 13c in the 0th layer, into signal point information indicating a signal point arrangement in a signal space managed by the LUT4-2 and LUT4-3, and output the signal point information to the outside.

[0031] Fig. 2 is a diagram showing an excerpt of the circuit configuration between the (x+1)th layer and the xth layer immediately below it as a representative example of the probability shaping coding circuit 1 shown in Fig. 1. In the following explanation, for convenience of explanation, the (x+1)th layer will be written as "layer x+1" and the xth layer will be written as "layer x". In addition, in Fig. 2, the LUTs shown in Fig. 1 are generalized to a form independent of the layer, and these LUTs are denoted by the reference characters 11, 14, and 15.

[0032] 2, the first LUT 11 of the layer x+1 is written as LUT[x+1][1], the first LUT 14 of the layer x is written as LUT[x][1], and the second LUT 15 of the layer x is written as LUT[x][2]. In addition, in FIG. 2, the number of bits of the input / output bit strings in the first LUT 11 of the layer x+1, the allocation circuit 12, and the address swapping circuit 13 are written as symbols A to D (all non-negative integers). At this time, the relationships C>B, A≧D, and A+D≧B hold between the number of bits.

[0033] <First LUT11 of layer x+1> The first LUT 11 of layer x+1 receives a first transmission bit sequence (number of bits: B) of layer x+1 from an external source (not shown) and outputs a first transmission shaping bit sequence (number of bits: C) of layer x+1. Specifically, the first LUT 11 of layer x+1 converts the input first transmission bit sequence of layer x+1 into a first transmission shaping bit sequence of layer x+1 by referring to a table and outputs it.

[0034] Here, the first transmission bit string of layer x+1 to be input is composed of, for example, a first transmission address bit string of layer x+1 from an external source (not shown) and a first transmission information bit string of layer x+1 from an external source (not shown). However, the first transmission address bit string of layer x+1 is 0 when layer x+1 is the top layer.

[0035] In addition, when layer x+1 is an intermediate layer from just below the top layer to just above the bottom layer, the first transmission address bit string of layer x+1 is a bit string output from the address swapping circuit 13 located before the first LUT 11 of layer x+1.

[0036] <First distribution circuit 12 of layer x> The first allocation circuit 12 of layer x receives as input the first transmission shaping bit string (number of bits: C) of layer x+1 output from the first LUT 11 of layer x+1, and outputs a first source address bit string (number of bits: A) of layer x and a second source address bit string (number of bits: D) of layer x.

[0037] Specifically, the first distribution circuit 12 of layer x converts the input first transmission shaping bit string of layer x+1 into a combination of a first source address bit string of layer x and a second source address bit string of layer x by referring to a table, and outputs each bit string obtained by the conversion.

[0038] Here, an example of the processing by the first distribution circuit 12 of layer x will be described with reference to Fig. 3. As shown in Figs. 3A and 3B, for example, the first distribution circuit 12 of layer x uses the first bit or the first and second bits of the input first transmission shaped bit string of layer x+1 as a delimiter signal, and changes the above conversion method according to the value of this delimiter signal.

[0039] In addition, at this time, the allocation circuit 12 performs the above conversion so that the magnitude relationship between the value indicated by the first source address bit string of layer x and the value indicated by the second source address bit string of layer x obtained by the conversion is either (a) equal to each other and an even value, or (b) different from each other, and the value indicated by the first source address bit string of layer x is greater than the value indicated by the second source address bit string of layer x.

[0040] As an example, assume that the number of bits of the first transmission shaped bit sequence of layer x+1 input to the distribution circuit 12 is 13 bits (C=13).

[0041] <Case 0> In this case, if the first bit of the input first transmission shaping bit string of layer x+1 is "0", the distribution circuit 12 distributes the 12 bits from the second bit to the thirteenth bit following this "0" into groups of six bits as shown in FIG. 3B. That is, the distribution circuit 12 sets the six bits from the second bit to the seventh bit of the first transmission shaping bit string of layer x+1 as the first source address bit string of layer x, and the six bits from the eighth bit to the thirteenth bit as the second source address bit string of layer x. In this case, the above-mentioned six bits become the first source address bit string of layer x, so that the effective bit width of the first source address bit string is 6 (=E) or less. Hereinafter, this case is also called "case 0".

[0042] <Case 1> Also, if the first bit of the input first transmission shaping bit string of layer x+1 is "1", the distribution circuit 12 refers to the second bit following this "1" as shown in Fig. 3A. If the second bit is "0", the distribution circuit 12 distributes the 11 bits from the third bit to the thirteenth bit following this "0" into six bits and five bits. In other words, the distribution circuit 12 sets the six bits from the third bit to the eighth bit of the first transmission shaping bit string of layer x+1 as the first source address bit string of layer x, and the five bits from the ninth bit to the thirteenth bit as the second source address bit string of layer x.

[0043] In this case, the distribution circuit 12 adds a new "1" as the seventh bit to the left of the most significant bit (sixth bit) of the first source address bit string in layer x and outputs it. This is equivalent to adding an offset value of "64" to the address determined by the first source address bit string in layer x. In this case, since the first source address bit string in layer x is seven bits long, the effective bit width of the bit string is greater than 6 (=E). Hereinafter, this case will also be referred to as "Case 1".

[0044] <Case 2> On the other hand, if the value of the second bit following the first bit "1" is "1", the distribution circuit 12 distributes the 11 bits from the third bit to the thirteenth bit following this "1" into 7 bits and 4 bits. In other words, the distribution circuit 12 sets the seven bits from the third bit to the ninth bit of the first transmission shaping bit string of layer x+1 as the first source address bit string of layer x, and the four bits from the tenth bit to the thirteenth bit as the second source address bit string of layer x.

[0045] In this case, the distribution circuit 12 adds a new "1" as the 8th bit to the left of the most significant bit (7th bit) of the first source address bit string in layer x and outputs it. This is equivalent to adding an offset value of "128" to the address determined by the first source address bit string in layer x. In this case, since the first source address bit string in layer x is 8 bits long, the effective bit width of the bit string is greater than 6 (=E). Hereinafter, this case will also be referred to as "Case 2".

[0046] Here, the processing by the first allocation circuit 12 of layer x will be further explained with reference to FIG. 4. FIG. 4 is a graph expressing a signal point constellation determined by signal point information as a combination of a first address (Address1) and a second address (Address2). In FIG. 4, the horizontal axis indicates the first address, and the vertical axis indicates the second address. For example, when the first address and the second address are each expressed by 8 bits, the signal point information indicating one signal point constellation is expressed by 16 bits (=8+8). In this case, the number of addresses that one signal point constellation can take is 65536 (=2 16 ) street.

[0047] Also, the straight line L in Fig. 4 shows a signal point constellation when the first address and the second address are equal. For example, among the signal point constellations on the straight line L, a signal point constellation in which the first address and the second address are both "2" is expressed as "0000001000000010", and a signal point constellation in which the first address and the second address are both "8" is expressed as "0000100000001000".

[0048] Among these, the stochastic shaping coding circuit 1 uses 4096 signal point constellations that are considered to include many "0"s in the signal point information as signal points with relatively low power. In this case, the 4096 constellations correspond to the signal point constellation of the gray part indicated by reference numeral 401 in Fig. 4. The signal point constellation indicated by reference numeral 401 can be expressed by 12 bits.

[0049] At this time, as described above, the distribution circuit 12 performs the above conversion so that the magnitude relationship between the value indicated by the first source address bit string in layer x and the value indicated by the second source address bit string in layer x obtained by the conversion is either (a) equal to each other and is an even value, or (b) different from each other, and the value indicated by the first source address bit string in layer x is greater than the value indicated by the second source address bit string in layer x.

[0050] Here, the signal point constellation when the above binary relationship is (a) is located exactly on the line L within the gray portion indicated by reference numeral 401. In this case, the signal point constellation is expressed, for example, as "0000001000000010," which corresponds to the first address and the second address being the same even number "2," or "0000100000001000," which corresponds to the first address and the second address being the same even number "8."

[0051] Moreover, the signal point constellation when the above binary relationship is (b) is exactly the gray part indicated by reference numeral 401, which is located to the right (closer to the horizontal axis) of line L. In this case, the signal point constellation is expressed as, for example, "0000001100000001," which corresponds to the case where the first address is "3" and the second address is "1," or "0000011100000001," which corresponds to the case where the first address is "7" and the second address is "1."

[0052] That is, by performing conversion so as to correspond to the above (a) or (b), the allocating circuit 12 determines a signal point arrangement that is located at least on the straight line L in the gray portion indicated by reference numeral 401 or on the right side (closer to the horizontal axis) of the straight line L. Furthermore, in order to improve the efficiency in determining the signal point arrangement as described above, the allocating circuit 12 adopts the above-mentioned concept of offset values.

[0053] For example, when the range of the first address is "0" to "63", that is, when the effective bit width of the first address is 6 or less (Case 0 described above), the allocation circuit 12 does not use an offset value. On the other hand, when the range of the first address is "64" to "127", that is, when the effective bit width of the first address is greater than 6 and corresponds to Case 1 described above, the allocation circuit 12 adds a new "1" as the 7th bit to the left of the most significant bit (6th bit) of the first source address bit string of layer x and outputs it. This is synonymous with adding an offset value of "64" to a value that can be expressed by the first source address bit string (6 bits) of layer x.

[0054] Furthermore, when the range of the first address is "128" to "255", that is, when the effective bit width of the first address is greater than 6 and corresponds to the above-mentioned case 2, the distribution circuit 12 adds a new "1" as the 8th bit to the left of the most significant bit (7th bit) of the first source address bit string (7 bits) of layer x and outputs it. This is synonymous with adding an offset value of "128" to the value that can be expressed by the first source address bit string (6 bits) of layer x.

[0055] In this way, the distribution circuit 12 can reduce the number of bits to be processed during conversion by adopting the concept of an offset value that adds a new "1" after conversion. This also leads to a reduction in the number of bits of the first transmission shaping bit string of layer x+1 that is input to the distribution circuit 12 from the first LUT 11 of layer x+1.

[0056] <First address swapping circuit 13 of layer x> The first address switching circuit 13 of layer x receives as input the first source address bit string of layer x (number of bits: A) and the second source address bit string of layer x (number of bits: D) output from the first distribution circuit 12 of layer x, and a first transmitting address switching bit of layer x from an external source (not shown), and outputs the first transmitting address bit string of layer x (number of bits: A at most) and the second transmitting address bit string of layer x (number of bits: A at most).

[0057] Specifically, the first address replacement circuit 13 of layer x performs processing on the first source address bit string of layer x and the second source address bit string of layer x according to the value of the first transmission address replacement bit of layer x to obtain the first transmission address bit string of layer x and the second transmission address bit string of layer x. The address replacement circuit 13 outputs each of the obtained bit strings. Note that the first transmission address replacement bit of layer x is a part of the transmission information bit string from the outside.

[0058] A specific example of the process by the address swapping circuit 13 will be described below. As described above, the magnitude relationship between the value indicated by the first source address bit string of layer x and the value indicated by the second source address bit string of layer x input to the address swapping circuit 13 can be in two cases: (a) they are equal even values, and (b) they are different, and the value indicated by the first source address bit string of layer x is greater than the value indicated by the second source address bit string of layer x. In addition, the first address swapping bit of layer x (hereinafter also simply referred to as "swap bit") input to the address swapping circuit 13 can be either "0" or "1".

[0059] Therefore, the address interchange circuit 13 performs processing according to the following four cases. An example of an algorithm describing the processing in the following four cases is shown in FIG. (1) Case A: The magnitude relationship is (a) and the swap bit is "0." (2) Case B: The magnitude relationship is (a) and the swap bit is "1." (3) Case C: The magnitude relationship is (b) and the swap bit is "0." (4) Case D: The magnitude relationship is (b) and the swap bit is "1."

[0060] (Case A) The address swapping circuit 13 sets the first transmission address bit string of layer x and the second transmission address bit string of layer x to be output to the same value as the first source address bit string of layer x (=second source address bit string of layer x) that is input.

[0061] (Case B) The address replacement circuit 13 outputs the first transmitting address bit string of layer x and the second transmitting address bit string of layer x as a value obtained by adding "1" to the input first source address bit string of layer x (= second source address bit string of layer x).

[0062] (Case C) The address swapping circuit 13 sets the first transmitting address bit string of layer x to be output as the first source address bit string of layer x that was input, and sets the second transmitting address bit string of layer x to be output as the second source address bit string of layer x that was input.

[0063] (Case D) The address swapping circuit 13 outputs the first transmitting address bit string of layer x as the second source address bit string of layer x that was input, and outputs the second transmitting address bit string of layer x as the first source address bit string of layer x that was input.

[0064] Here, the process by the address swapping circuit 13 will be further explained with reference to Fig. 4. In Fig. 4, the first address on the horizontal axis corresponds to the address defined by the first source address bit string of layer x, and the second address on the vertical axis corresponds to the address defined by the second source address bit string of layer x.

[0065] If the input replacement bit is "1", the address replacement circuit 13 basically replaces the first address with the second address. This replacement corresponds to the signal point arrangement shown by reference numeral 401 in Fig. 4 being moved to a symmetrical position on the opposite side (closer to the vertical axis) of the line L.

[0066] For example, if the signal point constellation is expressed as "0000011100000001," which corresponds to the case where the first address is "7" and the second address is "1," address swapping circuit 13 swaps the addresses as shown in the above case D if the input swap bit is "1," making the first address "1" and the second address "7." In this case, the signal point constellation is expressed as "0000000100000111," in which the first 8 bits and the latter 8 bits of the original bit string are swapped.

[0067] However, when the signal point constellation is located exactly on the straight line L, for example, when the signal point constellation is expressed as "0000001000000010" corresponding to the first address and the second address being equal to each other and being an even number "2", the address interchanging circuit 13 will only obtain the original signal point constellation even if it performs the above-mentioned interchanging. Therefore, in this case, as shown in the above-mentioned case B, the address interchanging circuit 13 sets the odd address obtained by adding "1" to the first address (=second address) as the new first address (i.e., the first transmission address bit string) and the new second address (i.e., the second transmission address bit string). In this case, the address interchanging circuit 13 obtains a signal point constellation expressed as "0000001100000011" where the first address is "3" and the second address is "3" as the new signal point constellation.

[0068] On the other hand, if the replacement bit is "0", the address replacement circuit 13 does not replace the first address with the second address as shown in the above cases A and C. This allows the stochastic shaping coding circuit 1 to uniformly and efficiently represent the 4096 signal point constellations shown by reference numeral 401 in FIG.

[0069] In the above description, the distribution circuit 12 converts the first source address bit string of layer x and the second source address bit string of layer x so that the magnitude relationship between the first source address bit string of layer x and the second source address bit string of layer x is either (a) equal to each other and an even value, or (b) different from each other and the value indicated by the first source address bit string of layer x is greater than the value indicated by the second source address bit string of layer x. However, this is only an example, and the conversion example is not limited to the above example. For example, the distribution circuit 12 may convert the first source address bit string of layer x to either (c) equal to each other and an odd value, or (d) different from each other and the value indicated by the first source address bit string of layer x is smaller than the value indicated by the second source address bit string of layer x. In the case of (c), if the switching bit is "1", the address switching circuit 13 may add "1" to the two values ​​to make it an even number.

[0070] <First LUT14 of layer x> The first LUT 14 of layer x receives the first transmission bit string of layer x as input, and outputs the first transmission shaping bit string of layer x to an external device (not shown). Specifically, the first LUT 14 of layer x converts the input first transmission bit string of layer x into the first transmission shaping bit string of layer x by referring to a table, and outputs the converted bit string.

[0071] Here, the first transmission bit string of layer x that is input is composed of two bit strings, namely, the first transmission address bit string of layer x (number of bits: at most A) output from the address swapping circuit 13, and the first transmission information bit string of layer x from the outside (not shown).

[0072] When layer x is the lowest layer, the first transmission shaping bit sequence of layer x to be output corresponds one-to-one to signal point information indicating a signal point arrangement in a signal space managed by the first LUT 14 of layer x. When layer x is an intermediate layer from immediately below the top layer to immediately above the bottom layer, the first transmission shaping bit sequence of layer x corresponds one-to-one to designation information designating a combination of signal points in a signal space managed by the first LUT 11 in the layer immediately below layer x.

[0073] <Layer x's second LUT15> The second LUT 15 of layer x receives the second transmission bit string of layer x as input, and outputs the second transmission shaping bit string of layer x to an external device (not shown). Specifically, the second LUT 15 of layer x converts the input second transmission bit string of layer x into the second transmission shaping bit string of layer x by referring to a table, and outputs the converted bit string.

[0074] Here, the second transmission bit string of layer x that is input is composed of two bit strings, namely, the second transmission address bit string of layer x (number of bits: at most A) output from the address swapping circuit 13, and the second transmission information bit string of layer x from the outside (not shown).

[0075] If layer x is the lowest layer, the second transmission shaping bit sequence of layer x to be output corresponds one-to-one to signal point information indicating a signal point arrangement in a signal space managed by the second LUT 15 of layer x. If layer x is an intermediate layer, the second transmission shaping bit sequence of layer x corresponds one-to-one to designation information designating a combination of signal points in a signal space managed by the second LUT 15 in the layer immediately below layer x.

[0076] In the above description, the first transmission information bit string of layer x+1 is input to the first LUT 11 of layer x+1, the first transmission information bit string of layer x is input to the first LUT 14 of layer x, and the second transmission information bit string of layer x is input to the second LUT 15 of layer x. However, the number of bits of each transmission information bit string input to each of the LUTs may be 0. In this case, the probability shaping coding circuit 1 can further suppress performance degradation.

[0077] In particular, in a circuit having a hierarchical LUT group such as the stochastic shaping coding circuit 1, the number of bits of the transmission information bit string input from outside may affect the performance of each LUT. This is because the value of the transmission information bit string input from outside is random. In this regard, the stochastic shaping coding circuit 1 sets the number of bits of the transmission information bit string input to any LUT among the LUTs to 0, so that the LUT does not handle a bit string whose value is random. In this case, the LUT only needs to generate a transmission shaping bit string from a transmission address bit string that is input from a higher layer, but the value of the transmission address bit string that is input from a higher layer is not random and can be set in advance. Therefore, the stochastic shaping coding circuit 1 can further suppress performance degradation.

[0078] In particular, in the stochastic shaping coding circuit 1, there may be cases where the number of bits of the input bit string is smaller than the number of bits of the output bit string, and in such a case, the number of bits of the input transmission information bit string may be set to 0, starting from the LUT located in the lower layer. For example, when the layer x is the lowest layer, the number of bits of at least one of the first transmission information bit string of the layer x input to the first LUT 14 of the layer x and the second transmission information bit string of the layer x input to the second LUT 15 of the layer x may be set to 0. This allows the stochastic shaping coding circuit 1 to further suppress performance degradation.

[0079] Next, the effect of the probability shaping coding circuit 1 according to the first embodiment will be described with reference to FIG.

[0080] Fig. 6A shows a configuration example of a conventional probability shaping coding circuit (hereinafter also referred to as the "conventional example"), and Fig. 6B shows a configuration example of the probability shaping coding circuit 1 according to the first embodiment (hereinafter also referred to as the "present configuration example"). The only difference between the conventional example and the present configuration example is whether or not they include a distribution circuit 12 and an address swapping circuit 13.

[0081] 6A and 6B, the number of bits of the bit string input to and output from each component is indicated as A to D (all non-negative integers). For example, in the conventional example shown in Fig. 6A, the number of bits of the bit string input to the m-th LUT 11 of the layer x+1 is indicated as B+1, and the number of bits of the bit string input to the (2m-1)-th LUT 14 of the layer x and the bit string input to the 2m-th LUT 15 of the layer x is indicated as A.

[0082] In addition, in this configuration example shown in Figure 6B, the number of bits of the mth transmission bit string of layer x+1 that is input to the mth LUT 11 of layer x+1 is denoted by B, the number of bits of the mth transmission shaping bit string of layer x+1 that is input to the mth allocation circuit 12 of layer x is denoted by C, the number of bits of the (2m-1)th source address bit string of layer x that is input to the mth address swapping circuit 13 of layer x is denoted by A, the number of bits of the 2mth source address bit string of layer x is denoted by D, and the number of bits of the mth transmission address swapping bit of layer x is denoted by 1.

[0083] In addition, in this configuration example shown in FIG. 6B, the number of bits in the (2m-1)th transmission address bit string of layer x input to the (2m-1)th LUT 14 of layer x and the 2mth transmission address bit string of layer x input to the 2mth LUT 15 of layer x is at most A (less than A).

[0084] For example, if A is 8 bits, B is 10 bits, C is 12 bits, and D is 6 bits, then in the conventional example shown in FIG. 6A, the number of bits in the input / output bit string for the first LUT 11 of layer x+1 is 11 bits (=B+1) for the input, and 16 bits (=A×2) for the output. Note that the "+1" in the number of bits on the input side means that in this configuration example shown in FIG. 6B, one bit of the swapped bit input to the address swapping circuit 13 is regarded as an input to the first LUT 11 of layer x+1. In this case, the size of the first LUT 11 of layer x+1 in the conventional example is 2A×2 B+1 =16×2 11 =32768.

[0085] On the other hand, in the present configuration example shown in FIG. 6B, the number of bits of the input / output bit string for the first LUT 11 of the layer x+1 is 10 bits (=B) for input and 12 bits (=C) for output. In this case, the scale of the first LUT 11 of the layer x+1 in this configuration example is C×2 B =12×2 10 =12228.

[0086] Therefore, in this configuration example, the scale of the first LUT 11 of the layer x+1 can be reduced by 60% or more compared to the conventional example. In general, the scale of the distribution circuit 12 and the address interchange circuit 13 is sufficiently small for an LUT of this scale (for example, an LUT of the order of 10 kilobits), and can be ignored.

[0087] In the conventional example, in order to suppress performance degradation, it is necessary to increase the number of input / output bits for each LUT (for example, the first LUT 11 of layer x+1), but increasing the number of input / output bits increases the circuit scale. On the other hand, in this configuration example, a distribution circuit 12 and an address interchange circuit 13 are provided after the first LUT 11 of layer x+1, and these circuits perform the above-mentioned processing, thereby making it possible to reduce the circuit scale while suppressing performance degradation compared to the conventional example. In particular, in this configuration example, the effect is remarkable by setting the relationship of the number of bits of the input / output bit string for each component to C>B, A≧D, and A+D≧B.

[0088] In this configuration example, it is possible to obtain a certain effect even if the address switching circuit 13 is omitted. For example, if the address switching circuit 13 is omitted in this configuration example, the first source address bit string of layer x output from the distribution circuit 12 is input as is to the first LUT 14 of layer x, and the second source address bit string of layer x output from the distribution circuit 12 is input as is to the second LUT 15 of layer x.

[0089] In this case, the first LUT 14 of layer x generates a first transmission shaping bit string of layer x from the first source address bit string of layer x output from the distribution circuit 12 and a first transmission information bit string of layer x from an external source (not shown). The second LUT 15 of layer x generates a second transmission shaping bit string of layer x from a second source address bit string of layer x output from the distribution circuit 12 and a second transmission information bit string of layer x from an external source (not shown).

[0090] In this case, one bit of the replacement bit input to the address replacement circuit 13 is input to, for example, the first LUT 11 of the layer x+1. In this case, the scale of the first LUT 11 of the layer x+1 is C×2 B+1 =12×2 11 = 24576. Therefore, in this configuration example, even if the address swapping circuit 13 is omitted, the size of the first LUT 11 in the layer x+1 can be reduced by 25% compared to the conventional example.

[0091] Next, an example of the operation of the stochastic shaping coding circuit 1 according to the first embodiment will be described with reference to the flowchart shown in Fig. 7. This flowchart starts with m=1 and x=L-1, where L is the number of layers in the LUT group hierarchically arranged in a tree shape.

[0092] First, the m-th LUT 11 of the layer x+1 converts the m-th transmission bit sequence of the layer x+1 into the m-th transmission shaped bit sequence of the layer x+1 by referring to the table (step ST1).

[0093] Next, the mth distribution circuit 12 of layer x converts the mth transmission shaping bit sequence of layer x+1 into the (2m-1)th source address bit sequence of layer x and the 2mth source address bit sequence of layer x (step ST2).

[0094] Next, the mth address swapping circuit 13 in layer x generates the (2m-1)th transmission address bit string in layer x and the 2mth transmission address bit string in layer x from the (2m-1)th source address bit string in layer x, the 2mth source address bit string in layer x, and the mth transmission address swapping bit in layer x (step ST3).

[0095] Next, the (2m-1)th LUT14 of layer x generates the (2m-1)th transmission shaping bit string of layer x from the (2m-1)th transmission address bit string of layer x and the (2m-1)th transmission information bit string of layer x (step ST4).

[0096] Next, the 2mth LUT 15 of the layer x generates the 2mth transmission shaping bit string of the layer x from the 2mth transmission address bit string of the layer x and the 2mth transmission information bit string of the layer x (step ST5).

[0097] Next, the probability shaping coding circuit 1 judges whether m is equal to n[x] (step ST6), where n[x] is a natural number indicating how many units, each of which includes the allocation circuit 12, the address swapping circuit 13, the LUT 14, and the LUT 15, exist in one layer.

[0098] As a result, if it is determined that m is not equal to n[x] (step ST6; NO), m is counted up by one (step ST7) and the process returns to step ST2. On the other hand, if it is determined that m is equal to n[x] (step ST6; YES), the process proceeds to step ST8, where the probability shaping coding circuit 1 determines whether x is equal to 1 (step ST8).

[0099] As a result, if it is determined that x is not equal to 1 (step ST8; NO), x is counted down by 1 (step ST9), and the process returns to step ST2. On the other hand, if it is determined that x is equal to 1 (step ST8; YES), the process ends.

[0100] Fig. 8A is a block diagram showing a hardware configuration for implementing the functions of the stochastic shaping encoding circuit 1. Fig. 8B is a block diagram showing a hardware configuration for executing software for implementing the functions of the stochastic shaping encoding circuit 1.

[0101] When the processing circuit is the dedicated hardware processing circuit 100 shown in Fig. 8A, the processing circuit 100 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination of these. The functions of the LUT in the stochastic shaping encoding circuit 1 may be realized by separate processing circuits, or these functions may be realized together by one processing circuit.

[0102] When the processing circuit is the processor 101 shown in Fig. 8B, the function of the LUT in the stochastic shaping coding circuit 1 is realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 102. The processor 101 realizes the function of the LUT in the stochastic shaping coding circuit 1 by reading and executing the program stored in the memory 102. That is, the stochastic shaping coding circuit 1 includes the memory 102 for storing a program that, when executed by the processor 101, results in the processing of steps ST1 to ST9 shown in Fig. 7 being executed.

[0103] These programs cause a computer to execute the procedure or method of the LUT in the probability shaping encoding circuit 1. The memory 102 may be a computer-readable storage medium having stored therein a program for causing a computer to function as the LUT in the probability shaping encoding circuit 1.

[0104] Memory 102 may include, for example, non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically-EPROM), magnetic disks, flexible disks, optical disks, compact disks, mini disks, DVDs, etc.

[0105] <Probability shaping decoding circuit 5> Next, the probability shaping decoding circuit 5 according to the embodiment 1 will be described. Fig. 9 is a block diagram showing the configuration of the probability shaping decoding circuit 5 according to the embodiment 1. The probability shaping decoding circuit 5 is provided in, for example, an optical receiving device, and restores (decodes) external input information from signal point information included in a received signal received from an optical transmitting device.

[0106] 9 shows a configuration in which the address swapping circuit 13 is omitted from the probability shaping encoding circuit 1 provided in the optical transmitting device on the transmitting side. The configuration of the probability shaping decoding circuit 5 in the case where the probability shaping encoding circuit 1 includes the address swapping circuit 13 will be described in the second embodiment.

[0107] The probability shaping decoding circuit 5 is configured on the premise of a circuit consisting of a group of hierarchically arranged look-up tables (LUTs) in the above-mentioned conventional circuit, and is configured such that an LUT for address conversion and an adder are additionally provided between the hierarchically arranged LUTs.

[0108] For example, as shown in Fig. 9, the probability shaping decoding circuit 5 includes a group of LUTs arranged in a tree-like hierarchy, namely LUT6-0, LUT6-1, LUT6-2, LUT6-3, LUT7-0, LUT7-1, and LUT8-0, and address conversion LUTs 53 (53a, 53b, 53c) and adders 54 (54a, 54b, 54c) provided between these LUTs. Data associated with an address is registered in each of these LUTs. The address conversion LUT 53 is also simply called the "address conversion LUT 53".

[0109] 9 shows a probability shaping decoding circuit 5 having LUTs arranged in a three-layer tree structure. However, the number of layers of the LUTs may be two or less or four or more, as long as it is the same as that of the probability shaping encoding circuit 1. LUT6-0, LUT6-1, LUT6-2, and LUT6-3 are LUTs in the 0th layer, which is the lowest layer. LUT7-0 and LUT7-1 are LUTs in the 1st layer, which is an intermediate layer. LUT7-0 is connected to LUT6-0 and LUT6-1 in the immediately lower layer via an address conversion LUT53a and an adder54a, and LUT7-1 is connected to LUT6-2 and LUT6-3 in the immediately lower layer via an address conversion LUT53b and an adder54b.

[0110] The LUT8-0 is a LUT in the second layer, which is the top layer, and is connected to the LUT7-0 and LUT7-1 in the layer immediately below via an address conversion LUT 53c and an adder 54c.

[0111] Each of LUT6-0, LUT6-1, LUT6-2, LUT6-3, LUT7-0, LUT7-1 and LUT8-0 manages a signal space. For example, the signal space managed by LUT6-0 is the space (S0) of two QAM signals, the signal space managed by LUT6-1 is the space (S1) of another two QAM signals, the signal space managed by LUT6-2 is the space (S2) of still another two QAM signals, and the signal space managed by LUT6-3 is the space (S3) of still another two QAM signals. At this time, the signal space managed by LUT7-0 is the signal space S0 and S1 managed by LUT6-0 and LUT6-1, and the signal space managed by LUT7-1 is the signal space S2 and S3 managed by LUT6-2 and LUT6-3. The signal space managed by LUT8-0 is the signal spaces S0, S1, S2, and S3 managed by LUT7-0 and LUT7-1. The signal points are points of complex amplitude values ​​in the signal space diagram.

[0112] Received shaped bit strings, which are bit strings corresponding to the signal point information from LUT4-0, LUT4-1, LUT4-2, and LUT4-3 in the stochastic shaping coding circuit 1, are input to LUT6-0, LUT6-1, LUT6-2, and LUT6-3.

[0113] LUT6-0 and LUT6-1 recover from the received shaping bit string a portion of the external input information input to LUT4-0 and LUT4-1 in the probability shaping encoding circuit 1 as part of the received information bit string, and also recover the designated information from LUT3-0 in the hierarchy immediately above LUT4-0 and LUT4-1 as a first received address bit string and a second received address bit string.

[0114] The address conversion LUT 53a converts the first received address bit string, which is the designation information output from the LUT 6-1, into a predetermined converted received address bit string, and outputs the converted bit string to the adder 54a. This converted received address bit string is information equivalent to an offset value that is added to the second received address bit string, which is the designation information output from the LUT 6-0, in the adder 54a.

[0115] The adder 54a adds the converted received address bit string output from the address conversion LUT 53a to the second received address bit string, which is the specification information output from LUT 6-0, and outputs the first received shaped bit string, which is a bit sequence indicating the addition result, to LUT 7-0 of the first layer, which is the intermediate layer.

[0116] LUT6-2 and LUT6-3 recover from the received shaping bit string a portion of the external input information input to LUT4-2 and LUT4-3 in the probability shaping encoding circuit 1 as part of the received information bit string, and also recover the designated information from LUT3-1 in the hierarchy immediately above LUT4-2 and LUT4-3 as a first received address bit string and a second received address bit string.

[0117] The address conversion LUT 53b converts the first received address bit string, which is the designation information output from the LUT 6-3, into a predetermined converted received address bit string, and outputs the converted bit string to the adder 54b. This converted received address bit string is information corresponding to an offset value added to the second received address bit string, which is the designation information output from the LUT 6-2, in the adder 54b.

[0118] The adder 54b adds the converted received address bit string output from the address conversion LUT 53b to the second received address bit string, which is the specification information output from the LUT 6-2, and outputs the first received shaped bit string, which is a bit sequence indicating the addition result, to the LUT 7-1 of the first layer, which is the intermediate layer.

[0119] LUT7-0 in the first layer, which is the intermediate layer, recovers part of the external input information input to LUT3-0 in the probability shaping coding circuit 1 from the first received shaping bit string input from adder 54a in the immediately lower layer as part of the received information bit string, and also recovers the designated information from LUT2-0 in the immediately higher layer of LUT3-0 as a second received address bit string.

[0120] The LUT7-1 in the first layer, which is the intermediate layer, recovers part of the external input information input to the LUT3-1 in the probability shaping coding circuit 1 from the first received shaping bit string input from the adder 54b in the immediately lower layer as part of the received information bit string, and also recovers the designated information from the LUT2-0 in the immediately higher layer of the LUT3-1 as the first received address bit string.

[0121] The address conversion LUT 53c converts the first received address bit string, which is the designation information output from the LUT 7-1, into a predetermined converted received address bit string, and outputs the converted bit string to the adder 54c. This converted received address bit string is information corresponding to an offset value that is added to the second received address bit string, which is the designation information output from the LUT 7-0, in the adder 54c.

[0122] The adder 54c adds the converted received address bit string output from the address conversion LUT 53c to the second received address bit string, which is the specification information output from LUT7-0, and outputs the first received shaped bit string, which is a bit sequence indicating the addition result, to LUT8-0 of the second layer, which is the top layer.

[0123] The LUT8-0 in the second layer, which is the top layer, restores a portion of the external input information input to the LUT2-0 in the second layer in the stochastic shaping coding circuit 1 as part of the received information bit string from the first received shaping bit string input from the adder 54c in the immediately lower layer, and outputs all of the restored received information bit strings to the outside.

[0124] As described above, the processing in the probability shaping decoding circuit 5 is the same as the processing in the probability shaping encoding circuit 1 in that the input and output are interchanged.

[0125] Fig. 10 is a diagram showing an excerpt of a circuit configuration between the (x+1)th layer and the xth layer immediately below it as a representative example of the probability shaping decoding circuit 5 shown in Fig. 9. In the following explanation, for convenience of explanation, the (x+1)th layer will be written as "layer x+1" and the xth layer will be written as "layer x". In addition, in Fig. 10, the LUTs shown in Fig. 9 are generalized to a form independent of the layer, and these LUTs are indicated by the reference characters 51, 52, 53, and 55.

[0126] 10, the first LUT 51 of layer x is denoted as LUT[x][1], the second LUT 52 of layer x is denoted as LUT[x][2], the first address conversion LUT 53 of layer x is denoted as ACLUT[x][1], and the first LUT 55 of layer x+1 is denoted as LUT[x+1][1]. In addition, in FIG. 10, the number of bits of the input / output bit strings in each of the first LUT 51 of layer x, the second LUT 52 of layer x, the first address conversion LUT 53 of layer x, the first adder 54 of layer x, and the first LUT 55 of layer x+1 are denoted by symbols A and B (both are non-negative integers). At this time, the relationship 2A>B≧A is established between the number of bits.

[0127] <First LUT51 of layer x> The first LUT 51 of layer x receives a first received shaped bit string of layer x from an external source (not shown) and outputs a first received bit string of layer x. Specifically, the first LUT 51 of layer x converts the input first received shaped bit string of layer x into a first received bit string of layer x by referring to a table and outputs the converted bit string.

[0128] Here, the first received bit string of layer x, which is the output, is composed of the first received address bit string of layer x (number of bits: A) which is the input to the address conversion LUT 53 described later, and the first received information bit string of layer x to the outside (not shown). In other words, the first LUT 51 of layer x restores the first received address bit string of layer x and the first received information bit string of layer x from the first received shaping bit string of layer x.

[0129] <Layer x's second LUT52> The second LUT 52 of layer x receives the second received shaped bit string of layer x from an external source (not shown) and outputs the second received bit string of layer x. Specifically, the second LUT 52 of layer x converts the input second received shaped bit string of layer x into the second received bit string of layer x by referring to a table and outputs it.

[0130] Here, the second received bit string of layer x, which is output, is composed of the second received address bit string of layer x (number of bits: A) which is input to an adder 54 described later, and the second received information bit string of layer x to the outside (not shown). In other words, the second LUT 52 of layer x restores the second received address bit string of layer x and the second received information bit string of layer x from the second received shaping bit string of layer x.

[0131] <First address translation LUT53 of layer x> The first address conversion LUT 53 of layer x receives the first received address bit string (number of bits: A) of layer x output from the first LUT 51 of layer x, and outputs the first converted received address bit string (number of bits: B) of layer x, which is input to the adder 54 described later.

[0132] Specifically, the first address conversion LUT 53 of layer x converts the input first received address bit string of layer x into a first converted received address bit string of layer x by referring to a table, and outputs the converted address bit string.

[0133] The value indicated by the first converted received address bit string of layer x, which is the output, corresponds to an offset value determined based on the first received address bit string of layer x, which is the input. This first converted received address bit string of layer x is added to the second received address bit string of layer x output from the second LUT 52 of layer x in a first adder 54 of layer x, which will be described later.

[0134] <First adder 54 of layer x> The first adder 54 of layer x adds the first converted received address bit string of layer x (number of bits: B) output from the first address conversion LUT 53 of layer x to the second received address bit string of layer x (number of bits: A) output from the second LUT 52 of layer x, and outputs the addition result as the first received shaping bit string of layer x+1 (number of bits: B) to the first LUT 55 of layer x+1 described later.

[0135] Here, an example of the processing by the address conversion LUT 53 and the adder 54 will be described with reference to Fig. 4. For example, consider a case where the stochastic shaping coding circuit 1 uses a signal point arrangement of 4096 ways (B=12 bits) shown by reference numeral 401 in Fig. 4. Also assume that A=8 bits.

[0136] In this case, each signal point constellation is expressed as a combination of a first address (Address1) and a second address (Address2), and each signal point constellation is expressed as an address Addr after addition processing by an adder 54, for example, as shown in the following equation (1). Addr=A_offset[Address1]+Address2 (1)

[0137] Here, A_offset[Address1] is an offset value determined according to the first address, and is set in the address conversion LUT 53. For example, A_offset[Address1] is set as follows: when the first address is 0, A_offset[0]=0; when the first address is 1, A_offset[1]=256; when the first address is 2, A_offset[2]=512; when the first address is 255, A_offset

[0255] =x (where x≦4095); etc.

[0138] For example, when the number of bits in the first address and the second address are both 8 bits, and the first address is "1" and the second address is "1", the signal point constellation expressed by the combination of this first address and second address is "0000000100000001." This bit string can be expressed as the result of adding an offset value of "100000000" (=256) to the second address "00000001."

[0139] Furthermore, when the number of bits in the first address and the second address are both 8 bits, and the first address is "2" and the second address is "1", the signal point constellation expressed by the combination of this first address and second address is "0000001000000001." This bit string can be expressed as the result of adding an offset value of "1000000000" (=512) to the second address "00000001."

[0140] This allows the address conversion LUT 53 and the adder 54 to accurately restore, as a received shaped bit string, the transmission shaped bit string that has been allocated to two bit strings using an offset value in the allocation circuit 12 of the probability shaping encoding circuit 1. This also allows the address conversion LUT 53 and the adder 54 to use the address space resulting from the combination of the first address and the second address without waste.

[0141] In addition, since the 4096 possible signal point arrangements indicated by symbol 401 are defined by B (=12) bits, the converted received address bit string (i.e., A_offset[Address1]) output from the address conversion LUT 53 and the received shaped bit string (i.e., Addr shown in equation (1)) after addition processing by the adder 54 do not exceed B bits.

[0142] <First LUT55 of layer x+1> The first LUT 55 of the layer x+1 receives the output of the first adder 54 of the layer x, The first received shaped bit string (number of bits: B) of layer x+1 is input, and the first received bit string (number of bits: B) of layer x+1 is output to an external device (not shown).

[0143] Specifically, the first LUT 55 of layer x+1 converts the input first received shaped bit sequence of layer x+1 into a first received bit sequence of layer x+1 by referring to a table, and outputs the converted first received bit sequence of layer x+1.

[0144] Here, the first reception bit string of layer x+1, which is output, is composed of, for example, a first reception address bit string of layer x+1 to the outside (not shown) and a first reception information bit string of layer x+1 to the outside (not shown). That is, the first LUT 55 of layer x+1 restores the first reception address bit string of layer x+1 and the first reception information bit string of layer x+1 from the first reception shaping bit string of layer x+1. However, when layer x+1 is the top layer, the first reception address bit string of layer x+1 is 0.

[0145] In the above description, the first LUT 51 of layer x, the second LUT 52 of layer x, and the first LUT 55 of layer x+1 each restore the received information bit string. However, each of these LUTs does not necessarily need to restore the received information bit string. For example, in the stochastic shaping encoding circuit 1 on the transmitting side, when the number of bits of each transmission information bit string input to one or more of the first LUT 11 of layer x+1, the first LUT 14 of layer x, and the second LUT 15 of layer x is 0, the number of bits of the received information bit string restored by one or more LUTs corresponding to the LUTs in which the number of bits of the transmission information bit string is set to 0 among the first LUT 51 of layer x, the second LUT 52 of layer x, and the first LUT 55 of layer x+1 may be 0 in the stochastic shaping decoding circuit 5 on the receiving side. In this case, the stochastic shaping decoding circuit 5 can accurately restore the received information bit string.

[0146] Also, for example, in the transmitting side probability shaping encoding circuit 1, when the layer x is the lowest layer, and the number of bits of at least one of the first transmission information bit string of layer x input to the first LUT 14 of layer x and the second transmission information bit string of layer x input to the second LUT 15 of layer x is set to 0, in the receiving side probability shaping decoding circuit 5, the number of bits of each reception information bit string restored by at least one of the LUTs corresponding to the LUT in which the number of bits of the transmission information bit string is set to 0 among the first LUT 51 of layer x and the second LUT 52 of layer x may be 0. In this case, the probability shaping decoding circuit 5 can accurately restore the reception information bit string.

[0147] Next, the effect of the probability shaping decoding circuit 5 according to the first embodiment will be described with reference to FIG.

[0148] Fig. 11A shows a configuration example of a conventional probability shaping decoding circuit (hereinafter also referred to as the "conventional example"), and Fig. 11B shows a configuration example of the probability shaping decoding circuit 5 according to the first embodiment (hereinafter also referred to as the "present configuration example"). The only difference between the conventional example and the present configuration example is whether or not an address conversion LUT 53 and an adder 54 are provided.

[0149] 11A and 11B, the number of bits of the bit string input and output to each component is indicated by A and B. If A is 6 bits and B is 10 bits, for example, in the conventional example shown in FIG. 11A, the number of bits of the input / output bit string to the first LUT 55 of layer x+1 is 12 bits (=A×2) for input and 10 bits (=B) for output. In this case, the scale of the first LUT 55 of layer x+1 in the conventional example is B×2 2A =10×2 12 =40960.

[0150] On the other hand, in the present configuration example shown in FIG. 11B, the number of bits of the input / output bit string for the first LUT 55 of the layer x+1 is 10 bits (=B) for input and 10 bits (=B) for output. In this case, the scale of the first LUT 55 of the layer x+1 in this configuration example is B×2 B =10×2 10 =10240.

[0151] 11B, the number of bits of the input / output bit string for the first address conversion LUT 53 of layer x is 6 bits (=A) for input and 10 bits (=B) for output. In this case, the scale of the first address conversion LUT 53 of layer x in this configuration example is B×2 A =10×2 6 =640.

[0152] Therefore, in this configuration example shown in FIG. 11B, the sum of the size of the first LUT 55 in the layer x+1 and the size of the first address conversion LUT 53 in the layer x is 10880 (=10240+640).

[0153] Therefore, in this configuration example, the scale of the LUT can be reduced to about 1 / 4 of the scale of the conventional example. Generally, for an LUT of this scale (e.g., an LUT of the order of 10 kilobits), the scale of the adder 54 is about 10 bits, which is sufficiently small and negligible.

[0154] In the conventional example, in order to suppress performance degradation, it is necessary to increase the number of input / output bits for each LUT (for example, the first LUT 55 of layer x+1), but increasing the number of input / output bits increases the circuit scale. On the other hand, in this configuration example, an address conversion LUT 53 and an adder 54 are provided in front of the first LUT 55 of layer x+1, and the above-mentioned processing is performed by these circuits, thereby making it possible to reduce the circuit scale while suppressing performance degradation compared to the conventional example. In particular, in this configuration example, the effect is remarkable by setting the relationship of the number of bits of the input / output bit string for each component to 2A>B≧A.

[0155] Next, an example of the operation of the probability shaping decoding circuit 5 according to the first embodiment will be described with reference to the flowchart shown in Fig. 12. This flowchart starts with m=1, x=1.

[0156] First, the mth LUT 51 of layer x converts the (2-1)th received shaped bit string of layer x into the (2-1)th received address bit string of layer x and the (2-1)th received information bit string of layer x by referring to a table (step ST11).

[0157] Next, the mth LUT 52 of layer x converts the 2mth received shaped bit string of layer x into a 2mth received address bit string of layer x and a 2mth received information bit string of layer x by referring to the table (step ST12).

[0158] Next, the m-th address conversion LUT 53 of the layer x converts the (2m-1)th received address bit string of the layer x into the (2m-1)th converted received address bit string of the layer x by referring to the table (step ST13).

[0159] Next, the mth adder 54 of layer x adds the (2-1)th converted received address bit string of layer x to the 2mth received address bit string of layer x, converting it into the mth received shaped bit string of layer x+1 (step ST14).

[0160] Next, the probability shaping decoding circuit 5 judges whether m is equal to n[x] (step ST5), where n[x] is a natural number indicating how many units, each of which includes the LUT 51, the LUT 52, the address conversion LUT 53, and the adder 54, exist in one layer.

[0161] As a result, if it is determined that m is not equal to n[x] (step ST15; NO), m is counted up by one (step ST16), and the process returns to step ST11. On the other hand, if it is determined that m is equal to n[x] (step ST15; YES), the process proceeds to step ST17, and the probability shaping decoding circuit 5 determines whether or not x is equal to L-1 (step ST17), where L is the number of layers in the LUT group hierarchically arranged in a tree shape.

[0162] As a result, if it is determined that x is not equal to L-1 (step ST17; NO), x is counted up by one (step ST18), and the process returns to step ST11. On the other hand, if it is determined that x is equal to L-1 (step ST17; YES), the process proceeds to step ST19.

[0163] In step ST19, the first LUT 55 of layer x+1 (=L) converts the first received shaped bit sequence of layer x+1 into the first received bit sequence of layer x+1 by referring to the table (step ST19), and ends the process.

[0164] Fig. 13A is a block diagram showing a hardware configuration for realizing the functions of the probability shaping decoding circuit 5. Fig. 13B is a block diagram showing a hardware configuration for executing software for realizing the functions of the probability shaping decoding circuit 5.

[0165] When the processing circuit is the dedicated hardware processing circuit 500 shown in Fig. 13A, the processing circuit 500 corresponds to, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination of these. The function of the LUT in the probability shaping decoding circuit 5 may be realized by a separate processing circuit, or these functions may be realized together by one processing circuit.

[0166] When the processing circuit is the processor 501 shown in Fig. 13B, the function of the LUT in the probability shaping decoding circuit 5 is realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 502. The processor 501 realizes the function of the LUT in the probability shaping decoding circuit 5 by reading and executing the program stored in the memory 502. That is, the probability shaping decoding circuit 5 includes a memory 202 for storing a program that, when executed by the processor 501, results in the processing of steps ST11 to ST19 shown in Fig. 12 being executed.

[0167] These programs cause a computer to execute the procedure or method of the LUT in the probability shaping decoding circuit 5. The memory 502 may be a computer-readable storage medium having stored therein a program for causing a computer to function as the LUT in the probability shaping decoding circuit 5.

[0168] Memory 502 may include, for example, non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically-EPROM), magnetic disks, flexible disks, optical disks, compact disks, mini disks, DVDs, etc.

[0169] As described above, according to the first embodiment, the probability shaping decoding circuit 5, where x, m, and n[x] are natural numbers (m=1, 2, . . . , n[x]), includes a (2m-1)th lookup table 51 for layer x that restores, from the (2m-1)th received shaped bit sequence of layer x, the (2m-1)th received address bit sequence of layer x and the (2m-1)th received information bit sequence of layer x, which is a part of the information bit sequence of the communication target, and a 2mth lookup table 52 for layer x that restores, from the 2mth received shaped bit sequence of layer x, the 2mth received address bit sequence of layer x and the 2mth received information bit sequence of layer x, which is a part of the information bit sequence of the communication target, and the mth address conversion lookup table 53 of layer x converting the (2m-1)th converted received address bit sequence of layer x into a (2m-1)th converted received address bit sequence of layer x corresponding to an offset value to be added to the 2mth received address bit sequence of layer x, the mth adder 54 of layer x adding the (2m-1)th converted received address bit sequence of layer x to the 2mth received address bit sequence of layer x and outputting a bit sequence indicating the addition result as the mth received shaped bit sequence of layer x+1, and the mth lookup table 55 of layer x+1 restoring the mth received address bit sequence of layer x+1 and the mth received information bit sequence of layer x, which is a part of the information bit sequence of the communication target, from the mth received shaped bit sequence of layer x+1. Each lookup table is hierarchically arranged in a tree shape, and the received shaped bit sequence input to each lookup table corresponds to designation information designating a combination of signal points in a signal space managed by each lookup table, or signal point information indicating a signal point arrangement in the signal space. As a result, the probability shaping decoding circuit 5 according to the first embodiment can reduce the circuit scale while suppressing performance degradation compared to conventional circuits.

[0170] In addition, in the probability shaping decoding circuit 5, where A and B are non-negative integers, A is the number of bits of the (2m-1)th received address bit string of layer x that is restored in the (2m-1)th lookup table 51 of layer x and input to the mth address conversion lookup table 53 of layer x, A is the number of bits of the 2mth received address bit string of layer x that is restored in the 2mth lookup table 52 of layer x and input to the mth adder 54 of layer x, B is the number of bits of the (2m-1)th converted received address bit string of layer x that is converted in the mth address conversion lookup table 53 of layer x and input to the mth adder 54 of layer x, and B is the number of bits of the mth received shaping bit string of layer x+1 that is output from the mth adder 54 of layer x. Then, the number of combinations of the (2m-1)th received address bit string of layer x and the 2mth received address bit string of layer x is 2 to the power of B, and 2A>B≧A. As a result, the probability shaping decoding circuit 5 according to the first embodiment can achieve significant effects of suppressing performance degradation and reducing the circuit scale compared to conventional circuits.

[0171] Moreover, in the probability shaping decoding circuit 5, the number of bits of the received information bit sequence restored in any one of the lookup tables is 0. This allows the probability shaping decoding circuit 5 according to the first embodiment to accurately restore the received information bit sequence.

[0172] Furthermore, when layer x is the lowest layer, the probability shaping decoding circuit 5 determines that the number of bits in at least one of the (2m-1)th received information bit sequence of layer x restored in the (2m-1)th lookup table 51 of layer x and the 2mth received information bit sequence of layer x restored in the 2mth lookup table 52 of layer x is 0. This allows the probability shaping decoding circuit 5 according to embodiment 1 to accurately restore the received information bit sequence.

[0173] Furthermore, in the probability shaping decoding circuit 5, when layer x+1 is the highest layer, the number of bits of the m-th received address bit string of layer x+1 restored in the m-th lookup table 55 of layer x+1 is 0. This makes it possible for the probability shaping decoding circuit 5 according to embodiment 1 to suppress an increase in circuit scale compared to conventional circuits.

[0174] Furthermore, in the probability shaping decoding circuit 5, when layer x is the lowest layer, the (2m-1)th received shaping bit sequence of layer x input to the (2m-1)th lookup table 51 of layer x and the 2mth received shaping bit sequence of layer x input to the 2mth lookup table 52 of layer x correspond to signal point information indicating a signal point arrangement in a signal space managed by each of the lookup tables. As a result, the probability shaping decoding circuit 5 according to the first embodiment can restore the received information bit sequence from the signal point information indicating a signal point arrangement in a signal space managed by each lookup table of the lowest layer.

[0175] Embodiment 2 In the first embodiment, the probability shaping decoding circuit 5 is described in the case where the address swapping circuit 13 is omitted in the probability shaping encoding circuit 1 on the transmitting side. In the second embodiment, the probability shaping decoding circuit 5b is described in the case where the probability shaping encoding circuit 1 on the transmitting side is provided with the address swapping circuit 13.

[0176] 14 is a block diagram showing the configuration of the probability shaping decoding circuit 5b according to the second embodiment, and shows an excerpt of the circuit configuration between the (x+1)th layer and the xth layer immediately below it as a representative example. The probability shaping decoding circuit 5b according to the second embodiment has a first address swapping circuit 56 of layer x added to the probability shaping decoding circuit 5 according to the first embodiment. The other configurations of the probability shaping decoding circuit 5b according to the second embodiment are the same as those of the probability shaping decoding circuit 5 according to the first embodiment shown in FIG. 1, so the same reference numerals are used and the description thereof is omitted.

[0177] <First Address Swap Circuit 56 of Layer x> The first address swapping circuit 56 of layer x is provided between the first LUT 51 of layer x and the second LUT 52 of layer x and the first address conversion LUT 53 of layer x and the first adder 54 of layer x, as shown in FIG. 14.

[0178] The first address replacement circuit 56 of layer x receives the first receiving address bit string (number of bits: A) of layer x output from the first LUT 51 of layer x and the second receiving address bit string (number of bits: A) of layer x output from the second LUT 52 of layer x, and outputs the first receiving source address bit string (number of bits: A) of layer x to the first address conversion LUT 53 of layer x, the second receiving source address bit string (number of bits: D) of layer x to the first adder 54 of layer x, and the first receiving address replacement bit of layer x to the outside (not shown). Of these, the first receiving address replacement bit of layer x becomes part of the receiving information bit string output to the outside.

[0179] A description will be given of an example of the processing of the first address swapping circuit 56 in the layer x. The first address swapping circuit 56 in the layer x basically performs processing that is the reverse of the processing of the address swapping circuit 13 in the probability shaping encoding circuit 1.

[0180] For example, the first address swapping circuit 56 in layer x determines the content of the processing depending on the magnitude relationship between the value indicated by the first received address bit string in layer x, which is the input, and the value indicated by the second received address bit string in layer x.

[0181] Specifically, the first address switching circuit 56 of the layer x performs processing according to the following four cases: An example of an algorithm describing the processing in the following four cases is shown in FIG. (1) Case A': The value indicated by the first received address bit string in layer x is greater than the value indicated by the second received address bit string in layer x. (2) Case B': The value indicated by the first received address bit string in layer x is smaller than the value indicated by the second received address bit string in layer x. (3) Case C': The value indicated by the first received address bit string in layer x is equal to the value indicated by the second received address bit string in layer x, and both are even numbers. (4) Case D': The value indicated by the first received address bit string in layer x is equal to the value indicated by the second received address bit string in layer x, and both are odd numbers.

[0182] (Case A´) The first address swapping circuit 56 in layer x outputs "0" as the first receiving address swapping bit in layer x, outputs the first receiving address bit string in layer x as the first receiving source address bit string in layer x, and outputs the second receiving address bit string in layer x as the second receiving source address bit string in layer x.

[0183] (Case B´) The first address swapping circuit 56 in layer x outputs "1" as the first receiving address swapping bit in layer x, outputs the second receiving address bit string in layer x as the first receiving source address bit string in layer x, and outputs the first receiving address bit string in layer x as the second receiving source address bit string in layer x.

[0184] (Case C´) The first address swapping circuit 56 in layer x outputs "0" as the first receiving address swapping bit in layer x, outputs the first receiving address bit string in layer x as the first receiving source address bit string in layer x, and outputs the second receiving address bit string in layer x as the second receiving source address bit string in layer x.

[0185] (Case D´) The first address swapping circuit 56 in layer x outputs "1" as the first receiving address swapping bit in layer x, outputs a bit string indicating a value obtained by subtracting 1 from the value indicated by the first receiving address bit string in layer x as the first receiving source address bit string in layer x, and outputs a bit string indicating a value obtained by subtracting 1 from the value indicated by the second receiving address bit string in layer x as the second receiving source address bit string in layer x.

[0186] The above cases A' to D' correspond to the opposite cases to cases A to D in which the first address swapping circuit 13 of the layer x determines the processing contents in the probability shaping encoding circuit 1 described above.

[0187] In this case, the first address conversion LUT 53 of layer x receives the first source address bit string (number of bits: A) of layer x output from the first address swapping circuit 56 of layer x instead of the (2-1)th received address bit string of layer x, and outputs the first converted received address bit string (number of bits: B) of layer x, which is input to the adder 54 described later.

[0188] Specifically, the first address conversion LUT 53 in layer x converts the input first source address bit string in layer x into a first converted received address bit string in layer x by referring to a table, and outputs the converted bit string.

[0189] Moreover, the first adder 54 of layer x adds the second source address bit string (number of bits: D) of layer x output from the first address swapping circuit 56 of layer x to the first converted received address bit string (number of bits: B) of layer x output from the first address conversion LUT 53 of layer x, instead of the 2m received address bit string of layer x, and outputs the addition result as the first received shaped bit string of layer x+1 (number of bits: B) to the first LUT 55 of layer x+1. At this time, the relationship of the bit numbers is 2A>B≧A and A≧D.

[0190] In this way, the stochastic shaping decoding circuit 5b according to the second embodiment includes a first address swapping circuit 56 in layer x configured to perform a process basically inverse to the process of the address swapping circuit 13 in the stochastic shaping coding circuit 1. Here, when the stochastic shaping coding circuit 1 includes the address swapping circuit 13, as described above, the stochastic shaping coding circuit 1 can uniformly and efficiently express, for example, 4096 signal point arrangements shown by reference numeral 401 in FIG. 4. In this regard, the stochastic shaping decoding circuit 5b according to the second embodiment includes the first address swapping circuit 56 in layer x, and thus can accurately restore the received shaping bit sequence coded by the stochastic shaping coding circuit 1 including the address swapping circuit 13 in addition to the effect of the first embodiment.

[0191] In the above example, the first address replacement circuit 56 of layer x performs processing according to the above four cases. However, this is just one example, and the processing example is not limited to the above example. For example, the first address replacement circuit 56 of layer x basically only needs to perform processing opposite to that of the first address replacement circuit 13 of layer x in the probability shaping coding circuit 1, and if the processing content of the first address replacement circuit 13 of layer x changes, the processing content may be changed according to the change.

[0192] As described above, according to the second embodiment, the probability shaping decoding circuit 5b includes an mth address swapping circuit 56 in layer x that restores the (2m-1)th source address bit string in layer x, the 2mth source address bit string in layer x, and the mth receiving address swapping bit in layer x, which is part of the information bit sequence of the communication target, from the (2m-1)th receiving address bit string in layer x restored in the (2m-1)th lookup table 51 in layer x and the 2mth receiving address bit string in layer x restored in the 2mth lookup table 52 in layer x. The m-th address conversion lookup table 53 of the layer x converts the (2m-1)th source address bit string of the layer x restored by the m-th address swapping circuit 56 of the layer x into the (2m-1)th converted received address bit string of the layer x corresponding to the offset value added to the 2mth source address bit string of the layer x, and the m-th adder 54 of the layer x adds the 2mth source address bit string of the layer x and the (2m-1)th converted received address bit string of the layer x, instead of the 2mth received address bit string of the layer x, and outputs the bit string indicating the addition result as the m-th received shaping bit string of the layer x+1. As a result, the probability shaping decoding circuit 5b according to the second embodiment can accurately restore the received shaping bit string coded by the probability shaping coding circuit 1 equipped with the address swapping circuit 13 in addition to the effect of the first embodiment.

[0193] Furthermore, when the value indicated by the (2m-1)th reception address bit string of layer x is greater than the value indicated by the 2mth reception address bit string of layer x, the mth address replacement circuit 56 of layer x sets the mth reception address replacement bit of layer x to 0, sets the (2m-1)th reception address bit string of layer x to the (2m-1)th reception source address bit string of layer x, and sets the 2mth reception address bit string of layer x to the 2mth reception source address bit string of layer x. Furthermore, when the value indicated by the (2m-1)th reception address bit string of layer x is less than the value indicated by the 2mth reception address bit string of layer x, the mth reception address replacement bit of layer x to 1, sets the 2mth reception address bit string of layer x to the (2m-1)th reception source address bit string of layer x, and sets the (2m-1)th reception address bit string of layer x to the 2mth reception source address bit string of layer x. Furthermore, if the value indicated by the (2m-1)th receiving address bit string in layer x is equal to the value indicated by the 2mth receiving address bit string in layer x and both are even numbers, the mth receiving address swap bit in layer x is set to 0, the (2m-1)th receiving address bit string in layer x is set to the (2m-1)th receiving source address bit string in layer x, and the 2mth receiving address bit string in layer x is set to the 2mth receiving source address bit string in layer x. Moreover, when the value indicated by the (2m-1)th reception address bit string of layer x is equal to the value indicated by the 2mth reception address bit string of layer x and both are odd numbers, the mth reception address swap bit of layer x is set to 1, the bit string indicating the value obtained by subtracting 1 from the value indicated by the (2m-1)th reception address bit string of layer x is set to the (2m-1)th reception source address bit string of layer x, and the bit string indicating the value obtained by subtracting 1 from the value indicated by the 2mth reception address bit string of layer x is set to the 2mth reception source address bit string of layer x. As a result, the probability shaping decoding circuit 5b according to the second embodiment can accurately restore the reception shaping bit string coded by the probability shaping coding circuit 1 including the address swapping circuit 13 in addition to the effect of the first embodiment.

[0194] In addition, the present disclosure allows free combination of the respective embodiments, modification of any of the components of each embodiment, or omission of any of the components of each embodiment. [Industrial Applicability]

[0195] The present disclosure makes it possible to reduce the circuit scale while suppressing performance degradation compared to conventional circuits, and is suitable for use in a probability shaping decoding circuit and a probability shaping decoding method. [Explanation of symbols]

[0196] 1 probability shaping coding circuit, 2-0, 3-0, 3-1, 4-0, 4-1, 4-2, 4-3, 6-0, 6-1, 6-2, 6-3, 7-0, 7-1, 8-0, 11, 14, 15, 51, 52, 55 lookup table (LUT), 12, 12a, 12b, 12c allocation circuit, 13, 13a, 13b, 13c, 56, 56a, 56b, 56c address swapping circuit, 53, 53a, 53b, 53c address conversion lookup table (LUT), 54, 54a, 54b, 54c adder, 100, 500 processing circuit, 101, 501 processor, 102, 502 memory, 401 signal point arrangement, L straight line.

Claims

1. Let x, m, and n[x] be natural numbers (m = 1, 2, ..., n[x]), a (2m-1)th lookup table of layer x for restoring a (2m-1)th received address bit string of layer x and a (2m-1)th received information bit string of layer x, which is a part of an information bit sequence of a communication target, from the (2m-1)th received shaped bit string of layer x; a 2mth lookup table in layer x for restoring a 2mth received address bit string in layer x and a 2mth received information bit string in layer x, which is a part of an information bit sequence to be communicated, from the 2mth received shaped bit string in layer x; an m-th address conversion lookup table for layer x, which converts the (2-1)-th received address bit string of layer x into the (2-1)-th converted received address bit string of layer x corresponding to an offset value added to the 2m-th received address bit string of layer x; an m-th adder in layer x that adds the (2-1)th converted received address bit string in layer x to the 2mth received address bit string in layer x and outputs a bit string indicating the addition result as the m-th received shaped bit string in layer x+1; an m-th lookup table in layer x+1 that restores the m-th received address bit string in layer x+1 and the m-th received information bit string in layer x, which is a part of the information bit string to be communicated, from the m-th received shaped bit string in layer x+1; Equipped with Each of the lookup tables is hierarchically arranged in a tree shape, The received shaped bit sequence input to each lookup table corresponds to designation information that designates a combination of signal points in a signal space managed by each lookup table, or signal point information that indicates a signal point arrangement in the signal space. A probability shaping decoding circuit comprising:

2. Let A and B be non-negative integers, Let A be the number of bits of the (2-1)th received address bit string of layer x that is restored in the (2-1)th lookup table of layer x and input to the mth address conversion lookup table of layer x. Let A be the number of bits of the 2mth received address bit string of layer x that is restored in the 2mth lookup table of layer x and input to the mth adder of layer x. The number of bits of the (2-1)th converted received address bit string of layer x that is converted by the mth address conversion lookup table of layer x and input to the mth adder of layer x is denoted by B, When the number of bits of the m-th received shaped bit sequence of layer x+1 output from the m-th adder of layer x is B, The probability shaping decoding circuit according to claim 1, characterized in that the number of combinations of the (2m-1)th received address bit string of layer x and the 2mth received address bit string of layer x is 2 to the power of B, and 2A > B ≧ A.

3. The number of bits of the received information bit string restored by any one of the lookup tables is 0.

3. The probability shaping decoding circuit according to claim 1 or 2.

4. When layer x is the lowest layer, The number of bits in at least one of the (2m-1)th reception information bit sequence of the layer x restored in the (2m-1)th lookup table of the layer x and the 2mth reception information bit sequence of the layer x restored in the 2mth lookup table of the layer x is 0.

3. The probability shaping decoding circuit according to claim 1 or 2.

5. When layer x+1 is the highest layer, The number of bits in the m-th received address bit string in the layer x+1 restored in the m-th lookup table in the layer x+1 is 0.

3. The probability shaping decoding circuit according to claim 1 or 2.

6. When layer x is the lowest layer, The (2m-1)th reception shaped bit sequence of layer x input to the (2m-1)th lookup table of layer x and the 2mth reception shaped bit sequence of layer x input to the 2mth lookup table of layer x correspond to signal point information indicating a signal point arrangement of a signal space managed by each lookup table.

3. The probability shaping decoding circuit according to claim 1 or 2.

7. From the (2-1)th reception address bit string of layer x restored in the (2-1)th lookup table of layer x and the 2mth reception address bit string of layer x restored in the 2mth lookup table of layer x, a layer x m-th address replacement circuit for restoring a layer x (2-1)-th source address bit string, a layer x 2m-th source address bit string, and a layer x m-th destination address replacement bit that is a part of an information bit string to be communicated; The mth address translation lookup table of layer x is converting the (2-1)th source address bit string of the layer x restored by the mth address replacement circuit of the layer x into the (2-1)th converted received address bit string of the layer x corresponding to an offset value added to the 2mth source address bit string of the layer x; The mth adder of layer x is adding the 2mth source address bit string of the layer x to the (2m-1)th converted received address bit string of the layer x instead of the 2mth received address bit string of the layer x, and outputting a bit string indicating the addition result as the mth received shaped bit string of the layer x+1; 2. The probability shaping decoding circuit according to claim 1.

8. The mth address swap circuit of layer x is If the value indicated by the (2-1)th received address bit string of layer x is greater than the value indicated by the 2mth received address bit string of layer x, Set the m-th receive address swap bit of layer x to 0; The (2-1)th receiving address bit string of layer x is defined as the (2-1)th receiving source address bit string of layer x, The 2mth receiving address bit string in layer x is defined as the 2mth receiving source address bit string in layer x, If the value indicated by the (2-1)th received address bit string of layer x is smaller than the value indicated by the 2mth received address bit string of layer x, The m-th receive address swap bit of layer x is set to 1, The 2mth receiving address bit string of the layer x is defined as the (2-1)th receiving source address bit string of the layer x, The (2-1)th receiving address bit string of layer x is defined as the 2mth receiving source address bit string of layer x, If the value indicated by the (2-1)th received address bit string of layer x is equal to the value indicated by the 2mth received address bit string of layer x and both are even numbers, Set the m-th receive address swap bit of layer x to 0; The (2-1)th receiving address bit string of layer x is defined as the (2-1)th receiving source address bit string of layer x, The 2mth receiving address bit string in layer x is defined as the 2mth receiving source address bit string in layer x, If the value indicated by the (2-1)th received address bit string of layer x is equal to the value indicated by the 2mth received address bit string of layer x and both are odd numbers, The m-th receive address swap bit of layer x is set to 1, A bit string indicating a value obtained by subtracting 1 from a value indicated by the (2-1)th receiving address bit string of layer x is defined as the (2-1)th receiving source address bit string of layer x, The bit string indicating the value obtained by subtracting 1 from the value indicated by the 2mth reception address bit string of layer x is defined as the 2mth reception source address bit string of layer x.

8. The probability shaping decoding circuit according to claim 7.

9. A probability shaping decoding method using a probability shaping decoding circuit having a plurality of lookup tables hierarchically arranged in a tree shape, comprising: Let x, m, and n[x] be natural numbers (m = 1, 2, ..., n[x]), A step in which the (2m-1)th lookup table of layer x restores the (2m-1)th received address bit string of layer x and the (2m-1)th received information bit string of layer x, which is a part of the information bit sequence of the communication target, from the (2m-1)th received shaped bit string of layer x; A step in which a 2m-th lookup table of the layer x restores a 2m-th received address bit string of the layer x and a 2m-th received information bit string of the layer x, which is a part of an information bit sequence of a communication target, from the 2m-th received shaped bit string of the layer x; a step of converting the (2-1)th received address bit string of the layer x into a (2-1)th converted received address bit string of the layer x corresponding to an offset value added to the 2mth received address bit string of the layer x by an mth address conversion lookup table of the layer x; an m-th adder of layer x adding the (2-1)th converted received address bit string of layer x to the 2mth received address bit string of layer x, and outputting a bit string indicating the addition result as the m-th received shaped bit string of layer x+1; A step in which the m-th lookup table of the layer x+1 restores the m-th received address bit string of the layer x+1 and the m-th received information bit string of the layer x, which is a part of the information bit string of the communication target, from the m-th received shaped bit string of the layer x+1; having The received shaped bit sequence input to each lookup table corresponds to designation information that designates a combination of signal points in a signal space managed by each lookup table, or signal point information that indicates a signal point arrangement in the signal space. A probability shaping decoding method comprising:

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