Processing device and calculation method

Abstract

To execute division at a high speed by reducing the number of logic stages included in a critical path of a recurrence formula arithmetic part and increasing the number of bits of a partial quotient calculated by single arithmetic processing by a recurrence formula.SOLUTION: An arithmetic processing device holds a product of an approximation value D of an inverse number of a divisor Y held in a table in each divisor Y of a prescribed range and a doubled operation value of a dividend X generated on the basis of comparison of the dividend X with the divisor Y or an operation value equal to the dividend X as an initial value (0) of a partial remainder R(n), calculates a product DY of the approximation value D output from the table and the divisor Y, calculates a product DY*q(n) of the product DY and a partial quotient q(n) being a prescribed number of upper bits of the held partial remainder R(n), calculates a new partial remainder R(n) by subtracting the product DY*q(n) with the partial quotient q(n) from the held partial remainder R(n) and left-shifting a prescribed number of bits, and arranges the partial quotient q(n) at a prescribed bit position of a quotient.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a processor and a computing method. [Background technology]

[0002] In a floating-point divider mounted on a processing unit, a method is known in which, when determining a quotient of a mantissa, a partial remainder and a partial quotient are calculated sequentially by repeating a subtraction and shift process using a recurrence formula (see, for example, Patent Documents 1 and 2). In this type of floating-point divider, a partial quotient of multiple bits is calculated by a single subtraction and shift process, thereby increasing the operation speed compared to the case where the quotient is calculated one bit at a time. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-118633 A [Patent Document 2] JP 2000-298576 A [Patent Document 3] US Patent Application Publication No. 2006 / 0294177 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional deduction and shift processing method using the recurrence formula, the partial quotient that can be calculated in one deduction and shift processing is limited to about 2 bits due to the delay critical path of the circuit that executes one deduction and shift processing.

[0005] In one aspect, the present invention aims to perform division quickly by reducing the number of logic stages included in the critical path of the recurrence formula calculation unit and increasing the number of bits of the partial quotient calculated in one calculation process using the recurrence formula. [Means for solving the problem]

[0006] According to one aspect, the arithmetic processing device includes a table that holds an approximation value D that approximates a reciprocal 1 / Y of a divisor Y for each divisor Y in a predetermined range; a first multiplication unit that calculates a product DY of the approximation value D output from the table corresponding to the divisor Y and the divisor Y; a dividend manipulation unit that compares the magnitudes of a dividend X and the divisor Y, and generates a manipulation value that is twice the dividend X when the dividend X is smaller than the divisor Y, and generates the manipulation value equal to the dividend X when the dividend X is equal to or larger than the divisor Y; a second multiplication unit that calculates the product of the approximation value D and the manipulation value as an initial value R(0) of a partial remainder R(n); a holding unit that holds the partial remainder R(n); and a multiplication unit that calculates a product DY and a higher order part of the partial remainder R(n) held in the holding unit. kbits a third multiplication unit for calculating a product DY*q(n) with a partial quotient q(n) such that kbits a first addition unit that calculates a new partial remainder R(n) by shifting the left side of the quotient q(n) and stores the calculated new partial remainder R(n) in the holding unit; and a quotient generation unit that places the partial quotient q(n) in a predetermined bit position of the quotient. death, The k bits are a fixed value determined by the accuracy of the approximation value D. . Effect of the Invention

[0007] Division can be performed quickly by reducing the number of logic stages included in the critical path of the recurrence formula calculation section and increasing the number of bits of the partial quotient calculated in one calculation process using the recurrence formula. [Brief description of the drawings]

[0008] [Figure 1] FIG. 2 is a block diagram illustrating an example of a processor according to an embodiment. [Diagram 2] FIG. 2 is a block diagram showing an example of a computing unit of FIG. 1. [Diagram 3] FIG. 3 is a block diagram illustrating an example of the floating-point divider of FIG. 2. [Figure 4] 4 is a circuit diagram illustrating an example of a quotient generation unit in FIG. 3. [Diagram 5] 4 is an explanatory diagram showing an example in which the partial quotient q(n) is right bit-shifted by the quotient generation unit in FIG. 3 to match the bit position of the quotient Q(n+1). FIG. [Figure 6] 4 is a flow diagram illustrating an example of the operation of the floating-point divider of FIG. 3. [Figure 7] FIG. 13 is a block diagram showing an example of a recurrence formula calculation unit of a calculation processing device according to another embodiment. [Figure 8] FIG. 13 is a block diagram showing an example of a recurrence formula calculation unit of a calculation processing device according to another embodiment. [Figure 9] FIG. 13 is a block diagram showing an example of a recurrence formula calculation unit of a calculation processing device according to another embodiment. [Figure 10] 9 is a circuit diagram illustrating an example of a quotient generation unit in FIG. 8. [Figure 11] FIG. 13 is a block diagram showing an example of a recurrence formula calculation unit of a calculation processing device according to another embodiment. [Figure 12] FIG. 13 is a block diagram showing an example of a recurrence formula calculation unit of a floating-point divider of another arithmetic processing device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, embodiments will be described with reference to the drawings.

[0010] Fig. 1 shows an example of a processing device according to an embodiment. A processor 100, which is an example of the processing device shown in Fig. 1, has multiple cores 110 and an L2 cache 150. Each core 110 has an arithmetic unit 120, a control unit 130, and an L1 cache 140.

[0011] The arithmetic unit 120 reads data from the L1 cache to a built-in register based on a load instruction, and stores data from the register to the L1 cache 140 based on a store instruction. The arithmetic unit 120 also executes an operation using data held in the register based on an operation instruction, and stores the operation result in the register. An example of the arithmetic unit 120 is shown in FIG. 2.

[0012] The control unit 130 includes, for example, an instruction fetch unit, an instruction buffer unit, an instruction decode unit, and a reservation station (not shown). The instruction fetch unit fetches instructions from the L1 cache 140 and stores the fetched instructions in the instruction buffer unit. The instruction decode unit sequentially decodes the instructions held in the instruction buffer unit and inputs the decoded instructions to the reservation station. The reservation station holds the instructions input from the instruction decode unit and issues them to the arithmetic unit 120 in order starting from executable instructions.

[0013] When the L1 cache 140 holds operand data requested by the arithmetic unit 120 or instruction data requested by the control unit 130 (cache hit), it outputs the held data to the arithmetic unit 120 or the control unit 130. When the L1 cache 140 does not hold the operand data requested by the arithmetic unit 120 or the instruction data requested by the control unit 130 (cache miss), it issues an access request to the L2 cache. The L1 cache 140 holds the data received from the L2 cache 150 and outputs it to the arithmetic unit 120 or the control unit 130 that made the request.

[0014] When the L2 cache 150 holds the target data of the access request from the L1 cache 140 (cache hit), it outputs the held data to the L1 cache 140. When the L2 cache 150 does not hold the target data of the access request from the L1 cache 140 (cache hit), it issues an access request to a lower cache such as a main memory or an L3 cache (not shown). Then, the L2 cache 150 holds the data received from the main memory or the lower cache, and outputs it to the L1 cache 140.

[0015] Although not limited thereto, in this embodiment, the processor 100 executes an operation using double-precision floating-point data. For example, when using the double-precision floating-point format of IEEE (The Institute of Electrical and Electronics Engineers) 754 (floating-point arithmetic standard), the sign is expressed by 1 bit, the exponent by 11 bits, and the mantissa by 52 bits.

[0016] Fig. 2 shows an example of the arithmetic unit 120 in Fig. 1. The arithmetic unit 120 has a floating-point register (FPR) 121, a general-purpose register (GPR) 122, a floating-point arithmetic unit 123, and a fixed-point arithmetic unit 124. The floating-point register 121 and the general-purpose register 122 each function as a register file having a plurality of registers.

[0017] The floating-point register 121 holds the load data transferred from the L1 cache 140 as floating-point data. The general-purpose register 122 holds the load data transferred from the L1 cache 140 as fixed-point data. The floating-point register 121 and the general-purpose register 122 output the data held in the register indicated by the store instruction as store data.

[0018] The floating-point arithmetic unit 123 has a fused multiply-add (FMA) 10 and a floating-point divider (FDIV) 20. The fixed-point arithmetic unit 124 has an arithmetic and logic unit (ALU) 30 and a shifter 40. An example of the floating-point divider 20 is shown in FIG.

[0019] The multiply-and-accumulate unit 10 and the floating-point divider 20 execute operations using the operand data held in the floating-point register 121 and store the results of the operations in the floating-point register 121. The logic unit 30 and the shift unit 40 execute operations using the operand data held in the general-purpose register 122 and store the results of the operations in the general-purpose register 122.

[0020] Figure 3 shows an example of the floating-point divider 20 in FIG. 2. Note that FIG. 3 shows the mantissa operation unit that operates on the mantissa parts of the dividend X and the divisor Y, and the description of the exponent operation unit is omitted. The floating-point divider 20 includes an initial value generation unit 200 that generates initial values before the iterative operation of the recurrence formula, a recurrence formula operation unit 220 that executes the operation process according to the recurrence formula, and a quotient generation unit 230 that generates a quotient. An example of the quotient generation unit 230 is shown in FIG. 4.

[0021] The initial value generation unit 200 includes registers 201 and 202, a table circuit 203, registers 204 and 205, a multiplier 206, a dividend operation unit 207, a register 210, and a multiplier 212. The dividend operation unit 207 includes a comparator 208 and a shifter 209. The table circuit 203 is an example of a table. The multiplier 206 is an example of a first multiplication unit. The multiplier 212 is an example of a second multiplication unit.

[0022] The recurrence formula operation unit 220 includes registers 221, 222, and 223, an adder 224, a multiplier 225, and a CSA (Carry Save Adder) 226. The registers 221 and 222 are examples of holding units. The multiplier 225 is an example of a third multiplication unit. The CSA 226 is an example of a first addition unit.

[0023] The initial value generation unit 200 uses the dividend X and the divisor Y to generate, as initial values, a value R(0)=DX' and a value DY that are suitable for generating a multi-bit quotient for each operation process of the recurrence formula by the recurrence formula operation unit 220. The value R(0)=DX' is an approximation of the quotient X' / Y, and the value DY is the product of an approximation D of the reciprocal 1 / Y of the divisor Y and Y. The value X' is, as shown in Equation (1) described later, 2X, which is the value obtained by shifting the dividend X one bit to the left when X < Y, and is the dividend X when X ≧ Y. Hereinafter, the value X' is also referred to as an operation value.

[0024] Although X' / Y and DX' / DY both converge to the same quotient according to the recurrence formula explained below, a circuit that converges faster for DX' / DY than for X' / Y can be constructed. In the following, the approximation value of the reciprocal 1 / Y of the divisor Y is referred to as the approximation value D.

[0025] In the initial value generating unit 200, the register 201 holds the dividend X (mantissa part), and the registers 202 and 205 sequentially hold the divisor Y (mantissa part). The dividend X and divisor Y input to the registers 201 and 202, respectively, have their mantissa parts in floating-point format appropriately pre-processed. For example, the dividend X is converted into a binary format that can be regarded as "1≦X<2", and the divisor Y is converted into a binary format that can be regarded as "1≦Y<2". For example, the dividend X and divisor Y are each 52 bits. When the floating-point divider 20 operates on single-precision floating-point number data, the dividend X and divisor Y are each 23 bits.

[0026] The table circuit 203 holds an approximation value D that approximates the reciprocal 1 / Y of the divisor Y for each divisor Y in a predetermined range. The table circuit 203 receives, for example, the most significant j bits of the divisor Y and outputs an approximation value D of i bits. Here, j and i are integers that are 2 or more and smaller than the number of bits of the divisor Y. The table circuit 203 is set so that the approximation value D of 1 / Y is smaller than 1 / Y (D<1 / Y) so that the partial quotient q(n), which is the most significant k bits of the partial remainder R(n) described later, is 0 or more. The number of bits indicated by k can be increased as the approximation value D approaches 1 / Y (the higher the accuracy), and the faster the division can be performed, but the size of the table circuit 203 increases accordingly.

[0027] Depending on how the values of j and i are taken, the circuit area and the depth of the logic stages of the table circuit 203 change, and also the circuit area, the depth of the logic stages, and the quotient generation speed of the recurrence calculation unit 220 change. Here, the quotient generation speed depends on the number of bits k of the partial quotient q(n) obtained by one operation using the recurrence formula, and the larger the number of bits k, the higher it becomes. The values of j and i are preferably set appropriately by comprehensively judging the circuit area allowed for the floating-point divider 20, the operating frequency of the core 110, and the target division speed. In order to have an advantage over existing floating-point dividers, it is preferable to appropriately determine j and i within the ranges of "number of bits where 2 ≤ j < Y" and "number of bits where 2 ≤ i < Y".

[0028] The approximate value D output from the table circuit 203 is held in the register 204 and then input to the multipliers 206 and 212. The multiplier 206 generates the product DY of the approximate value D and the divisor Y. Since the product DY is the product of the approximate value D of 1 / Y and the divisor Y, it becomes a value close to 1. The product DY is held in the register 223 of the recurrence calculation unit 220 and is a constant that is always used during the repeated calculation of the recurrence formula.

[0029] In the dividend operation unit 207, the comparator 208 compares the magnitudes of the dividend X and the divisor Y. When X < Y, the comparator 208 outputs the shift signal LSFT1, and when X ≥ Y, it suppresses the output of the shift signal LSFT1. The shifter 209 executes a left shift operation on the dividend X when it receives the shift signal LSFT1 and generates the operation value X'.

[0030] Equation (1) shows the operation of the dividend operation unit 207 that generates the operation value X'. X' = 2X (if X < Y) or X (if X ≥ Y) ‥(1) As shown in Equation (1), when X < Y, the dividend operation unit 207 outputs 2X obtained by left-shifting the dividend X by 1 bit as the operation value X', and when X ≥ Y, it outputs the dividend X as the operation value X'. The operation of the dividend operation unit 207 is executed to determine the most significant bit of the quotient as "1" in the arithmetic processing by the recurrence calculation unit 220.

[0031] A register 210 holds an operation value X'. A multiplier 212 generates a product D*X' of the operation value X' and an approximation value D. The sign * indicates a multiplication sign. The product D*X' is divided into a sum S and a carry C and stored in registers 221 and 222, respectively, as an initial value R(0) of a recurrence formula for calculating a partial remainder R(n).

[0032] 3, in order to operate the multiplier 212 at high speed, the multiplication result is output separately as a sum S and a carry C, but the multiplication result obtained by full addition may be output from the multiplier 212. In this case, the result of full addition is stored in one of the registers 221 and 222 as an initial value, and "0" is stored in the other of the registers 221 and 222.

[0033] In recurrence formula operation unit 220, adder 224 adds the most significant k bits of the sum S of product D*X' held in register 221 to the most significant k bits of the carry C of product D*X' held in register 222, and outputs the addition result as a k+2-bit partial quotient q(n). Partial quotient q(n) is output to multiplier 225 and quotient generation unit 230. Partial quotient q(n) corresponds to the value obtained by extracting the most significant k bits of partial remainder R(n).

[0034] Multiplier 225 multiplies the partial quotient q(n) from adder 224 by the value DY held in register 223 and outputs the result as a value DY*q(n). CSA 226 subtracts the value DY*q(n) from the partial remainder R(n) held in registers 221 and 222, and outputs the sum S and carry C of the subtraction result.

[0035] The sum S and carry C of the subtraction result are shifted left by k bits and stored in the registers 221 and 222, respectively, as a new partial remainder R(n). The sum S and carry C stored in the registers 221 and 222, respectively, are used as inputs for the next recurrence formula calculation process. It is mathematically possible to prove that the k bits of data that are shifted out and discarded in the k-bit left shift all become "0". For this reason, even when k bits of the partial remainder R(n+1) output from the CSA 226 are shifted left, it is possible to prevent cancellation of digits in the partial remainder R(n+1).

[0036] Note that "k" is a fixed value within the floating-point divider 20. Therefore, a k-bit left shift is realized by connecting the output wiring of each bit of the sum S and carry C of the CSA 226 to inputs of the registers 221 and 222 that are shifted by k bits. This makes it possible to eliminate the need for a shifter that performs the k-bit left shift. Note that the k-bit left shift may be performed by a shifter.

[0037] "k" is the number of bits of the quotient calculated in one cycle of the recurrence formula, and the upper limit of "k" is determined by the precision of the approximation D of 1 / Y. The larger "k" is, the faster the division quotient is calculated, but the circuit area becomes larger and the number of transistor stages in one cycle also becomes larger. For example, if the precision of the approximation D is doubled (=1 bit is added), "k" increases by "1", but the area of ​​the table circuit 203 almost doubles, the areas of the multipliers 206, 212, adder 224 and multiplier 225 become almost (1+1 / k) times, and the number of logic stages increases.

[0038] Equation (2) shows the recurrence formula for calculating the partial remainder R(n+1). R(n+1)=m(R(n)-DY*q(n)) ‥(2) The symbol m is a constant represented as 2^k. The symbol ^ indicates the exponentiation symbol.

[0039] In this embodiment, an approximation value D (D<1 / Y) of 1 / Y generated by the table circuit 203 is input to the multipliers 206 and 212 to calculate the initial value R(0) of the partial remainder and the value DY. This allows the partial remainder R(n+1) and the partial quotient q(n), which is the upper k bits of the partial remainder R(n), to always be greater than or equal to 0. In addition, by using the upper k bits of the partial remainder R(n) as the partial quotient q(n), the partial remainder R(n+1) calculated by the CSA 226 can always be positive.

[0040] In the recurrence formula of the partial remainder R(n+1) shown in formula (2), the delay critical path is the path of the adder 224 and multiplier 225 used to calculate DY*q(n). Because the partial remainder R(n+1) is always positive, the adder 224 and multiplier 225 included in the delay critical path can be made to have simple logic, and the number of logic stages can be minimized. As a result, if the execution cycle time of the recurrence formula of formula (2) is not changed, it is possible to increase the number of bits k of the quotient calculated in one calculation according to the recurrence formula, and the division by the floating-point divider 20 can be executed at high speed.

[0041] Fig. 4 shows an example of the quotient generation unit 230 in Fig. 3. It has a right shifter 231, an adder 232, and a register 233. The right shifter 231 shifts the k+2-bit partial quotient q(n) output from the adder 224 of the recurrence formula operation unit 220 in Fig. 2 to the right by "k*n" bits to align it to a predetermined bit position of the quotient.

[0042] The adder 232 adds the output value of the right shifter 231 and the output value of the register 233, and stores the addition result as a quotient Qn+1 in the register 233. Note that the initial value Q(0) of the quotient held in the register 233 is set to "0". The quotient Qn+1 held in the register 233 is output to the outside of the floating-point divider 20.

[0043] Equation (3) shows the recurrence formula for calculating the quotient Q(n+1). Q(n+1)=Q(n)+q(n) / (m^n) ‥(3) In equation (3), the symbol m is a constant represented by 2^k, as in equation (2), so q(n) / (m^n) indicates that q(n) is shifted to the right by k*n bits.

[0044] Fig. 5 shows an example in which the partial quotient q(n) is bit-shifted to the right to match the bit position of the quotient Q(n+1) by the quotient generation unit 230 in Fig. 3. The partial quotient q(n) is shifted to the right by k*n bits by performing the calculation process of the recurrence formula of the quotient Q(n+1) shown in equation (3), and is placed at a predetermined bit position of the quotient Q(n+1).

[0045] Here, the carry C input to the adder 224 in Fig. 3 is shifted one bit to the left with respect to the sum S. Furthermore, if a carry occurs as a result of the addition of the sum S and the carry C, one more bit is added. Therefore, the partial quotient q(n), which is the result of the addition by the adder 224, can be up to k+2 bits long. Therefore, the quotient generation unit 230 adds the partial quotient q(n) by overlapping two bits at a time, as shown in Fig. 5. This allows the partial quotient q(n) to be shifted by k bits and placed in the correct position of the quotient Q(n+1).

[0046] Fig. 6 shows an example of the operation of the floating-point divider 20 in Fig. 3. That is, Fig. 6 shows an example of a calculation method by the processor 100, which is an arithmetic processing device. The flow shown in Fig. 6 is executed every time the dividend X and the divisor Y are supplied to the floating-point divider 20. Steps S201 to S204 show an example of the operation of the initial value generation unit 200 in Fig. 3. Steps S205 to S207 show an example of the operation of the recurrence formula calculation unit 220 in Fig. 3. Steps S208 to S209 show an example of the operation of the quotient generation unit 230 in Fig. 3.

[0047] In step S201, the initial value generation unit 200 provides the divisor Y to the table circuit 203, and generates an approximation value D of the reciprocal 1 / Y of the divisor Y. Next, in step S202, the initial value generation unit 200 uses the comparator 208 to compare the magnitudes of the dividend X and the divisor Y. When the dividend X is equal to or greater than the divisor Y, the initial value generation unit 200 sets the dividend X as the operation value X' and executes step S204. When the dividend X is smaller than the divisor Y, the initial value generation unit 200 executes step S203.

[0048] In step S203, the initial value generation unit 200 shifts the dividend X one bit to the left using the shifter 209, thereby setting a value twice the dividend X as the operation value X', and then executes step S204.

[0049] In step S204, the initial value generation unit 200 generates an initial value R(0) of the recurrence formula by multiplying the approximation value D by the operation value X' using the multiplier 212. The initial value generation unit 200 generates a value DY by multiplying the approximation value D by the divisor Y using the multiplier 206. The initial value generation unit 200 outputs the generated initial value R(0) and value DY to the recurrence formula calculation unit 220.

[0050] In step S205, the recurrence formula operation unit 220 outputs, by the adder 224, the upper k bits of the partial remainder R(n) (the sum S and carry C of the value D*X') held in the registers 221 and 222 as the partial quotient q(n).

[0051] After step S205, in step S206, the recurrence formula calculation unit 220 multiplies the partial quotient q(n) from the adder 224 by the value DY held in the register 223 using the multiplier 225 to calculate a value DY*q(n). Next, in step S207, the recurrence formula calculation unit 220 executes the operation of the recurrence formula shown in equation (2) by subtracting the value DY*q(n) from the partial remainder R(n) held in the registers 221 and 222 using the CSA 226. Then, the recurrence formula calculation unit 220 calculates the partial remainder R(n+1), stores the sum S and carry C of the calculated new partial remainder R(n+1) in the registers 221 and 222, respectively, and returns the operation to step S205.

[0052] After step S205, in step S208, the quotient generation unit 230 sets the initial value Q(0) to "0" before executing the first recurrence formula. The quotient generation unit 230 also performs the operation of the recurrence formula shown in formula (3) by shifting the partial quotient q(n) to the right by "k*n" bits using the right shifter 231 and adder 232 in FIG. 4 and adding the shift result to the previous quotient Qn held by the register 233. The right shift of "k*n" bits is equivalent to dividing the partial quotient q(n) by "m^n". The quotient generation unit 230 then stores the calculated new quotient Q(n+1) in the register 233 and executes step S209.

[0053] In step S209, if "n" reaches a predetermined number, the quotient generation unit 230 completes the operation of generating the quotient Q(n+1). If "n" does not reach the predetermined number, the quotient generation unit 230 returns the operation to step S208 to calculate the next quotient Q(n+1). Note that the processes of steps S206 and S207 and the processes of steps S208 and S209 are executed in parallel with each other.

[0054] As described above, in this embodiment, the approximation value D of the reciprocal 1 / Y of the divisor Y generated by the table circuit 203 is input to the multipliers 206 and 212 to calculate the initial value R(0) of the partial remainder and the value DY. At this time, by configuring the table circuit 203 so that the approximation value D is smaller than the reciprocal, the partial quotient q(n), which is the upper k bits of the partial remainder R(n), can always be 0 or more. This makes it possible to calculate the value DY*q(n) by minimizing the number of logic stages of the adder 224 and the multiplier 225 included in the delay critical path. As a result, it becomes possible to increase the number of bits k of the quotient obtained by one calculation using the recurrence formula compared to the conventional method, and the division by the floating-point divider 20 can be performed at high speed.

[0055] 7 shows an example of a recurrence formula calculation unit of a processor according to another embodiment. The same elements as those in FIG. 3 are given the same reference numerals, and detailed description thereof will be omitted. The configuration of the recurrence formula calculation unit 220A shown in FIG. 7 is the same as the configuration of the recurrence formula calculation unit 220 in FIG. 1, except that it has a multiplication unit 225A instead of the multiplier 225. The other configurations of the floating-point divider 20 including the recurrence formula calculation unit 220A are the same as the configuration of the floating-point divider 20 in FIG. 3.

[0056] The arithmetic processing device of this embodiment is similar to the processor 100 of Fig. 1 and the arithmetic unit 120 of Fig. 2, except that the configuration of the floating-point divider 20 provided in the arithmetic unit 120 is different from that of Fig. 3. That is, the floating-point divider 20 of this embodiment has a recurrence formula calculation unit 220A, and an initial value generation unit 200 and a quotient generation unit 230 shown in Fig. 3.

[0057] The multiplication unit 225A of the recurrence formula calculation unit 220A has an adder 224 and a multiplier 225. The multiplication unit 225A is an example of a third multiplication unit. The adder 224 is an example of a second addition unit. The configurations of the adder 224 and the multiplier 225 in FIG. 7 are similar to the configurations of the adder 224 and the multiplier 225 in FIG. 3. That is, the recurrence formula calculation unit 220A of this embodiment has an adder 224 that calculates a partial quotient q(n) to be output to the quotient generation unit 230, and an adder 224 that calculates the partial quotient q(n) used to generate the value DY*q(n) to be output to the CSA 226.

[0058] The recurrence formula used by the recurrence formula calculation unit 220A to calculate the partial remainder R(n+1) is the same as formula (2). The recurrence formula used by the quotient generation unit 230 to calculate the quotient Q(n+1) is the same as formula (3).

[0059] As described above, in this embodiment as well, as in the above-mentioned embodiment, it is possible to reduce the number of logic stages of the adder 224 and the multiplier 225 included in the delay critical path. As a result, it is possible to increase the number of bits k of the quotient calculated in one calculation using the recurrence formula compared to the conventional method, and the floating-point divider 20 can perform division at high speed.

[0060] 8 shows an example of a recurrence formula calculation unit of a processor according to another embodiment. The same elements as those in FIG. 3 and FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the recurrence formula calculation unit 220B shown in FIG. 8 is the same as the configuration of the recurrence formula calculation unit 220A in FIG. 7, except that it has multiplication units 225B and CSA 226B instead of multiplication units 225A and CSA 226. The other configurations of the floating-point divider 20 including the recurrence formula calculation unit 220B are the same as the configuration of the floating-point divider 20 in FIG. 3.

[0061] The arithmetic processing device of this embodiment is similar to the processor 100 of Fig. 1 and the arithmetic unit 120 of Fig. 2, except that the configuration of the floating-point divider 20 provided in the arithmetic unit 120 is different from that of Fig. 3. That is, the floating-point divider 20 of this embodiment has a recurrence formula operation unit 220B, and an initial value generation unit 200 and a quotient generation unit 230 shown in Fig. 3.

[0062] The multiplication section 225B of the recurrence formula calculation section 220B has two multipliers 225. The multiplication section 225B is an example of a third multiplication section. The two multipliers 225 are an example of a first multiplier and a second multiplier, respectively.

[0063] One of the multipliers 225 multiplies the most significant k bits of the sum S of the partial remainder R(n) held in the register 221 by the value DY held in the register 223, and outputs the sum S and carry C of the multiplication result to the CSA 226. The other of the multipliers 225 multiplies the most significant k bits of the carry C of the partial remainder R(n) held in the register 222 by the value DY held in the register 223, and outputs the sum S and carry C of the multiplication result to the CSA 226. The sum S and carry C output from the two multipliers 225 respectively correspond to the value DY*q(n).

[0064] The CSA 226B subtracts the value DY*q(n) indicated by the sum S and carry C output from the two multipliers 225, respectively, from the partial remainder R(n) held in the registers 221 and 222, and outputs the sum S and carry C of the subtraction result. The sum S and carry C of the subtraction result are shifted left by k bits and stored in the registers 221 and 222, respectively, as the new partial remainder R(n).

[0065] The recurrence formula used by the recurrence formula calculation unit 220B to calculate the partial remainder R(n+1) is the same as formula (2). The recurrence formula used by the recurrence formula calculation unit 220B to calculate the quotient Q(n+1) is the same as formula (3). However, in this embodiment, the adder 224 is not included in the path from the registers 221 and 222 to the multiplier 225 (i.e., the delay critical path). Therefore, the number of logic stages of the delay critical path corresponding to the recurrence formula of the partial remainder R(n+1) shown in formula (2) can be reduced compared to the above-mentioned embodiment. As a result, it is possible to further increase the number of bits k of the quotient obtained by one calculation using the recurrence formula, and the division by the floating-point divider 20 can be executed at a higher speed.

[0066] As described above, in this embodiment, by removing the adder 224 from the delay critical path, it is possible to further increase the number of bits k of the quotient calculated in one calculation, and the division by the floating-point divider 20 can be performed even faster.

[0067] 9 shows an example of a recurrence formula calculation unit of a processor according to another embodiment. The same elements as those in FIG. 3 and FIG. 7 are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the recurrence formula calculation unit 220C shown in FIG. 9 is the same as the configuration of the recurrence formula calculation unit 220A in FIG. 7, except that it does not have the adder 224 that calculates the partial quotient q(n) to be output to the quotient generation unit 230. The other configurations of the floating-point divider 20 including the recurrence formula calculation unit 220C are the same as the configuration of the floating-point divider 20 in FIG. 3.

[0068] The arithmetic processing device of this embodiment is similar to the processor 100 of Fig. 1 and the arithmetic unit 120 of Fig. 2, except that the configuration of the floating-point divider 20 provided in the arithmetic unit 120 is different from that of Fig. 3. The floating-point divider 20 of this embodiment has a recurrence formula operation unit 220C, and an initial value generation unit 200 and a quotient generation unit 230C shown in Fig. 3. The recurrence formula used in the calculation of the partial remainder R(n+1) by the recurrence formula operation unit 220C is the same as equation (2).

[0069] The quotient generation unit 230C directly receives the most significant k bits of the sum S of the partial remainder R(n) held in the register 221 and the most significant k bits of the carry C of the partial remainder R(n) held in the register 222. The recurrence formula used by the quotient generation unit 230C to calculate the quotient Q(n+1) is the same as formula (3). An example of the quotient generation unit 230C is shown in FIG.

[0070] Fig. 10 is a circuit diagram showing an example of the quotient generation unit 230C of Fig. 8. The same elements as those of the quotient generation unit 230 of Fig. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. The quotient generation unit 230C has two right shifters 231s and 231c, an adder 232C, and a register 233.

[0071] The right shifter 231s shifts the most significant k bits of the sum S(n) of the partial remainder R(n) output from the recurrence formula operation unit 220C in Fig. 9 right by "k*n" bits, and outputs the shift result to the adder 232C. The right shifter 231c shifts the most significant k bits of the carry C(n) of the partial remainder R(n) output from the recurrence formula operation unit 220C in Fig. 9 right by "k*n-1" bits, and outputs the shift result to the adder 232C. Since the carry C(n) is placed on the more significant side (left side) of the sum S(n) by one bit, it is set to one bit less than the shift number of the sum S(n).

[0072] The adder 232C adds the output values ​​of the right shifters 231s and 231c and the output value of the register 233, and stores the addition result as the quotient Qn+1 in the register 233. In the quotient generation unit 230C, the initial value Q(0) held in the register 233 is also "0".

[0073] As described above, in this embodiment as well, as in the above-mentioned embodiment, it is possible to reduce the number of logic stages of the adder 224 and the multiplier 225 included in the delay critical path. As a result, it is possible to increase the number of bits k of the quotient calculated in one calculation according to the recurrence formula, and the floating-point divider 20 can perform division at high speed.

[0074] Fig. 11 shows an example of a recurrence formula calculation unit of a processor according to another embodiment. The same elements as those in Figs. 3 and 8 are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the recurrence formula calculation unit 220D shown in Fig. 11 is similar to the configuration of the recurrence formula calculation unit 220B in Fig. 8, except that it does not have an adder 224 that calculates the partial quotient q(n) to be output to the quotient generation unit 230C. The configuration of the floating-point divider 20 including the recurrence formula calculation unit 220D is similar to the configuration of the floating-point divider 20 in Fig. 3.

[0075] The arithmetic processing device of this embodiment is similar to the processor 100 of Fig. 1 and the arithmetic unit 120 of Fig. 2, except that the configuration of the floating-point divider 20 provided in the arithmetic unit 120 is different from that of Fig. 3. The floating-point divider 20 of this embodiment has a recurrence formula calculation unit 220D, an initial value generation unit 200 shown in Fig. 3, and a quotient generation unit 230C shown in Fig. 10.

[0076] As described above, in this embodiment as well, as in the above-mentioned embodiment, it is possible to reduce the number of logic stages of the adder 224 and the multiplier 225 included in the delay critical path. As a result, it is possible to increase the number of bits k of the quotient calculated in one calculation according to the recurrence formula, and the floating-point divider 20 can perform division at high speed.

[0077] FIG. 12 shows an example of a recurrence formula operation unit of a floating-point divider of another arithmetic processing device. The recurrence formula operation unit 220E shown in FIG. 12 calculates a partial remainder R(n+1) using the recurrence formula shown in equation (2). The recurrence formula operation unit 220E also calculates a partial quotient q(n) used in the recurrence formula shown in equation (3). In FIG. 12, only elements included in the delay critical path in the recurrence formula operation unit 220 are shown. The recurrence formula operation unit 220E has a plurality of adders 227, a partial quotient coefficient generation circuit 228, and a partial quotient generation circuit 229.

[0078] If the table circuit 203 shown in Fig. 3 is not used and the approximation value D (D<1 / Y) of the reciprocal 1 / Y of the divisor Y is not used, the partial quotient q(n) is not necessarily 0 or more. In this case, as shown in Fig. 12, the circuit size (i.e., the number of logic stages) included in the delay critical path increases compared to the above-mentioned embodiment. As a result, it becomes difficult to increase the number of bits k of the quotient obtained in one calculation using the recurrence formula, and it becomes difficult to perform division using a floating-point divider at high speed.

[0079] The above-described embodiment has been described with reference to an example applied to the floating-point divider 20. However, the embodiment can also be applied to a fixed-point divider by performing an appropriate conversion, such as aligning the most significant bits of the dividend X and the divisor Y.

[0080] The features and advantages of the embodiments will be apparent from the above detailed description. It is intended that the claims cover the features and advantages of the embodiments as described above without departing from the spirit and scope of the claims. In addition, any improvements and modifications can be easily made by a person having ordinary skill in the art. Therefore, it is not intended to limit the scope of the inventive embodiments to the above, and appropriate improvements and equivalents within the scope of the embodiments disclosed can be used. [Explanation of symbols]

[0081] 10 Multiply-and-accumulate unit 20 Floating Point Divider 30 Logic Operation Unit 40 Shift calculator 100 processors 110 cores 120 Calculation Units 121 floating point registers 122 General Purpose Registers 123 Floating Point Unit 124 Fixed-point arithmetic unit 130 Control Unit 140 L1 cache 150 L2 cache 200 Initial value generator 201, 202 Registers 203 Table Circuit 204, 205 Registers 206 Multiplier 207 Dividend operation section 208 Comparator 209 Shifter 210 Register 212 Multiplier 220, 220A, 220B Recurrence formula calculation section 220C, 220D, 220E Recurrence formula calculation section 221, 222, 223 Registers 224 Adder 225 Multiplier 225A, 225B Multiplication section 226 CSA 227 Adder 228 Coefficient Generation Circuit 229 Partial quotient generation circuit 230, 230C Commercial generation department 231, 231c, 231s right shifter 232, 232C adder 233 Register ALU logic operator C Carry D Approximation R(n+1) partial remainder q(n) partial quotient Q(n), Q(n+1) quotient S Sam X Dividend X' operation value Y divisor

Claims

1. a table for storing an approximation value D of an inverse 1 / Y of a divisor Y for each of the divisors Y within a predetermined range; a first multiplication unit that calculates a product DY of the approximation value D output from the table corresponding to the divisor Y and the divisor Y; a dividend operation unit that compares the size of a dividend X with the divisor Y, and generates an operation value twice the dividend X when the dividend X is smaller than the divisor Y, and generates the operation value equal to the dividend X when the dividend X is equal to or larger than the divisor Y; a second multiplication unit that calculates a product of the approximation value D and the operation value as an initial value R(0) of a partial remainder R(n); a storage unit for storing the partial remainder R(n); a third multiplication unit that calculates a product DY*q(n) of the product DY and a partial quotient q(n) that is the most significant k bits of the partial remainder R(n) held in the holding unit; a first addition unit that calculates a new partial remainder R(n) by subtracting the product DY*q(n) from the partial remainder R(n) held in the holding unit and left-shifting the k bits, and stores the calculated new partial remainder R(n) in the holding unit; a quotient generator for placing the partial quotient q(n) at a predetermined bit position of the quotient; having The k bits are a fixed value determined by the accuracy of the approximation value D. Processing unit.

2. The table holds the approximate value D that is smaller than the reciprocal 1 / Y. The processor according to claim 1 .

3. the holding unit holds a sum and a carry as the partial remainder R(n); The third multiplication unit receives the k most significant bits of the sum and carry held in the holding unit as the partial quotient q(n). The processor according to claim 1 or 2.

4. The third multiplication unit: a second addition unit that calculates the partial quotient q(n) by adding the k most significant bits of the sum and carry held in the holding unit; a multiplier that outputs the product DY*q(n) of the partial quotient q(n) output by the second adder to the first adder; The processor according to claim 3 ,

5. The third multiplication unit: a first multiplier that outputs a product of the k most significant bits of the sum held in the holding unit and the product DY as a sum and a carry to the first adding unit; a second multiplier that outputs a product of the k most significant bits of the carry held in the holding unit and the product DY as a sum and a carry to the first addition unit; The processor according to claim 3 ,

6. The quotient generation unit has an adder that adds the most significant k bits of the sum and carry held in the holding unit, and places the sum result of the adder at a predetermined bit position of the quotient as the partial quotient q(n). The processor according to any one of claims 3 to 5.

7. calculating a product DY of the divisor Y and an approximate value D outputted corresponding to the divisor Y from a table that holds an approximate value D obtained by approximating the reciprocal 1 / Y of the divisor Y for each divisor Y in a predetermined range; comparing the size of a dividend X with the divisor Y, and if the dividend X is smaller than the divisor Y, generating an operation value that is twice the dividend X, and if the dividend X is equal to or greater than the divisor Y, generating the operation value that is equal to the dividend X; The product of the approximation value D and the operation value is stored in a storage unit as an initial value R(0) of a partial remainder R(n); calculating a product DY*q(n) of the product DY and a partial quotient q(n) which is the most significant k bits of the partial remainder R(n) held in the holding unit; subtracting the product DY*q(n) from the partial remainder R(n) held in the holding unit and shifting the k bits to the left to calculate a new partial remainder R(n), and storing the calculated new partial remainder R(n) in the holding unit; placing the partial quotient q(n) at a predetermined bit position of the quotient; The k bits are a fixed value determined by the accuracy of the approximation value D. Calculation method.

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