Multilayer Substrate

Abstract

To provide a multilayer substrate that has capacitor function, and that can be disposed on a circuit board having a multilayer integrated circuit.SOLUTION: The multilayer substrate 1 comprises a substrate body 10 that includes a dielectric layer 8 and a plurality of internal electrodes, a first surface side contact group 51 which is formed on the surface side of the substrate body 10 and has a plurality of surface side contacts 50, and a second surface side contact group 52 which is formed on the surface side of the substrate body 10 and has the plurality of surface side contacts 50. The internal electrodes have a first internal electrode layer 31 and a first counter internal electrode layer 41, a first surface side contact 511 of the first surface side contact group 51 being electrically connected to the first internal electrode layer 31 that is disposed inside of the substrate body 10, a second surface side contact 521 of the second surface side contact group 52 being electrically connected to the first counter internal electrode layer 41 that is disposed facing the first internal electrode layer 31 across the dielectric layer 8.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a laminated substrate. [Background technology]

[0002] Conventionally, there is known a circuit board in which a substrate and integrated circuits (ICs) arranged on the substrate are connected by wire bonding or the like. However, in the case of such a circuit board, as the number of integrated circuits increases, the mounting area and wiring length increase, and signal delay between the integrated circuits becomes large. Patent Document 1 discloses a TSV structure in which multiple integrated circuits are stacked by connecting the integrated circuits to each other using a large number of through-silicon vias (TSVs) provided on a substrate constituting the integrated circuits. This reduces signal delay between the integrated circuits. In addition, it is possible to reduce the size of a circuit board on which multiple integrated circuits are mounted. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-99850 Summary of the Invention [Problem to be solved by the invention]

[0004] Even in a circuit board using a TSV structure, it is expected that the current path will be longer and the impedance of the current path will be higher as the integrated circuit is stacked and placed farther from the base substrate. Therefore, when a decoupling capacitor is required as a circuit, it is preferable to place the decoupling capacitor in close proximity to the integrated circuit placed farther from the base substrate. However, in a circuit board using a TSV structure, it is difficult to place a normal chip-type decoupling capacitor in a stable position close to the integrated circuit placed farther from the base substrate.

[0005] An object of the present invention is to provide a laminated substrate having a capacitor function that can also be arranged on a circuit board having stacked integrated circuits. [Means for solving the problem]

[0006] The laminated substrate is A substrate body including a dielectric layer and a plurality of internal electrodes; a first surface-side contact group formed on a surface side of the substrate body and having a plurality of surface-side contacts; a second surface-side contact group formed on the surface side of the substrate body and having a plurality of surface-side contacts; The plurality of internal electrodes include a first internal electrode layer and a first opposing internal electrode layer, a first surface side contact of the first surface side contact group is electrically connected to the first internal electrode layer disposed inside the substrate body; A first surface side contact of the second surface side contact group is electrically connected to the first opposing internal electrode layer arranged opposite the first internal electrode layer with the dielectric layer in between. Effect of the Invention

[0007] According to the present invention, it is possible to provide a laminated substrate having a capacitor function, which can also be arranged on a circuit board having laminated integrated circuits. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a laminated substrate according to an embodiment of the present invention as viewed from the front surface side. [Diagram 2] FIG. 2 is a schematic diagram of the laminated substrate according to the embodiment when viewed from the back surface side. [Diagram 3] 3 is a side view of the laminated substrate according to the embodiment when viewed from the direction of arrow III in FIG. [Figure 4A] 4 is a cross-sectional view of the laminated board according to the embodiment taken along line IVA-IVA in FIG. 3. [Figure 4B]4 is a cross-sectional view of the laminated board according to the embodiment taken along line IVB-IVB in FIG. [Diagram 5] 4C is a cross-sectional view of the laminated substrate according to the embodiment taken along line VV in FIGS. 4A and 4B. FIG. [Figure 6] 1 is an enlarged cross-sectional view of a contact of the laminated substrate according to the embodiment of the present invention, and is a schematic cross-sectional view of a dielectric layer of the laminated substrate according to the embodiment of the present invention. [Figure 7] 11A and 11B are diagrams showing modified examples of the shape of the internal electrodes. [Figure 8] 13A to 13C are diagrams showing modified examples of the layer structure of the dielectric layer that constitutes the substrate body. [Figure 9] 2 is a schematic cross-sectional view showing a mounting structure of a laminated substrate according to the embodiment and a circuit substrate including a silicon substrate having an integrated circuit. FIG. [Figure 10] 1 is a partially enlarged view showing a connection between a contact of a laminated substrate and a TSV of a silicon substrate. [Figure 11] 4 is a schematic cross-sectional view showing an example in which a capacitor portion is formed in the laminated substrate according to the embodiment. FIG. [Figure 12] 4 is a schematic cross-sectional view showing an example in which the laminated substrate according to the embodiment has a laminated substrate through-electrode. FIG. [Figure 13] 13 is a diagram showing an equivalent circuit when the laminated substrate shown in FIG. 12 is applied to a silicon substrate on which an integrated circuit is mounted. [Figure 14] FIG. 4 is a diagram showing a first modified example of the laminated substrate according to the embodiment. [Figure 15] FIG. 4 is a diagram showing a second modified example of the laminated substrate according to the embodiment. [Figure 16] FIG. 11 is a diagram showing a third modified example of the laminated substrate according to the embodiment. [Figure 17] FIG. 11 is a diagram showing a fourth modified example of the laminated substrate according to the embodiment. [Figure 18] 18 is a diagram showing an equivalent circuit when the laminated substrate shown in FIG. 17 is applied to a silicon substrate on which an integrated circuit is mounted. [Figure 19] FIG. 11 is a diagram showing a fifth modified example of the laminated substrate according to the embodiment. [Figure 20] 20 is a diagram showing an equivalent circuit when the laminated substrate shown in FIG. 19 is applied to a silicon substrate on which an integrated circuit is mounted. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, a laminated substrate 1 according to one embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram of the laminated substrate 1 as viewed from the front side. FIG. 2 is a schematic diagram of the laminated substrate 1 as viewed from the back side. FIG. 3 is a side view of the laminated substrate 1 as viewed from the direction of arrow III in FIG. 1. FIG. 4A is a cross-sectional view of the laminated substrate 1 taken along line IVA-IVA shown in FIG. 3. FIG. 4B is a cross-sectional view of the laminated substrate 1 taken along line IVB-IVB shown in FIG. 3. FIG. 5 is a cross-sectional view of the laminated substrate 1 taken along line VV shown in FIGS. 4A and 4B. <Laminated substrate> 1, the laminated substrate 1 includes a substrate body 10 and a plurality of surface side contact groups 5. The surface side contact groups 5 of the laminated substrate 1 include at least a first surface side contact group 51 and a second surface side contact group 52. The laminated substrate 1 of the present embodiment further includes third to ninth surface side contact groups 53 to 59 as the surface side contact groups 5.

[0010] The laminated substrate 1 further includes a plurality of back side contact groups 6 on the back side thereof, as shown in Fig. 2. The laminated substrate 1 further includes a plurality of via connections 7 that penetrate the laminated substrate 1 and electrically connect the front side contact groups 5 and the back side contact groups 6, as shown in Fig. 5.

[0011] <Board body> The substrate body 10 has a dielectric layer 8 and a plurality of internal electrodes. The substrate body 10 is configured by laminating a plurality of dielectric layers 8 as shown in Figs. 3 and 5. In this embodiment, the substrate body 10 is configured by laminating three dielectric layers 8. The substrate body 10 has a substrate body front surface (first main surface) 10A and a substrate body back surface (second main surface) 10B that face each other in the lamination direction of the dielectric layers 8. Note that either the front surface or the back surface of the substrate body 10 may be arranged to be the upper surface.

[0012] The thickness of the substrate body 10 is not particularly limited, but the thickness of the substrate body 10 in the stacking direction is preferably 30 μm or more and 110 μm or less.

[0013] <Dielectric layer> The dielectric layer 8 is made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The dielectric material may also be one in which a subcomponent such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to the main components.

[0014] The thickness of the dielectric layer 8 is preferably 0.2 μm or more and 2.0 μm or less. The number of laminated dielectric layers 8 is preferably 3 layers or more and 40 layers or less. The number of dielectric layers 8 is the total number of dielectric layers 8 including the dielectric layers 8 on the substrate body front surface 10A side of the substrate body 10 and the dielectric layers 8 on the substrate body back surface 10B side. The layers on the substrate body front surface 10A side and the layers on the substrate body back surface 10B side of the substrate body 10 do not have to be dielectric layers 8.

[0015] <Internal electrode> 4A, 4B, and 5, the multiple internal electrodes include internal electrode layers 3 such as a first internal electrode layer 31, and opposing internal electrode layers 4 such as a first opposing internal electrode layer 41. The multiple internal electrode layers 3 extend radially from a first front surface side contact group 51. The multiple opposing internal electrode layers 4 are disposed opposite these internal electrode layers 3 with a dielectric layer 8 interposed therebetween.

[0016] As shown in Figures 4A and 5, the multiple internal electrode layers 3 include a first internal electrode layer 31 and a second internal electrode layer 32. As shown in Figures 4B and 5, the multiple opposing internal electrode layers 4 include a first opposing internal electrode layer 41 arranged opposite the first internal electrode layer 31 with the dielectric layer 8 interposed therebetween, and a second opposing internal electrode layer 42 arranged opposite the second internal electrode layer 32 with the dielectric layer 8 interposed therebetween.

[0017] The first internal electrode layer 31 is disposed on the dielectric layer 8. The first internal electrode layer 31 has a first internal electrode layer facing portion 311 facing the first facing internal electrode layer 41, and a first internal electrode layer lead portion 312 led out from the facing portion to the first front surface side contact group 51 side.

[0018] The first opposing internal electrode layer 41 is disposed so as to face the first internal electrode layer 31 across the dielectric layer 8. The first opposing internal electrode layer 41 has a first opposing internal electrode layer opposing portion 411 facing the first internal electrode layer 31, and a first opposing internal electrode layer lead portion 412 led from the opposing portion to the second front surface side contact group side.

[0019] In this manner, the first internal electrode layer facing portion 311 and the first opposing internal electrode layer facing portion 411 face each other via the dielectric layer 8, forming a capacitance and exhibiting the characteristics of a capacitor.

[0020] The second internal electrode layer 32 is disposed on the dielectric layer 8. The second internal electrode layer 32 has a facing portion facing the second opposing internal electrode layer 42, and an extended portion extended from the facing portion to the first front surface side contact group 51 side.

[0021] The second opposing internal electrode layer 42 is disposed so as to face the second internal electrode layer 32 across the dielectric layer 8. The second opposing internal electrode layer 42 has a facing portion facing the second internal electrode layer 32, and an extended portion extended from the facing portion to the second front surface side contact group side.

[0022] In this manner, the opposing portions of the second internal electrode layers 32 and the opposing portions of the second opposing internal electrode layers 42 face each other via the dielectric layer 8, forming a capacitance, thereby realizing the characteristics of a capacitor.

[0023] The area of ​​the opposing portion between the first internal electrode layer 31 and the first opposing internal electrode layer 41 may be the same as the area of ​​the opposing portion between the second internal electrode layer 32 and the second opposing internal electrode layer 42. This makes it easier to design the wiring when mounting the laminated substrate 1. The area of ​​the opposing portion between the first internal electrode layer 31 and the first opposing internal electrode layer 41 may be different from the area of ​​the opposing portion between the second internal electrode layer 32 and the second opposing internal electrode layer 42. This makes it possible to select capacitors with different capacitances according to the wiring design when mounting the laminated substrate 1.

[0024] As shown in FIG. 4A, the multiple internal electrode layers 3 of this embodiment further include third to eighth internal electrode layers 33 to . Also, as shown in FIG. 4B, the multiple opposing internal electrode layers 4 further include third to eighth opposing internal electrode layers 43 to . The first to eighth internal electrode layers 31 to 38 extend radially. Also, the first to eighth opposing internal electrode layers 41 to , which partially overlap with these internal electrode layers 3, similarly extend radially. The relationship between these internal electrode layers 3 and the opposing internal electrode layers 4 will be described in detail later.

[0025] As shown in FIG. 4A and FIG. 4B, the shape of the opposing portion of each internal electrode layer is not particularly limited, but is preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The shape of the lead-out portion is not particularly limited, but is preferably rectangular. However, the corners of the rectangular shape may be rounded, or the corners of the rectangular shape may be formed at an angle. The width dimension of the opposing portion and the width dimension of the lead-out portion may be formed to be the same dimension, or one of the dimensions may be formed to be smaller. In this embodiment, the width dimensions of the first to eighth internal electrode layers 31 to 38 and the first to eighth opposing internal electrode layers 41 to 48 are approximately the same dimension. The longitudinal dimension of the fifth to eighth internal electrode layers 35 to 38 is longer than the longitudinal dimension of the first to fourth internal electrode layers 31 to 34. The longitudinal dimension of the fifth to eighth opposing internal electrode layers 45 to 48 is longer than the longitudinal dimension of the first to fourth internal electrode layers 41 to 44. However, this is not limited to the above.

[0026] The internal electrode layer 3 is made of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the internal electrode layer 3 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of the internal electrode layer 3 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The number of layers of the internal electrode layer 3 is preferably 2 layers or more and 40 layers or less.

[0028] <Front contact group> As shown in FIG. 1, the laminated substrate 1 of this embodiment has a first surface-side contact group 51 and a second surface-side contact group 52 as the multiple surface-side contact groups 5. Furthermore, the laminated substrate 1 of this embodiment further has third to ninth surface-side contact groups 53 to 59 as the multiple surface-side contact groups 5. The laminated substrate 1 may have even more surface-side contact groups 5. Each surface-side contact group 5 has a plurality of contacts. Since the contacts constituting each surface-side contact group 5 have the same configuration, each contact constituting each surface-side contact group 5 may be referred to as a surface-side contact 50.

[0029] The first front surface side contact group 51 is formed on the front surface side of the substrate body 10.

[0030] In this embodiment, the first front-side contact group 51 is configured by nine front-side contacts 511 to 519 as the multiple front-side contacts 50, including a first front-side contact 511 and a second front-side contact 512.

[0031] As shown in Figure 5, the first surface side contacts 511 of the first surface side contact group 51 are electrically connected to the first internal electrode layer 31 arranged inside the substrate body 10 via the via connection portion 7 described below.

[0032] The second surface side contacts 512 of the first surface side contact group 51 are electrically connected to a second internal electrode layer 32 arranged inside the substrate body 10 through a via connection portion 7 described below.

[0033] The second front surface side contact group 52 is formed on the front surface side of the substrate body 10 .

[0034] In this embodiment, the second surface-side contact group 52 is composed of nine surface-side contacts 521 to 529 as the multiple surface-side contacts 50, including the first surface-side contact 521 of the second surface-side contact group 52.

[0035] The first surface side contact 521 of the second surface side contact group 52 is electrically connected to the first opposing internal electrode layer 41 arranged opposite the first internal electrode layer 31 across the dielectric layer 8, via a via connection portion 7 described below.

[0036] The third front surface side contact group 53 is formed on the front surface side of the substrate body 10.

[0037] In this embodiment, the third surface-side contact group 53 is composed of nine surface-side contacts 50 including a first surface-side contact 531 of the third surface-side contact group 53 as the multiple surface-side contacts 50.

[0038] The first surface side contact 531 of the third surface side contact group 53 is electrically connected to the second opposing internal electrode layer 42 arranged opposite the second internal electrode layer 32 across the dielectric layer 8, via a via connection portion 7 described below.

[0039] As described above, a capacitance is formed by the opposing portion of the first internal electrode layer 31 and the opposing portion of the first opposing internal electrode layer 41 facing each other through the dielectric layer 8. Therefore, the characteristics of a capacitor are exhibited between the surface side contact 50 to which the first internal electrode layer 31 is connected among the first surface side contact group 51 and the surface side contact 50 to which the first opposing internal electrode layer 41 is connected among the second surface side contact group 52. Similarly, the characteristics of a capacitor are exhibited between the surface side contact 50 to which the second internal electrode layer 32 is connected among the first surface side contact group 51 and the surface side contact 50 to which the second opposing internal electrode layer 42 is connected among the third surface side contact group 53. In this way, the contacts connected to the internal electrodes constitute the external electrodes of the capacitor.

[0040] 1, the fourth to ninth surface-side contact groups 54-59 are also formed on the surface side of the substrate body 10. Each of the fourth to ninth surface-side contact groups 54-59 is made up of a plurality of surface-side contacts 50. In this embodiment, each of the fourth to ninth surface-side contact groups 54-59 has the same configuration as the first to third surface-side contact groups 51-53, and is made up of nine surface-side contacts 50.

[0041] The fourth to ninth front surface side contact groups 54-59 are connected to the opposing internal electrode layers 4 by via connections 7. As with the second and third front surface side contact groups 52 and 53, the opposing internal electrode layers 4 connected thereto appropriately form capacitances at opposing portions with the internal electrode layers 3.

[0042] <Front contact group: layout of front contacts> The arrangement of the surface side contacts 50 of the surface side contact group 5 will be described using the eighth surface side contact group 58 shown in the lower left of FIG. 1 as an example. Each surface side contact group 5 is preferably composed of a surface side center contact 509 and three or more surface side peripheral contact groups 510 arranged to surround the surface side center contact 509. In this embodiment, the surface side peripheral contact group 510 is composed of eight surface side contacts 50 arranged to surround the surface side center contact 509. It is preferable that the surface side peripheral contact groups 510 are arranged at equal angular intervals with the surface side center contact 509 as a reference. In this embodiment, the surface side peripheral contact groups 510 are arranged at 45° angular intervals with the surface side center contact 509 as a reference. Each surface side contact group 5 is arranged in a 3×3 grid.

[0043] 1, for example, the first surface side contact group 51 is composed of a surface side central contact 519 and eight surface side peripheral contacts 511 to 518. The eight surface side peripheral contacts 511 to 518 are arranged at equal intervals of 45 degrees around the surface side central contact 519 of the first surface side contact group 51. Similarly, the second surface side contact group 52 is composed of a surface side central contact 529 and eight surface side peripheral contacts 521 to 528. Similarly, the third surface side contact group 53 is composed of a surface side central contact 539 and eight surface side peripheral contacts.

[0044] The size and shape of each of the surface side contacts 50 may be, for example, a circular shape with a diameter of 20 μm or more and 80 μm or less, but is not limited thereto. In this embodiment, each contact has a circular shape with a diameter D1 of about 50 μm as shown in FIG. 1. The thickness t1 (see FIG. 3) of each contact in the stacking direction is preferably, but not limited to, 6 μm or more and 45 μm or less. The distance D2 (see FIGS. 1 and 3) between each of the contacts is preferably, but not limited to, for example, 10 μm or more and 40 μm or less. In this embodiment, the distance D2 between each of the contacts is about 25 μm. In other words, the arrangement pitch P of each of the surface side contacts arranged in a lattice pattern is about 75 μm.

[0045] <Front contact group: Arrangement of front contact group> 1 and 4, the multiple front-side contact groups 5 are arranged in a lattice pattern. In this embodiment, the first to ninth front-side contact groups 51 to 59 are arranged in a 3×3 lattice pattern with the first front-side contact group 51 at the center.

[0046] The size and shape of each surface side contact group 5 may be, for example, a rectangular shape of 80 μm×80 μm or more and about 320 μm×320 μm, but is not limited thereto. In this embodiment, each surface side contact group 5 is a rectangular shape of about 200 μm×200 μm. That is, each contact constituting one surface side contact group 5 is formed in a rectangular area of ​​about 200 μm×200 μm.

[0047] The distance D3 between each of the front-side contact groups is preferably, for example, 100 μm or more and 200 μm or less, but is not limited thereto. In this embodiment, the distance D3 between each of the front-side contact groups is about 150 μm. In other words, the arrangement pitch P1 of each of the front-side contact groups arranged in a lattice pattern is about 350 μm.

[0048] Among the multiple surface-side contacts 50 constituting one surface-side contact group 5, the distance D2 between adjacent surface-side contacts 50 is smaller than the distance D3 between adjacent surface-side contact groups 5. Specifically, the distance D2 between the first surface-side contact 511 and the ninth surface-side contact 519 constituting the first surface-side contact group 51 is shorter than the distance D3 between the first surface-side contact group 51 and the second surface-side contact group 52, i.e., the distance D3 between the first surface-side contact 511 of the first surface-side contact group 51 and the first surface-side contact 521 of the second surface-side contact group 52.

[0049] <Back side contact group> As shown in FIG. 2, the laminated substrate 1 has a plurality of rear surface side contact groups 6 in the same form as the front surface side contact group 5. The laminated substrate 1 may have a first rear surface side contact group 61 and a second rear surface side contact group 62 as the plurality of rear surface side contact groups 6. The laminated substrate 1 of this embodiment further has third to ninth rear surface side contact groups 63 to 69 as the plurality of rear surface side contact groups 6. The laminated substrate 1 may have even more rear surface side contact groups 6. Each rear surface side contact group 6 has a plurality of contacts. Since the configuration of each contact constituting each rear surface side contact group 6 is the same, each contact constituting each rear surface side contact group 6 may be referred to as a rear surface side contact 60.

[0050] The first back surface side contact group 61 is formed on the back surface side of the substrate body 10 at positions on the back surface side corresponding to the positions of the first front surface side contact group 51 .

[0051] In this embodiment, the first rear surface side contact group 61 is configured by nine rear surface side contacts 611 to 619 as the multiple rear surface side contacts 60, including a first rear surface side contact 611.

[0052] The second rear surface side contact group 62 is formed on the rear surface side of the substrate body 10. In this embodiment, the second rear surface side contact group 62 is formed at a position on the rear surface side corresponding to the position of the second front surface side contact group 52.

[0053] In this embodiment, the second back surface side contact group 62 is composed of nine back surface side contacts 60 including the first back surface side contact 621 of the second back surface side contact group 62 as the multiple back surface side contacts 60.

[0054] The third rear surface side contact group 63 is formed on the rear surface side of the substrate body 10. In this embodiment, the third rear surface side contact group 63 is formed at a position on the rear surface side corresponding to the position of the third front surface side contact group 53.

[0055] In this embodiment, the third back surface side contact group 63 is composed of nine back surface side contacts 60 including the first back surface side contact 631 of the third back surface side contact group 63 as the multiple back surface side contacts 60.

[0056] The fourth to ninth rear surface side contact groups 64-69 are similarly formed on the rear surface side of the substrate body 10. Each of the fourth to ninth rear surface side contact groups 64-69 is made up of a plurality of rear surface side contacts 60. In this embodiment, each of the fourth to ninth rear surface side contact groups 64-69 has the same configuration as the first to third rear surface side contact groups 61-63, and is made up of nine rear surface side contacts 60.

[0057] The first to ninth rear surface side contact groups 61 to 69 are connected to the internal electrode layers 3 or the opposing internal electrode layers 4 through via connections 7 as appropriate.

[0058] <Back side contact group: Arrangement of back side contacts> The arrangement of the back side contacts 60 of the back side contact group 6 will be described using the ninth back side contact group 69 shown in the lower left of FIG. 2 as an example. Each back side contact group 6 is preferably composed of a back side center contact 609 and three or more back side peripheral contact groups 610 arranged to surround the back side center contact 609. In this embodiment, the back side peripheral contact group 610 is composed of eight back side contacts 60 arranged to surround the back side center contact 609. It is preferable that the back side peripheral contact groups 610 are arranged at equal angular intervals with the back side center contact 609 as the reference. In this embodiment, the back side peripheral contact groups 610 are arranged at 45° angular intervals with the back side center contact as the reference. Each back side contact group is arranged in a 3×3 grid.

[0059] For example, the first rear surface side contact group 61 is composed of a rear surface side central contact 619 and eight rear surface side peripheral contact groups 611-618. For example, the second rear surface side contact group 62 is composed of a rear surface side central contact 629 and eight rear surface side peripheral contact groups. In this embodiment, the nine rear surface side contacts 611-619 of the first rear surface side contact group 61 are formed at positions on the rear surface side corresponding to the positions of the nine front surface side contacts 511-519 of the first front surface side contact group 51, respectively.

[0060] The size and shape of each rear contact may be, for example, a circular shape with a diameter of 20 μm or more and 80 μm or less, but is not limited to this. In this embodiment, each contact is a circular shape with a diameter D4=50 μm or so. The thickness of each contact in the stacking direction is preferably, but is not limited to, 6 μm or more and 45 μm or less. The distance between each contact is preferably, but is not limited to, for example, 10 μm or more and 40 μm or less. In this embodiment, the distance between each contact is about 25 μm. In other words, the arrangement pitch of each front contact arranged in a lattice is about 75 μm.

[0061] <Back side contact group: Layout of back side contact group> The multiple rear surface side contact groups 6 are arranged in a lattice pattern. The first to ninth rear surface side contact groups 61 to 69 of this embodiment are arranged in a 3×3 lattice pattern with the first rear surface side contact group 61 at the center. In this embodiment, the first to ninth rear surface side contact groups 61 to 69 are formed at positions on the rear surface side corresponding to the positions of the first to ninth front surface side contact groups 51 to 59, respectively. However, this is not limited thereto. For example, the second rear surface side contact group 62 may be formed at a position on the rear surface side corresponding to the position of the third front surface side contact group 53. The third rear surface side contact group 63 may be formed at a position on the rear surface side corresponding to the position of the second front surface side contact group 52, for example.

[0062] The size and shape of each rear surface side contact group 6 may be, for example, a rectangular shape of 80 μm×80 μm or more and about 320 μm×320 μm, but is not limited thereto. Each rear surface side contact group 6 is a rectangular shape of about 250 μm×250 μm. That is, each contact constituting one rear surface side contact group 6 is formed in a rectangular area of ​​about 250 μm×250 μm.

[0063] As shown in Fig. 2, the distance D6 between each rear surface side contact group is preferably, for example, 100 μm or more and 200 μm or less, but is not limited thereto. In this embodiment, the distance D6 between each rear surface side contact group is about 150 μm. In other words, the arrangement pitch P2 (see Fig. 2) of each rear surface side contact group 6 arranged in a lattice pattern is about 350 μm.

[0064] In addition, the distance D5 between adjacent back side contacts 60 among the multiple back side contacts 60 constituting one back side contact group 6 is smaller than the distance D6 between adjacent back side contact groups. For example, the distance D5 between the first back side contact 611 and the ninth back side contact 619 constituting the first back side contact group 61 is shorter than the distance D6 between the first back side contact group 61 and the second back side contact group 62, i.e., the distance D6 between the first back side contact 611 of the first back side contact group 61 and the first back side contact 621 of the second back side contact group 62.

[0065] <Via connection> A plurality of via connections 7 are arranged in the laminated substrate 1. The via connections 7 are arranged inside holes extending in the lamination direction provided in the substrate body 10. The via connections 7 electrically connect the contacts (front surface side contacts 50, back surface side contacts 60) constituting the external electrodes to the internal electrodes.

[0066] 5 illustrates via connection portions 711, 712, 719, 721, 729, 731, and 739 as the via connection portion 7. For example, as shown in FIG. 5, the via connection portion 711 electrically connects the first surface side contact 511 of the first surface side contact group 51 and the first internal electrode layer 31. The via connection portion 721 electrically connects the first surface side contact 521 of the second surface side contact group 52 and the first opposing internal electrode layer 41.

[0067] For example, the via connection portion 712 electrically connects the second surface side contact 512 of the first surface side contact group 51 and the second internal electrode layer 32. The via connection portion 731 electrically connects the first surface side contact 531 of the third surface side contact group 53 and the second opposing internal electrode layer 42.

[0068] In this embodiment, the via connection portion 7 is a through via that penetrates from the front surface to the back surface of the substrate body 10. For example, the via connection portion 711 electrically connects the first front surface side contact 511 of the first front surface side contact group 51, the first internal electrode layer 31, and the first back surface side contact 611.

[0069] The via connection portion 7 may be a blind via in which the via connection portion 7 is not exposed on the back surface of the substrate body 10, instead of a through via that penetrates from the front surface to the back surface of the substrate body 10. The blind via penetrates, for example, from the front surface of the substrate body 10 to the layer in which the internal electrode layer 3 is arranged.

[0070] The shape of the via connection portion 7 may be, but is not limited to, a cylindrical shape. In this embodiment, the via connection portion 7 has a cylindrical shape with a diameter slightly smaller than that of the contact point.

[0071] The via connection portion 7 is made of a conductor. In this embodiment, the via connection portion 7 is made of, for example, copper (Cu).

[0072] Here, at least one front surface side contact 50 in the first front surface side contact group 51 and at least one back surface side contact 60 in the first back surface side contact group 61 are electrically connected via a through via connection portion 7 to form a through electrode for the laminated substrate 1. In this embodiment, a ninth front surface side contact 519 which is a front surface side central contact of the first front surface side contact group 51 and a ninth back surface side contact 619 which is a back surface side central contact of the first back surface side contact group 61 are electrically connected via a through via connection portion 719 to form a laminated substrate through electrode 2.

[0073] In addition, the through via connection portion 719 connecting the ninth front surface side contact 519 and the ninth back surface side contact 619 is preferably a connection portion to which the internal electrode layer 3 is not connected. That is, the first front surface side contact group 51 has a front surface side contact 50 (for example, the first front surface side contact 511) electrically connected to the internal electrode layer 3 and a through front surface side contact 50 (for example, the ninth front surface side contact 519) not electrically connected to the internal electrode layer 3, and it is preferable that at least the through front surface side contact 50 is electrically connected to a through back surface side contact 60 (for example, the ninth back surface side contact 619) arranged on the back surface side of the substrate body 10 via a through via connection portion 7 (for example, the via connection portion 719).

[0074] In addition, the contacts of the laminated substrate through-electrode 2 of the laminated substrate 1 are formed by the front-side central contact 509 of the front-side contact group 5 and the back-side central contact 609 of the back-side contact group 6, and three or more front-side peripheral contact groups 510 and back-side peripheral contact groups 610 arranged to surround the front-side central contact 509 and the back-side central contact 609 are electrically connected to the internal electrode layer 3, respectively, thereby ensuring the area in which the internal electrode layer 3 extends. This makes it easy to ensure the capacitance. In addition, the degree of freedom in designing the laminated substrate 1 is increased.

[0075] The back surface side contact group 6 may not be formed on the laminated substrate 1. In this case, the laminated substrate 1 has one through back surface side contact 60 (e.g., back surface side contact 619) formed on the back surface side of the substrate body 10 at a position on the back surface side corresponding to the position of the first front surface side contact group 51, and at least one front surface side contact 50 (e.g., first front surface side contact 519) in the first front surface side contact group 51 and the through back surface side contact 60 (e.g., back surface side contact 619) are preferably electrically connected via a through via connection portion 7 (e.g., via connection portion 719). In this case, the internal electrode layer 3 and the front surface side contact 50 electrically connected to the internal electrode layer 3 are connected by the above-mentioned blind via.

[0076] In this manner, the laminated substrate 1 of this embodiment further includes a back surface side contact 60 formed on the back surface side of the substrate main body 10 at a position on the back surface side corresponding to the position of the first front surface side contact group 51, and the ninth front surface side contact 519 of the first front surface side contact group 51 and the back surface side contact 60 are electrically connected via a through via connection portion 719.

[0077] Similarly, via connections 7 are provided to appropriately electrically connect the front surface side contacts 50, the back surface side contacts 60, the internal electrode layers 3, and the opposing internal electrode layers 4. Back side contacts 60 are arranged at positions on the back side of all of the front side contacts 50 corresponding to each other. The front side contacts 50 and the back side contacts 60 arranged at corresponding positions on the front and back sides are electrically connected by via connection parts 7. In this embodiment, the via connection part 7 connecting the front side central contact 509 and the back side central contact 609 is formed as a through via connection part 7. An internal electrode is connected to the via connection part 7 connecting the front side peripheral contact group 510 and the back side peripheral contact group 610.

[0078] <Contact structure> The structure of each contact (front surface contacts 50, rear surface contacts 60) constituting the front surface contact group 5 and the rear surface contact group 6 as external electrodes will be described below. Each contact can basically be configured to have the same structure.

[0079] 6 shows a cross section of the front side contact 50 or the back side contact 60. Hereinafter, this will be referred to as the front side contact 50, but the same applies to the back side contact 60. The front side contact 50 has a base electrode layer 101 and a plating layer 102 disposed on the base electrode layer 101. The base electrode layer 101 includes at least one selected from a thin film layer, a baked layer, and the like.

[0080] In this embodiment, the base electrode layer 101 is a thin film layer. The thin film layer is a layer on which metal particles are deposited. When the base electrode layer 101 is formed as a thin film layer, it is preferably formed by a thin film formation method such as a sputtering method or a vapor deposition method. Here, a sputtered electrode formed by a sputtering method will be described.

[0081] The base electrode layer 101 of this embodiment is composed of a thin film layer formed by a sputtered electrode. When the base electrode layer 101 is formed by a sputtered electrode, it is preferable to form the sputtered electrode so as to cover the exposed surface of the via connection portion 7.

[0082] The thin film layer formed by the sputtering electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. The thin film layer may be a single layer or may be formed of multiple layers. For example, the thin film layer may be formed of a two-layer structure of a layer of Ni-Cr alloy and a layer of Ni-Cu alloy.

[0083] The thickness of the sputtered electrode in the lamination direction is preferably 50 nm or more and 400 nm or less, and more preferably 50 nm or more and 130 nm or less.

[0084] The plating layer 102 is disposed so as to cover the base electrode layer 101 .

[0085] The plating layer 102 may contain, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The plating layer 102 may each be formed of a plurality of layers.

[0086] The plating layer 102 may have a two-layer structure in which a Sn plating layer 105 is formed on a Ni plating layer 104. In this case, the Ni plating layer 104 prevents the base electrode layer 101 from being eroded by solder when mounting the laminated substrate 1. The Sn plating layer also improves the wettability of the solder when mounting the laminated substrate 1. This makes it easier to mount the laminated substrate 1.

[0087] A Cu plating layer 103 may be formed between the base electrode layer 101 and the Ni plating layer 104. The Cu plating layer 103 has the effect of suppressing the intrusion of plating solution and moisture.

[0088] 8, the plating layer 102 of this embodiment is formed of a three-layer structure including a Cu plating layer 103 as a lower plating layer, a Ni plating layer 104 as a middle plating layer, and a Sn plating layer 105 as an upper plating layer.

[0089] The Cu plating layer 103 is disposed so as to cover the exposed surface of the via connection portion 7. The Ni plating layer 104 is disposed so as to cover the Cu plating layer 103. The Sn plating layer 105 is disposed so as to cover the Ni plating layer 104.

[0090] By providing plating layer 102 consisting of Cu plating layer 103 and Ni plating layer 104 so as to cover base electrode layer 101, erosion of base electrode layer 101 by solder when mounting laminated substrate 1 is prevented. Furthermore, by further providing Sn plating layer 105 on the surface of Ni plating layer 104, wettability of solder when mounting laminated substrate 1 is improved. This allows laminated substrate 1 to be easily mounted.

[0091] The thickness of each plating layer 102 is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the Cu plating layer 103, the Ni plating layer 104, and the Sn plating layer 105 is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of the Cu plating layer 103 is more preferably 5 μm or more and 8 μm or less. Also, the average thickness of each of the Ni plating layer 104 and the Sn plating layer 105 is more preferably 2 μm or more and 4 μm or less.

[0092] Note that the base electrode layer 101 may not be provided, and only the plating layer 102 may form a contact point. In this case, the plating layer 102 is disposed directly on the exposed surface of the via connection portion 7. When the plating layer 102 is formed directly on the exposed surface of the via connection portion 7 without forming the base electrode layer 101, it is preferable to form a Cu plating layer 103 between the exposed surface of the via connection portion 7 and the Ni plating layer 104. The Cu plating layer 103 has the effect of suppressing the intrusion of a plating solution and moisture.

[0093] The via connection portion 7 may be integral with the front surface side contact 50 and the back surface side contact 60, and the exposed surface of the via connection portion 7 may be used as a contact as it is.

[0094] Here, with reference to FIGS. 1, 4A, 4B, and 5, the relationship between the internal electrode layers 3 and the opposing internal electrode layers 4 in this embodiment will be described in detail below, including the relationship with the front surface side contact group 5.

[0095] The laminated substrate 1 includes a substrate body 10 including a dielectric layer 8 and a plurality of internal electrodes, a first surface side contact group 51 formed on the surface side of the substrate body 10 and having a plurality of surface side contacts 50, and a second surface side contact group 52 formed on the surface side of the substrate body 10 and having a plurality of surface side contacts 50, the internal electrodes having a first internal electrode layer 31 and a first opposing internal electrode layer 41, the first surface side contact 511 of the first surface side contact group 51 being electrically connected to the first internal electrode layer 31 disposed inside the substrate body 10, and the first surface side contact 521 of the second surface side contact group 52 being electrically connected to the first opposing internal electrode layer 41 disposed opposite the first internal electrode layer 31 across the dielectric layer 8. The electrical connection between the surface side contact 50 and the internal electrodes is realized by a via connection portion 7. The electrical connection between the surface side contact 50 and the internal electrodes is realized by the via connection portion 7 in the following configurations as well.

[0096] The laminated substrate 1 further includes a third surface side contact group 53 formed on the surface side of the substrate main body 10 and having a plurality of surface side contacts 50, and the plurality of internal electrodes further includes a second internal electrode layer 32 and a second opposing internal electrode layer 42, the second surface side contacts 512 of the first surface side contact group 51 being electrically connected to the second internal electrode layer 32 arranged inside the substrate main body 10, and the first surface side contacts 531 of the third surface side contact group 53 being electrically connected to the second opposing internal electrode layer 42 arranged opposite the second internal electrode layer 32 across the dielectric layer 8.

[0097] The laminated substrate 1 further includes a fourth surface side contact group 54 formed on the surface side of the substrate main body 10 and having a plurality of surface side contacts 50, and the plurality of internal electrodes further includes a third internal electrode layer 33 and a third opposing internal electrode layer 43, and the third surface side contact 513 of the first surface side contact group 51 is electrically connected to the third internal electrode layer 33 arranged inside the substrate main body 10, and the first surface side contact 541 of the fourth surface side contact group 54 is electrically connected to the third opposing internal electrode layer 43 arranged opposite the third internal electrode layer 33 across the dielectric layer 8.

[0098] The laminated substrate 1 further includes a fifth surface side contact group 55 formed on the surface side of the substrate main body 10 and having a plurality of surface side contacts 50, and the plurality of internal electrodes further includes a fourth internal electrode layer 34 and a fourth opposing internal electrode layer 44, and the fourth surface side contact 514 of the first surface side contact group 51 is electrically connected to the fourth internal electrode layer 34 arranged inside the substrate main body 10, and the first surface side contact 551 of the fifth surface side contact group 55 is electrically connected to the fourth opposing internal electrode layer 44 arranged opposite the fourth internal electrode layer 34 across the dielectric layer 8.

[0099] The laminated substrate 1 further includes a sixth surface side contact group 56 formed on the surface side of the substrate main body 10 and having a plurality of surface side contacts 50, and the plurality of internal electrodes further includes a fifth internal electrode layer 35 and a fifth opposing internal electrode layer 45, and the fifth surface side contact 515 of the first surface side contact group 51 is electrically connected to the fifth internal electrode layer 35 arranged inside the substrate main body 10, and the first surface side contact 561 of the sixth surface side contact group 56 is electrically connected to the fifth opposing internal electrode layer 45 arranged opposite the fifth internal electrode layer 35 across the dielectric layer 8.

[0100] The laminated substrate 1 further includes a seventh surface side contact group 57 formed on the surface side of the substrate main body 10 and having a plurality of surface side contacts 50, and the plurality of internal electrodes further includes a sixth internal electrode layer 36 and a sixth opposing internal electrode layer 46, and the sixth surface side contact 516 of the first surface side contact group 51 is electrically connected to the sixth internal electrode layer 36 arranged inside the substrate main body 10, and the first surface side contact 571 of the seventh surface side contact group 57 is electrically connected to the sixth opposing internal electrode layer 46 arranged opposite the sixth internal electrode layer 36 across the dielectric layer 8.

[0101] The laminated substrate 1 further includes an eighth surface side contact group 58 formed on the surface side of the substrate main body 10 and having a plurality of surface side contacts 50, and the plurality of internal electrodes further includes a seventh internal electrode layer 37 and a seventh opposing internal electrode layer 47, and the seventh surface side contact 517 of the first surface side contact group 51 is electrically connected to the seventh internal electrode layer 37 arranged inside the substrate main body 10, and the first surface side contact 581 of the eighth surface side contact group 58 is electrically connected to the seventh opposing internal electrode layer 47 arranged opposite the seventh internal electrode layer 37 across the dielectric layer 8.

[0102] The laminated substrate 1 further includes a ninth surface side contact group 59 formed on the surface side of the substrate main body 10 and having a plurality of surface side contacts 50, and the plurality of internal electrodes further includes an eighth internal electrode layer 38 and an eighth opposing internal electrode layer 48, and the eighth surface side contact 518 of the first surface side contact group 51 is electrically connected to the eighth internal electrode layer 38 arranged inside the substrate main body 10, and the first surface side contact 591 of the ninth surface side contact group 59 is electrically connected to the eighth opposing internal electrode layer 48 arranged opposite the eighth internal electrode layer 38 across the dielectric layer 8.

[0103] This increases the degree of freedom in wiring design when mounting the multilayer substrate 1.

[0104] Here, the laminated substrate 1 having the rear surface side contact group 6 will be described with reference to FIG.

[0105] The laminated substrate 1 includes a first back surface side contact group 61 having a plurality of back surface side contacts 60 formed on the back surface side of the substrate body 10 at positions corresponding to the positions of the first front surface side contact group 51, and a second back surface side contact group 62 formed on the back surface side of the substrate body 10 and having a plurality of back surface side contacts 60. At least one back surface side contact 60 (e.g., the first back surface side contact 611) of the first back surface side contact group 61 is electrically connected to at least one internal electrode layer 3 (e.g., the first internal electrode layer 31) disposed inside the substrate body 10, and at least one back surface side contact 60 (e.g., the first back surface side contact 621) of the second back surface side contact group 62 is electrically connected to at least one opposing internal electrode layer 4 (e.g., the first opposing internal electrode layer 41) disposed opposite one internal electrode layer 3 with a dielectric layer 8 interposed therebetween. The electrical connection between the back surface side contact 60 and the internal electrode is realized by a via connection portion 7. The electrical connection between the back surface side contact 60 and the internal electrode is achieved by the via connection portion 7, which is the same in the following configurations.

[0106] The laminated substrate 1 is formed on the back side of the substrate main body 10 and has a second back side contact group 62 having a plurality of back side contacts 60, and at least one front side contact 50 (e.g., the first front side contact 511) of the first front side contact group 51 is electrically connected to at least one internal electrode layer 3 (e.g., the first internal electrode layer 31) arranged inside the substrate main body 10, and at least one back side contact 60 (e.g., the first back side contact 621) of the second back side contact group 62 is electrically connected to at least one opposing internal electrode layer 4 (e.g., the first opposing internal electrode layer 41) arranged opposite one internal electrode layer 3 across a dielectric layer 8.

[0107] For example, in FIG. 5, the back surface side contact 631 is connected to the second opposing internal electrode layer 42, and the front surface side contact 512 is connected to the internal electrode 32, forming a capacitor via the dielectric layer 8.

[0108] This allows greater freedom in wiring design when mounting the multilayer substrate 1.

[0109] The laminated substrate 1 has a back side contact 60 (e.g., back side contact 619) formed on the back side of the substrate main body 10 at a position on the back side corresponding to the position of the first surface side contact group 51, and at least one surface side contact 50 (e.g., the ninth surface side contact 519) in the first surface side contact group 51 and the back side contact 60 are electrically connected via a via connection portion 7 (e.g., via connection portion 719).

[0110] The laminated substrate 1 has a first back surface side contact group 61 having a plurality of back surface side contacts 60 formed on the back surface side of the substrate main body 10 at positions on the back surface side corresponding to the positions of the first front surface side contact group 51, and at least one front surface side contact 50 (e.g., the ninth front surface side contact 519) in the first front surface side contact group 51 and at least one back surface side contact 60 (e.g., the ninth back surface side contact 619) in the first back surface side contact group 61 are conductively connected via a via connection portion 7 (e.g., via connection portion 719).

[0111] 5, the back surface side contact 619 is electrically connected to the front surface side contact 519 through a via connection portion 719. The back surface side contact 629 is electrically connected to the front surface side contact 529 through a via connection portion 729. The back surface side contact 619 is electrically connected to the front surface side contact 519 through a via connection portion 739.

[0112] This allows the capacitor function and the through function to be used in appropriate combination, which increases the degree of freedom in wiring design when mounting the multilayer substrate 1.

[0113] Fig. 7 shows a modified example of the shape of the internal electrode. As shown in Fig. 7, the shape of the internal electrode layer 3 and the opposing internal electrode layer 4 is not limited to the rectangular shape of Fig. 4, but may be an ellipse or an oval shape. Also, as shown in Fig. 7, when the portion where the internal electrode layer 3 and the opposing internal electrode layer 4 face each other is defined as a facing portion, the facing portions may have different areas.

[0114] Fig. 8 shows a modified example of the layer structure of the dielectric layers 8 constituting the substrate body 10. As shown in Fig. 8, the substrate body 10 may be configured by laminating a large number of dielectric layers 8. In the example shown in Fig. 8, there are eight interlayer spaces between the dielectric layers 8, B1 to B8. In the example shown in Fig. 8, the first internal electrode layer 31 is disposed at the interlayer position indicated by B5, and the second internal electrode layer 32 is disposed at the interlayer position indicated by B6.

[0115] The first internal electrode layer 31 and the second internal electrode layer 32 may be disposed on the same dielectric layer 8 or on different dielectric layers 8. The first opposing internal electrode layer 41 (not shown in FIG. 8) and the second opposing internal electrode layer 42 (not shown in FIG. 8) may be disposed on the same dielectric layer 8 or on different dielectric layers 8. For example, the first internal electrode layer 31 and the second opposing internal electrode layer 42 may be disposed on the same dielectric layer 8, and the first opposing internal electrode layer 41 and the second internal electrode layer 32 may be disposed on the same dielectric layer 8. Also, the first internal electrode layer 31, the first opposing internal electrode layer 41, the second internal electrode layer 32, and the second opposing internal electrode layer 42 may all be disposed on different dielectric layers. Also, the first to eighth internal electrode layers 31 to 38 may all be disposed on different dielectric layers.

[0116] As shown in FIG. 8, blind vias such as via connection portion 711 and via connection portion 712 may be used as the via connection portion 7.

[0117] <Manufacturing method> Next, a method for manufacturing the multilayer substrate 1 of this embodiment will be described.

[0118] A dielectric sheet for the dielectric layer 8 and a conductive paste for the internal electrodes are prepared. The dielectric sheet and the conductive paste for the internal electrodes contain a binder and a solvent. The binder and the solvent may be known. The paste made of a conductive material is, for example, a metal powder to which an organic binder and an organic solvent are added.

[0119] A conductive paste for the internal electrodes is printed in a predetermined pattern on the dielectric sheets by, for example, screen printing, gravure printing, etc. In this way, a plurality of types of dielectric sheets on which the patterns of the internal electrodes are formed are prepared.

[0120] A predetermined number of dielectric sheets not printed with an internal electrode pattern are laminated to form a portion that will become the dielectric layer 8 on the front side. On top of that, multiple types of dielectric sheets printed with an internal electrode pattern are laminated. On top of that, a predetermined number of dielectric sheets not printed with an internal electrode pattern are laminated to form a portion that will become the dielectric layer 8 on the back side. In this way, a laminated sheet is produced.

[0121] The laminated sheets are pre-pressed at a low pressure by means of a hydrostatic press or the like to produce a laminated block. Via holes are formed at predetermined positions in the laminated block. The via holes are formed, for example, by a laser or the like. Via paste for via connections is prepared, and the via paste that becomes the via connections 7 is filled into the via holes formed in the laminated block.

[0122] The laminated block filled with the via paste is pressed at high pressure by means of a hydrostatic press or the like to produce a laminated block after the press. The front and back surfaces of the laminated block after the press are polished by a grinder or the like. The polished laminated block is cut to a predetermined substrate size to obtain laminated chips.

[0123] The laminated chip is fired to produce a substrate body 10 having via connections 7. The firing temperature depends on the materials of the dielectric layers 8 and the internal electrode layers 3, but is preferably 900° C. or higher and 1400° C. or lower.

[0124] When the base electrode layer 101 is formed as a thin film layer, a thin film layer is formed as the base electrode layer 101 on the exposed surface of the via connection portion 7 by performing masking or the like. The thin film layer is formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0125] Thereafter, a plating layer 102 is formed on the surface of the laminate and on the base electrode layer 101 made of a thin film layer. In this embodiment, as shown in Fig. 8, three plating layers 102 are formed, that is, a Cu plating layer 103, a Ni plating layer 104, and a Sn plating layer 105.

[0126] Through the manufacturing process described above, the multilayer substrate 1 having ceramic capacitors in its inner layers is manufactured. <Mounting structure>

[0127] FIG. 9 shows a mounting structure of a circuit board 200 including a silicon substrate 201 having an integrated circuit (not shown) and the laminated substrate 1 of this embodiment.

[0128] The mounting structure of the circuit board 200 includes a base substrate 206, a plurality of silicon substrates 201 carrying integrated circuits stacked on the base substrate 206, and the laminated substrate 1 of this embodiment sandwiched between the two silicon substrates 201.

[0129] The multiple silicon substrates 201 have through-silicon vias (TSVs) 204. Connection terminals of the base substrate 206 and the TSVs 204 of the integrated circuits are connected by solder bumps 207. The TSVs 204 of the multiple stacked integrated circuits are connected by solder bumps 205. The circuit substrate 200 is mounted on an electronic circuit (not shown in FIG. 9) through bumps 208 as appropriate.

[0130] 10 is a partial enlarged view showing a connection portion between the contacts (front surface side contact group 5, back surface side contact group 6) of the laminated substrate 1 of this embodiment in FIG. 9 and the TSVs 204 of the silicon substrate 201. The laminated substrate 1 is inserted between two silicon substrates 201. The contacts of the laminated substrate 1 and the TSVs 204 of the silicon substrate 201 are connected by solder bumps 205.

[0131] One solder bump 205 covers one front side contact group 5 or one back side contact group 6. The arrangement pitch L1 of the solder bumps 205 is the same as the arrangement pitch P1 (see FIG. 1) of the front side contact group 5 and the back side contact group 6 of the laminated substrate 1 of this embodiment, and is, for example, about 350 μm. The size of the solder bump 205 is preferably the same as the size of the front side contact group 5 and the back side contact group 6, and is, for example, about 200 μm or more and 250 μm or less in diameter. The thickness of the solder bump 205 in the stacking direction is preferably thicker than the thickness of the contact of the laminated substrate 1 in the stacking direction, and is, for example, 50 μm or more, preferably about 140 μm. This allows the solder bump 205 to almost cover one front side contact group 5 or one back side contact group 6.

[0132] Figure 11 is a schematic diagram showing a portion of the laminated substrate 1 immediately before being mounted by solder bumps 205, and is an example in which a capacitor is formed between a first surface side contact 511 of the first surface side contact group 51 and a first surface side contact 521 of the second surface side contact group 52.

[0133] The multiple front surface side contacts 50 and back surface side contacts 60 of the laminated substrate 1 of this embodiment are covered with an insulating film 209, except for some of the contacts, before being mounted by the solder bumps 205. For example, the front surface side contacts 50 and back surface side contacts 60 of the laminated substrate 1 are covered with the insulating film 209 so that the first front surface side contacts 511 of the first front surface side contact group 51 and the first front surface side contacts 521 of the second front surface side contact group 52 are exposed.

[0134] Thereafter, solder bumps 205 are arranged so as to correspond to each of the contact groups, and the laminated substrate 1 is mounted.

[0135] This results in the function of a capacitor being realized between the first internal electrode layer 31 connected to the first surface side contact 511 of the first surface side contact group 51 and the first opposing internal electrode layer 41 connected to the first surface side contact 521 of the second surface side contact group 52.

[0136] Figure 12 shows an example in which a laminated substrate through electrode 2 is formed using the ninth surface side contact 539 of the third surface side contact group 53, the ninth back surface side contact 639 of the third back surface side contact group 63, and a through via connection portion 739.

[0137] For example, except for the first surface side contact 511 of the first surface side contact group 51, the first surface side contact 521 of the second surface side contact group 52, the ninth surface side contact 539 of the third surface side contact group 53, and the ninth back side contact 639 of the third back side contact group 63, the surface side contacts 50 and the back side contacts 60 of the laminated substrate 1 are covered by the insulating film 209.

[0138] Thereafter, the solder bumps 205 are arranged so as to correspond to the front surface side contact group 5 and the back surface side contact group 6, and the laminated substrate 1 is mounted.

[0139] This results in the function of a capacitor being realized between the first internal electrode layer 31 connected to the first surface side contact 511 of the first surface side contact group 51 and the first opposing internal electrode layer 41 connected to the first surface side contact 521 of the second surface side contact group 52.

[0140] Furthermore, the ninth front surface side contact 539 of the third front surface side contact group 53 and the ninth back surface side contact 639 of the third back surface side contact group 63 form the contact of the multilayer substrate through electrode 2 .

[0141] FIG. 13 is an example of a circuit diagram in which the laminated substrate 1 of FIG. 12 and the silicon substrate 201 arranged on the surface of the laminated substrate 1 are connected, and the capacitor portion of the laminated substrate 1 and the integrated circuit 202 of the silicon substrate 201 are connected to configure a predetermined circuit. The laminated substrate through electrode 2 mentioned in FIG. 12 connects the common electrode or ground (GND) of the base substrate 206 to the integrated circuit 202 in FIG. 13, for example. Then, the capacitance formed between the first internal electrode layer 31 and the first opposing internal electrode layer 41 mentioned in FIG. 12 is set between the Vdd line and the GND line. This allows a decoupling capacitor to be provided close to the integrated circuit 202. Note that the configuration of the line (laminated substrate through electrode 2) connecting the power supply V and the Vdd line shown on the right side of FIG. 13 is omitted in FIG. 12, but this configuration can be formed by connecting any of the front side contact group 5 and the back side contact group 6 not shown in FIG. 12 with the via connection portion 7.

[0142] (Variation 1) 14 shows an example in which a capacitor is formed between a first back surface side contact 611 of the first back surface side contact group 61 and a first back surface side contact 621 of the second back surface side contact group 62. The setting of the insulating film 209 is different from that in FIG.

[0143] The laminated substrate 1 further includes a first back surface side contact group 61 having a plurality of back surface side contacts 60 formed on the back surface side of the substrate body 10 at positions corresponding to the positions of the first front surface side contact group 51, and a second back surface side contact group 62 formed on the back surface side of the substrate body 10 and having a plurality of back surface side contacts 60. The first back surface side contacts 611 of the first back surface side contact group 61 are electrically connected to the first internal electrode layer 31 arranged inside the substrate body 10, and the first back surface side contacts 621 of the second back surface side contact group 62 are electrically connected to the first opposing internal electrode layer 41 arranged opposite the first internal electrode layer 31 across the dielectric layer 8. In this modified example, the plurality of front surface side contacts 50 and the back surface side contacts 60 of the laminated substrate 1 are covered with an insulating film 209 except for the contacts used as actual contacts. This point is the same in the following modified examples.

[0144] (Variation 2) FIG. 15 shows an example in which a capacitor is formed between a first front surface side contact 511 of the first front surface side contact group 51 and a first back surface side contact 621 of the second back surface side contact group 62. In FIG.

[0145] The laminated substrate 1 is formed on the back side of the substrate main body 10 and has a second back side contact group 62 having a plurality of back side contacts 60, and a first front side contact 511 which is one of the front side contacts 50 in the first front side contact group 51 is electrically connected to a first internal electrode layer 31 arranged inside the substrate main body 10, and a first back side contact 621 which is one of the back side contacts 60 in the second back side contact group 62 is electrically connected to a first opposing internal electrode layer 41 arranged opposite the first internal electrode layer 31 across the dielectric layer 8.

[0146] (Variation 3) FIG. 16 shows an example in which the formation of through electrodes, the formation of decoupling capacitors, and the formation of capacitors between integrated circuits, which are described in FIGS. 12, 14, and 15, are simultaneously realized. The front side contact group 5 and the back side contact group 6 are increased, but are not referenced here. As shown in FIG. 16, the laminated substrate 1 according to this embodiment allows the appropriate combination of capacitors and throughs to be used. When used for decoupling purposes, one is connected to a power supply line and the other to a GND line. The power supply line and the GND line run to the integrated circuits located above and below the laminated substrate 1, respectively, and are connected via the laminated substrate through electrodes 2 of the laminated substrate 1.

[0147] (Variation 4) Fig. 17 is a cross-sectional view of an example in which the laminated substrate 1 functions as a decoupling capacitor for integrated circuits located above and below the laminated substrate 1. Fig. 18 is an equivalent circuit corresponding to the configuration of Fig. 17. In Fig. 17, each electrode is given a generic reference symbol, for example, front-side contact 50.

[0148] 17, in the area surrounded by dotted line A, the front surface side contacts 50 and the back surface side contacts 60 are electrically connected by the laminated substrate through-hole electrode 2. In the area surrounded by dotted line B, adjacent back surface side contacts 60 are connected to the internal electrode layer 3 and the opposing internal electrode layer 4 in a shifted manner, thereby forming a capacitance. In the area surrounded by dotted line C, adjacent front surface side contacts 50 are connected to the internal electrode layer 3 and the opposing internal electrode layer 4 in a shifted manner, thereby forming a capacitance.

[0149] As shown in Fig. 18, in the area surrounded by dotted line A, the laminated substrate through electrode 2 grounds the upper integrated circuit 202 and the lower integrated circuit 202. In the area surrounded by dotted line B, the capacitor portion of the laminated substrate 1 functions as a decoupling capacitor for the lower integrated circuit 202. In the area surrounded by dotted line C, the capacitor portion of the laminated substrate 1 functions as a decoupling capacitor for the upper integrated circuit 202. Although not shown in Fig. 17, by further providing the laminated substrate through electrode 2, a power supply Vdd is supplied to the upper and lower integrated circuits 202, as shown in the area surrounded by dotted line D in Fig. 18.

[0150] (Variation 5) Fig. 19 is a cross-sectional view of an example in which the laminated substrate 1 functions as a decoupling capacitor for integrated circuits located above and below the laminated substrate 1. Fig. 20 is an equivalent circuit corresponding to the configuration in Fig. 19. In Fig. 19, each electrode is given a generic reference symbol, for example, front-side contact 50.

[0151] 19, in the area surrounded by dotted line A, the front side contact 50 and the back side contact 60 are electrically connected by the laminated substrate through electrode 2. In the area surrounded by dotted line B, the front side contact 50 is connected to the internal electrode layer 3, and the back side contact 60 is connected to the opposing internal electrode layer 4, forming a capacitance. Similarly, in the area surrounded by dotted line C, the front side contact 50 is connected to the internal electrode layer 3, and the back side contact 60 is connected to the opposing internal electrode layer 4, forming a capacitance.

[0152] As shown in Fig. 20, in the portion surrounded by dotted line A, the laminated substrate through electrode 2 grounds the upper integrated circuit 202 and the lower integrated circuit 202. In the portion surrounded by dotted line B, the capacitor portion of the laminated substrate 1 functions as a decoupling capacitor for the lower integrated circuit 202. In the portion surrounded by dotted line C, the capacitor portion of the laminated substrate 1 functions as a decoupling capacitor for the upper integrated circuit 202. Although not shown in Fig. 19, by further providing the laminated substrate through electrode 2, a power supply Vdd is supplied to the upper and lower integrated circuits 202, as shown in the portion surrounded by dotted line D in Fig. 20.

[0153] As described above, the laminated substrate 1 of this embodiment can be placed between the laminated integrated circuits 202 with a high degree of freedom simply by forming the insulating film 209 at a desired position.

[0154] The insulating film 209 is preferably formed by a film formation method such as a sputtering method, a baking method, or a CVD method, but is not limited to these.

[0155] A case where the insulating film 209 is formed by sputtering will be described. First, masking is performed on the portions where the insulating film 209 is not to be formed, such as the contacts to be connected by the solder bumps 205. After that, the insulating film 209 is formed on the front and back surfaces of the laminated substrate 1 by sputtering. As a result, the contacts not connected by the solder bumps 205 are covered with the insulating film 209.

[0156] A case where the insulating film 209 is formed by a baking method will be described. If necessary, masking is performed on portions where the insulating film 209 is not to be formed, such as contacts to be connected by solder bumps 205. Then, an insulating paste is printed by screen printing at desired portions on the front and back surfaces of the laminated substrate 1. Then, a baking process is performed to bake the insulating paste and form the insulating film 209. As a result, the contacts not connected by the solder bumps 205 are covered with the insulating film 209.

[0157] The case of forming the insulating film 209 by the CVD method will be described. First, masking is performed on the portions where the insulating film 209 is not to be formed, such as the contacts to be connected by the solder bumps 205. After that, the insulating film 209 is formed on the front and back surfaces of the laminated substrate 1 by the CVD method. As a result, the contacts not connected by the solder bumps 205 are covered with the insulating film 209.

[0158] The present invention is not limited to the configurations of the above-mentioned embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-mentioned embodiments. [Explanation of symbols]

[0159] 1. Laminated substrate 2. Multilayer substrate through-hole electrode 3 Internal electrode layer 4 Opposing internal electrode layer 5. Surface contact group 6 Back side contact group 7 Via connection 8 Dielectric Layer 10 Board body 10A Board body surface 10B Back side of the board 31 First internal electrode layer 32 Second internal electrode layer 41 First opposing internal electrode layer 42 Second opposing internal electrode layer 50 Surface contact 509 Front side center contact 51 First front surface contact group 510 Surface side peripheral contact group 511 First front surface side contact of the first front surface side contact group 52 Second surface side contact group 521 First surface side contact of the second surface side contact group 60 Back side contact 609 Back side center contact 61 First rear contact group 610 Back side peripheral contact group 611 First back surface contact of the first back surface contact group 62 Second rear contact group

Claims

1. A substrate body including a dielectric layer and a plurality of internal electrodes; a plurality of surface-side contact groups formed on the surface side of the substrate body, the surface-side contact groups including a surface-side central contact and a surface-side peripheral contact group including three or more surface-side peripheral contacts arranged to surround the surface-side central contact; a back surface side contact group formed on the back surface side of the substrate body, the back surface side contact group including a back surface side central contact and a back surface side peripheral contact group including three or more back surface side peripheral contacts arranged to surround the back surface side central contact; Equipped with the plurality of front surface side contact groups include at least a first front surface side contact group and a second front surface side contact group, the rear surface side contact group includes a first rear surface side contact group formed at positions on the rear surface side corresponding to positions of the first front surface side contact group, a front surface side central contact of the first front surface side contact group and a rear surface side central contact of the first rear surface side contact group are electrically connected via a laminated substrate through electrode; the laminated substrate through-hole electrode is not connected to the plurality of internal electrodes, The plurality of internal electrodes include a first internal electrode layer and a first opposing internal electrode layer, a first surface-side peripheral contact of the first surface-side contact group is electrically connected to the first internal electrode layer disposed inside the substrate body; A laminated substrate, wherein a first surface side peripheral contact of the second surface side contact group is electrically connected to the first opposing internal electrode layer arranged opposite the first internal electrode layer across the dielectric layer.

2. The plurality of surface side contact groups further includes a third surface side contact group, The plurality of internal electrodes further includes a second internal electrode layer and a second opposing internal electrode layer, a second surface side peripheral contact of the first surface side contact group is electrically connected to the second internal electrode layer disposed inside the substrate body; 2. The laminated substrate of claim 1, wherein a first surface side peripheral contact of the third surface side contact group is electrically connected to the second opposing internal electrode layer arranged opposite the second internal electrode layer across the dielectric layer.

3. The plurality of surface side contact groups further includes a fourth surface side contact group, The plurality of internal electrodes further includes a third internal electrode layer and a third opposing internal electrode layer, a third surface-side peripheral contact of the first surface-side contact group is electrically connected to the third internal electrode layer disposed inside the substrate body; 3. The laminated substrate of claim 2, wherein a first surface side peripheral contact of the fourth surface side contact group is electrically connected to the third opposing internal electrode layer arranged opposite the third internal electrode layer across the dielectric layer.

4. The plurality of surface side contact groups further includes a fifth surface side contact group, the plurality of internal electrodes further includes a fourth internal electrode layer and a fourth opposing internal electrode layer, a fourth surface-side peripheral contact of the first surface-side contact group is electrically connected to the fourth internal electrode layer disposed inside the substrate body; The laminated substrate according to claim 3, wherein a first surface side peripheral contact of the fifth surface side contact group is electrically connected to the fourth opposing internal electrode layer arranged opposite the fourth internal electrode layer across the dielectric layer.

5. The plurality of surface side contact groups further includes a sixth surface side contact group, The plurality of internal electrodes further includes a fifth internal electrode layer and a fifth opposing internal electrode layer, a fifth peripheral contact of the first group of surface side contacts is electrically connected to the fifth internal electrode layer disposed inside the substrate body; 5. The laminated substrate of claim 4, wherein a first surface side peripheral contact of the sixth surface side contact group is electrically connected to the fifth opposing internal electrode layer arranged opposite the fifth internal electrode layer across the dielectric layer.

6. The plurality of surface side contact groups further includes a seventh surface side contact group, The plurality of internal electrodes further includes a sixth internal electrode layer and a sixth opposing internal electrode layer, a sixth peripheral contact of the first group of surface side contacts is electrically connected to the sixth internal electrode layer disposed inside the substrate body; The laminated substrate of claim 5, wherein a first surface side peripheral contact of the seventh surface side contact group is electrically connected to the sixth opposing internal electrode layer arranged opposite the sixth internal electrode layer across the dielectric layer.

7. The plurality of surface side contact groups further includes an eighth surface side contact group, the plurality of internal electrodes further includes a seventh internal electrode layer and a seventh opposing internal electrode layer, a seventh front surface side peripheral contact of the first front surface side contact group is electrically connected to the seventh internal electrode layer disposed inside the substrate body; The laminated substrate of claim 6, wherein a first surface side peripheral contact of the eighth surface side contact group is electrically connected to the seventh opposing internal electrode layer arranged opposite the seventh internal electrode layer across the dielectric layer.

8. The plurality of front-side contact groups further includes a ninth front-side contact group, The plurality of internal electrodes further includes an eighth internal electrode layer and an eighth opposing internal electrode layer, an eighth front surface side peripheral contact of the first front surface side contact group is electrically connected to the eighth internal electrode layer disposed inside the substrate body; The laminated substrate of claim 7, wherein a first surface side peripheral contact of the ninth surface side contact group is electrically connected to the eighth opposing internal electrode layer arranged opposite the eighth internal electrode layer across the dielectric layer.

9. A laminated substrate described in any one of claims 1 to 8, wherein each of the plurality of surface side peripheral contact groups is composed of eight surface side peripheral contacts.

10. A laminated substrate as described in Claim 9, wherein each of the multiple surface side peripheral contact groups is arranged at equal angular intervals with respect to the surface side central contact.

11. A laminated substrate according to any one of claims 1 to 10, wherein the distance between adjacent surface side contacts among the multiple surface side contacts constituting one of the surface side contact groups is smaller than the distance between adjacent surface side contact groups.

12. The back surface side contact group further includes a second back surface side contact group, At least one rear side peripheral contact of the first rear side contact group is electrically connected to at least one internal electrode layer disposed inside the substrate body; A laminated substrate as described in any one of claims 1 to 11, wherein at least one of the rear surface side peripheral contacts of the second rear surface side contact group is electrically connected to at least one opposing internal electrode layer arranged opposite the one internal electrode layer across the dielectric layer.

13. The back surface side contact group further includes a second back surface side contact group, At least one of the first surface-side peripheral contacts is electrically connected to at least one internal electrode layer disposed inside the substrate body; A laminated substrate as described in any one of claims 1 to 12, wherein at least one of the rear surface side peripheral contacts of the second rear surface side contact group is electrically connected to at least one opposing internal electrode layer arranged opposite the one internal electrode layer across the dielectric layer.

14. A laminated substrate described in any one of claims 1 to 13, wherein at least one surface side contact in the first surface side contact group and at least one back side contact in the first back side contact group are conductive through a via connection portion.

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