Ratiometric Multi-Sensing Converter

Abstract

To provide an apparatus and method for capacitance-to-digital code conversion.SOLUTION: An apparatus comprises a bridge circuit 120 and a modulator front-end circuit 130. The bridge circuit 120 includes a first terminal to be coupled to a reference cell 115 and a second terminal to be coupled to a sensor cell 105. The modulator front-end circuit 130 includes a comparator 142 coupled to the bridge circuit 120, a first modulation capacitor 141.1 coupled to a first input side of the comparator 142, and a second modulation capacitor 141.2 coupled to a second input side of the comparator 142. The modulator front-end circuit 130 provides a digital bit stream. A duty cycle of the digital bit stream represents a ratio between a capacitance of the sensor cell 105 and a reference capacitance of the reference cell 115.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Related Applications This patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 072,329, filed August 31, 2020, which is incorporated by reference in its entirety.

[0002] Technical Field The present disclosure relates generally to sensing systems, and more particularly to capacitive sensing systems configurable to measure capacitance or convert capacitance into a digital value representative of the capacitance. [Background technology]

[0003] A capacitive sensing system can sense electrical signals generated on an electrode that reflect a change in capacitance. Such a change in capacitance can indicate a touch event (i.e., the proximity of an object to a particular electrode). Capacitive sensing elements can be used to replace mechanical buttons, knobs, and other similar mechanical user interface controls. By using capacitive sensing elements, complicated mechanical switches and buttons can be eliminated and reliable operation can be provided under harsh conditions. In addition, capacitive sensing elements are widely used in modern consumer applications to provide new user interface options in existing products. Capacitive sensing elements can range from a single button to many arranged in the form of a capacitive sensing array relative to the touch sensing surface.

[0004] An array of capacitive sensing elements operates by measuring the capacitance of the capacitive sensing elements and determining a delta (change) in capacitance that indicates the contact or presence of a conductive object. When a conductive object (e.g., a finger, hand, or other object) contacts or is in close proximity to a capacitive sensing element, the capacitance changes and the conductive object is detected. The change in capacitance of the capacitive contact sensing elements can be measured by an electrical circuit that converts the measured capacitance of the capacitive sensing elements into a digital value.

[0005] There are two typical types of capacitance: 1) mutual capacitance, where a capacitive sensing circuit is coupled to two electrodes in a drive / receive configuration to measure the capacitance between these electrodes, and 2) self-capacitance, where a capacitive sensing circuit is coupled to one electrode of a capacitor. In self-capacitance, the second electrode is tied to a direct current (DC) voltage level or the second electrode is parasitically coupled to ground. Touch panels have distributed loads of both types (1) and (2) capacitance, and some touch solutions sense the two capacitances, either uniquely or in a hybrid fashion with various sensing modes. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 illustrates a capacitance-to-digital converter (CDC) configured for ratiometric self-capacitance-to-code conversion, according to an embodiment. [Diagram 2] FIG. 2 illustrates voltage waveforms at various nodes of the CDC of FIG. 1, according to an embodiment. [Figure 3A] FIG. 1 illustrates a CDC configured for ratiometric self-capacitance-to-code conversion including a compensation branch, according to an embodiment. [Figure 3B] FIG. 1 illustrates a CDC configured for ratiometric self-capacitance-to-code conversion including a compensation branch according to another embodiment. [Figure 3C] FIG. 1 illustrates a CDC configured for ratiometric self-capacitance-to-code conversion including a compensation branch according to another embodiment. [Figure 3D] FIG. 13 illustrates a CDC configured for ratiometric self-capacitance-to-code conversion including a feedback switch for a reference cell according to another embodiment. [Figure 4] FIG. 3E illustrates voltage waveforms at various nodes of the CDC of FIG. 3D, according to an embodiment. [Diagram 5] FIG. 1 illustrates a CDC configured for ratiometric self-capacitance-to-code conversion with a mutual capacitance reference cell, according to an embodiment. [Figure 6] 6A-6D are diagrams showing effective representations of the CDC of FIG. 5 in the first, second, third and fourth phases, respectively, according to an embodiment, and FIGS. 6E-6H are diagrams showing effective representations of the CDC of FIG. 1 in the first, second, third and fourth phases, respectively, according to an embodiment. [Figure 7] FIG. 2 illustrates a CDC with a single-ended analog front-end (AFE) configured for ratiometric self-capacitance-to-code conversion, according to an embodiment. [Figure 8] FIG. 8 illustrates voltage waveforms at various nodes of the CDC of FIG. 7, according to an embodiment. [Figure 9] FIG. 1 illustrates a CDC with an active shield driver, according to an embodiment. [Figure 10] FIG. 2 illustrates a CDC with a single-ended AFE configured for ratiometric self-capacitance-to-code conversion, according to an embodiment. [Figure 11A] FIG. 1 illustrates a CDC configured for ratiometric self-capacitance-to-code conversion with a compensation branch, according to an embodiment. [Figure 11B]FIG. 1 illustrates a CDC configured for ratiometric self-capacitance-to-code conversion with improved resolution, according to an embodiment. [Figure 12] FIG. 2 illustrates a CDC with a single-ended AFE configured for ratiometric mutual capacitance-to-code conversion, according to an embodiment. [Figure 13] FIG. 13 illustrates voltage waveforms at various nodes of the CDC of FIG. 12, according to an embodiment. [Figure 14] FIG. 2 illustrates a CDC with a single-ended AFE configured for ratiometric mutual capacitance-to-code conversion, according to an embodiment. [Figure 15] FIG. 2 illustrates a flow chart of one embodiment of a method for capacitance-to-digital code conversion, according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] The requirements for sensing devices demand robustness and high performance while being relatively inexpensive and consuming relatively little power. Sensing devices such as multi-sensing converters can include capacitive, inductive, resistive and voltage sensing devices and can convert sensing signals manifested as currents into digital codes. However, variations in power supply voltage, clock frequency, reference voltage and current digital-to-analog converters (IDACs) can cause problems for sensitive applications. For example, noise impacts from the above-listed sources can cause a reduction in signal-to-noise ratio (SNR) for sensitive and high-speed scanning applications. A low SNR can limit the performance of various applications.

[0008] Described herein are various embodiments of apparatus and methods for ratiometric capacitance-to-digital conversion. Ratiometric measurements relate to a ratio of known values ​​(e.g., a ratio of capacitance values) rather than to direct current (DC) voltage source values, etc. Ratiometric capacitance-to-digital conversion can eliminate the problems mentioned above and others. Ratiometric capacitance-to-digital conversion can be insensitive to variations in clock frequency, current sources, and supply and reference voltages, supporting capacitance, inductance, resistance, voltage, and current measurements. Aspects of the present disclosure provide a fast, simple, high-performance, and low-cost solution to capacitance-to-digital conversion. Aspects of the present disclosure may be implemented in various configurations, including a (pseudo) differential analog front-end (AFE) or a single-ended AFE.

[0009] A ratiometric capacitance-to-digital converter (CDC) can include a sensor cell having a sensor capacitance and a reference cell having a reference capacitance. The sensor cell can include a sensor electrode, and the reference cell can include a reference electrode. The sensor electrode and the reference electrode can be discharged in a specific phase to alternately charge and discharge a first modulation capacitor and a second modulation capacitor, thereby generating a bit stream with a duty cycle representing a ratio between the sensor capacitance and the reference capacitance to cancel common mode noise between the sensor cell and the reference cell.

[0010] FIG. 1 illustrates a capacitance-to-digital converter (CDC) 100 configured for ratiometric self-capacitance-to-code conversion, according to an embodiment. The CDC 100 may be a four-phase CDC and may include a bridge circuit 120 and a modulator front-end circuit 130. The CDC 100 further includes a sensor capacitor 112 (C s ) and a reference capacitor 122 (C ref ) and a reference cell 115 comprising:

[0011] The modulator front-end circuit 130 may be a differential analog front-end (AFE) and may include a comparator 142, a modulation capacitor 141.1, and a modulation capacitor 141.2. In one embodiment, the modulation capacitor 141.1 and the modulation capacitor 141.2 have the same capacitance. In another embodiment, the modulation capacitor 141.1 and the modulation capacitor 141.2 may have different capacitance values. The modulation capacitor may also be referred to as a summing capacitor. The modulator front-end circuit 130 may further include a voltage detector, an AND gate 148.2 and an AND gate 148.4, and a clock signal divider.

[0012] The modulation capacitor 141.1 may be coupled to a first input of the comparator 142, and the modulation capacitor 141.2 may be coupled to a second input of the comparator 142. The comparator 142 may be coupled to a bridge circuit 120. The bridge circuit 120 may have a first terminal coupled to the reference cell 115 and a second terminal coupled to the sensor cell 105. The bridge circuit 120 may include switches that may be closed to couple the sensor cell 105 and / or the reference cell 115 to the modulator front-end circuit 130 when the corresponding phase is enabled. The signals for switching between the phases (Ph0, Ph1, Ph2, and Ph3) may be based on the sensor clock frequency F s The clock may be clocked by

[0013] The modulator front-end circuit 130 may include or be coupled to a digitization circuit, thereby providing a digital bit stream (e.g., one or more digital values) to the processing unit 160. The digital bit stream is a digital representation of the sensor capacitance C of the sensor cell 105. s , which may represent the reference capacitance C of the reference cell 115. ref The duty cycle of the digital bit stream can be as low as the sensor capacitance C s and the reference capacitance C of the reference cell 115 refmay represent a ratio to. In particular, the duty cycle may be obtained by [Number] and here 0 < DC < 1. Equation 1 is satisfied in the case of where 0 < DC < 1. Equation 1 is satisfied when [Number] .

[0014] The modulator front-end circuit 130 may include a sequencer 146 that generates various phases (e.g., Ph0, Ph1, Ph2, Ph3), and these phases may be sequenced through a frequency of F (also referred to as the sensor excitation frequency), thereby generating a bit stream that may include a low value (0) and a high value (1). The phases shown may correspond to labeled switches. In particular, for a CDC configured for ratiometric self-capacitance - code conversion, such as CDC100, the duty cycle of the bit stream may represent the ratio between the sensor capacitance C of the sensor cell 105 s and the reference capacitance C of the reference cell 115 s and the reference capacitance C of the reference cell 115 ref . These phases are designed such that the modulation capacitors 141.1 and 141.2 can be alternately charged and discharged by the sensor cell and the reference cell, respectively. The reference capacitance of the reference cell 115 may be set by one capacitor or may be a variable capacitance. This may use, for example, a capacitance digital - analog converter (DAC).

[0015] In the first phase Ph0, the supply voltage VDDA may be applied to the sensor electrode of the sensor cell 105 to charge the sensor electrode to the supply voltage level VDDA, and the supply voltage VDDA may be applied to the reference electrode of the reference cell 115 to charge the sensor electrode to the supply voltage level VDDA.

[0016] In the second phase Ph1, the sensor electrode of the sensor cell 105 may be coupled to the modulation capacitor 141.1 to charge the modulation capacitor 141.1. In the case where the bit stream is low (0), the output of the first AND gate generating the second feedback phase Ph1_fb is low and therefore the reference cell is not coupled to the bridge circuit 120. In the case where the bit stream is high (1), the output of the first AND gate generating the second feedback phase Ph1_fb is high and the reference electrode of the reference cell 115 is coupled to the modulation capacitor 141.2 to charge the modulation capacitor 141.2.

[0017] In the third phase Ph2, the sensor electrode of the sensor cell 105 is disconnected from the modulation capacitor 141.1 and is coupled to ground potential to ground the sensor electrode, and the reference electrode of the reference cell 115 is disconnected from the modulation capacitor 141.2 and is coupled to ground potential to ground the reference electrode.

[0018] In the fourth phase Ph3, the sensor electrode of the sensor cell 105 may be coupled to the modulation capacitor 141.2 to discharge the modulation capacitor 141.2. In the case where the bit stream is low (0), the output of the second AND gate generating the fourth feedback phase Ph3_fb is low, and therefore the reference cell is not coupled to the bridge circuit 120. In the case where the bit stream is high (1), the output of the second AND gate generating the fourth feedback phase Ph3_fb is high, and the reference electrode of the reference cell 115 is coupled to the modulation capacitor 141.1 to discharge the modulation capacitor 141.1. In other words, in the second and fourth phases, the sensor cell 105 and the reference cell 115 alternate between charging and discharging different capacitors (the modulation capacitors 141.1 and 141.2).

[0019] At any given time, the first input of the comparator 142 has a voltage Vm1, and the second input of the comparator 142 has a voltage Vm2, which varies with time. When the second feedback phase Ph1_fb and the fourth feedback phase Ph3_fb are enabled (e.g., when the bitstream is high), the difference ΔV between Vm2 and Vm1 (ΔV=Vm2-Vm1) is calculated as C ref C s , the feedback phases Ph1_fb and Ph3_fb may be disabled when the reference cell 115 is switched out (in other words, isolated from the bridge circuit 120), since the difference ΔV changes polarity. This can be seen as two processes occurring in parallel. The first process reduces the capacitance C s This allows the charging of the modulation capacitor 141.1 and the discharging of the modulation capacitor 141.2 uninterrupted during the conversion time. ref This allows the charging of the modulation capacitor 141.2 and the discharging of the modulation capacitor 141.1. If the difference ΔV between Vm2 and Vm1 is positive, then C ref C s If the common-mode voltage is greater than 1 V, the process is interrupted. Therefore, a precise common-mode DC voltage is not required. s During a clock cycle, ΔV can be half the current voltage VDDA due to the synchronous switching process. The first phase Ph0 and the third phase Ph2 are designed to excite the sensor cell 105 and the reference cell 115.

[0020] In other embodiments, these processes may be reversed. In such a case, a first process of switching the sensor cell 105 allows the modulation capacitor 141.2 to be charged and the modulation capacitor 141.1 to be discharged, and a second process of switching the reference cell 115 allows the modulation capacitor 141.1 to be charged and the modulation capacitor 141.2 to be discharged. To account for this reversal, the output of the comparator 142 should be reversed.

[0021] It is worth noting that while CDC 100 is depicted as having four phases (Ph0, Ph1, Ph2, and Ph3) and two feedback phases (Ph1_fb and Ph3_fb), in other embodiments there may be a fewer or greater number of phases, and the number of feedback phases may be equal to or less than the number of phases. In some embodiments there may be more feedback phases than the number of phases, such as when some feedback phases require positive feedback from only one phase and other feedback phases require positive feedback from a combination of phases.

[0022] As shown in Figure 1, the CDC100 operates at a sensor excitation frequency F s is the clock frequency F of the modulator front-end circuit 130. mod The CDC 100 may operate as a combination of a charge transfer circuit and a modulator front-end circuit. The modulator front-end circuit may be a differential sigma-delta modulator or other type of modulator. The CDC 100 and the method of converting capacitance to a digital value are completely independent of variations in voltage, current and time parameters.

[0023] FIG. 2 illustrates voltage variations at various nodes of the CDC 100 of FIG. 1 according to an embodiment. The sequencer 146 sequentially generates a first phase Ph0, a second phase Ph1, a third phase Ph2, and a fourth phase Ph3. The second feedback phase Ph1_fb and the fourth feedback phase Ph3_fb are enabled simultaneously with the second phase Ph1 and the fourth phase Ph3, respectively, but only when the bit stream is high (1). When the bit stream is low, the second feedback phase Ph1_fb and the fourth feedback phase Ph3_fb are not enabled even when the first phase Ph1 and the fourth phase Ph3 are enabled.

[0024] In Fig. 2, VCs represents the voltage of the sensor cell 105. During the first phase (Ph0 is high, and Ph1, Ph2 and Ph3 are low), the sensor cell 105 may be coupled to a supply voltage source, and the sensor electrode of the sensor cell 105 may be charged to the supply voltage VDDA. During the second phase (Ph1 is high, and Ph0, Ph2 and Ph3 are low), the sensor electrode may be coupled to the modulation capacitor 141.1 to charge the modulation capacitor 141.1, and thus the voltage at the sensor electrode is reduced. During the third phase (Ph2 is high, and Ph0, Ph1 and Ph3 are low), the sensor electrode may be coupled to ground potential to ground the sensor electrode, and thus the voltage at the sensor electrode is reduced to ground potential. During the fourth phase (Ph3 is high and Ph0, Ph1 and Ph2 are low), the sensor electrode may be coupled to the modulation capacitor 141.2 to discharge the modulation capacitor 141.2 (which may have been charged by the reference electrode of the reference cell 115 during the second phase when the bit stream is high), thus increasing the voltage at the sensor electrode.

[0025] The described method of CDC conversion may be independent of the variations in voltage, current and chronological (time) parameters. As revealed by Equation 1, the output duty cycle of the bit stream is only related to the relationship between the sensor capacitance and the reference capacitance.

[0026] It should be noted that a CDC, such as the CDC 100, may include more than one sensor cell with a sensor capacitance. Each sensor cell may be used as a sensor. Multiple sensor cells may be combined or coupled and used simultaneously. The number of charge transfer cycles may define the resolution of the CDC. Digital time may be used to calculate the number of charge transfer cycles, and the measurement process may be terminated when the required number of charge transfer cycles is reached. Thus, the CDC output result is not related to the clock frequency (Fclk), but rather to the number of clock cycles (N res ) This allows the CDC to use different types of sequencers with a fixed number of clock cycles, including spread spectrum clock sequencers, random clock sequencers, pseudorandom clock sequencers, fixed frequency clock sequencers, etc. The raw count of the digital bit stream for a CDC with a first order decimator is

number

[0027] Figures 3A-3D show various CDC configurations that include a compensation circuit. Figures 3A-3C include a compensation branch, which improves the resolution of the capacitance-to-digital conversion by removing parasitic capacitance from the conversion. Figure 3D improves the resolution by including an additional feedback phase.

[0028] 3A illustrates a CDC 300a configured for ratiometric self-capacitance-to-code conversion including a compensation branch 340a, according to an embodiment. As indicated by similar reference numbers, the CDC 300a is the same as or similar to the CDC 100 of FIG. 1, except that the CDC 300a includes a compensation branch 340a. The CDC 300a may be a four-phase CDC with a four-phase compensation branch 340a. The compensation branch 340a may include a compensation cell 325a having a compensation capacitance that is a self-capacitance. The compensation capacitance is a capacitor C comp 322, which may be a variable capacitance (e.g., as provided by a capacitor stack) or an intrinsic capacitance. In some embodiments, the compensation cell 325a may include at least a portion of a bridge circuit 320a. The bridge circuit 320a may be similar to the bridge circuit 120 of FIG. 1, except that a portion of the bridge circuit 320a may be part of the compensation branch 340a. The bridge circuit 320a may include a third terminal that couples to the compensation cell 325a (in addition to a first terminal that couples to the sensor cell 105 and a second terminal that couples to the reference cell 115). A portion of the bridge circuit 320a may or may not be coupled to the modulator front-end circuit 130 by a switch 350a, which is operated in synchronization with the phases (Ph0, Ph1, Ph2, and Ph3) generated by the sequencer 146. In other words, the compensation branch 340a may be a four-phase controlled compensation branch, which means that the compensation branch 340a may have different operation in each of the four phases (Ph0, Ph1, Ph2 and Ph3) generated by the sequencer 146.

[0029] In addition to the phase operation described with reference to FIG. 1, in a first phase (Ph0), a supply voltage VDDA may be applied to the compensation electrode of compensation cell 325a to charge compensation capacitor 322. In a second phase (Ph1), the compensation electrode may be coupled to modulation capacitor 141.2 to charge modulation capacitor 141.2. In a third phase (Ph2), the compensation electrode may be coupled to ground potential to ground the compensation electrode. In a fourth phase (Ph3), the compensation electrode may be coupled to modulation capacitor 141.1 to discharge modulation capacitor 141.1.

[0030] The inclusion of a compensation branch, such as compensation branch 340a, can affect the duty cycle of the bit stream to increase the CDC resolution. For example, the duty cycle may be related to the compensation capacitance in addition to the sensor capacitance and the reference capacitance. As described above (in the case without a compensation branch), the duty cycle may be determined by the ratio of the sensor capacitance to the reference capacitance. When the compensation branch 340a is included, this ratio may be based on the reference capacitance, the sensor capacitance, and the compensation capacitance. In particular, for CDC 300a, the duty cycle is:

number

[0031] 3B illustrates a CDC 300b configured for ratiometric self-capacitance-to-code conversion including a compensation branch 340b according to another embodiment. As indicated by similar reference numbers, the CDC 300b is the same as or similar to the CDC 100 of FIG. 1, except that the CDC 300b includes a compensation branch 340b. The CDC 300b may be a four-phase CDC with a two-phase compensation branch 340b. The compensation branch 340b includes a compensation capacitor (C comp ) 332. Compensation capacitor 332 may be a variable capacitor or a fixed capacitor. Compensation branch 340b may be a two-phase controlled compensation branch, meaning that in a first compensation branch phase (e.g., Ph0 and / or Ph1), compensation branch 340b may have a particular operation and in a second compensation branch phase (e.g., Ph2 and / or Ph3), compensation branch 340b may have another operation.

[0032] 1, except that a portion of bridge circuit 320b may be part of compensation branch 340b. Bridge circuit 320b may include a third terminal that couples to compensation capacitor 332. Compensation capacitor 332 may or may not be coupled to modulator front-end circuit 130 by a switch, which is operated in synchronization with the phases (Ph0, Ph1, Ph2, and Ph3) generated by sequencer 146.

[0033] In addition to the phase operation described with reference to Fig. 1, in the first phase (Ph0) and in the second phase (Ph1), a first compensation electrode of the compensation capacitor 332 may be coupled to ground potential. In particular, in the first phase, a second compensation electrode of the compensation capacitor 332 may be coupled to the supply voltage and to the sensor electrode of the sensor cell 105, so that the sensor electrode may be supplied with a voltage lower than the supply voltage level VDDA. In particular, in the second phase, a second electrode of the compensation capacitor 332 may be coupled to the modulation capacitor 141.1 as well as to the sensor electrode of the sensor cell 105.

[0034] In the third phase (Ph2) and the fourth phase (Ph3), the first compensation electrode of the compensation capacitor 332 may be coupled to the supply voltage. In particular, in the third phase, the second compensation electrode of the compensation capacitor 332 may be coupled to ground potential and to the sensor electrode of the sensor cell 105, so that the sensor electrode is not fully discharged to ground potential. In particular, in the fourth phase, the second compensation electrode of the compensation capacitor 332 may be coupled to the sensor electrode and to the modulation capacitor 141.2, so that the modulation capacitor 141.2 may be partially discharged to both the sensor electrode and the second compensation electrode.

[0035] Similar to the added compensation branch 340a of FIG. 3A, the added compensation branch 340b may increase the CDC resolution by affecting the duty cycle of the bit stream. For example, the duty cycle may be related to the compensation capacitance in addition to the sensor capacitance and the reference capacitance. As mentioned above (in the case without the compensation branch), the duty cycle may be determined by the ratio of the sensor capacitance to the reference capacitance. When the compensation branch 340a is included, this ratio may be based on the reference capacitance, the sensor capacitance, and the compensation capacitance. In particular, for CDC 300b, the duty cycle is:

number

[0036] 3C illustrates a CDC 300c configured for a ratiometric self-capacitance-code including a compensation branch 340c according to another embodiment. As indicated by similar reference numbers, the CDC 300c is the same as or similar to the CDC 100 of FIG. 1, except that the CDC 300c includes a compensation branch 340c. The CDC 300c may be a four-phase CDC with two phases of compensation branches 340c. The compensation branch 340c includes a compensation capacitor (C comp ) 342. The compensation branch 342 may be a variable or fixed capacitor. The compensation branch 340c may be a two-phase controlled compensation branch, meaning that in a first compensation branch phase (e.g., Ph0 and / or Ph1), the compensation branch 340c may have a particular operation and in a second compensation branch phase (e.g., Ph2 and / or Ph3), the compensation branch 340c may have another operation.

[0037] 1, except that a portion of bridge circuit 320c may be part of compensation branch 340c. Bridge circuit 320c may include a third terminal that couples to compensation capacitor 342. Compensation capacitor 342 may or may not be coupled to modulator front-end circuit 130 by a switch, which is operated in synchronization with the phases (Ph0, Ph1, Ph2, and Ph3) generated by sequencer 146.

[0038] The compensation cell 342 may be coupled to the reference cell 115 during a particular phase, which may relate to the output bitstream being high (1) or low (0).

[0039] If the output bit stream is low, the second feedback phase (Ph1_fb) and the fourth feedback phase (Ph3_fb) may remain low (not enabled) even if the second phase and / or the third phase are enabled. Thus, in addition to the phase operations described with reference to FIG. 1, in the first phase (Ph0) and the second phase (Ph1), a supply voltage may be applied to the first compensation electrode of the compensation cell 342. Furthermore, in the first phase and the second phase, the second compensation electrode of the compensation cell 342 may be coupled to the modulation capacitor 141.2 and may charge the modulation capacitor 141.2. In the third phase (Ph2) and the fourth phase (Ph3), the first compensation electrode may be coupled to ground potential and the second compensation electrode may be coupled to the modulation capacitor 141.1 to partially discharge the modulation capacitor 141.1.

[0040] When the output bitstream is high, during the second phase, the second compensation electrode may further be coupled to the reference cell 115, and both the reference electrode and the second compensation electrode may be coupled to the modulation capacitor 141.2 to charge the modulation capacitor 141.2. During the fourth phase, the second compensation electrode may be coupled to the reference cell 115, and both the reference electrode and the second compensation electrode may be coupled to the modulation capacitor 141.1 to discharge the modulation capacitor 141.1. Further, similar to the CDC 300b of FIG. 3B, the duty cycle of the output bitstream may be given by Equation 4:

[0041] As in the case of Figures 3A-3B, the addition of a compensation branch can increase the CDC resolution. ref is the reference compensation value C ref_compTherefore, the new C ref The value is C in Eq. ref value, but the sensitivity of the sensor remains the same. This is due to the relationship ΔC s / C ref This means that the converter resolution increases as the s_comp When is the mutual capacitance of the sensor, the converter mode becomes hybrid, and the conversion result reflects the changes in self-capacitance and mutual capacitance at the same time. In other words, there may be a kind of two-electrode sensor, which has both self-capacitance property and mutual capacitance property, and the variation of mutual capacitance may affect the sensing result.

[0042] The second way to increase the resolution is to increase the sensor clock frequency F s Higher modulation frequency F mod FIG. 3D shows the F mod F s 4 shows the schematic diagrams of the converter for the case where K is higher by a factor of 2, 3, 4, etc. Figure 4 shows the voltage waveforms at the key nodes for K=4.

[0043] FIG. 3D illustrates a CDC 300d configured for ratiometric self-capacitance-code including a feedback switch for a reference cell according to another embodiment. As indicated by similar reference numbers, the CDC 300d is the same as or similar to the CDC 100 of FIG. 1, except that it has a modified bridge circuit 320d and a modified modulator front-end circuit 330d. The CDC 300d may be a four-phase CDC. In the illustrated embodiment, the reference cell 115 may be coupled to the modulator front-end circuit 330d only if the bitstream is high when the corresponding feedback phase (Ph0_fb, Ph1_fb, Ph2_fb, and Ph3_fb) is enabled by one or more feedback signals. A divider 347.2 receives a clock signal and divides the frequency of the signal by half, and a second divider 347.1 receives the divided frequency from divider 347.2 and further divides this signal by four and switches between phases Ph0, Ph1, Ph2 and Ph3.

[0044] These phases are designed so that each modulation capacitor 141.1 and 141.2 can be charged and discharged alternately by the sensor cell and the reference cell. The reference capacitance of the reference cell 115 can be set by a single capacitor or by a variable capacitance, for example using a capacitance digital-to-analog converter (DAC). These phases can be generated by the sequencer 346 and the feedback phases can be generated by the sequencer 345. The feedback phases can relate to a bit stream being high and the corresponding phase being enabled via the AND gates 348.1-348.4.

[0045] In the first phase Ph0, a supply voltage VDDA may be applied to the sensor electrode of the sensor cell 105 to charge the sensor electrode to the supply voltage level VDDA, and a supply voltage VDDA may be applied to the reference electrode of the reference cell 115 to charge the sensor electrode to the supply voltage level VDDA. In the case where the bit stream is high (1), the output of the AND gate 348.1 generating the first feedback phase Ph0_fb is high and the reference cell may be coupled to the supply voltage and charged to the supply voltage level. In the case where the bit stream is low (0), the output of the AND gate 348.1 generating the first feedback phase Ph0_fb is low and therefore the reference cell is not coupled to the supply voltage and is not charged to the supply voltage level.

[0046] In the second phase Ph1, the sensor electrode of the sensor cell 105 may be coupled to the modulation capacitor 141.1 to charge the modulation capacitor 141.1. In the case where the bit stream is high (1), the output of the AND gate 348.2 generating the second feedback phase Ph1_fb is high, and the reference electrode of the reference cell 115 may be coupled to the modulation capacitor 141.2 to charge the modulation capacitor 141.2. In the case where the bit stream is low (0), the output of the AND gate 348.2 generating the second feedback phase Ph1_fb is low, and therefore the reference cell may not be coupled to the bridge circuit 320d.

[0047] In the third phase Ph2, the sensor electrode of the sensor cell 105 may be decoupled from the modulation capacitor 141.1 and may be coupled to ground potential to ground the sensor electrode. In the case where the bit stream is high, the output of the AND gate 348.3 generating the third feedback phase Ph2_fb may be high and the reference electrode of the reference cell 115 may be decoupled from the modulation capacitor 141.2 and may be coupled to ground potential to ground the reference electrode. In the case where the bit stream is low, the output of the AND gate 348.3 may be low and the reference electrode of the reference cell may be decoupled from the modulation capacitor 141.2 but may not be coupled to ground potential.

[0048] In the fourth phase Ph3, the sensor electrode of the sensor cell 105 may be coupled to the modulation capacitor 141.2 to discharge the modulation capacitor 141.2. In the case where the bit stream is high (1), the output of the AND gate 348.4 generating the fourth feedback phase Ph3_fb is high, and the reference electrode of the reference cell 115 may be coupled to the modulation capacitor 141.1 to discharge the modulation capacitor 141.1. In the case where the bit stream is low (0), the output of the AND gate 348.4 generating the fourth feedback phase Ph3_fb is low, and therefore the reference cell may not be coupled to the bridge circuit 320d.

[0049] FIG. 4 illustrates voltage waveforms at various nodes of the CDC 300d of FIG. 3D, according to an embodiment. ref / C s =3 / 2), and the ratio between the modulation frequency (e.g., the modulator front-end circuit clock frequency) and the sensor excitation frequency is 4 (F mod / F s The case where F = 4 is shown. mod / F s Note that is also denoted here as K.

[0050] The duty cycle of the output bit stream is

number

[0051] Equation 6 is a reference capacitance C lowered by a factor K. ref This indicates that a value is available, which can be useful for a reference capacitor (or reference cell) integrated on the chip.

[0052] Returning to Equation 3, the measurement time T mea While maintaining the factor K, F mod By increasing , the resolution can be increased.

[0053] The two described methods for increasing the resolution can be combined. comp FIG. 1 shows a CDC 300a-300c including compensation branches that can be controlled by four phases or two phases that can be sequenced by a digital sequencer having a comp is the sensor clock frequency F s The relationship between them is the factor K comp (This may also be called the compensation factor) (e.g. F comp =K comp F s In some embodiments, F comp is the sensor clock frequency F s In this case, K comp = 1. In such a case, the modulation frequency F mod , the sensor clock frequency F s and the compensation frequency F comp In another embodiment, F comp is the sensor clock frequency F s It can be higher or lower. In this general case the transfer function is

number

[0054] On the other hand, FIG. 3D shows a CDC 300d, which has a sensor capacitance C s and a reference capacitance C ref , and a configuration that uses different clock frequencies to sequence the reference cells 115 having F mod ≧F s The CDC 300d may additionally include any of the compensation branches 340a, 340b, and / or 340c. When the CDC 300d includes any of the compensation branches 340a-340c, the transfer function is

number

[0055] Each of the CDCs 100 and 300a to 300d uses a grounded reference cell (e.g., a reference capacitance C ref is the self-capacitance). In other embodiments, the reference cell can be configured to operate with mutual reference capacitance, as described with reference to FIG.

[0056] FIG. 5 illustrates a CDC 500 configured for ratiometric self-capacitance-to-code conversion with a mutual capacitance reference cell 515, according to an embodiment. The CDC 500 may be a four-phase CDC and may include a bridge circuit 520 and a modulator front-end circuit (not explicitly shown in FIG. 5). The modulator front-end circuit may be the same as or similar to the modulator front-end circuit of FIG. 1 and FIG. 3A-3D. The modulation circuit may include a four-phase sequencer and two or more feedback loops. The four-phase sequencer may generate a first phase, a second phase, a third phase, and a fourth phase and a first modulated phase (Ph0_mod) and a third modulated phase (Ph2_mod) for coupling the sensor cell 505 and / or the reference cell 515 to one of the bridge circuit 520, a supply voltage VDDA, or a ground potential.

[0057] The sensor cell 505 may include a sensor electrode and may have a self-capacitance, the sensor capacitance C s 512. The reference cell 515 may include a reference capacitor 522 having a first reference electrode and a second reference electrode. ref may have a first reference electrode and a second reference electrode and a mutual capacitance, a reference capacitance 522. The first reference electrode may be coupled to the bridge circuit 520 by switches, which are enabled by the second feedback phase (Ph1_fb) or the fourth feedback phase (Ph3_fb).

[0058] These phases are designed such that each modulation capacitor 141.1 and 141.2 can be alternately charged and discharged by the sensor cell and the reference cell. In the first phase Ph0, the sensor electrode of the sensor cell 505 may be coupled to the supply voltage VDDA. In other words, the supply voltage may be applied to charge the sensor electrode. During the first phase, the second reference electrode may be coupled to and decoupled from the supply voltage (by the Ph0_mod switch) at a modulated frequency. For example, the phases (Ph0, Ph1, Ph2 and Ph3) are F s During the first phase Ph0, the first modulated phase Ph0_mod is modulated at a frequency of F by a factor of K. s The modulation may be at a higher modulation frequency than

[0059] In the second phase Ph1, the sensor electrode of the sensor cell 505 may be coupled to the modulation capacitor 141.1 to charge the modulation capacitor 141.1. In the case where the bit stream is low (0), the reference cell 515 is not coupled to the bridge circuit 520, but in the case where the bit stream is high (1), the second electrode of the reference cell 515 may be coupled (by the Ph1_fb switch) to the modulation capacitor 141.2 to charge the modulation capacitor 141.2.

[0060] In the third phase Ph2, the sensor electrode of the sensor cell 505 may be coupled to ground potential to ground the sensor electrode. The second reference electrode of the reference cell 515 may be isolated from the modulation capacitor 141.2. During the third phase, the first electrode of the reference cell 515 may be coupled to and separated from the ground potential (by the Ph2_mod switch) at the modulated frequency.

[0061] In the fourth phase Ph3, the sensor electrode of the sensor cell 505 may be coupled to the modulation capacitor 141.2 to discharge the modulation capacitor 141.2. In the case where the bit stream is low, the reference cell 515 is not coupled to the bridge circuit 520, but in the case where the bit stream is high (1), the second electrode of the reference cell 515 may be coupled (by the Ph3_fb switch) to the modulation capacitor 141.1 to discharge the modulation capacitor 141.1.

[0062] The duty cycle of the bit stream output by the modulator front-end circuit is

number

[0063] Implementing a mutual reference capacitance relative to the reference capacitance may provide the advantage of reducing the parasitic capacitance associated with the reference cell. Such parasitic capacitance may affect sensing. High sensitivity applications of capacitive sensing may benefit from a relatively low mutual reference capacitance value. A relatively low mutual reference capacitance value may be achieved by replacing the reference capacitor by a capacitive T-bridge. For example, C ref may be replaced by a capacitive T-bridge, which may include a first capacitor, a second capacitor, and a third capacitor (C1, C2, and C3, respectively). The equivalent capacitance of the capacitive T-bridge (representing the mutual reference capacitance) is:

number

[0064] 6A-6D are effective representations of a CDC 500 in a first phase, a second phase, a third phase, and a fourth phase, respectively, according to an embodiment. FIG. 6A-6D show modulation capacitors 141.1 and 141.2, capacitor C1 representing an effective sensor capacitor cell 505 with self-capacitance. s and a capacitor C, which represents an effective reference cell 515 having a mutual capacitance mref 1 shows. The first phase, the second phase, the third phase, and the fourth phase are generated (e.g., enabled) by a sequencer of the modulator front-end circuit. When a given phase is enabled, one or more switches corresponding to that phase may be closed, and when the phase changes (e.g., a different phase is enabled and the given phase is disabled), one or more switches may be opened and another set of one or more switches may be closed. (Capacitor C mref Whether a reference cell (represented by capacitor C) is coupled to the CDC 500 may depend on whether the bit stream is high (1) or low (0). s Whether a sensor cell (represented by ) is coupled to the CDC 500 or not does not matter whether the bit stream is high or low.

[0065] In the first phase Ph0, the CDC 500 may be configured to apply a supply voltage VDDA to the sensor electrodes of the sensor cells to charge them to a first voltage level. If the bitstream is high, the CDC 500 may be further configured to apply a supply voltage to a first reference electrode of the reference cell to charge it to the first voltage level.

[0066] In the second phase Ph1, the CDC500 switches the first modulation capacitor C mod1 To charge the first modulation capacitor C, the sensor electrode is connected to mod1When the bitstream is high, the CDC 500 may be further configured to couple to a second modulation capacitor C mod2 The second reference electrode is connected to the second modulation capacitor C mod2 The device may be configured to couple to the

[0067] In the third phase Ph2, the CDC 500 may be configured to couple the sensor electrode to a ground potential to ground the sensor electrode, and if the bit stream is high, the CDC 500 may be further configured to couple the first reference electrode to a ground potential to ground the first reference electrode.

[0068] In the fourth phase, Ph3, the CDC500 switches the second modulation capacitor C mod2 To discharge the mod2 When the bitstream is high, the CDC 500 may be further configured to couple to the first modulation capacitor C mod1 To discharge the first modulation capacitor C, the second reference electrode is connected mod1 The device may be configured to couple to the

[0069] When the bit stream is low, in the second and fourth phases, the sensor cell alternately switches the first modulation capacitor C mod1 Charging the second modulation capacitor C mod2 and discharging the second modulation capacitor C mod2 is charged), and the reference cell is not coupled to the bridge circuit, and therefore is not coupled to the first or second modulation capacitors. The reference cell may be coupled to the bridge circuit only when the bit stream is high. In particular, in the second and fourth phases, the reference cell alternately couples the second modulation capacitor C mod2 Charging the first modulation capacitor C mod1 and discharging the same.

[0070] CDC 500 may include compensation branches 340a, 340b and / or 340c, similar to that described above in connection with CDCs 300a-300d of Figures 3A-3D. In such a case, the transfer function is

number

[0071] 6E-6H are effective representations of the CDC 100 in a first phase, a second phase, a third phase, and a fourth phase, respectively, according to an embodiment. FIGs. 6E-6H show modulation capacitors 141.1 and 141.2, capacitor C1 representing an effective sensor capacitor cell 105 with self-capacitance. s and a capacitor C representing an effective reference cell 115 with self-capacitance. sref 1 shows. The first phase, the second phase, the third phase, and the fourth phase are generated (e.g., enabled) by a sequencer of the modulator front-end circuit. When a given phase is enabled, one or more switches corresponding to that phase may be closed, and when the phase changes (e.g., a different phase is enabled and the given phase is disabled), one or more switches may be opened and another set of one or more switches may be closed. (Capacitor C sref Whether a reference cell (represented by capacitor C) is coupled to the CDC 100 may depend on whether the bit stream is high (1) or low (0). s Whether a sensor cell (represented by ) is coupled to the CDC 100 or not does not matter whether the bit stream is high or low.

[0072] In the first phase Ph0, the CDC 100 may be configured to apply a supply voltage VDDA to the sensor electrodes of the sensor cells to charge them to a first voltage level, and if the bit stream is high, the CDC 100 may be further configured to apply a supply voltage to the reference electrodes of the reference cells to charge them to the first voltage level.

[0073] In the second phase Ph1, the CDC 100 switches the first modulation capacitor C mod1 To charge the first modulation capacitor C, the sensor electrode is connected to mod1 When the bitstream is high, the CDC 100 may be further configured to couple to a second modulation capacitor C mod2 The reference electrode is connected to the second modulation capacitor C mod2 The device may be configured to couple to the

[0074] In the third phase Ph2, the CDC 100 may be configured to couple the sensor electrode to a ground potential to ground the sensor electrode, and if the bit stream is high, the CDC 100 may be further configured to couple the reference electrode to a ground potential to ground the reference electrode.

[0075] In the fourth phase Ph3, the CDC100 switches the second modulation capacitor C mod2 To discharge the mod2 When the bit stream is high, the CDC 100 may be further configured to couple to the first modulation capacitor C mod1 To discharge the reference electrode, connect the reference electrode to the first modulation capacitor C mod1 The device may be configured to couple to the

[0076] When the bit stream is low, in the second and fourth phases, the sensor cell alternately switches the first modulation capacitor C mod1 Charging the second modulation capacitor C mod2and discharging the second modulation capacitor C mod2 is charged), and the reference cell is not coupled to the bridge circuit, and therefore is not coupled to the first or second modulation capacitors. The reference cell may be coupled to the bridge circuit only when the bit stream is high. In particular, in the second and fourth phases, the reference cell alternately couples the second modulation capacitor C mod2 Charging the first modulation capacitor C mod1 and discharging the same.

[0077] FIG. 7 illustrates a CDC 700 with a single-ended AFE configured for ratiometric self-capacitance-to-code conversion, according to an embodiment. In particular, FIG. 7 illustrates a ratiometric self-capacitance-to-code sigma-delta converter AFE. Capacitive sensing techniques can provide some applications that may be less demanding and can be implemented at a relatively low power consumption cost. In such cases, a single-ended architecture for the modulator front-end circuitry may be used. In general, the ratiometric CDCs described herein do not require specific hardware due to their ratiometric nature. This means that a differential ratiometric architecture may have all of the elements necessary to form a single-ended CDC such as CDC 700. In particular, a CDC such as CDC 700 may be implemented for ratiometric applications and does not require specific hardware. For example, a modulator front-end circuit with a single-ended architecture may be used.

[0078] Although the measurement method is ratiometric, the single-ended modulator front-end circuit may differ from differential modulator front-end circuits for conventional capacitive sensing architectures in that the single-ended modulator front-end circuit does not need to include a reference voltage source and in that the initialization method may not require an analog buffer.

[0079] The CDC 700 may include a modulator front-end circuit 730. The modulator front-end circuit 730 may include a modulation capacitor 741 (also referred to as a summing capacitor) coupled to a first input of a comparator 742. A second input of the comparator 742 may be coupled to a ground potential. The modulator front-end circuit 730 may include or be coupled to a digitization circuit to provide a digital bitstream (e.g., one or more digital values) to the processing unit 160.

[0080] A signal may be used to control the phase, sensor clock frequency, e.g. F s Each effective capacitor having a capacitance (e.g., the sensor capacitance 712 of the sensor cell 705, the reference capacitance 722 of the reference cell 715, the modulation capacitance 741, etc.) is clocked by a power supply current (herein referred to as I sen In one embodiment, a charge transfer circuit may be formed that can generate a charge transfer current (referred to as a charge transfer current).

[0081] The first and second phases (enabled by the Ph0 and Ph1 switches, respectively) are synchronized with the sensor clock frequency (F s ) may be enabled / disabled by a non-overlapping signal that may be clocked by the Ph0_mod switch and the Ph1_mod switch. Furthermore, the first and second modulating signals (enabled by the Ph0_mod and Ph1_mod switches, respectively) may be non-overlapping signals modulated by the bitstream. The modulating signals may be modulated by the bitstream signal. In other words, they may be alternately enabled and disabled only when the bitstream is high. The modulating signals have a modulation frequency F mod The modulation frequency may be higher than the sensor clock frequency. For example, the modulation frequency may be K ref It's okay if it's twice as expensive.

number

[0082] Reference capacitance C ref , modulation capacitance C mod , the modulation switches Ph0_mod and Ph1_mod sink current I bal Similarly, a charge transfer circuit may be formed to generate the sensor capacitance C s , modulation capacitance C mod And switches Ph0 and Ph1 are sensing current I sen The sink current and the sensing current may be respectively formed as

number

number

[0083] As a result of the sigma-delta modulation of the sigma-delta modulator, the sink current may be designed to be equal to the sensing current;

number

number

number

[0084] For the CDC700 configuration, the capacitance-to-code transfer function (i.e., duty cycle of the bitstream signal) is

number

[0085] In particular, equation (15) shows that the capacitance-to-code conversion (e.g., capacitance-to-digital code conversion (CDC)) is neither related to the supply voltage VDDA nor to the clock frequency. Thus, the conversion is ratiometric, and the reference source for the measurement is the reference capacitance C ref It should be noted that since there is no reference voltage (e.g., the reference voltage is zero), the CDC 700 can provide a simple initialization scheme, as well as simple waterproof capacitive scanning with active shielding. This is further described in relation to FIG.

[0086] FIG. 8 shows voltage waveforms at various nodes of the CDC 700 of FIG. 7, according to an embodiment. mod is shown at the top. As described in connection with FIG. 7, the first switch Ph0 and the second switch Ph1 may be controlled by a non-overlapping signal. The modulation switches Ph0_mod and Ph1_mod may be controlled by a non-overlapping signal that is modulated at the modulation frequency only when the bitstream signal is high. The sensing current may peak when the second switch Ph1 is enabled, while the sink current may peak when the second modulation switch Ph1_mod is enabled, which in the illustrated example occurs three times when the bitstream is high, so the sink current may peak three times. The sensing current and the sink current have opposite polarities, and the magnitude of each sink current peak may be one-third the magnitude of the sensing current, which leads to the vanishing of the average current. Thus, during the balancing process, V mod The variation of V can be kept to less than a few tens of millivolts, which means that the sensor excitation signal (e.g., V) has a rectangular waveform that varies between the supply voltage VDDA and ground potential.

[0087] 9 shows a CDC 900 with an active shield driver 902, according to an embodiment. The CDC 900 is similar to the CDC 900 in that the sensor cell 905 includes a mutual capacitance 912 and two parasitic capacitances C PS The CDC900 is the same as the CDC700, except that it is susceptible to the effects of . The CDC900 is a CDC capable of waterproof capacitive scanning with active shielding.

[0088] The current balancing mentioned above (e.g. I sen =I bal ) is a schematic diagram of a modulation voltage V varying around zero. mod As mentioned above, during the equilibration process, V mod The variation of V can be kept to less than a few tens of millivolts, which means that the sensor excitation signal (e.g., V) has a rectangular waveform that varies between the supply voltage VDDA and ground potential, as shown in FIG.

[0089] To create waterproofing for the CDC 900, the active shield driver 902 may generate an active shield signal having a shield waveform that repeats the sensor excitation signal. The active shield signal may be designed with pull-up and pull-down switches on a general-purpose input / output (GPIO) driver pin. In other words, the sensor cell 905 containing the sensor capacitance 912 may be coupled to the same supply voltage as in FIG. 7, but through the active shield driver 902.

[0090] FIG. 10 illustrates a CDC1000 with a single-ended AFE configured for ratiometric self-capacitance-to-code conversion according to an embodiment. The CDC1000 detects the sensing current I sen and the sink current I balis the same as the CDC700, except that the polarity of both is reversed by swapping the terminals to which the supply voltage and ground potential are coupled. The duty cycle of the CDC1000 is described by and given by equations (9)-(15).

[0091] Generally, the initialization circuit diagram has a buffered voltage source coupled to the modulation capacitor 1041 during the initialization period. The CDC 1000 does not require a buffered voltage source, and furthermore, the initialization scheme can be designed such that there is only one pull-down switch (S_init). This initialization of the CDC 1000 can reduce the overall power consumption of the CDC 1000. In particular, the current to charge the modulation capacitor 1041 is approximately zero, and no analog buffer is required.

[0092] The CDC1000 may include a voltage comparator 1042 to allow a minimum input voltage between 0V and 0.1V. Such a minimum input is a typical requirement for rail-to-rail input comparators, for example for which the common mode includes both the positive and negative supply voltages, as well as the mid-supply voltage. The CDC1000 may be used when the comparator supports only the VDDA rail voltage. In such a case, the Vmod balance voltage will vary around VDDA, rather than zero. The sensing capacitance switching will sink the current I sen , and the reference capacitance switching generates the source current. As described in connection with Figures 11A-11B, there can be two ways to increase the scanning resolution of the CDC 1000.

[0093] 11A shows a CDC 1100a configured for ratiometric self-capacitance-to-code conversion with a compensation branch 1132, according to an embodiment. The resolution of the CDC can be increased in various ways. First, the ratio of the modulator clock frequency to the sensor clock frequency may be increased, and at the same time, the reference capacitance C refIn such a case, the same architecture as the CDC 1000 can be used. Second, as described above, the compensation capacitance 1132 (C scomp ) can be added. Adding a compensation branch requires adding a switching capacitor as part of the compensation branch, as shown by CDC1100a. It is worth noting that the compensation branch shown by CDC1100a is a self-capacitance compensation branch.

[0094] Compensation switch Ph0 comp and Ph1 comp is the compensation branch clock frequency F comp In some embodiments, the switch Ph0 comp and Ph1 comp can be switched synchronously with Ph0 and Ph1. In the above embodiment, Ph0 comp and Ph1 comp switching is typically at the sensor clock frequency F s When the switching of Ph0 and Ph1 is synchronized with that of Ph0 and Ph1, which are switched by comp F s In another embodiment, Ph0 comp and Ph1 comp and are switched by separate clock signals, the compensation factor K comp may be defined, which characterizes the ratio of the compensation branch compensation frequency to the sensor clock frequency, and the capacitance-to-code transfer function (duty cycle) is

number

[0095] FIG. 11B illustrates a CDC 1100b configured for ratiometric self-capacitance-to-code conversion with increased resolution, according to an embodiment. The CDC 1100b includes a compensation branch that reduces the mutual capacitance 1120 (C comp11A, except that the CDC 1100a is a mutually compensating branch with a current I comp is Ph0 comp and Ph1 comp via switching to the compensation branch.

[0096] FIG. 12 illustrates a CDC 1200 with a single-ended AFE configured for ratiometric mutual capacitance-to-code conversion, according to an embodiment. The CDC 1200 uses mutual capacitance 1212 (C M 10. The mutual capacitance is the same as or similar to the CDC1000 of FIG. 10, except for the sensor cell which contains the parasitic capacitance C PS As in the case of the CDC1000, the switches Ph0, Ph1 and at least one feedback switch Ph 1_fb By switching between and, the sensing current I sen The sink current I that balances bal , causing a zero average current at the first input of the comparator 1242.

[0097] The CDC1200 architecture uses mutual capacitance measurements to sen Parasitic capacitance C to ps Eliminates the effect of C on the performance of the CDC1200 PS The effect of the voltage drop can be eliminated. Also, VCs is maintained around the extinction voltage level. The capacitance-code transfer function of the CDC1200 is as follows:

number

[0098] FIG. 13 shows voltage waveforms at various nodes of the CDC 1200 of FIG. 12, according to an embodiment. modis shown at the top. Similar to the CDC 700 in FIG. 7 and the corresponding waveforms shown in FIG. 8, the first switch Ph0 and the second switch Ph1 may be controlled by a non-overlapping signal. The modulation switches Ph0_mod and Ph1_mod may be controlled by a non-overlapping signal that is modulated at the modulation frequency only when the bitstream signal is high. The sensing current may peak when the second switch Ph1 is enabled, while the sink current may peak when the second modulation switch Ph1_mod is enabled, which in the illustrated example occurs three times when the bitstream is high, so the sink current may peak three times. The sensing current and the sink current have opposite polarities, and the magnitude of each sink current peak may be one-third of the magnitude of the sensing current, which leads to the vanishing of the average current. Thus, during the balancing process, V mod The variation of V can be kept to less than a few tens of millivolts, which means that the sensor excitation signal (e.g., V) has a rectangular waveform that varies between the supply voltage VDDA and ground potential.

[0099] FIG. 14 illustrates a CDC1400 with a single-ended AFE configured for ratiometric mutual capacitance-to-code conversion according to an embodiment. The CDC1400 detects the sensing current I sen and the sink current I bal is the same as the CDC1200, except that the polarity of both is reversed by swapping the terminals to which the supply voltage and ground potential are coupled.

[0100] To increase the resolution of the CDCs 1200 and 1400, a compensation branch, such as the compensation branch in FIG. 11A and FIG. 11B, may be added. Such a compensation branch may generate a DC current. The DC current may be calculated based on the sensing current I sen and can be controlled by switching one or more modulation switches, similar to Ph0_mod and Ph1_mod. In this case, the modulation balance voltage V modmay be approximately the supply voltage VDDA.

[0101] FIG. 15 is a flow chart of one embodiment of a method 1500 of capacitance-to-digital code conversion, according to an embodiment. In some embodiments, processing logic may be used to perform the method 1500. The processing logic may include hardware, software, or any combination thereof. In one embodiment, the processing device 160 of FIG. 1, 3, 5, 7, 9-12, or 14 may perform the method 1500. In another embodiment, the CDC of FIG. 1, 3, 5, 6, 9-12, or 14 may perform the method 1500. Alternatively, other components may be used to perform some or all of the operations of the method 1500.

[0102] In block 1502, the processing logic may apply a supply voltage to charge a sensor electrode of the sensor cell to a first voltage level in a first phase. In block 1504, the processing logic may couple the sensor electrode to a first modulation capacitor to charge the first modulation capacitor in a second phase. The first modulation capacitor may be coupled to a first input of the comparator. In block 1506, the processing logic may couple the sensor electrode to a ground potential to ground the sensor electrode in a third phase. In block 1508, the processing logic may couple the sensor electrode to a second modulation capacitor to discharge the second modulation capacitor in a fourth phase. The second modulation capacitor may be coupled to a second input of the comparator. The modulator front-end circuit includes a first modulation capacitor, a second modulation capacitor, and a comparator, and provides a digital bit stream. A duty cycle of the digital bit stream represents a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell. In some embodiments, the reference cell includes a reference electrode and the reference capacitance is a self-capacitance. In other embodiments, the reference cell includes a reference electrode and a second reference electrode and the reference capacitance is a mutual capacitance.

[0103] In a further embodiment, the processing logic may apply a supply voltage in a first phase to charge a reference electrode of the reference cell to a first voltage level. The processing logic may couple the reference electrode to a second modulation capacitor in a second phase to charge the second modulation capacitor. The processing logic may couple the reference electrode to a ground potential in a third phase to ground the reference electrode. The processing logic may couple the reference electrode to a first modulation capacitor in a fourth phase to discharge the first modulation capacitor.

[0104] In a further embodiment, the processing logic may apply a supply voltage to a compensation electrode of a compensation cell having a compensation capacitance in a first phase. The processing logic may couple the compensation electrode to a second modulation capacitor to charge the second modulation capacitor in a second phase. The processing logic may couple the compensation electrode to a ground potential to ground the compensation electrode in a third phase. The processing logic may couple the compensation electrode to a first modulation capacitor to discharge the first modulation capacitor in a fourth phase. The duty cycle of the digital bit stream is a ratio between the capacitance of the reference cell and the difference between the capacitance of the sensor cell and the capacitance of the compensation cell.

[0105] The embodiments described herein may be used in various designs of mutual capacitance sensing arrays or self-capacitance sensing arrays of capacitive sensing systems. In one embodiment, the capacitive sensing system can detect multiple sensing elements activated in the array and analyze the signal patterns on adjacent sensing elements to separate noise from the actual signal. The embodiments described herein are not tied to a particular capacitive sensing solution and may be used well with other sensing solutions, including optical sensing solutions, as would be understood by one of ordinary skill in the art having the benefit of this disclosure.

[0106] In the above description, numerous details have been set forth. However, it will be apparent to one skilled in the art having the benefit of this disclosure that embodiments of the invention may be practiced without these specific details. In some instances, well-known structures and devices have been shown in block diagram form, rather than in detail, in order to avoid obscuring the description.

[0107] Some portions of the detailed descriptions are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. These steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated. It is sometimes convenient, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0108] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. As is apparent from the above discussion, unless otherwise noted, throughout the description, discussions utilizing terms such as "applying," "coupling," "communicating," and the like will be understood to refer to the actions and processes of a computing system, or similar electronic computing device, which manipulates and transforms data represented as physical (e.g., electronic) quantities in the registers and memory of the computing system into other data similarly represented as physical quantities in the memory or registers of the computing system or other such information storage, transmission, or display devices.

[0109] The word "example" or "exemplary" is used herein to mean serving as an example, illustration, or illustration. Any aspect or design described herein as "example" or "exemplary" should not necessarily be construed as preferred or advantageous over other aspects or designs. Rather, use of the word "example" or "exemplary" is intended to present a concept in a concrete manner. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." That is, unless otherwise specified or clear from the context, "X contains A or B" is intended to mean any natural inclusive permutation. That is, "X contains A or B" is satisfied if X contains A, if X contains B, or if X contains both A and B, in any of the foregoing cases. Furthermore, the articles "a" and "an" as used in this application and the appended claims should be construed generally to mean "one or more," unless otherwise specified or clearly directed to the singular form from the context. Additionally, use of the terms "embodiment" or "one embodiment" or "implementation" or "one implementation" throughout is not intended to refer to the same embodiment or implementation unless so described.

[0110] The embodiments described herein may also relate to an apparatus for performing the operations herein. This apparatus may be specially constructed for the required purpose or may include a general-purpose computer, which is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored on a non-transitory computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, flash memory or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be interpreted to include one medium or multiple media (e.g., centralized or distributed databases and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be interpreted to include any medium that can store, encode or carry a set of instructions for execution by a machine, causing the machine to perform any one or more of the methodologies of the present embodiments. Accordingly, the term "computer-readable storage medium" should be taken to include, but not be limited to, solid-state memory, optical media, magnetic media, and any medium capable of storing a sequence of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present embodiments.

[0111] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required steps. The required structure for a variety of these systems will appear from the description that follows. In addition, the present embodiments are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0112] The above description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a thorough understanding of some embodiments of the present invention. However, it will be apparent to one of ordinary skill in the art that at least some embodiments of the present invention may be practiced without these specific details. In other instances, well-known components or methods have not been described in detail or have been presented in simple block diagram form to avoid unnecessarily obscuring the present invention. Thus, the above-described specific details are merely illustrative. A particular implementation may differ from these illustrative details and still be considered within the scope of the present invention.

[0113] It should be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. A capacitance-to-digital converter, comprising: a bridge circuit including a first terminal coupled to a reference cell, a second terminal coupled to a sensor cell, and a number of switches that are closed to couple the reference cell and / or the sensor cell to a modulator front-end circuit when a corresponding phase is enabled; the modulator front-end circuit; Contains the modulator front-end circuit includes a comparator coupled to the bridge circuit, a first modulation capacitor coupled to a first input of the comparator, and a second modulation capacitor coupled to a second input of the comparator; the modulator front-end circuit provides a digital bitstream; a duty cycle of the digital bit stream representing a ratio between a capacitance of the sensor cell and a reference capacitance of the reference cell; The sensor cell includes a sensor electrode. The modulator front-end circuit further includes a sequencer that generates a first phase, a second phase, a third phase, and a fourth phase, and the capacitance-to-digital converter further includes: applying a supply voltage to charge the sensor electrodes to a first voltage level during the first phase; during the second phase, coupling the sensor electrode to the first modulation capacitor to charge the first modulation capacitor; during the third phase, coupling the sensor electrode to a ground potential to ground the sensor electrode; in the fourth phase, coupling the sensor electrode to the second modulation capacitor to discharge the second modulation capacitor; It is structured as follows: The reference cell includes a reference electrode, and the capacitance-to-digital converter further comprises: applying the supply voltage in the first phase to charge the reference electrode to the first voltage level; during the second phase, coupling the reference electrode to the second modulation capacitor to charge the second modulation capacitor; during the third phase, coupling the reference electrode to the ground potential to ground the reference electrode; during the fourth phase, coupling the reference electrode to the first modulation capacitor to discharge the first modulation capacitor; Capacitance-to-digital converter.

2. the reference cell includes a reference electrode, and the reference capacitance is a self-capacitance; 2. The capacitance-to-digital converter of claim 1.

3. the reference cell includes a first electrode and a second electrode, and the reference capacitance is a mutual capacitance; 2. The capacitance-to-digital converter of claim 1.

4. the bridge circuit further includes a third terminal coupled to a compensation cell having a compensation capacitance, the ratio being based on the reference capacitance, the capacitance of the sensor cell, and the compensation capacitance.

2. The capacitance-to-digital converter of claim 1.

5. The compensation cell includes a compensation electrode, and the capacitance-to-digital converter further includes: applying the supply voltage in the first phase to charge the compensation electrode to the first voltage level; during the second phase, coupling the compensation electrode to the second modulation capacitor to charge the second modulation capacitor; in the third phase, coupling the compensation electrode to the ground potential to ground the compensation electrode; in the fourth phase, coupling the compensation electrode to the first modulation capacitor to discharge the first modulation capacitor; 5. The capacitance-to-digital converter according to claim 4.

6. the duty cycle of the digital bit stream is a ratio between the capacitance of the reference capacitance and the difference between the capacitance of the sensor cell and the capacitance of the compensation cell.

5. The capacitance-to-digital converter according to claim 4.

7. the sensor cell includes a sensor electrode, and the capacitance of the sensor cell is a self-capacitance.

2. The capacitance-to-digital converter of claim 1.

8. 1. A method, comprising: applying a supply voltage in a first phase to charge a sensor electrode of a sensor cell to a first voltage level; in a second phase, coupling the sensor electrode to a first modulation capacitor coupled to a first input of a comparator to charge the first modulation capacitor; in a third phase, coupling the sensor electrode to a ground potential to ground the sensor electrode; in a fourth phase, coupling the sensor electrode to a second modulation capacitor coupled to a second input of the comparator to discharge the second modulation capacitor; Contains a modulator front-end circuit including the first modulation capacitor, the second modulation capacitor, and the comparator; the modulator front-end circuit provides a digital bitstream; a duty cycle of the digital bit stream representing a ratio between a capacitance of the sensor cell and a reference capacitance of a reference cell; a plurality of switches are closed to couple the reference cell and / or the sensor cell to the modulator front-end circuit when a corresponding phase is enabled; The method comprises: applying, in the first phase, the supply voltage to charge a reference electrode of the reference cell to the first voltage level; during the second phase, coupling the reference electrode to the second modulation capacitor to charge the second modulation capacitor; during the third phase, coupling the reference electrode to the ground potential to ground the reference electrode; during the fourth phase, coupling the reference electrode to the first modulation capacitor to discharge the first modulation capacitor; Further comprising: method.

9. the reference cell includes the reference electrode, and the reference capacitance is a self-capacitance; The method of claim 8.

10. the reference cell further includes the reference electrode and a second reference electrode, and the reference capacitance is a mutual capacitance. The method of claim 8.

11. The method comprises: applying, in the first phase, the supply voltage to a compensation electrode of a compensation cell having a compensation capacitance; during the second phase, coupling the compensation electrode to the second modulation capacitor to charge the second modulation capacitor; during the third phase, coupling the compensation electrode to the ground potential to ground the compensation electrode; during the fourth phase, coupling the compensation electrode to the first modulation capacitor to discharge the first modulation capacitor; Further comprising: The method of claim 8.

12. the duty cycle of the digital bit stream is a ratio between the capacitance of the reference cell and the difference between the capacitance of the sensor cell and the capacitance of the compensation cell. The method of claim 11.

13. 1. A system comprising: A reference cell; A sensor cell; A capacitance-to-digital converter according to any one of claims 1 to 7; Contains system.

14. the system further includes a compensation cell having a compensation capacitance, the ratio being based on the reference capacitance, the capacitance of the sensor cell, and the compensation capacitance. The system of claim 13.

Images