DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD

Abstract

To enable detecting an address fault even in a case where an address value of an internal address cannot be monitored from outside.SOLUTION: In a storage system 1-3, bit width is a (a≥2) bits; pieces of write data 1-6 are written into 2a addresses in which address values are continuous; and pieces of write data 1-6 are read using a FIFO method. A redundancy bit generation section 1-1 generates redundancy bits 1-9 having bit width of r (r<a) bits by increment. A synthesis sections 1-21 outputs pieces of write data 1-6 which are synthesis between the redundancy bits 1-9 and pieces of actual data 1-8 to the storage system 1-3. A control section 1-23 controls an unread data number in the storage system 1-3 on the basis of c (integer) bits and the a bits being address intervals in which redundancy bits match between a right address value and an address value having an error generated due to a difference of the bit width between the a bits and the r bits when 1 bit error occurs in the address value.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to techniques for detecting address failures. [Background technology]

[0002] The effects of radiation are unavoidable when operating an artificial satellite (hereinafter simply referred to as a satellite) in orbit. It is generally known that radiation can cause temporary malfunctions such as Single Event Upsets (SEU). For this reason, the equipment installed on satellites must be highly reliable. In the design of FPGA (Field-Programmable Gate Array), the FIFO (First-In First-Out) method is generally used for data transfer between functions, etc. In order to shorten the design and verification period, it is common to use hard IP (Intellectual Property) already built into the FPGA. The effects of radiation on hard IP include data corruption and address errors. Error correction codes and error detection circuits are known to be effective countermeasures against these. To prevent data corruption, error correction codes such as Reed-Solomon (RS) codes can be used. By using error correction codes, errors in the read data can be detected and the read data can be corrected to be error-free. However, address errors cannot be detected by only protecting data using error correction codes, because if an address error causes data encoded with error correction codes stored at a different address to be read, the decoded result will be deemed normal and no errors will be detected and output.

[0003] Patent Document 1 describes a method and technology for detecting an address error. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 5-257822 Summary of the Invention [Problem to be solved by the invention]

[0005] However, the technology described in Patent Document 1 is effective when it is possible to monitor the address values ​​of the internal addresses (write addresses and read addresses). Therefore, when it is not possible to monitor the address values ​​of the internal addresses due to the specifications of the hard IP, the technology described in Patent Document 1 cannot be applied.

[0006] Once an address error occurs, it becomes difficult to guarantee that the FIFO will operate normally thereafter. In order to maintain the reliability of the system, it is necessary to take appropriate action, such as performing a reset when an error occurs. Therefore, it is necessary to create a mechanism that can detect address errors even in a FIFO circuit in which it is not possible to monitor the address value of the internal address.

[0007] The present disclosure has been made in consideration of the above circumstances. More specifically, a main object of the present disclosure is to enable detection of an address error even in a case where the address value of an internal address cannot be monitored from the outside. [Means for solving the problem]

[0008] The data processing device according to the present disclosure comprises: Each bit width is a (a ≥ 2) bits and the address values ​​are consecutive. a The above two addresses are a According to a write order that is either ascending order or descending order of address values ​​of the addresses, the combined data obtained by combining the actual data and the redundant bits is written, and the two addresses are written in the combined data. aConnected to a storage system that cannot externally monitor the address value, where the synthesized data written to any one of the addresses is read out by the FIFO (First-In First-Out) method. Each time real data is generated, if the writing order is ascending, increment the bit value, and if the writing order is descending, decrement the bit value to generate redundant bits with a bit width of r (r < a) bits. A synthesizing unit that synthesizes the redundant bits generated by the redundant bit generation unit and the generated real data to generate synthesized data, and outputs the generated synthesized data to the storage system. Based on c (an integer) bits, which is the address interval at which the redundant bits match between the correct address value and the address value with an error due to the difference in bit width between the a bits and the r bits when a 1-bit error occurs in the address value, and the a bits, a control unit that controls the number of unread data, which is the number of synthesized data that has not been read out among the synthesized data written to the storage system.

Advantages of the Invention

[0009] According to the present disclosure, even when the address values of internal addresses (write addresses and read addresses) cannot be externally monitored, address faults can be detected.

Brief Description of the Drawings

[0010] [Figure 1] A diagram showing a configuration example of a data processing system according to Embodiment 1. [Diagram 2] A diagram showing the address shift caused by a 1-bit address fault according to Embodiment 1. [Diagram 3] A diagram showing an example of the address value and the stored data stored in each address according to Embodiment 1 (a = 3, r_loop = 8, no address fault). [Figure 4]13 is a diagram showing an example of a determination result (a=3, r_loop=8, no address error) of the redundant bit determination unit according to the first embodiment. FIG. [Diagram 5] 13 is a diagram showing an example of a determination result (a=3, r_loop=8, there is an address error) of the redundant bit determination unit according to the first embodiment. FIG. [Figure 6] FIG. 13 is a diagram showing an example of address values ​​and data stored at each address (a=3, r_loop=3) according to the first embodiment. [Figure 7] 13 is a diagram showing an example of a determination result (a=3, r_loop=3, there is an address error) of the redundant bit determination unit according to the first embodiment. FIG. [Figure 8] FIG. 13 is a diagram showing an example of address values ​​and data stored at each address (a=3, r_loop=3) according to the first embodiment. [Figure 9] 13 is a diagram showing an example of a determination result (a=3, r_loop=3, there is an address error, and error detection is not possible) of the redundant bit determining unit according to the first embodiment. FIG. [Figure 10] FIG. 13 is a diagram showing an example of the number of unread data items (a=3, r_loop=3) according to the first embodiment. [Figure 11] 5 is a flowchart showing an example of operation of a redundant bit generation unit according to the first embodiment. [Figure 12] 5 is a flowchart showing an example of the operation of a synthesis unit according to the first embodiment. [Figure 13] 5 is a flowchart showing an operation example of a separation unit according to the first embodiment. [Figure 14] 5 is a flowchart showing an example of operation of a redundant bit determination unit according to the first embodiment. [Figure 15] 5 is a flowchart showing an example of the operation of a control unit according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. In the following description of the embodiments and in the drawings, the same reference numerals denote the same or corresponding parts.

[0012] Embodiment 1 ***Configuration Description*** FIG. 1 shows an example of the configuration of a data processing system 10 according to the present embodiment.

[0013] The data processing system 10 comprises a storage system 1-3, a redundant bit generating section 1-1, a redundant bit determining section 1-2, a combining section 1-21, a separating section 1-22, and a control section 1-23. The combination of the redundant bit generating unit 1-1, the redundant bit determining unit 1-2, the combining unit 1-21, the separating unit 1-22 and the control unit 1-23 corresponds to the data processing device 100. As shown in Fig. 1, the data processing device 100 is connected to a storage system 1-3. The data processing device 100 and the storage system 1-3 are included in the same FPGA. The FPGA is broadly divided into a hard IP and an area other than the hard IP. The storage system 1-3 is realized by the hard IP included in the FPGA, and the data processing device 100 is realized by the area other than the hard IP. Moreover, the operation procedure of the data processing device 100 corresponds to a data processing method.

[0014] The storage system 1-3 follows the FIFO method, that is, the storage system 1-3 outputs data in the order in which the data was input. More specifically, the storage system 1-3 acquires composite data obtained by combining the real data 1-8 and the redundant bits 1-9 as the write data 1-6, and stores the acquired write data 1-6. The real data 1-8 is data that is the target of error detection. The real data 1-8 is data that does not include the redundant bits 1-9 and should be originally stored in the storage circuit 1-32. In this embodiment, the real data 1-8 is d (d≧1) bit data. Also, the redundant bits 1-9 are error detection codes. In this embodiment, the redundant bits 1-9 are r bits. The definition of r bits will be described later. The write data 1-6 is (d+r) bit data. Furthermore, when a read enable 1-13 is output, the storage system 1-3 reads out the composite data as read data 1-7 by the FIFO method. The read data 1-7 is also (d+r)-bit data. The read data 1-7 is made up of actual data 1-11 and redundant bits 1-12. Incidentally, the address values ​​of the internal addresses (write addresses and read addresses) of the storage system 1-3 cannot be monitored from the outside.

[0015] The storage system 1-3 has, as its internal components, a write address generation circuit 1-31, a storage circuit 1-32, and a read address generation circuit 1-33.

[0016] When the write enable 1-10 is output, the write address generation circuit 1-31 generates a write address 1-4 and outputs the generated write address 1-4 to the memory circuit 1-32. More specifically, the write address generation circuit 1-31 generates two consecutive address values ​​each having a bit width of a (a≧2). a These addresses are generated as write addresses 1-4 in ascending order of address value. Then, the generated write addresses 1-4 are output to the memory circuit 1-32. The write addresses 1-4 indicate addresses to which the write data 1-6 is to be written.

[0017] The memory circuit 1-32 writes the write data 1-6 to the address specified by the write address 1-4. a Write data 1-6 is written to any one of these addresses. Moreover, the memory circuit 1-32 reads out the composite data from the address specified by the read address 1-5 output from the read address generation circuit 1-33, and outputs the read out composite data as read data 1-7.

[0018] When the read enable 1-13 is output, the read address generation circuit 1-33 generates a read address 1-5 and outputs the generated read address 1-5 to the memory circuit 1-32. More specifically, the read address generation circuit 1-33 generates the read address 1-5 according to the FIFO method. That is, the read address generation circuit 1-33 generates two a addresses as the read address 1-5 in ascending order of the address value. Then, the generated read address 1-5 is output to the memory circuit 1-32. As described above, the memory circuit 1-32 reads the read data 1-7 from the address specified by the read address 1-5.

[0019] The redundant bit generation unit 1-1 has a counter inside. And every time the actual data 1-8 is generated, the redundant bit generation unit 1-1 increments (counts up) the counter value to generate a redundant bit 1-9. More specifically, every time the write enable 1-10 is output, the redundant bit generation unit 1-1 generates a redundant bit 1-9 with a bit width of r (r < a) bits by incrementing (counting up). Then, the redundant bit generation unit 1-1 outputs the generated redundant bit 1-9 to the synthesis unit 1-21.

[0020] Every time the actual data 1-8 is generated, the synthesis unit 1-21 synthesizes the redundant bit 1-9 generated by the redundant bit generation unit 1-1 and the generated actual data 1-8 to generate synthesized data. Then, the synthesis unit 1-21 outputs the generated synthesized data as write data 1-6 to the memory system 1-3.

[0021] Every time the read enable 1-13 is output and the read data 1-7 is read from the memory system 1-3, the separation unit 1-22 acquires the read read data 1-7. Then, the separation unit 1-22 separates the acquired read data 1-7 into actual data 1-11 and redundant bits 1-12. The actual data 1-11 is d-bit data, similar to the actual data 1-8. Also, the redundant bit 1-12 is r-bit data, similar to the redundant bit 1-9.

[0022] The redundant bit determination unit 1-2 acquires the separated redundant bit 1-12 every time the separation unit 1-22 separates the redundant bit 1-12 from the read data 1-7. Then, the redundant bit determination unit 1-2 judges whether the bit value of the acquired redundant bit 1-12 is correct or not. The redundant bit determination unit 1-2 has an internal counter. Specifically, the redundant bit determination unit 1-2 increments (counts up) the counter value to judge whether the counter value matches the bit value of the acquired redundant bit 1-12. In other words, the redundant bit determination unit 1-2 judges whether the bit value of the redundant bit 1-12 acquired during the previous data read and the bit value of the redundant bit 1-12 acquired during the current data read are continuous or not. If the bit value of the acquired redundant bit 1-12 is incorrect, that is, if the counter value and the bit value of the acquired redundant bit 1-12 do not match, the redundant bit determination unit 1-2 warns by error notification 1-14 that an error has occurred in at least one of the writing of write data 1-6 and the reading of read data 1-7 in the storage system 1-3.

[0023] The storage system 1-3 outputs a programmable full signal and a programmable empty signal as the current status based on the write and read status. The upper and lower thresholds can be specified by the user. In this system, the upper threshold is c (an integer). The lower threshold is (2 a -(c-1)) units. Details of c will be described later. More specifically, each time write data 1-6 is written to the memory circuit 1-3 and each time read data 1-7 is read from the memory circuit 1-32, the control unit 1-23 receives updated programmable full signals and programmable empty signals from the memory circuit 1-32. Then, the control unit 1-23 controls the write permission signal and the read permission signal so that the number of unread data items falls within the range between the upper threshold and the lower threshold. In response to the programmable full signal received from the memory circuit 1-32, the control unit 1-23 determines that the number of unread data has reached an upper threshold, negates the write enable signal 1-18, and requests the source of the actual data 1-8 to stop generating the actual data 1-8. In response to the programmable empty signal received from the memory circuit 1-32, the control unit 1-23 determines that the number of unread data has reached a lower threshold, negates the read enable signal 1-19, and requests the source of the read data 1-7 to stop reading the read data 1-7. Furthermore, when the control unit 1-23 determines that the number of unread data items falls below the upper limit threshold based on the programmable full signal received from the memory circuit 1-32, the control unit 1-23 asserts the write permission signal 1-18 to permit the generator of the actual data 1-8 to resume generating the actual data 1-8. Furthermore, when the control unit 1-23 determines that the number of unread data items exceeds the lower limit threshold based on the programmable empty signal received from the memory circuit 1-32, the control unit 1-23 asserts the read permission signal 1-19 to permit the source of the read data 1-7 to resume reading the read data 1-7. In this way, the control unit 1-23 determines whether the number of unread data items is equal to the upper threshold c or the lower threshold (2 a The range is controlled so that the number of pieces is within the range of (c-1).

[0024] In this embodiment, the redundant bits 1-9 have a simple structure in which there is no duplication of elements and they are reset every r_loop times. Furthermore, in this embodiment, r_loop is set to be prime (avoiding divisors) with respect to address deviations that may occur due to address errors (0≦n≦a-1, n is the bit position). In this way, even in the case of a storage system 1-3 that is a hard IP and in which the internal addresses (write addresses 1-4 and read addresses 1-5) cannot be monitored from the outside, it is possible to realize detection of address errors with a compact configuration.

[0025] During data writing, the redundant bit generation unit 1-1 generates redundant bits 1-9 (r bits) triggered by write enable 1-10. Then, the synthesis unit 1-21 synthesizes the actual data 1-8 (d bits) and the redundant bits 1-9, and writes the write data 1-6 ((d+r) bits) to the memory circuit 1-32. The FIFO of the hard IP often has a fixed bit width. When the bit width of the write data 1-6 is smaller than the bit width of the memory circuit 1-32, additional bits corresponding to the number of missing bits may be added to the write data 1-6. By doing so, the difference in bit width between the write data 1-6 and the memory circuit 1-32 can be absorbed without increasing resources.

[0026] During data reading, the separation unit 1-22 extracts the actual data 1-11 (d bits) and the redundant bits 1-12 (r bits) from the read data 1-7 ((d+r) bits). Then, the redundant bit determination unit 1-2 compares the bit value of the redundant bits 1-12 with the bit value obtained from the count-up of the internal counter. When they do not match, the redundant bit determination unit 1-2 outputs an error notification 1-14 notifying that an address failure has been detected, for example, to a control system that determines the issuance of a reset.

[0027] As described above, in this embodiment, it is assumed that the bit width r of the redundant bits is smaller than the bit width a of the address (write address, read address) (r < a). Here, for ease of understanding, first, the address failure detection when the bit width r of the redundant bits is the same as the bit width a of the address (write address, read address) (r = a) will be described. Then, the address failure detection when the bit width r of the redundant bits is smaller than the bit width a of the address (write address, read address) (r < a) will be described. Note that hereinafter, it is assumed that a = 3 and the internal counter of the redundant bit generation unit 1-1 is a counter that makes one full cycle with r_loop.

[0028] ***Address Failure Detection in the Case of (r = a)*** The address deviation (positive or negative) that can occur due to a 1-bit address error in the address (a bits) is shown in Figure 2. When considering overlaps, there are a total of 10 possibilities.

[0029] Consider the case where a 1-bit address error occurs at bit 0 of address b000, causing it to become b001. Normally, the count would go up as b001 → b010 → b011 → ... → b111 → b000 → b001, so it is thought that this error has caused an address deviation of "+1" or "-7". Thinking in the same way, if a 1-bit address error occurs at address b000, the error at bit 0 will cause an address deviation of "+1" or "-7". Furthermore, an error at bit 1 will cause an address error of "+2" or "-6". Furthermore, an error at bit 2 will cause an address deviation of "±4". Similarly, if an address error occurs at address b111, the error in the 0th bit will cause an address shift of -1 or +7. The error in the 1st bit will cause an address shift of -2 or +6. The error in the 2nd bit will cause an address shift of ±4. Therefore, the sign of the address shift that can occur due to a 1-bit address error differs depending on the address value at the time the error occurs. Also, since there are four types of address shifts, including positive and negative, for the location where the address error occurs, the total number of address shifts that can occur is 4 x a [bit] if overlaps are not taken into account.

[0030] The bit width of the redundant bits is r=a, and the internal counter of the redundant bit generator 1-1 is r_loop=2. a Assume that a counter with r_loop counts is set to 8 (0,1,2,...,7,0,1,2,...). The internal counter can be implemented in either hardware or software. In this case, the redundant bits have no overlaps among elements in r_loop counts, and are completely prime to the address shift (Figure 2) that occurs due to a 1-bit address error. Therefore, 100% error detection is possible for a 1-bit address error.

[0031] FIG. 3 shows the address value of each address and the data (actual data 1-8 and redundant bits 1-9) stored at each address when no address error occurs. Assume that address b000 is written to at time t=twr1, and address b001 is written to at time t=twr1+1. Figure 3 shows the state after address b111 is written to at time t=twr1+7. As shown in FIG. 3, when no address failure occurs, the address value of each address matches the bit values ​​of redundant bits 1-9 stored in each address. That is, the redundant bit generator 1-1 generates a redundant bit 1-9 having the same bit value as the address value of the write destination address of the write data 1-6.

[0032] FIG. 4 shows the determination result of the redundant bit determination unit 1-2 when no address error occurs. The stored data is read out from the memory circuit 1-32 in order starting from address b000. The read address 1-5 to be read is generated by a read address generation circuit 1-33 using a read enable 1-13 as a trigger. The redundant bit determination unit 1-2 compares the bit value of the redundant bit 1-12 separated by the separation unit 1-22 from the read stored data (read data 1-7) with a reproduced value of the address value of the read address from which the data was read. In the example of FIG. 4, the redundant bits change in the order (0, 1, 2, . . . 7) set in the redundant bit generator 1-1, so that the redundant bits are counted as set and an address error is not detected. The address and redundant bits 1-9 become counter values ​​that are reset eight times to b000, b001, . . . , b111 at times t=trd1 to t=trd1+7.

[0033] FIG. 5 shows the determination result of the redundant bit determination unit 1-2 when an address error occurs. In the example of Fig. 5, until time t = trd2 + 1, the correct read data 1-7 are read out, and the redundant bits are performing the counting operation as set. Normally, next, assuming it corresponds to address b010, the actual data C and b010 are read out. However, assume that an address fault occurs at the 0th bit of read addresses 1-5, and the read addresses 1-5 change from b010 to b011. For this reason, at time t = trd2 + 2, the read data 1-7 corresponding to the incorrect read address b011 and the actual data D and b011 which are the redundant bits 1-12 are output. Since the redundant bit determination unit 1-2 determines that the redundant bits 1-12 (b011) do not match the reproduced value of the address value (b010) of the read address (not counted up normally), it determines that an address fault has occurred and outputs an error notification 1-14 to, for example, a control system that determines the issuance of a reset. Even if the user of the data processing system 10 cannot monitor the address value of the internal address of the memory system 1-3, the occurrence of an address fault can be confirmed by the error notification 1-14.

[0034] ***Detection of address fault when (r < a)*** Hereinafter, assume that the bit width of the redundant bit is r < a, and r_loop = 2 as the internal counter of the redundant bit generation unit 1-1 r -1 counter (0, 1, …, 2 r -1, 0, 1, …) is set. In this case, the redundant bit can detect a partial 1-bit address fault with respect to the address shift (Fig. 2) caused by a 1-bit address fault. In this case, it is impossible to completely eliminate the address shift that can occur with r_loop. That is, it becomes impossible to detect a fault when the redundant bit becomes a divisor with respect to the address shift. Compared with the case where the bit width of the redundant bit is r = a, fault detection is possible on a smaller scale.

[0035] As an example, consider the case where r=2 and the internal counter (0,1,2,0,1,...) is set to 3, and r_loop=3. Since r_loop is a divisor of 6, if an address error in the first bit causes a deviation of "+6" or "-6", the address error cannot be detected. In other words, if a one-bit error occurs in an address value and the address interval between the correct address value and the address value where the error occurred becomes "±6", the redundant bits of the correct address value and the address value where the error occurred will match due to the difference in bit width between a and r bits. For this reason, the address error cannot be detected by checking the redundant bits. This address interval "±6" corresponds to c bits.

[0036] Consider the data storage state in storage system 1-3 when an internal counter of r_loop=3 is set as redundant bit generator 1-1. The probability that an address error occurs in the first bit of r=3 bits is 1 / 3. Also, the probability that an address error in the first bit will cause a shift in six address errors is 2 / 8 on average. Therefore, the detectability rate of a 1-bit address error is roughly 91.7% (1-(1 / 3*2 / 8)*100≒91.7). Note that the actual detection rate differs depending on the timing of reads and writes.

[0037] FIG. 6 shows the address values ​​of addresses and the data stored at each address (actual data 1-8 and redundant bits 1-9) when an internal counter (0, 1, 2, 0, 1, ...) is set to r=2 and r_loop=3 and no address failure occurs.

[0038] Assume that address b000 is written to at time t=twr2, and address b001 is written to at time t=twr2+1. Figure 6 shows the state after address b111 is written to at time t=twr2+7.

[0039] FIG. 7 shows the determination result of the redundant bit determination unit 1-2 when an address error occurs in the case where data is stored in the state shown in FIG. In FIG. 7, it is assumed that after reading is performed in order from address b000, a failure occurs in the first bit of the address value during a transition from address b001 to address b010. Therefore, at time t=trd3+2, the read data corresponding to the erroneous read address b000 and the redundant bits, that is, actual data A and b00, are output. In Fig. 7, after reading is performed in order from address b000, suppose that an error occurs in the first bit of the address value when transitioning from address b001 to address b010. In this case, taking into account the write order in Fig. 6, it appears that an address shift of "-2" has occurred, so the redundant bit determination unit 1-2 can output an error notification 1-14 of a 1-bit address error.

[0040] Similarly, at time t=trd4, reading is performed in order starting from address b000, and after reading is completed up to address b100, real data I and redundant bit b10 are newly written at time t=twr2+8 as shown in Fig. 8. Furthermore, real data J and redundant bit b00 are written at time t=twr2+9, and thereafter, writing of real data and redundant bits continues, and finally, real data M and redundant bit b00 are written at time t=twr2+12. The newly written real data and redundant bit are written starting from address b000 that has already been output.

[0041] FIG. 9 shows the results when reading is performed in the order in which data was written in the state of FIG. It is assumed that reading of address b101 is completed and during the next read, that is, during the transition from address b101 to address b110, a failure occurs in the first bit of the read address. At this time, the actual data M at the address b100 and the redundant bit b00 are mistakenly read out. When only redundant bits are monitored, it appears that the count is incremented normally, so no error is detected in the redundant bit determination unit 1-2 and the address fault is overlooked. Considering the write order in Fig. 8, this is because an address shift of "+6" occurs, and the redundant bits of the correct address b110 and the incorrect address b100 where an error occurred have the same value.

[0042] The control unit 1-23 outputs a write permission signal 1-18 and a read permission signal 1-19, and it is possible to increase the detection rate of a 1-bit address fault by keeping the number of unread data within the range of the upper limit threshold and the lower limit threshold. Specifically, the control unit 1-23 can increase the detection rate of a 1-bit address fault even when r < a by performing the following control.

[0043] As described above, when r_loop is a divisor of the address shift that can occur due to a 1-bit address fault, the detection of the fault may fail. Among these, the address shift for which the detection rate is desired to be improved is set to c bits. That is, the c bits are the address interval at which the redundant bits match between the correct address value and the incorrect address value due to the difference in the bit widths of the a bits and the r bits when a 1-bit error occurs in the address value. At this time, when c > (2 (a-1) ) and r_loop is not a divisor of (2 a ) - c, an improvement in the detection rate can be expected by controlling the number of unread data.

[0044] As described above, when the number of unread data in the memory circuit 1-32 reaches the upper limit threshold, the control unit 1-23 negates the write permission signal. When the write permission signal is negated, the source of the actual data 1-8 stops generating the actual data 1-8 until the write permission signal 1-18 is asserted thereafter. When the programmable read permission signal is negated, the source of the read data 1-7 stops reading the read data 1-7 until the read permission signal 1-19 is output thereafter.

[0045] Next, the number of unread data is set as the upper threshold c and the lower threshold (2 a -(c-1)) is chosen. As an example, consider the case where an internal counter (0,1,2,0,1,...) with r=2 and r_loop=3 is used for the aforementioned address bit width a=3. Of the 10 possible address deviations that can occur due to a 1-bit address error, the only one for which r_loop is a divisor is "6", so "c=±6". In this case, the upper threshold c=6 and the lower threshold (2 a -(c-1))=(2 3 -(6-1))=3.

[0046] FIG. 10 shows address values ​​and data (actual data 1-8 and redundant bits 1-9) stored at each address when the address bit width a=3 and the redundant bit width r=2. In Fig. 10, the address where the write data 1-6 was last stored is b101. For this reason, in Fig. 10, the address b110 where the write data 1-6 was stored the oldest is placed at the top. Note that the correspondence between the address value (e.g., "b110") and the redundant bit value (e.g., "b00") is the same as in Figs. 8 and 9. In FIG. 10, "7 unread data items" indicates the distribution of unread data when the number of unread data items is 7. "2 unread data items" indicates the distribution of unread data when the number of unread data items is 2. "4 unread data items" indicates the distribution of unread data when the number of unread data items is 4. In other words, the actual data and redundant bits at the addresses indicated as "unread data" have been written to memory circuits 1-32 but have not yet been read out.

[0047] First, the case where the number of unread data items is 7 (the number of unread data items exceeds the upper limit threshold) will be described. If reading of address b110 is complete and the actual data and redundant bits from address b111 onwards are unread (7 pieces of unread data), the data read out during the next read will be the actual data B at address b111 and redundant bit b01. Here, the address shift caused by a fault occurring in the first bit of the address is +c bits (i.e., +6 bits). If a fault occurs in the first bit of the address and the address shifts by +c bits from address b111, which is the address that is originally the target for reading, address b101, which is +c bits away, will be the erroneous target for reading. Since the redundant bits of addresses b111 and b101 are the same as b01, the address fault cannot be detected.

[0048] Next, the case of "unread data number 2" (when the unread data number is below the lower limit threshold) will be described. If reading of address b011 is complete and the actual data and redundant bits from address b100 onwards are unread (two pieces of unread data), the data read out during the next read will be the actual data G at address b100 and the redundant bits b00. Here, the address shift caused by a fault occurring in the first bit of the address is -c bits (i.e. -6 bits). If a fault occurs in the first bit of the address and the address shifts by -c bits from address b100, which is the address that is originally the target for reading, address b110, which is -c bits away, becomes the erroneous target for reading. Since the redundant bits of addresses b100 and b110 are the same as b00, the address fault cannot be detected.

[0049] From the above, if the number of unread data bits is not within the range between the upper and lower thresholds, the redundant bit of the address ±c bits away caused by a 1-bit address error will have the same value as the redundant bit of the address that was originally intended to be read. As a result, the address error cannot be detected.

[0050] Next, a case where the number of unread data items is within the range between the upper and lower thresholds will be described. Specifically, the case where the number of unread data items is 4 will be described. If reading of address b001 is complete and the actual data and redundant bits from address b010 onwards are unread (four pieces of unread data), the data read out during the next read will be the actual data E at address b010 and the redundant bits b01. Here, the address deviation caused by a fault occurring in the first bit of the address is not ±c bits. If a fault occurs in the first bit of the address b010, it appears to be an address deviation of -2 when focusing on the continuity of the redundant bits, so the actual data C of address b000 and redundant bit b10 are erroneously read. In this case, the erroneously read redundant bit b10 is different from the redundant bit b01 that was originally intended to be read. This makes it possible to detect address errors.

[0051] As a result, the control unit 1-23 sets the number of unread data items to the lower limit threshold (2 a By controlling the number of unread data items to be within the range of c (-(c-1)) and the upper threshold c, that is, to be within the range of 3 to 6, an address error can be detected.

[0052] In the above, we have explained the case where an error occurs in the first bit of the address. However, the same applies when an error occurs in another bit position. In other words, even if an error occurs in another bit position, the number of unread data items will not exceed the lower limit threshold (2 a By controlling the number of addresses to within the range of c (-(c-1)) and the upper threshold c, an address error can be detected.

[0053] ***Explanation of Operation*** Next, an example of the operation of the data processing device 100 according to the present embodiment will be described.

[0054] FIG. 11 shows an example of the operation of the redundant bit generator 1-1.

[0055] First, in step S101, the redundant bit generation unit 1-1 acquires the write enable 1-10.

[0056] Next, in step S102, the redundant bit generator 1-1 counts up the counter value to obtain a redundant bit 1-9.

[0057] Next, in step S103, the redundant bit generator 1-1 outputs the generated redundant bit 1-9 to the combiner 1-21.

[0058] FIG. 12 shows an example of the operation of the synthesis unit 1-21.

[0059] First, in step S111, the synthesis unit 1-21 acquires the actual data 1-8.

[0060] Next, in step S112, the combiner 1-21 obtains the redundant bit 1-9.

[0061] Next, in step S113, the combiner 1-21 combines the actual data 1-8 and the redundant bits 1-9 to generate the write data 1-6. Specifically, the combiner 1-21 adds the redundant bits 1-9 to the end of the actual data 1-8.

[0062] Finally, in step S114, the combiner 1-21 outputs the write data 1-6 to the storage system 1-3.

[0063] FIG. 13 shows an example of the operation of the separator 1-22.

[0064] First, in step S121, the separator 1-22 acquires the read data 1-7 output from the storage system 1-3.

[0065] Next, in step S122, the separator 1-22 separates the read data 1-7 into actual data 1-11 and redundant bits 1-12. Specifically, the separator 1-22 sets the first d bits of the read data 1-7 as actual data 1-11 and the remaining r bits as redundant bits 1-12.

[0066] Next, in step S124, the separation unit 1-22 outputs the actual data 1-11 to a predetermined output destination.

[0067] Finally, in step S125, the separator 1-22 outputs the redundant bit 1-12 to the redundant bit determiner 1-2.

[0068] FIG. 14 shows an example of the operation of the redundant bit determination unit 1-2.

[0069] First, in step S131, the redundant bit determination unit 1-2 acquires the read enable 1-13. Next, in step S132, the redundant bit determination unit 1-2 counts up an internal counter using the acquisition of the read enable 1-13 as a trigger.

[0070] Next, in step S133, the redundant bit determination unit 1-2 obtains the redundant bit 1-12.

[0071] Next, in step S134, the redundant bit determination unit 1-2 determines whether or not the bit value of the redundant bit 1-12 matches the counter value obtained in step S132.

[0072] If the redundant bit 1-12 does not match the counter value (NO in step S134), the redundant bit determination unit 1-2 outputs an error notification 1-14 in step S135. On the other hand, if the redundant bit 1-12 matches the counter value (YES in step S134), the redundant bit determination unit 1-2 ends the process.

[0073] FIG. 15 shows an example of the operation of the control unit 1-23.

[0074] First, in step S141, the control unit 1-23 determines whether the programmable full signal or the programmable empty signal from the storage circuit 1-32 has been updated. If it is confirmed that the programmable full signal or the programmable empty signal has been updated from the storage circuit 1-32, the process proceeds to step S142. On the other hand, if there is no update of the programmable full signal or the programmable empty signal from the storage circuit 1-32, the process is completed.

[0075] When the control unit 1-23 confirms an update of the programmable full signal or the programmable empty signal from the memory circuit 1-32 (YES in step S141), in step S142, the control unit 1-23 judges whether the programmable full signal is asserted or not. The fact that the programmable full signal is asserted indicates that the number of unread data has reached the upper limit threshold. If the programmable full signal is asserted (YES in step S142), the control unit 1-23 negates the write enable signal 1-18 and asserts the read enable signal 1-19 (step S144). If the programmable full signal is not asserted (NO in step S142), in step S143, the control unit 1-23 judges whether or not the programmable empty is asserted. The fact that it is asserted indicates that the number of unread data has reached the lower limit threshold. If the programmable empty signal is asserted (YES in step S143), the control unit 1-23 asserts the write enable signal 1-18 and negates the read enable signal 1-19 (step S145). If the programmable empty signal is not asserted (NO in step S143), the control unit 1-23 asserts the write enable signal 1-18 and asserts the read enable signal 1-19 (step S146).

[0076] ***Description of the Effects of the Embodiment*** As described above, according to the present embodiment, even when r < a, it is possible to detect an address failure caused by radiation in a small-scale configuration for a hard IP whose internal address value cannot be monitored. Then, it is possible to notify the upper-level system of the occurrence of the address failure, and appropriate processing can be performed to return to normal operation such as reset. As a result, it is possible to improve the reliability of the system.

[0077] Above, an example in which the writing order of the write data 1-6 in the memory system 1-3 is in ascending order of the address value has been described. The writing order of the write data 1-6 in the memory system 1-3 may be in descending order of the address value.

[0078] Also, the redundant bit generation unit 1-1 and the redundant bit determination unit 1-2 may use other than a counter (including PN (Pseudorandom Noise)) as long as they can generate the reproduced values of the redundant bit 1-9 and the read address 1-5 that make one round in r_loop times.

[0079] Only a part of the procedures described in the present embodiment may be implemented. Also, at least a part of the procedures described in the present embodiment may be combined with procedures not described in the present embodiment and implemented. Also, the configurations and procedures described in the present embodiment may be changed as necessary.

Explanation of Reference Numerals

[0080] 1-1 redundant bit generation unit, 1-2 redundant bit determination unit, 1-3 memory system, 1-4 write address, 1-5 read address, 1-6 write data, 1-7 read data, 1-8 actual data, 1-9 redundant bit, 1-10 write enable, 1-11 actual data, 1-12 redundant bit, 1-13 read enable, 1-14 error notification, 1-18 write enable signal, 1-19 read enable signal, 1-21 synthesis unit, 1-22 separation unit, 1-23 control unit, 1-31 write address generation circuit, 1-32 memory circuit, 1-33 read address generation circuit, 10 data processing system, 100 data processing device, 901 processor, 902 main memory device, 903 auxiliary memory device, 904 communication device, 905 input / output device.

Claims

1. Each bit width is a (a≧2) bits, and the address values ​​are two consecutive ａ The two addresses are ａ According to a write order that is either ascending order or descending order of address values ​​of the addresses, composite data obtained by combining the actual data and the redundant bits is written, and the two addresses are written in the same order. ａ the composite data written to any one of the addresses is read out in a FIFO (First-In First-Out) manner, and the address value cannot be monitored from the outside; a redundant bit generator that generates redundant bits having a bit width of r (r<a) bits by incrementing a bit value if the write order is ascending and decrementing a bit value if the write order is descending, each time real data is generated; a combining unit that combines the redundant bits generated by the redundant bit generating unit with generated actual data to generate combined data and outputs the generated combined data to the storage system; A data processing device having: c (integer) bits, which is an address interval in which, when a one-bit error occurs in an address value, a redundant bit will match between a correct address value and an address value in which an error occurs due to a difference in bit width between the a bits and the r bits; and a control unit that controls a number of unread data, which is the number of composite data written to the storage system that has not been read, based on the a bits.

2. The control unit is The number of unread data items is (2 ａ 2. The data processing device according to claim 1, wherein the number of the inputs is controlled to be within the range of -(c-1)) to c.

3. The control unit is The number of unread data items is (2 ａ 3. The data processing device according to claim 2, further comprising: a data processing device which requests a source of the actual data to stop generating the actual data when the number of unread data reaches c (-(c-1)), and requests a source of the synthetic data to stop reading the synthetic data when the number of unread data reaches c.

4. The data processing device further comprises: a separation unit that acquires the read composite data each time the composite data is read from the storage system and separates the acquired composite data into actual data and redundant bits; 2. The data processing device according to claim 1, further comprising a redundant bit determination unit which acquires the separated redundant bit each time the redundant bit is separated by the separation unit and determines whether or not a bit value of the acquired redundant bit is correct.

5. The redundant bit determination unit 5. The data processing device according to claim 4, wherein, if the bit value of the acquired redundant bit is incorrect, a warning is given that an error has occurred in at least one of writing the composite data in the storage system and reading the composite data.

6. A FPGA (Field-Programmable Gate Array) is roughly divided into a hard IP (Intellectual Property) and an area other than the hard IP. Each of the hard IPs has a bit width of a (a≧2) bits and has two consecutive address values. ａ The two addresses are ａ According to a write order that is either ascending order or descending order of address values ​​of the addresses, composite data obtained by combining the actual data and the redundant bits is written, and the two addresses are written in the same order. ａ In an FPGA, a storage system in which composite data written to any one of the addresses is read out in a FIFO (First-In First-Out) manner and address values ​​cannot be monitored from the outside is included in the hard IP, The area other than the hard IP of the FPGA, Each time real data is generated, if the writing order is ascending, a bit value is incremented, and if the writing order is descending, a bit value is decremented to generate a redundant bit having a bit width of r (r<a); Combining the generated redundant bits and the generated actual data to generate composite data, and outputting the generated composite data to the storage system; A data processing method for controlling the number of unread data, which is the number of composite data written to the storage system that has not been read, based on c (integer) bits, which is an address interval in which, when a one-bit error occurs in an address value, a redundant bit will match between a correct address value and an address value in which an error occurs due to a difference in bit width between the a bits and the r bits, and the a bits.

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